JP2006196673A - Split laminated wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a split laminated wiring board which is stabilized in electric characteristics, with little generation of curvature and without mounting expensive parts, such as a chip capacitor. <P>SOLUTION: In the split laminated wiring board wherein a first wiring board 1 is mounted in a second wiring board 31, the second wiring board 31 is mounted to a printed circuit board 51. A capacitor 7 is formed in the first wiring board 1, and furthermore, the dielectric constant of the first wiring board 1 is larger than the dielectric constant of the second wiring board 2. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a divided multilayer wiring board, for example, a multilayer ceramic wiring board for protecting a semiconductor element, and more particularly, to a divided multilayer wiring board suitable for high-speed transmission with high reliability for flip-chip mounting of a semiconductor element.

  In recent years, with the advent of advanced information technology, information and communication technology has been rapidly developed, and as a result, various electrical devices represented by semiconductor devices have been increased in speed and size, and even in the wiring layer, signal transmission loss has been reduced. In order to reduce and transmit higher-speed signals, it is required to reduce the resistance of the wiring layer and the dielectric constant of the insulating substrate.

  In particular, with the increase in the speed of semiconductor elements, it is necessary to stably supply a power supply voltage. In such an electric device, it is disclosed that a chip capacitor is mounted on the surface of a package (see, for example, Patent Document 1).

  However, the method of mounting such a chip capacitor has not only high cost of components, but also has a barrier because it requires cost and labor to mount it. In addition, since the distance from the chip capacitor portion to the semiconductor element through the package becomes long, this portion works as an inductance component, and therefore, it goes against the movement of speeding up itself.

Therefore, by stacking two types of materials with different dielectric constants and firing them simultaneously, a capacitor is formed inside the package, eliminating the trouble of mounting the chip capacitor and reducing the distance from the capacitor portion to the semiconductor element portion. Is disclosed (for example, see Patent Document 2).
JP 2003-17650 A JP 2000-31328 A

  However, although the wiring board described in Patent Document 2 has an advantage that it does not need to mount a chip capacitor because it has a built-in capacitor, since two types of materials are fired at the same time, it depends on the difference in firing shrinkage behavior of the materials. There was a problem of warping.

  Accordingly, an object of the present invention is to provide a divided multilayer wiring board with less warpage without mounting expensive components such as chip capacitors.

  The divided laminated wiring board of the present invention is the divided laminated wiring board in which the first wiring board is mounted on the second wiring board, and the second wiring board is further mounted on the printed wiring board. A capacitor is formed on one wiring board, and a dielectric constant of the first wiring board is larger than a dielectric constant of the second wiring board.

In particular, when the thermal expansion coefficient of the first wiring board at 0 to 150 ° C. is α ₁ , the thermal expansion coefficient of the second wiring board is α ₂ , and the thermal expansion coefficient of the printed wiring board is α ₃ , 2 It is preferable that 0.0 × 10 ⁻⁶ / ° C. <α ₁ <5.0 × 10 ⁻⁶ / ° C. <α ₂ <α ₃ .

  Moreover, it is preferable that at least one wiring layer of the first and second wiring boards contains copper, silver, or gold as a main component.

  The present invention divides the wiring board into two parts, and forms a capacitor inside the wiring board having a high dielectric constant, so that a wiring board with less warpage can be obtained without mounting expensive parts such as a chip capacitor. It is based on the knowledge that it can be realized.

  That is, the first wiring board having a dielectric constant larger than that of the second wiring board mounted on the printed wiring board is mounted on the second wiring board, and the electric element is mounted on the first wiring board. By forming a capacitor inside the first wiring board, it is possible to provide a split multilayer wiring board with less warping without mounting expensive components such as chip capacitors.

  In addition, even if the difference in coefficient of thermal expansion between the printed wiring board and the electrical element is large, mounting the two kinds of wiring boards in a stacked manner increases the choice of wiring board material, and between the printed wiring board and the electrical element. It is easy to reduce the generated thermal stress and further improve the mounting reliability.

  Hereinafter, the present invention will be described in detail with reference to the accompanying drawings showing embodiments. FIG. 1 shows a preferred application example of a divided multilayer wiring board according to the present invention, a package for housing a semiconductor element comprising a divided multilayer wiring board in which two multilayer wiring boards are connected to each other via a brazing material. It is a partially expanded sectional view for demonstrating the mounting structure.

  According to FIG. 1, it is important that the divided laminated wiring board of the present invention is formed by laminating two types of wiring boards, ie, the first wiring board 1 and the second wiring board 31. It is important that a capacitor is formed inside the first wiring board 1 having a larger dielectric constant than that of the wiring board 31.

  The first wiring board 1 is for mounting an electric element (not shown) such as a semiconductor element or an electric component on the first wiring board 1 on the surface of the laminated board 2 formed by laminating the insulating boards 2a to 2c. The semiconductor element mounting connection pads 3 are formed.

  A second wiring board mounting connection pad 4 is formed on the back surface (the surface opposite to the electric element mounting surface) of the first wiring board 1 and is electrically connected to the second wiring board 21. Further, a via-hole conductor 5 is provided inside the first wiring board 1 to electrically connect the semiconductor element mounting connection pads 3 and the second wiring board mounting connection pads 4.

  Further, a pair of capacitor electrodes 7a and 7b is provided inside the first wiring board 1, and the capacitor 7 is formed by the pair of capacitor electrodes 7a and 7b and the insulating substrate 2b sandwiched therebetween. ing.

  The second wiring board 31 has a first wiring board mounting connection pad 33 on one surface of a laminated board 32 formed by laminating insulating substrates 32a to 32c, and a printed wiring board mounting connection pad on the other surface. 34, the first wiring board mounting connection pad 33 is provided on the second wiring board mounting connection pad 4 of the first wiring board 1, and the printed wiring board mounting connection pad 34 is provided on the printed wiring board. It is electrically connected to the connected pad. Furthermore, a via-hole conductor 35 is provided inside the second wiring board 31 to electrically connect the first wiring board mounting connection pad 33 and the printed wiring board mounting connection pad 34. An internal wiring layer 36 is also formed inside the second wiring substrate 31.

  The first wiring board 1 and the second wiring board 31 are connected between the second wiring board mounting connection pads 4 and the first wiring board mounting connection pads 33 which are connection electrodes arranged to face each other. It is electrically connected through solder 101 which is a brazing material. In addition, the second wiring board 31 and the printed wiring board 51 are brazed between the printed wiring board mounting connection pads 34 and the connecting pads 53 of the printed wiring board, which are connecting electrodes arranged opposite to each other. Are electrically connected through the solder 102.

  Then, although not shown, flip chip mounting (primary mounting) is performed via solder on the connection electrodes formed on the back surface of the semiconductor element and the semiconductor element mounting connection pads 3 on the first wiring board surface 1. Electrically connected.

  The connection between the semiconductor element and the first wiring board, the first wiring board and the second wiring board, and the second wiring board and the printed wiring board is formed by solder balls in the BGA type package of FIG. However, other than this, it is also possible to form with a brazing agent.

  Further, an underfill agent or a potting agent containing at least an organic resin can be injected and cured in a part or all of these connecting portions. Thereby, since the stress relaxation effect by an organic resin generate | occur | produces, it becomes easy to obtain higher connection reliability. At that time, it is preferable to lower the Young's modulus of the resin in order to increase the stress relaxation effect and obtain higher connection reliability.

The printed wiring board 51 is made of, for example, an insulating material containing at least an organic resin, specifically, a glass-epoxy composite material, and generally has a linear thermal expansion coefficient of 14 to 20 × 10 ^{−6 at} 0 to 150 ° C. A printed wiring board at / ° C. is used, and connection pads 53 made of a metal conductor such as Cu, Au, Al, Ni, Pb—Sn are formed on the surface of the insulating substrate.

  In the divided laminated wiring board of the present invention, the capacitor 7 is formed on the first wiring board 1 by the capacitor electrodes 7a and 7b and the insulating board 2b sandwiched between them, and the dielectric constant of the first wiring board 1 is The dielectric constant of the second wiring board 31 is larger. With this configuration, the distance from the capacitor portion to the semiconductor element can be significantly shortened, so that the inductance component is reduced and power supply is stabilized.

  The capacitor electrodes 7a and 7b formed on the first wiring board 1 may be single, but if there is a margin in the limitation of the substrate thickness, a plurality of capacitors are formed as desired to increase the capacitance of the capacitors. be able to.

  2 to 4 are plan views showing the appearance of the first wiring board 1 shown in FIG. In addition, the same number is provided to the common site | part.

  According to FIG. 2, semiconductor element mounting connection pads are collectively formed as a semiconductor element mounting connection pad group in the central portion C of the surface of the first wiring board 1, Has a capacitor 7 formed therein.

  In FIG. 3, a semiconductor element mounting connection pad group is formed at the corner E of the surface of the first wiring board 1, and the capacitor 7 is formed inside the remaining portion A. Furthermore, as shown in FIG. 4, the capacitor 7 can be formed in the central portion C, and the semiconductor element mounting connection pad group can be formed around the capacitor 7.

  As shown in FIGS. 2 to 4, the semiconductor element mounting connection pads involved in the wiring are concentrated in one place, and the capacitor 7 is formed on the remaining surface, so that a wider area can be secured and a larger capacity can be secured. Obtainable.

  Although the semiconductor element mounting connection pads 3 may be integrated in one place as described above, they may be formed in a plurality of places in island shapes.

In the temperature range of 0 to 150 ° C., the thermal expansion coefficient of the first wiring board 1 is α ₁ , the thermal expansion coefficient of the second wiring board 31 is α ₂ , and the thermal expansion coefficient of the printed wiring board 51 is α ₃ . It is preferable to set so that 2.0 × 10 ⁻⁶ / ° C. <α ₁ <5.0 × 10 ⁻⁶ / ° C. <α ₂ <α ₃ . Thereby, the thermal stress generated by the difference in thermal expansion coefficient between the semiconductor element and the printed wiring board can be distributed to both the first wiring board and the second wiring board. Therefore, it is easy to alleviate the stress concentration on the semiconductor element, the divided laminated wiring board, and the connection portion thereof, and the connection reliability of the primary mounting and the secondary mounting can be further increased.

  In addition, the semiconductor element mounting connection pad 3, the second wiring board mounting connection pad 4, the internal wiring layer 53 of the second wiring board 31, the first wiring board mounting connection pad 33, and the print It is preferable that at least one of the wiring board mounting connection pads 34 contains copper, silver, or gold as a main component. This facilitates transmission of a high-speed signal with lower loss.

  In addition to these low-resistance metals, glass frit, crystalline fillers, and other metals are included as sintering regulators to suppress the warpage of the substrate and increase the adhesive strength in accordance with the shrinkage behavior with the insulating substrate. It is possible.

  When the second wiring board 31 uses a low-resistance metal such as copper, silver, or gold for the internal wiring layer 53 or the connection pads 33, 34, the low-temperature sinterability viewpoint that can be fired simultaneously with the insulating boards 32a-32d, Glass ceramic is preferable from the viewpoint of permitting adjustment of the dielectric constant and thermal expansion coefficient relatively freely. The component constituting the glass ceramic is preferably composed of glass having a softening point of 600 ° C. to 800 ° C. and a filler close to the desired characteristics as an insulating substrate.

  As the glass component, crystalline glass is desirable from the viewpoint of increasing strength, and amorphous glass is desirable from the viewpoint of improving sinterability and increasing the amount of filler. Generally, borosilicate glass containing an alkali metal oxide, an alkaline earth metal oxide, zinc oxide or the like is used. Examples of filler components include simple oxides and composite oxides selected from the group of alumina, silica, alkali metal oxides, alkaline earth metal oxides, titanium oxide, and the like. The type can be selected.

  For example, when a low dielectric constant is desired, silica, cordierite, and the like are suitable. When a high dielectric constant is desired, titanium oxide and a composite oxide containing the same are suitable. When low thermal expansion is desired, cordierite, mullite, gehlenite, diopsite, spodumene and steatite are suitable. Furthermore, when high thermal expansion is desired, quartz, forsterite, enstatite, garnite, lithium silicate and the like are suitable. It is also possible to select and blend a plurality of these components.

  An organic binder such as an acrylic resin, a plasticizer and a solvent are added to the glass / filler mixture thus selected to produce a slurry, which is then formed into a sheet by a doctor blade to obtain a green sheet. A through hole is formed in this green sheet by an NC punch, a mold, a laser processing machine, or the like, and a paste made of a low resistance metal such as copper, silver, or gold is filled to form a via hole conductor.

  Similarly, a wiring pattern is formed with a paste made of a low resistance metal.

  A plurality of green sheets on which the via conductors and patterns thus formed are stacked and pressed to obtain a laminate. The laminated body is held at a temperature at which the organic binder is scattered and the insulating substrate is not sintered, and the binder is removed. Thereafter, the insulating substrate and the conductor are simultaneously fired to obtain a wiring substrate.

  In particular, when copper is selected as the conductor material, after holding in a humidified nitrogen atmosphere at a temperature range of 600 to 800 for 1 to 5 hours, in a similar atmosphere at a temperature range of 850 to 1000 ° C. By maintaining the time, the insulating substrate and the conductor can be fired simultaneously. In addition, when silver or gold is selected as the conductor material, it is kept in the temperature range of 400 to 600 ° C. for 1 to 3 hours in the air, and then held in the same atmosphere at the temperature range of 850 to 1000 ° C. for 1 to 3 hours. By doing so, the insulating substrate and the conductor can be fired simultaneously.

  Here, the same manufacturing method as that of the second wiring board can be applied to the first wiring board.

  As described above in detail based on FIG. 1, in the present invention, even if other than the above example, the effect can be exhibited as long as it does not depart from the present invention, and the present invention is not limited to the above example. Absent. For example, in the above example, a semiconductor element mainly composed of silicon is used as the electric element, and flip chip mounting is adopted as the primary mounting. However, the electric element is not limited to a semiconductor element other than silicon or a semiconductor element. The above-described electric element material such as MEMS may be used, and a known mounting method using wire bonding mounting, various bumps, or the like can be selected according to the application.

  The divided laminated wiring board shown in FIG. 1 was produced as an evaluation board.

First, a first wiring board was produced. With respect to crystallized glass having a composition of SiO ₂ : Al ₂ O ₃ : MgO: ZnO: B ₂ O _{3 in} a ratio of 44: 29: 11: 7: 9, alumina is used as the first filler (filler 1). As a second filler (filler 2), cordierite, strontium titanate, and titania were added at a ratio shown in Table 1.

Next, a second wiring board was produced. SiO ₂ : Al ₂ O ₃ : CaO: BaO: B ₂ O ₃ is a silica as a first filler (filler 1) with respect to amorphous glass having a composition of 45: 10: 5: 35: 5. (SiO ₂ ) was added in the ratio shown in Table 1.

  These raw material powders were mixed, molded, and fired to produce a first wiring board having a thickness of 0.4 mm and a second wiring board having a thickness of 1 mm. Next, a Pb 36 mass% -Sn 64 mass% eutectic solder paste is printed by a printing method, a semiconductor element mounting connection pad, a second wiring board mounting connection pad, a first wiring board mounting connection pad, and a printed wiring board. A mounting connection pad was prepared. These connection pads were arranged in a matrix with a diameter of 0.13 mm and an electrode center distance of 0.23 mm.

  Each wiring board measured warpage with a three-dimensional measuring machine.

Further, the capacitance of the capacitor formed inside the first substrate was measured by a bridge circuit method using an LCR meter. The results are shown in Table 1.

  Sample No. of the present invention. In Nos. 1 to 4, the warp of the first wiring board was 60 μm or less, and the warp of the second wiring board was 40 μm. Further, the capacitance of each capacitor was 1 nF or more, which was almost the same as the comparative example described later.

(Comparative Example 1)
75 parts by weight of crystallized glass having a composition of SiO ₂ : Al ₂ O ₃ : MgO: ZnO: B ₂ O _{3 in} a ratio of 44: 29: 11: 7: 9, and alumina as a first filler (filler 1) 15 parts by weight, strontium titanate prepared in the proportion of 10 parts by weight as the second filler (filler 2), the raw material mixture to obtain a shaped green sheet G _a high-dielectric constant.

Further, 75 parts by weight of crystallized glass having a composition of SiO ₂ : Al ₂ O ₃ : MgO: ZnO: B ₂ O _{3 in} a ratio of 44: 29: 11: 7: 9, the first filler (filler 1) 20 parts by weight of alumina as, as the second filler (filler 2) to prepare a cordierite in an amount of 5 parts by weight, the raw material mixture, after molding, to obtain a green sheet G _B for a low dielectric constant.

Thereafter, the green sheet _{G A} and _{G B} and plural bonding calcination, the composite wiring board with a thickness of 1.4 mm (the inner 0.4mm is green sheet _{G A,} constituted the remainder 1mm is in the green sheet _{G B)} Was made.

  The capacitance of the capacitor was 3 nF, and the warp was 400 μm.

  The first wiring board and the second wiring board used in Example 1 were mounted in combination. A φ0.1 mm eutectic solder ball is placed on the first wiring board mounting connection pad of the second wiring board on which the solder is printed, and the first wiring board is positioned and placed thereon. A reflow treatment was performed to obtain a divided laminated wiring board.

Subsequently, a semiconductor device for evaluation having a thermal expansion coefficient of 2.5 × 10 ⁻⁶ / ° C. and a surface area of 100 mm ² at 0 to 150 ° C. having a porous insulating film mainly composed of silicon and having a low dielectric constant is prepared. Then, the semiconductor element was placed on the first wiring board through solder having a thickness of 0.1 mm, and the semiconductor element was flip-chip mounted.

Furthermore, a printed wiring board 5 having a thermal expansion coefficient of 16 × 10 ⁻⁶ / ° C. at 0 to 150 ° C. is prepared, a eutectic solder paste is printed on the surface by a printing method, and reflow treatment is performed to connect the connection pads. Formed. At that time, the connection pads were arranged in the same arrangement as the printed wiring board mounting connection pads of the second wiring board so that each connection pad was opposed to each printed wiring board mounting connection pad. The size of the connection pad was φ0.8 mm and the distance between the centers of the electrodes was 1.3 mm.

  Next, a divided multilayer wiring board in which a high-temperature solder ball of φ0.8 mm Pb 90 mass% -Sn 10 mass% is aligned and placed on the connection pad of the printed wiring board, and a semiconductor element is further mounted thereon. A semiconductor chip is divided by flip-chip mounting by placing it on the solder ball so that each connection pad faces the connection pad for mounting on each printed wiring board, and performing reflow processing again. Twenty evaluation samples in which a multilayer wiring board was mounted on a printed board were produced.

The sample for evaluation was subjected to a temperature cycle test in the temperature range of 0 to 100 ° C. up to 6000 cycles, and the disconnection of the junction was examined after every 500 cycles. It should be noted that, as the primary mounting evaluation, the presence / absence of disconnection of the solder joint connecting the silicon chip and the first wiring board is determined. The resistance value was measured for the presence / absence of disconnection of the joint, and the presence / absence of disconnection of the solder joint connecting the second wiring board and the printed circuit board as a secondary mounting evaluation. The resistance value was more than 20% larger than the initial resistance value. In case, it was judged as a disconnection. The above results are shown in Table 2.

  The divided multilayer wiring board of the present invention had durability of 2000 cycles or more for the primary mounting part, 2500 cycles or more for the multilayer wiring board part, and 3500 cycles or more for the secondary mounting part.

(Comparative Example 2)
A semiconductor element was mounted on the composite wiring board produced in Comparative Example 1 in the same manner as in Example 2. Then, this was mounted on a printed circuit board in the same manner as in Example 2 to obtain an evaluation sample. . Next, a temperature cycle test was conducted in the same manner as in Example 2. As a result, the primary mounting part was greatly warped, and the secondary mounting part was broken in 1500 cycles due to thermal stress.

It is a general | schematic fragmentary sectional view which shows the structure of the division | segmentation laminated wiring board of this invention. It is a top view of the division | segmentation laminated wiring board of this invention. It is a top view of the other division | segmentation laminated wiring board of this invention. It is a top view of the other division | segmentation laminated wiring board of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... 1st wiring board 2, 32 ... Laminated substrate 2a, 2b, 2c, 32a, 32b, 32c ... Insulating substrate 3 ... Connection pad 4 for semiconductor element mounting ... 2nd wiring Substrate mounting connection pad 5 ... via hole conductor 7 ... capacitor 7a, 7b ... capacitor electrode 31 ... second wiring substrate 33 ... first wiring substrate mounting connection pad 34 ... print Wiring board mounting connection pads 36 ... internal wiring layer 51 ... printed wiring board 53 ... connection pads 101, 102 ... solder A ... remaining part C ... central part E ... corner part S ... Peripheral part

Claims (3)

In a divided laminated wiring board formed by mounting the first wiring board on the second wiring board and further mounting the second wiring board on the printed wiring board, a capacitor is formed on the first wiring board, In addition, the divided wiring board is characterized in that the dielectric constant of the first wiring board is larger than the dielectric constant of the second wiring board. When the thermal expansion coefficient of the first wiring board at 0 to 150 ° C. is α ₁ , the thermal expansion coefficient of the second wiring board is α ₂ , and the thermal expansion coefficient of the printed wiring board is α ₃ , 2.0 _2. The divided multilayer wiring board according to claim 1, wherein x 10 ⁻⁶ / ° C. <α ₁ <5.0 × 10 ⁻⁶ / ° C. <α ₂ <α ₃ . 3. The divided laminated wiring board according to claim 1, wherein at least one wiring layer of the first and second wiring boards contains copper, silver, or gold as a main component.

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