JP2006196500A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2006196500A
JP2006196500A JP2005003626A JP2005003626A JP2006196500A JP 2006196500 A JP2006196500 A JP 2006196500A JP 2005003626 A JP2005003626 A JP 2005003626A JP 2005003626 A JP2005003626 A JP 2005003626A JP 2006196500 A JP2006196500 A JP 2006196500A
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external lead
semiconductor chip
semiconductor device
substrate
bonding
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Hirotaka Hama
宏高 浜
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Fuji Electric Co Ltd
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Fuji Electric Device Technology Co Ltd
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Priority to JP2005003626A priority Critical patent/JP2006196500A/en
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
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    • H01L2224/481—Disposition
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device where an input/output signal can be inputted/outputted from an arbitrary outer terminal without changing a design. <P>SOLUTION: The semiconductor device is provided with a conductive support substrate 1, a semiconductor chip 4 fixed to the substrate 1, an insulating substrate 6 which is fixed to the substrate 1 and to which components 10 (electric/electronic components) are fixed, an outer lead terminal 2, bonding wires 8 connecting bonding pads 7 formed on the substrate 6 and the terminal 2, and mold resin 12. A part of the outer lead terminal 2 is formed in such a way that it is confronted with one side of the substrate 6 on a connected bonding pad 7-side and it becomes parallel. Length L2 of the parallel part 3 of the outer lead terminal confronted with the bonding pads 7 is set to be longer than length L1 between both ends of the bonding pad 7. The bonding wires 8 are fixed to the parallel part 3 of the outer lead terminal so that they do not cross each other. Consequently, the input/output signal can be inputted/outputted from the arbitrary outer lead terminal without changing the design. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

この発明は、複数の外部導出端子を有する樹脂封止された半導体装置に関する。   The present invention relates to a resin-sealed semiconductor device having a plurality of external lead-out terminals.

自動車、農機具および芝刈機などの内燃機関（エンジン）に用いられる点火装置の一例をつぎに示す。
図８は、従来の点火装置の要部構成図である。磁石付きフライホイール７１（磁石がフライホイールの円周面に内蔵されている）と点火コイル７２の１次コイル７２ａとは磁気的に結合し、２次コイル７２ｂは点火プラグ７３と接続する。１次コイル７２ａおよび２次コイル７２ｂはパワートランジスタである半導体チップ４および制御回路７６と接続する。
また、制御回路７６は制御部を内蔵したＩＣチップ７５とトリガ回転数設定用の抵抗７４とで構成される。つぎに、この点火装置の動作を説明する。
フライホイール７１は内燃機関の出力回転数（ｒｐｍ）に連動して回転し、フライホイール７１の回転に応じて１次コイル７２ａに電圧が誘起される。制御回路７６は誘起された電圧により回転数を検知し、回転数が設定されたトリガ開始回転数以下の場合は、パワートランジスタ（半導体チップ４）を遮断状態または導通状態のいずれかに固定して、１次コイル７２ａの誘起電圧による電流の遮断を行わないように制御回路７６を設定する。回転数が設定されたトリガ開始回転数以上になると、パワートランジスタのオン、オフ制御が開始され、所定の位相でパワートランジスタの遮断が行われる。パワートランジスタの遮断時に１次コイル７２ａを介して２次コイル７２ｂに高電圧が発生し、点火プラグ７３の好適な高電圧が印加される。抵抗７４の値を変えると、トリガ開始回転数を変えることができ、抵抗７４の値を大きくするとトリガ開始回転数が高くなるように制御回路７６は設計されている。この制御回路７６とパワートランジスタとはモールド樹脂６２内に収納される。 An example of an ignition device used in an internal combustion engine (engine) such as an automobile, agricultural equipment, and lawn mower will be described below.
FIG. 8 is a main part configuration diagram of a conventional ignition device. The flywheel 71 with magnet (the magnet is built in the circumferential surface of the flywheel) and the primary coil 72 a of the ignition coil 72 are magnetically coupled, and the secondary coil 72 b is connected to the spark plug 73. The primary coil 72a and the secondary coil 72b are connected to the semiconductor chip 4 and the control circuit 76 which are power transistors.
The control circuit 76 includes an IC chip 75 with a built-in control unit and a trigger 74 setting resistor 74. Next, the operation of this ignition device will be described.
The flywheel 71 rotates in conjunction with the output rotation speed (rpm) of the internal combustion engine, and a voltage is induced in the primary coil 72 a according to the rotation of the flywheel 71. The control circuit 76 detects the number of revolutions by the induced voltage, and when the number of revolutions is equal to or less than the set trigger start number of revolutions, the power transistor (semiconductor chip 4) is fixed to either the cutoff state or the conduction state. The control circuit 76 is set so as not to cut off the current due to the induced voltage of the primary coil 72a. When the rotation speed is equal to or higher than the set trigger start rotation speed, on / off control of the power transistor is started, and the power transistor is shut off at a predetermined phase. When the power transistor is shut off, a high voltage is generated in the secondary coil 72b via the primary coil 72a, and a suitable high voltage of the spark plug 73 is applied. The control circuit 76 is designed so that the trigger start speed can be changed by changing the value of the resistor 74, and the trigger start speed is increased by increasing the value of the resistor 74. The control circuit 76 and the power transistor are accommodated in the mold resin 62.

尚、図中の６は導電パターン付き絶縁基板、７ａ〜７ｅは絶縁基板６上に形成されたボンディングパッド、５１は半導体チップ４と絶縁基板６を固着する導電支持基板、５２ａ〜５２ｅは外部導出端子である。
図９は、従来の半導体装置の構成図であり、同図（ａ）は要部平面図、同図（ｂ）は要部側面図である。図８のパワートランジスタ（半導体チップ４）と、制御回路を構成する抵抗７４やＩＣチップ７５などの部品１０を固着した導電パターン付きの絶縁基板６を導電支持基板５１に固着する。絶縁基板６のボンディングパッド１１と半導体チップ４のボンディングパッド５をボンディングワイヤ９で接続する。外部導出端子５２と絶縁基板６のボンディングパッド７（７ａ〜７ｅ）はボンディングワイヤ５８で接続する。導電支持基板５１、半導体チップ４、絶縁基板６、外部導出端子５２およびボンディングワイヤ９、５８をモールド樹脂６２で封止して固定する。 In the figure, 6 is an insulating substrate with a conductive pattern, 7a to 7e are bonding pads formed on the insulating substrate 6, 51 is a conductive support substrate for fixing the semiconductor chip 4 and the insulating substrate 6, and 52a to 52e are externally derived. Terminal.
9A and 9B are configuration diagrams of a conventional semiconductor device, in which FIG. 9A is a plan view of the main part and FIG. 9B is a side view of the main part. The power transistor (semiconductor chip 4) shown in FIG. 8 and the insulating substrate 6 with the conductive pattern to which the components 10 such as the resistor 74 and the IC chip 75 constituting the control circuit are fixed are fixed to the conductive support substrate 51. The bonding pads 11 of the insulating substrate 6 and the bonding pads 5 of the semiconductor chip 4 are connected by bonding wires 9. The external lead-out terminal 52 and the bonding pads 7 (7a to 7e) of the insulating substrate 6 are connected by bonding wires 58. The conductive support substrate 51, the semiconductor chip 4, the insulating substrate 6, the external lead-out terminal 52, and the bonding wires 9 and 58 are sealed and fixed with a mold resin 62.

前記の外部導出端子５２は、制御回路７６への入出力信号を入出力したり、パワートランジスタのエミッタ・コレクタ間の電圧を出力したりする。この外部導出端子５２は、顧客側の仕様で設計されるフライホイール７１や点火コイル７２や制御回路７６などと接続する。
尚、共通のパッケージに相互に絶縁された複数の半導体ダイ（半導体チップ）を装着した例が特許文献１に開示されている。
特開平４−２３３２６２号公報 第１図 The external lead-out terminal 52 inputs / outputs an input / output signal to / from the control circuit 76 and outputs a voltage between the emitter and collector of the power transistor. The external lead-out terminal 52 is connected to a flywheel 71, an ignition coil 72, a control circuit 76, and the like designed according to customer specifications.
An example in which a plurality of semiconductor dies (semiconductor chips) insulated from each other are mounted on a common package is disclosed in Patent Document 1.
JP-A-4-233262 FIG. 1

しかし、例えば、Ａという顧客は、図９のように、外部導出端子５２から入出力される信号を左側から、例えば、ａ、ｂ、ｃ、ｄ、ｅとする設計を行うものとする。また、Ｂという顧客は、図１０のように、外部導出端子５２から入出力される信号を左側から、例えば、ｃ、ａ、ｅ、ｄ、ｂとする設計を行うものとする。このように設計が顧客で異なるのは、顧客の設計思想がそれぞれで異なるためである。
このような場合、Ａの顧客の設計に対応する場合は、図９のように、ボンディングパッド７ａ、７ｂ、７ｃ、７ｄ、７ｅと外部導出端子２ａ、２ｂ、２ｃ、２ｄ、２ｅをボンディングワイヤ５８で配線する。この場合はボンディングワイヤ８同士は交叉せずに平行に配線できるので半導体装置として組み立てすることができる。
しかし、Ｂという顧客の設計に対応しようとした場合には、図１０のように、ボンディングワイヤ５８が交叉してしまいボンディングワイヤ５８を配線することがきなくなり、半導体装置として組み立てすることができない。 However, for example, as shown in FIG. 9, the customer A is assumed to design the signals input / output from the external lead-out terminal 52 from the left side, for example, a, b, c, d, e. Further, as shown in FIG. 10, the customer B is assumed to design the signals input / output from the external lead-out terminal 52 from the left side, for example, c, a, e, d, b. The design is different for each customer because the customer's design philosophy is different.
In such a case, when it corresponds to the design of the customer A, as shown in FIG. 9, the bonding pads 7a, 7b, 7c, 7d, 7e and the external lead-out terminals 2a, 2b, 2c, 2d, 2e are connected to the bonding wire 58. Wiring with. In this case, since the bonding wires 8 can be wired in parallel without crossing each other, the semiconductor device can be assembled.
However, when trying to cope with the design of the customer B, as shown in FIG. 10, the bonding wires 58 cross each other so that the bonding wires 58 cannot be wired and cannot be assembled as a semiconductor device.

Ｂの顧客に対応しようとすると、平行に配線できるようにボンディングパッド７ａ、７ｂ、７ｃ、７ｄ、７ｅに入出力する信号を変更する必要がでてくる。これは絶縁基板６の導電パターンを変更することになる。
つまり、顧客の設計に応じて、その都度、半導体装置の設計変更が必要となり、製造コストが増大し、リードタイム（製造時間で納期に関係する）が長くなってしまう。
この発明の目的は、前記の課題を解決して、設計変更することなく、入出力信号を任意の外部導出端子から入出力できる半導体装置を提供することにある。 In order to deal with the customer of B, it is necessary to change the signals inputted to and outputted from the bonding pads 7a, 7b, 7c, 7d, and 7e so that they can be wired in parallel. This changes the conductive pattern of the insulating substrate 6.
In other words, each time the design of the semiconductor device is changed according to the customer's design, the manufacturing cost increases, and the lead time (related to the delivery time in the manufacturing time) becomes longer.
An object of the present invention is to solve the above-described problems and provide a semiconductor device capable of inputting / outputting input / output signals from an arbitrary external lead-out terminal without changing the design.

前記の目的を達成するために、四角形の半導体チップと、該半導体チップを固着する四角形の導電支持基板と、複数の外部導出端子と、半導体チップと外部導出端子を接続するワイヤと、半導体チップを封止するモールド樹脂とを有する半導体装置において、前記複数の外部導出端子のうち少なくとも一部の外部導出端子の一部が導電支持基板の一辺と平行して配置される構成とする。
また、四角形の半導体チップと、電気部品が固着した導電パターンが形成された四角形の絶縁基板と、前記半導体チップと前記絶縁基板を固着する導電支持基板と、複数の外部導出端子と、半導体チップと外部導出端子を接続するワイヤと、前記半導体チップと前記絶縁基板を封止するモールド樹脂とを有する半導体装置において、前記複数の外部導出端子のうち少なくとも一部の外部導出端子の一部が導電支持基板の一辺と平行して配置される構成とする。 To achieve the above object, a rectangular semiconductor chip, a rectangular conductive support substrate for fixing the semiconductor chip, a plurality of external lead terminals, wires connecting the semiconductor chip and the external lead terminals, and a semiconductor chip are provided. In the semiconductor device having a mold resin to be sealed, at least some of the plurality of external lead terminals are arranged in parallel with one side of the conductive support substrate.
Further, a rectangular semiconductor chip, a rectangular insulating substrate on which a conductive pattern to which an electrical component is fixed is formed, a conductive support substrate that fixes the semiconductor chip and the insulating substrate, a plurality of external lead terminals, a semiconductor chip, In a semiconductor device having a wire for connecting an external lead terminal and a mold resin for sealing the semiconductor chip and the insulating substrate, at least some of the external lead terminals of the plurality of external lead terminals are electrically conductively supported. The configuration is arranged in parallel with one side of the substrate.

また、前記該平行に配置される箇所の外部導出端子の長さが、導電支持基板の一辺に形成される複数の第２ボンディングパッドの最も外側に配置された２つの第２ボンディングパッド間の長さ以上であるとよい。
また、前記半導体チップがリードフレームに固着されるとよい。
また、前記半導体チップと前記絶縁基板がリードフレームに固着されるとよい。 In addition, the length of the external lead-out terminal at the portion disposed in parallel is a length between two second bonding pads disposed on the outermost side of the plurality of second bonding pads formed on one side of the conductive support substrate. It is good if it is more than that.
The semiconductor chip may be fixed to a lead frame.
The semiconductor chip and the insulating substrate may be fixed to a lead frame.

この発明は、複数の外部導出端子のうち少なくとも一部の外部導出端子の一部を導電支持基板と平行に配置し、複数のボンディングパッドの両側に配置されるボンディングパッド間の長さより平行に配置された外部導出端子の長さを長くすることで、絶縁基板の導電パターンの設計変更なしで、入出力信号を任意の外部導出端子から入出力することができるようになる。
つまり、半導体装置の設計変更なしで、顧客の設計に対応できるので、低コストでリードタイムが短い半導体装置を提供することができる。 In the present invention, at least some of the plurality of external lead-out terminals are arranged in parallel with the conductive support substrate, and are arranged in parallel with the length between the bonding pads arranged on both sides of the plurality of bonding pads. By increasing the length of the externally derived terminal, input / output signals can be input / output from any externally derived terminal without changing the design of the conductive pattern of the insulating substrate.
In other words, since the design of the semiconductor device can be accommodated without changing the design of the semiconductor device, a semiconductor device with a low cost and a short lead time can be provided.

この発明の最良の形態を以下の実施例で説明する。   The best mode of the present invention will be described in the following examples.

図１は、この発明の第１実施例の半導体装置の構成図であり、同図（ａ）は要部平面図、同図（ｂ）は要部側面図である。この半導体装置は、導電支持基板１と、この導電支持基板１に固着した半導体チップ４と、この導電支持基板１に固着され、抵抗やＩＣチップなどの部品１０（電気・電子部品）を固着した導電パターン付き絶縁基板６と、外部導出端子２と、絶縁基板６上に形成したボンディングパッド７と外部導出端子２とを接続するボンディングワイヤ８と、これらを封止するモールド樹脂１２で構成される。尚、ＩＣチップと導電パターン月絶縁基板６との電気的接続はフェイスダウンボンディング（フリップチップ）もしくは図示しないワイヤボンディングにより行われる。外部導出端子２は５本の外部導出端子２ａ、２ｂ、２ｃ、２ｄ、２ｅから構成され、絶縁基板６上に形成されたボンディングパッド７は５個のボンディングパッド７ａ、７ｂ、７ｃ、７ｄ、７ｅで構成され、それぞれボンディングワイヤ８で接続する。この外部導出端子２の一部を、接続するボンディングパッド７側の絶縁基板６の一辺に対向し、且つ、平行になるように形成し、ボンディングパッド７と対向する外部導出端子の平行箇所３の長さＬ２を、ボンディングパッド７の両端の間の長さＬ１と同程度もしくはそれ以上の長さとする。長さＬ２は長さＬ１より短くてもよいが、望ましくはＬ２≧Ｌ１である。本実施例では長さＬ２を長さＬ１より長くする。この外部導出端子の平行箇所３にボンディングワイヤ８をそれぞれ交叉しないように固着する。   FIGS. 1A and 1B are configuration diagrams of a semiconductor device according to a first embodiment of the present invention, in which FIG. 1A is a plan view of the main part and FIG. 1B is a side view of the main part. This semiconductor device has a conductive support substrate 1, a semiconductor chip 4 fixed to the conductive support substrate 1, and a component 10 (electrical / electronic component) such as a resistor or an IC chip fixed to the conductive support substrate 1. An insulating substrate 6 with a conductive pattern, an external lead terminal 2, a bonding wire 8 connecting the bonding pad 7 formed on the insulating substrate 6 and the external lead terminal 2, and a mold resin 12 for sealing them. . The electrical connection between the IC chip and the conductive pattern lunar insulating substrate 6 is performed by face-down bonding (flip chip) or wire bonding (not shown). The external lead-out terminal 2 is composed of five external lead-out terminals 2a, 2b, 2c, 2d and 2e, and the bonding pad 7 formed on the insulating substrate 6 has five bonding pads 7a, 7b, 7c, 7d and 7e. These are connected by bonding wires 8 respectively. A part of the external lead-out terminal 2 is formed so as to face and be parallel to one side of the insulating substrate 6 on the bonding pad 7 side to be connected. The length L2 is set to the same length as or more than the length L1 between both ends of the bonding pad 7. The length L2 may be shorter than the length L1, but preferably L2 ≧ L1. In this embodiment, the length L2 is longer than the length L1. Bonding wires 8 are fixed to the parallel portions 3 of the external lead terminals so as not to cross each other.

例えば、ボンディングパッド７ａ、７ｂ、７ｃ、７ｄ、７ｅからの入出力信号を左側からａ、ｂ、ｃ、ｄ、ｅとしたとき、顧客の設計で外部導出端子２ａ、２ｂ、２ｃ、２ｄ、２ｅからそれぞれ入出力する入出力信号をｃ、ａ、ｅ、ｄ、ｂとした場合（これはすなわち、図１０に示すように従来の半導体装置では対応不可能な場合である）、図１のように、ボンディングパッド７ａと外部導出端子２ｂ、ボンディングパッド７ｂと外部導出端子２ｅ、ボンディングパッド７ｃと外部導出端子２ａ、ボンディングパッド７ｄと外部導出端子２ｄ、ボンディングパッド７ｅと外部導出端子２ｃをそれぞれボンディングワイヤ８で接続すると、顧客の要求する位置の外部導出端子から顧客が要求する入出力信号を入出力させることができる。また、ボンディングワイヤ８を外部導出端子の平行箇所３に固着するので、ボンディングワイヤ８は互いに交叉することなく平行に配線することができる。つまり、ボンディングワイヤ８を固着する外部導出端子２を平行箇所３で変えるだけで、顧客の要求する位置の外部導出端子から顧客が要求する入出力信号を入出力させることができる。   For example, when the input / output signals from the bonding pads 7a, 7b, 7c, 7d, and 7e are a, b, c, d, and e from the left side, the external lead terminals 2a, 2b, 2c, 2d, and 2e are designed according to the customer's design. As shown in FIG. 1, when the input / output signals to be input / output from c are a, c, a, e, d, and b (that is, the conventional semiconductor device cannot cope with them as shown in FIG. 10). Bonding pad 7a and external lead-out terminal 2b, bonding pad 7b and external lead-out terminal 2e, bonding pad 7c and external lead-out terminal 2a, bonding pad 7d and external lead-out terminal 2d, bonding pad 7e and external lead-out terminal 2c are bonded to the bonding wires, respectively. When connected at 8, the input / output signal requested by the customer can be input / output from the external lead-out terminal at the position requested by the customer. Moreover, since the bonding wire 8 is fixed to the parallel portion 3 of the external lead-out terminal, the bonding wire 8 can be wired in parallel without crossing each other. That is, the input / output signal requested by the customer can be input / output from the external derived terminal at the position requested by the customer only by changing the external derived terminal 2 to which the bonding wire 8 is fixed at the parallel portion 3.

このように、外部導出端子の平行箇所３にボンディングワイヤ８を固着することで、絶縁基板６の導電パターンの設計変更なしで、顧客が要求する位置の外部導出端子から顧客が要求する任意の入出力信号を入出力することができるので、低コストで、リードタイムの短い半導体装置を提供することができる。
前記の外部導出端子２は、図１では導電支持基板１の一辺に対向するように形成されているが、必要に応じて、二辺から四辺に対向するように外部導出端子２を形成し、外部導出端子２をモールド樹脂１２の根元で直角に折り曲げて、ＩＣのパッケージのようにしてもよい。
尚、図中の１１は、半導体チップ４に形成したボンディングパッド５とボンディングワイヤ９で接続する絶縁基板６に形成したボンディングパッドである。 In this way, by fixing the bonding wire 8 to the parallel portion 3 of the external lead-out terminal, any input requested by the customer from the external lead-out terminal at the position requested by the customer can be made without changing the design of the conductive pattern of the insulating substrate 6. Since output signals can be input and output, a semiconductor device with low cost and short lead time can be provided.
The external lead-out terminal 2 is formed so as to face one side of the conductive support substrate 1 in FIG. 1, but if necessary, the external lead-out terminal 2 is formed so as to face two sides to four sides. The external lead-out terminal 2 may be bent at a right angle at the base of the mold resin 12 to form an IC package.
In the figure, reference numeral 11 denotes a bonding pad formed on the insulating substrate 6 connected to the bonding pad 5 formed on the semiconductor chip 4 and the bonding wire 9.

つぎに、この半導体装置の製造方法について説明する。
図２から図６は、図１の半導体装置の製造方法を示す図であり、工程順に示した要部製造工程平面図である。
平行箇所３のある外部導出端子となる箇所２３と導電支持基板１を有するリードフレーム２０を形成する。リ−ドフレーム２０は、枠板２１および接続板２２により導電支持基板１および外部導出端子となる箇所２３が互いに接続し、一体となっている（図２）。
つぎに、リードフレーム２０の導電支持基板１上に半導体チップ４と部品１０が固着された導電パターン付き絶縁基板６を固着する（図３）。
つぎに、外部導出端子となる箇所２３の平行箇所３と絶縁基板６に形成されたボンディングパッド７ａ〜７ｅおよび半導体チップ４と絶縁基板６に形成されたボンディングパッド１１とをボンディングワイヤ８、９でそれぞれ接続する。このとき、ボンディングワイヤ８同士が交叉しないように平行になるようにする（図４）。 Next, a method for manufacturing this semiconductor device will be described.
2 to 6 are views showing a method of manufacturing the semiconductor device of FIG. 1, and are main part manufacturing process plan views shown in the order of steps.
A lead frame 20 having a portion 23 serving as an external lead terminal having the parallel portion 3 and the conductive support substrate 1 is formed. In the lead frame 20, the conductive support substrate 1 and the portion 23 serving as the external lead-out terminal are connected to each other by the frame plate 21 and the connection plate 22 (FIG. 2).
Next, the insulating substrate 6 with the conductive pattern to which the semiconductor chip 4 and the component 10 are fixed is fixed on the conductive support substrate 1 of the lead frame 20 (FIG. 3).
Next, the parallel part 3 of the part 23 serving as an external lead terminal, the bonding pads 7a to 7e formed on the insulating substrate 6 and the bonding pad 11 formed on the semiconductor chip 4 and the insulating substrate 6 are bonded with bonding wires 8 and 9. Connect each one. At this time, the bonding wires 8 are made parallel so as not to cross each other (FIG. 4).

つぎに、導電支持基板１、半導体チップ４、絶縁基板６、外部導出端子となる箇所２３の平行箇所３およびボンディングワイヤ８、９などをモールド樹脂１２で封止する（図５）。
つぎに、外部導出端子となる箇所２３同士を接続している接続板２２と枠板２１を図５の切断線２４で切り離して外部導出端子２（２ａ〜２ｅ）を形成して、半導体装置が完成する（図６）。 Next, the conductive support substrate 1, the semiconductor chip 4, the insulating substrate 6, the parallel portion 3 of the portion 23 serving as the external lead-out terminal, the bonding wires 8, 9 and the like are sealed with the mold resin 12 (FIG. 5).
Next, the connection plate 22 and the frame plate 21 that connect the portions 23 to be the external lead-out terminals are separated by the cutting line 24 in FIG. 5 to form the external lead-out terminals 2 (2a to 2e). Completed (FIG. 6).

図７は、この発明の第２実施例の半導体装置の構成図であり、同図（ａ）は要部平面図、同図（ｂ）は要部側面図である。図１との違いは、導電支持基板１上に絶縁基板６が固着されず半導体チップ１３のみ固着している点である。半導体チップ１３上に形成されたボンディングパッド１４（１４ａ〜１４ｅ）と外部導出端子２（２ａ〜２ｅ）の平行箇所３とがボンディングワイヤ８で接続され、外部導出端子の平行箇所３の長さＬ２がボンディングパッドの両端の長さＬ３より長くする。こうすることで、図１と同様の効果を得ることができる。
尚、必ずしも全ての外部導出端子に平行箇所３を設けなくてもよい。例えば、ある辺にモンディングパッドが１つしかない場合、そのボンディングパッドに対応する外部導出端子に平行箇所を設けても、本発明の効果は得られない。 FIGS. 7A and 7B are configuration diagrams of a semiconductor device according to a second embodiment of the present invention, in which FIG. 7A is a plan view of the main part and FIG. 7B is a side view of the main part. The difference from FIG. 1 is that the insulating substrate 6 is not fixed on the conductive support substrate 1 and only the semiconductor chip 13 is fixed. The bonding pads 14 (14a to 14e) formed on the semiconductor chip 13 and the parallel part 3 of the external lead-out terminal 2 (2a to 2e) are connected by the bonding wire 8, and the length L2 of the parallel part 3 of the external lead-out terminal Is longer than the length L3 at both ends of the bonding pad. By doing so, the same effect as in FIG. 1 can be obtained.
It is not always necessary to provide the parallel portions 3 for all the external lead-out terminals. For example, when there is only one mondding pad on a certain side, the effect of the present invention cannot be obtained even if a parallel portion is provided on the external lead-out terminal corresponding to the bonding pad.

この発明の第１実施例の半導体装置の構成図であり、（ａ）は要部平面図、（ｂ）は要部側面図BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram of the semiconductor device of 1st Example of this invention, (a) is a principal part top view, (b) is a principal part side view. 図１の半導体装置の要部製造工程平面図FIG. 1 is a plan view of a main part manufacturing process of the semiconductor device of FIG. 図２に続く、図１の半導体装置の要部製造工程平面図FIG. 2 is a plan view of the main part manufacturing process of the semiconductor device of FIG. 図３に続く、図１の半導体装置の要部製造工程平面図FIG. 3 is a plan view of the main part manufacturing process of the semiconductor device of FIG. 図４に続く、図１の半導体装置の要部製造工程平面図FIG. 4 is a plan view of the main part manufacturing process of the semiconductor device of FIG. 図５に続く、図１の半導体装置の要部製造工程平面図FIG. 5 is a plan view of the main part manufacturing process of the semiconductor device of FIG. この発明の第２実施例の半導体装置の構成図であり、（ａ）は要部平面図、（ｂ）は要部側面図It is a block diagram of the semiconductor device of 2nd Example of this invention, (a) is a principal part top view, (b) is a principal part side view. 従来の点火装置の要部構成図Main part configuration diagram of conventional ignition device 従来の半導体装置の構成図であり、（ａ）は要部平面図、（ｂ）は要部側面図2A and 2B are configuration diagrams of a conventional semiconductor device, in which FIG. 図９のボンディングワイヤが交叉する場合の要部平面図Fig. 9 is a plan view of the main part when the bonding wires of Fig. 9 cross each other.

符号の説明Explanation of symbols

１ 導電支持基板
２、２ａ〜２ｅ 外部導出端子
３ 平行箇所 ４、１３ 半導体チップ
５、１４、１４ａ〜１４ｅ ボンディングパッド（半導体チップ上）
６ 導電パターン付き絶縁基板
７、７ａ〜７ｅ、１１ ボンディングパッド（絶縁基板上）
８、９ ボンディングワイヤ
１０ 部品
１２ モールド樹脂
２０ リードフレーム
２１ 枠板
２２ 接続板
２３ 外部導出端子となる箇所
２４ 切断線 DESCRIPTION OF SYMBOLS 1 Conductive support board 2, 2a-2e External lead-out terminal 3 Parallel location 4, 13 Semiconductor chip 5, 14, 14a-14e Bonding pad (on semiconductor chip)
6 Insulating substrate with conductive pattern 7, 7a to 7e, 11 Bonding pad (on insulating substrate)
8, 9 Bonding wire 10 Parts 12 Mold resin 20 Lead frame 21 Frame plate 22 Connection plate 23 Location to be an external lead terminal 24 Cutting line

Claims (5)

四角形の半導体チップと、該半導体チップを固着する四角形の導電支持基板と、複数の外部導出端子と、半導体チップと外部導出端子を接続するワイヤと、半導体チップを封止するモールド樹脂とを有する半導体装置において、
前記複数の外部導出端子のうち少なくとも一部の外部導出端子の一部が導電支持基板の一辺と平行して配置されることを特徴とする半導体装置。 A semiconductor having a rectangular semiconductor chip, a rectangular conductive support substrate for fixing the semiconductor chip, a plurality of external lead terminals, wires connecting the semiconductor chip and the external lead terminals, and a mold resin for sealing the semiconductor chip In the device
A semiconductor device, wherein at least some of the plurality of external lead-out terminals are arranged in parallel with one side of the conductive support substrate. 四角形の半導体チップと、電気部品が固着した導電パターンが形成された四角形の絶縁基板と、前記半導体チップと前記絶縁基板を固着する導電支持基板と、複数の外部導出端子と、半導体チップと外部導出端子を接続するワイヤと、前記半導体チップと前記絶縁基板を封止するモールド樹脂とを有する半導体装置において、
前記複数の外部導出端子のうち少なくとも一部の外部導出端子の一部が導電支持基板の一辺と平行して配置されることを特徴とする半導体装置。 A rectangular semiconductor chip, a rectangular insulating substrate on which a conductive pattern to which electrical components are fixed is formed, a conductive support substrate for fixing the semiconductor chip and the insulating substrate, a plurality of external lead terminals, a semiconductor chip and an external lead In a semiconductor device having a wire for connecting a terminal, and a mold resin for sealing the semiconductor chip and the insulating substrate,
A semiconductor device, wherein at least some of the plurality of external lead-out terminals are arranged in parallel with one side of the conductive support substrate. 前記該平行に配置される箇所の外部導出端子の長さが、導電支持基板の一辺に形成される複数の第２ボンディングパッドの最も外側に配置された２つの第２ボンディングパッド間の長さ以上であることを特徴とする請求項１または２に記載の半導体装置。 The length of the external lead-out terminal at the portion disposed in parallel is greater than or equal to the length between the two second bonding pads disposed on the outermost side of the plurality of second bonding pads formed on one side of the conductive support substrate. The semiconductor device according to claim 1, wherein: 前記半導体チップがリードフレームに固着されることを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the semiconductor chip is fixed to a lead frame. 前記半導体チップと前記絶縁基板がリードフレームに固着されることを特徴とする請求項２に記載の半導体装置。 The semiconductor device according to claim 2, wherein the semiconductor chip and the insulating substrate are fixed to a lead frame.
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Publication number Priority date Publication date Assignee Title
CN118335526A (en) * 2024-06-14 2024-07-12 永锦电容器有限公司 Capacitor and method for improving current-carrying strength of connection between capacitor terminal and core

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118335526A (en) * 2024-06-14 2024-07-12 永锦电容器有限公司 Capacitor and method for improving current-carrying strength of connection between capacitor terminal and core

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