JP2006186546A - Semiconductor device and method of designing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology which optimizes a semiconductor device using a programmable device with a shipping configuration as not prototype but a product. <P>SOLUTION: The semiconductor device which has a plurality of the semiconductor devices on a package substrate includes, as at least one semiconductor device, the programmable device (3) which makes variable a logical function by many logic elements according to definition data held by a rewritable memory circuit; and has a synchronous DRAM (7) as one of the other semiconductor devices. The synchronous DRAM is planely arranged or stack arranged adjacent to the programmable device, and the logic function which becomes the access principal of the above synchronous DRAM is chiefly assigned to the programmable device. When the accessing function over the synchronous DRAM is chiefly assigned to the programmable device, it is optimized in respect of a high-speed access. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technique using a programmable device in which a plurality of semiconductor devices are provided on a package substrate, and a logic function of a large number of logic elements is variable according to definition data held by a rewritable memory circuit as at least one semiconductor device. For example, the present invention relates to a technique that is effective when applied to the development of a SIP (System In Package) semiconductor device equipped with an FPGA (Field Programmable Gate Array).

  A technique for configuring a semiconductor device by mounting a programmable device such as FPGA and other semiconductor devices on a high-density mounting substrate is described in Patent Document 1 and the like. Further, Patent Document 2 describes that a desired logic function is achieved by a rewritable programmable logic regarding the system configuration or architecture in such a semiconductor device.

Japanese Patent Laid-Open No. 2-83576 JP-A-11-40739

  The inventor has studied a semiconductor device on which a programmable device such as an FPGA and other semiconductor devices are mounted. In particular, the present inventor examined not using a prototype in a development stage but using a programmable device such as an FPGA in a shipment form as a product. When the FPGA is used in the prototype, the FPGA is realized as an ASIC in the final form. However, when a programmable device such as an FPGA is used in the shipment form, it is necessary to optimize the logic function setting itself for the FPGA. Was found by the inventors. For example, it is considered necessary to optimize the target application applied to the FPGA, optimize the performance of the entire system, and optimize the test form.

  An object of the present invention is to provide a technique for optimizing a semiconductor device having a programmable device in a shipment form as a product, not as a prototype.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] A semiconductor device provided with a plurality of semiconductor devices on a package substrate includes a programmable device in which logic functions of a large number of logic elements are variable according to definition data held by a rewritable memory circuit as at least one semiconductor device. A synchronous DRAM as one of the other semiconductor devices, the synchronous DRAM is placed horizontally or stacked adjacent to the programmable device, and the logical function that is the main access to the synchronous DRAM is provided in the programmable device. Assigned. When the access function for the synchronous DRAM is exclusively assigned to the programmable device, it is optimized in terms of high-speed access.

  In the above, an electrically rewritable nonvolatile memory is provided as another semiconductor device, and the definition data is transferred from the nonvolatile memory to a programmable device. Consider the case where the storage circuit is volatile.

  A plurality of the programmable devices are provided, and the memory circuits of some programmable devices are electrically rewritable nonvolatile, and the memory circuits of the remaining programmable devices are electrically rewritable volatile. The optimization that the circuit type of the memory circuit is determined from the viewpoint of the power consumption by the memory circuit and the operability of the function setting is achieved.

  Another one of the other semiconductor devices includes a processing device, and the processing device includes a non-volatile memory that is electrically writable with a central processing unit, and the central processing unit receives the definition data from the non-volatile memory. Internally transferred to the memory circuit. Consideration is being given to the use of processing devices with built-in nonvolatile memory.

  In a semiconductor device provided with a plurality of semiconductor devices on a package substrate, the package substrate has a ball grid array that is concentrically wound in a plurality of rows as an external connection electrode, and the external connection electrode near the outer peripheral edge of the ball grid array A connection with a semiconductor device having a high use frequency is assigned, and a connection with a semiconductor device with a low use frequency is assigned to an external connection electrode near the inner periphery of the ball grid array. Since the wiring on the mounting substrate on which the semiconductor device is mounted is shorter when it is connected to the external connection electrode near the outer peripheral edge of the ball grid array, the load caused by wiring routing is small. Optimization can be achieved in that high processing performance is obtained by reducing the load on the wiring to which a frequently used device is connected.

  In a semiconductor device provided with a plurality of semiconductor devices on a package substrate, the package substrate has a ball grid array that is concentrically circulated in a plurality of rows as external connection electrodes, and is assigned to a connection with a frequently used semiconductor device The number of external connection terminals for use is made larger than the number of signal external connection terminals assigned to connection with a semiconductor device that is not frequently used. The limited number of external terminal assignments is optimized.

  A programmable device whose logic function by a large number of logic elements is variable according to definition data held by a rewritable memory circuit includes a plurality of first external terminals for mounting on a package substrate, and a semiconductor device separate from the programmable device And a plurality of second external terminals used for mounting in a stacked state, and the plurality of second external terminals have an arrangement located on three sides of the rectangle. In most cases, the external terminals of the memory are arranged at the center of the device along the two opposite sides of the device or along the long side of the device, and the address and data terminals of the microcomputer are at most three rectangular sides. In addition, since it is only straddling, when stacking a programmable device and a memory or a microcomputer, optimization is achieved in terms of easy connection between terminals.

  In a semiconductor device comprising a programmable device whose logic function by a large number of logic elements can be changed according to definition data held by a rewritable memory circuit and a processing device having a central processing unit, the programmable device has an arithmetic processing function The control device is assigned a control function for the arithmetic processing function of the programmable device. As a result, the user can set image processing, audio processing, communication processing, encryption / decryption processing, and the like in the programmable device, and in that case, user-designed assets can be applied to function settings for them. Utilize design assets. The processing device only needs to perform a control function such as an initial setting for the arithmetic processing function set in the programmable device, and the occurrence of a situation in which the load on the processing device becomes extremely large in the specific processing is suppressed. In this way, optimization is achieved in terms of utilization of design assets owned by the user and variation in processing device load. A user means a person who manufactures an electronic device using a semiconductor device.

  In a semiconductor device comprising a programmable device whose logic function by a large number of logic elements can be changed according to definition data held by a rewritable memory circuit, and a memory, the memory is bused to a bus realized in the programmable device. Connected. When the bus connected to the memory is configured in the programmable device, the bus configuration becomes programmable. Therefore, the correspondence is possible regardless of the interface specification of the memory connected to the programmable device and the bus interface specification of other devices. It is easy, and it becomes easy to cope with future specification changes. Optimized in terms of bus connection diversity. A user who has trouble creating function determination data for determining the bus configuration by the programmable device may adopt a configuration in which a bus is formed on the package substrate, but the bus configuration is fixed.

  The external input / output interface is preferably realized by the programmable device. It is possible to flexibly cope with changes in external input / output interface specifications and changes in connected external input / output circuits.

  A semiconductor device having a plurality of semiconductor devices on a package substrate includes, as at least one semiconductor device, a programmable device in which logic functions of a large number of logic elements can be changed according to definition data held by a rewritable memory circuit. A memory device as one semiconductor device, and a processing device having a central processing unit as another semiconductor device, and the programmable device is tested by the processing device, and the memory device test is the programmable device The processing device uses a built-in self-test circuit implemented in the device. It can contribute to the optimization of the test.

  In an electronic apparatus in which a semiconductor device including a plurality of semiconductor devices is mounted on a package substrate, the semiconductor device has at least one semiconductor device having a logic function by a large number of logic elements according to definition data held by a rewritable memory circuit. The electronic device includes a programmable device that is variable, and has a communication port that receives the definition data from the outside. It becomes easy to handle definition data version upgrades or bug fixes.

  [2] In a method for designing a semiconductor device in which a plurality of semiconductor devices are mounted on a package substrate, as at least one semiconductor device, a logic function by a large number of logic elements is made variable according to definition data held by a rewritable memory circuit. In accordance with the function assigned to the programmable device, a variation (modified form) is selectively used, a synchronous DRAM is used as one of the other semiconductor devices, and the synchronous DRAM is accessed. When assigning the main logic function to the programmable device, as the selectable variation, a first variation in which the synchronous DRAM is horizontally disposed adjacent to the programmable device, and the program A second variation in which a mable device and the synchronous DRAM are stacked and an electrically rewritable nonvolatile memory is used as another semiconductor device, and the definition is changed from the nonvolatile memory to the programmable device. A third variation that enables internal transfer of data is prepared. When the access function for the synchronous DRAM is exclusively assigned to the programmable device, it is possible to optimize the point of high-speed access to the SDRAM. The third variation is a variation to cope with the case where the memory circuit is volatile.

  A fourth variation is prepared in which a plurality of programmable devices are used, the memory circuits of some programmable devices are electrically rewritable and non-volatile, and the remaining memory circuits of programmable devices are electrically rewritable and volatile. Has been. From the viewpoints of power consumption by the memory circuit and operability of function setting, it is a variation that makes it possible to optimize the circuit format of the memory circuit.

  When another processing device is used as another semiconductor device, and the processing device includes a central processing unit and an electrically writable nonvolatile memory, the central processing unit receives the definition data from the nonvolatile memory. A fifth variation for enabling internal transfer to the storage circuit is prepared. This is a variation when optimizing in terms of the use of a processing device incorporating a non-volatile memory.

  The package substrate has a ball grid array that is concentrically circulated in multiple rows as external connection electrodes, and the external connection electrodes near the outer periphery of the ball grid array are allocated for connection to frequently used semiconductor devices. The external connection electrode near the inner periphery of the array is provided with a sixth variation that is assigned to connection with a semiconductor device that is less frequently used. Since the wiring on the mounting substrate on which the semiconductor device is mounted is shorter when it is connected to the external connection electrode near the outer peripheral edge of the ball grid array, the load caused by wiring routing is small. This is a variation for optimizing that high processing performance is obtained by reducing the load on the wiring to which a frequently used device is connected.

  The package substrate has a ball grid array that is concentrically wound in a plurality of rows as external connection electrodes, and the number of external connection terminals for signals assigned to connection to semiconductor devices that are frequently used is reduced. A seventh variation is prepared in which the number of external connection terminals for signals allocated to connection with a device is increased. This is a variation for optimizing the allocation of external terminals with a limited number.

  The programmable device has a plurality of first external terminals for mounting on the package substrate, and a plurality of second external terminals used for mounting another semiconductor device on the programmable device in a stacked state. An eighth variation is provided in which a plurality of second external terminals are arranged on three sides of a rectangle. The arrangement of the external terminals of the memory is almost the center of the device along the two opposite sides of the device or the longitudinal side of the device, and the address and data terminals of the microcomputer extend over three sides of the rectangle at the maximum. Therefore, when stacking a programmable device and a memory or a microcomputer, it is a variation for optimization in terms of easy connection between terminals.

  When the arithmetic processing function is realized in the programmable device, a ninth variation for assigning a control function for the arithmetic processing function of the programmable device is prepared in the processing device. This is a variation for optimization in terms of utilization of assets owned by the user and variation in processing device load.

  A tenth variation is provided in which a bus is realized in the programmable device, and the bus can be connected to the bus by another semiconductor. This is a variation for optimization in terms of diversity of bus connections.

  An eleventh variation for assigning an external input / output interface function to the programmable device is prepared. This is a variation for enabling flexible handling of changes in external input / output interface specifications and changes in connected external input / output circuits.

  A twelfth variation is prepared in which the processing of the programmable device is performed by the processing device, and the testing of the memory device is performed by the processing device using a built-in self-test circuit implemented in the programmable device. This is a variation for optimizing the mass production test of the semiconductor device.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to contribute to optimization of a semiconductor device using a programmable device in a shipment form as a product instead of a prototype.

  Here, a method for developing a SIP (System In Package) semiconductor device and a typical form of the semiconductor device developed thereby will be described. The semiconductor device uses an FPGA (Field Programmable Gate Array) as a programmable device in which the logic functions of a large number of logic elements are variable according to definition data held by a rewritable memory circuit as at least one semiconductor device. By using a PLD (Programmable Logic Device) as a similar programmable device, it is possible to realize the same function as when an FPGA is used. In developing a semiconductor device, various variations are selectively used according to the function assigned to the programmable device. The basic variation is a chip arrangement. For example, in FIG. 1, a semiconductor device 1 includes a package substrate 2, an FPGA 3, a microprocessing unit (MPU) 4, a programmable ROM (PROM) 5, a flash memory (FLASH) 6, a synchronous DRAM (SDRAM) 7, and other devices. 8 has.

  The FPGA 3 is one of programmable devices, and includes a rewritable memory circuit and a number of logic elements whose logic functions are variable according to definition data held in the memory circuit. The logic element includes, for example, an AND gate, an OR gate, a flip-flop, and an arithmetic logic unit. Adjacent logic elements are connected to each other by a signal line. A connection form of signal lines between the logic elements, a signal line inside the logic element. The connection form can be determined programmably by the definition data. This makes it possible to form a desired bus function, arithmetic processing function, storage function, and the like in the FPGA 3. Some of the memory circuits are nonvolatile or volatile.

  The microprocessing unit 4 includes peripheral circuits such as a central processing unit (CPU) that executes instructions, a work RAM, a program memory, and a timer of the central processing unit.

  Both the PROM 5 and the FLASH 6 are electrically rewritable nonvolatile memories. The PROM 5 is a non-volatile memory such as an EEPROM, and can be rewritten by random access, and is suitable for applications in which rewriting is frequently performed during data processing by the CPU. The FLASH 6 can be rewritten in a relatively large unit such as a sector and is suitable for storing a program or the like. The SDRAM 7 is a high-speed accessible DRAM that operates synchronously with a clock signal. The SDRAM 7 may be a single data rate SDRAM, a double data rate SDRAM, or an SDRAM having other data transfer functions. It is not limited to the memory PROM or FLASH, but may be composed of other memories such as SRAM.

  The other device 8 may be a semiconductor device having any function such as an analog semiconductor device such as ADC / DAC, a high-frequency semiconductor device such as RF, and a high voltage semiconductor device such as a power IC.

  In addition, the semiconductor device not only includes all the semiconductor devices shown in FIG. 1 as a single semiconductor device, but also includes at least one programmable device and another semiconductor device. Good.

  In developing a semiconductor device, attention is paid to a physical configuration and a functional system configuration. In the design of the physical configuration, variations relating to chip arrangement and pin arrangement are prepared. In the design of a functional system configuration, variations related to function classification, application model, test method, and function definition are prepared.

《Chip Arrangement》
The basic variation is a chip arrangement. In FIG. 1, first to fifth mounting forms are prepared and selectable as mounting forms of semiconductor devices. In the first mounting form, a large number of ball electrodes are arranged as a ball grid array on the bottom surface side of the package substrate 2 formed of a build-up substrate, a semiconductor device is mounted on the surface layer of the substrate, and the semiconductor device and the ball are bonded by wire bonding. It is configured to take electrical continuity with the electrode (Wire Bonding + BGA). In the second mounting form, a plurality of semiconductor devices are stacked on a package substrate, and wire bonding is used for connection to the ball electrode (Stack BGA). The third mounting form is a form using a flip chip as a semiconductor device (Flip Chip). The fourth implementation form is an implementation form using a QFP package (QFP SIP). The fifth mounting form is a mounting form in which two semiconductor devices that have been made into SIP are stacked (PKG on PKG SIP).

  FIG. 2 shows yet another variation of the implementation. (A) illustrates a case where 4 chips are horizontally placed, and (B) illustrates a case where a 3 chips structure is selected. Here, a logical function that becomes an access subject of the synchronous DRAM 7 is assigned to the FPGA 3, and the SDRAM 7 is arranged adjacent to the FPGA 3. The mounting form may be either flat or stacked as shown in FIG. In short, it may be a first variation in which the SDRAM 7 is disposed horizontally adjacent to the FPGA 3 or a second variation in which the FPGA 3 and the SDRAM 7 are stacked. By appropriately using these variations, when the access function for the SDRAM 7 is exclusively assigned to the programmable device, optimization in terms of high-speed access becomes possible.

  FIG. 2C illustrates a case where a two-chip two-layer stack configuration is selected, and FIG. 2D illustrates a case where a three-chip three-layer stack configuration is selected. Considering that the memory circuit of the FPGA 3 may be volatile, a third variation for enabling the internal transfer of the definition data from the stacked FLASH 6 to the FPGA 3 is prepared to be selectable.

  When assigning a logical function as an access subject of the synchronous DRAM 7 to the FPGA 3, as the selectable variations, a first variation in which the SDRAM 7 is arranged horizontally adjacent to the FPGA 3, and the FPGA 3 and the SDRAM 7 are stacked. A second variation to be arranged and a third variation that uses electrically rewritable FLASH 6 as another one of the other semiconductor devices and allows the definition data to be internally transferred from the FLASH 6 to the FPGA 3 are prepared. Thus, when the access function for the SDRAM 7 is exclusively assigned to the FPGA 3, it is possible to optimize the point of high-speed access to the SDRAM 7. In particular, the third variation is a variation that copes with the case where the memory circuit of the FPGA 3 is volatile.

  3A is a flat placement of four FPGAs 3A to 3D, FIG. 3B is a flat placement of four FPGAs 3A to 3C, FIG. 3C is a stack of two FPGAs 3A to 3B, and FIG. A case where the stack configuration of the FPGAs 3A to 3C is selected is illustrated. For example, the memory circuit of the FPGA 3A is electrically rewritable and nonvolatile, and the other FPGAs 3B to 3D are electrically rewritable and volatile. By preparing a fourth variation in which some FPGA memory circuits are electrically rewritable and non-volatile, and the remaining FPGA memory circuits are electrically rewritable and volatile, power consumption by the memory circuit is reduced. The circuit format of the memory circuit can be optimized from the viewpoint of function setting operability.

《Pin Arrangement》
Another variation is a pin arrangement of a semiconductor device. FIG. 4 shows an example of a ball grid array of the semiconductor device 1. A ball grid array concentrically wound in a plurality of rows is formed as an external connection electrode on the bottom side of the semiconductor device 1, and the external connection electrode 10 (indicated by a hexagon) near the outer periphery of the ball grid array is used frequently. A connection with a semiconductor device having a higher frequency of use is assigned, and a connection with a semiconductor device having a lower frequency of use is assigned to the external connection electrode 11 (indicated by a cross) near the inner periphery of the ball grid array. The electrode 12 in the center portion displayed in a rectangle is used as a test terminal, a power supply terminal, and a circuit ground terminal. Since the wiring on the mounting substrate on which the semiconductor device 1 is mounted is shorter when it is connected to the external connection electrode 10 near the outer periphery of the ball grid array, the load caused by wiring routing is small. Optimization can be achieved in that high processing performance is obtained by reducing the load on the wiring to which a frequently used device is connected. The external connection electrode 10 near the outer periphery of the ball grid array is assigned to connection with a frequently used semiconductor device, and the external connection electrode 11 near the inner periphery of the ball grid array is assigned with a semiconductor device with lower use frequency. By preparing the sixth variation to be assigned to the connection, it becomes easy to optimize in that a high processing performance can be obtained by reducing a load of a wiring to which a frequently used device is connected.

  FIG. 5 shows another example of the ball grid array of the semiconductor device 1. The number of signal external connection terminals 13 (indicated by hexagons) assigned to connections with frequently used semiconductor devices is equal to the number of signal external connection terminals 14 (shown with hexagons) assigned to connections with less frequently used semiconductor devices. More than the number shown). In FIG. 5, the semiconductor device that is used frequently is MPU4, and the semiconductor device that is used less frequently is FPGA3. In FIG. 6, the frequently used semiconductor device is FPGA3, and a large number of external connection terminals 15 (indicated by a cross) are assigned to the FPGA3, and the infrequently used semiconductor device is MPU4. A small number of external connection terminals 16 (indicated by hexagons) are assigned to the connection. The limited number of external terminal assignments is optimized. A seventh variation in which the number of external connection terminals for signals assigned to connection with a semiconductor device with high use frequency is larger than the number of external connection terminals for signals assigned with connection to a semiconductor device with low use frequency By preparing, it becomes easy to optimize the allocation of the limited number of external terminals.

  FIG. 7 exemplifies the stack terminals held by the FPGA. The FPGA 3 has a plurality of first external terminals 20 for mounting on the package substrate 2 and a plurality of second external terminals 21 used for mounting another semiconductor device on the FPGA 3 in a stacked state. The second external terminal 21 has an arrangement located on three sides of the rectangle. The plurality of second external terminals 21 are connected to external terminals of another semiconductor device mounted in a stacked state, and further connected to the first external terminals. Other configurations may also be used. As illustrated in FIG. 8, the arrangement of the external terminals of the memory is almost the center of the device along two opposite sides of the device or the longitudinal side of the device, and the address and data of the microcomputer. Since the terminals only extend over the three sides of the rectangle, positioning the second external end 21 on the three sides of the rectangle means that when the FPGA 3 and the SDRAM 7 or MPU 4 are stacked, the terminals are connected to each other. Optimization in terms of ease is achieved. As illustrated in FIG. 9, the stack structure may or may not have a spacer between the FPGA 3 and the MPU 4. By preparing an eighth variation in which a plurality of second external terminals are arranged on three sides of a rectangle, when stacking FPGA 3 and SDRAM 7 or MPU 4, it is optimal in terms of easy connection between the terminals. Can be achieved.

<Function isolation>
FIG. 10 shows a concept related to function separation for the FPGA 3 and the MPU 4. An arithmetic processing function (EXECUTION) is realized in the FPGA 3, and a control function (CONTROL) for the arithmetic processing function of the FPGA 3 is assigned to the MPU 4. As a result, the user can set image processing, audio processing, communication processing, encryption / decryption processing, and the like in the FPGA 3, and in this case, the design assets held by the user can be applied to the function settings for the FPGA 3. Utilize design assets. The MPU 4 only needs to perform a control function such as an initial setting for the arithmetic processing function set in the FPGA 3, and the occurrence of a situation in which the load on the MPU 4 becomes extremely large in the specific process is suppressed. In this way, optimization is achieved in terms of utilization of design assets owned by the user and variation in the load on the MPU 4. When realizing an arithmetic processing function in the FPGA 3, by preparing a ninth variation in which the MPU 4 is assigned a control function for the arithmetic processing function of the FPGA 3, the utilization of design assets owned by the user and the variation in the load on the MPU 4 are referred to. It is easy to optimize in terms of points.

  FIG. 11 shows a bus configuration for connecting semiconductor devices whose functions are separated. The SDRAM 7, MPU 4, and FLASH 6 are connected to a bus 25 defined inside the FPGA 3. Since the bus 25 is configured using the FPGA 3, the bus configuration is programmable. Therefore, it is easy to cope with the bus connection regardless of the interface specifications of the SDRAM 7 and FLASH 6 connected to the FPGA 3 and the bus interface specifications of other devices, and it is easy to cope with future specification changes. Optimized in terms of bus connection diversity. A user who has trouble creating function determination data for determining the bus configuration by the FPGA 3 may adopt a configuration in which the bus 25 is formed on the package substrate 2 as shown in FIG. 12, but the bus configuration is fixed. Become. By realizing the bus 25 in the FPGA 3 and preparing a tenth variation that enables the bus 25 to be connected with other semiconductors, it becomes easy to optimize the bus connection in terms of diversity. .

<Application model>
FIG. 13 illustrates a configuration when an input / output device is connected to the semiconductor device 1 as an application model. An external input / output interface (EXIO) 26 for connecting an external input / output device (EXDEV) is preferably realized by the FPGA 3. It is possible to flexibly cope with changes in external I / O interface specifications and changes in connected external I / O devices. By preparing the eleventh variation for assigning the external input / output interface function to the FPGA 3, it becomes possible to flexibly cope with the change of the external input / output interface specification and the change of the connected external input / output circuit.

《Test method》
FIG. 14 shows considerations related to the mass production test of the semiconductor device 1. The test of the FPGA 3 is performed by the MPU 4, and the test of the SDRAM 7 is performed by the MPU 4 using a built-in self-test circuit (BIST) realized in the FPGA 3. Since the FPGA 3 constitutes the BIST of the SDRAM 7, the FPGA 3 can be connected to the internal circuit of the SDRAM 7. From the above, it can contribute to the optimization of the test. The MPU 4 performs a test of the FPGA 3, and the SDRAM 7 is tested by the MPU 4 using a built-in self-test circuit implemented in the FPGA 3, thereby providing a mechanism for a mass production test of the semiconductor device 1. It becomes easy. FIG. 15 schematically shows the test path set when testing the FPGA 3 and the state of the logic elements in the test path. 27 is a logic element, and 28 is a test path.

<Function definition>
16 and 17 illustrate a basic form of a function definition method for FPGA. In FIG. 16, the definition data held by the FLASH 7 is loaded into the memory circuit of the FPGA 3 to determine the logic function by a large number of logic elements. FIG. 17 loads the definition data of the FPGA 3 from the on-chip flash memory 29 of the MPU 4 to the storage circuit of the FPGA 3 to determine the function of the FPGA 3. In any case, a non-volatile memory for holding definition data is not required on the mounting substrate of the semiconductor device 1. Preparing a third variation that enables the definition data to be transferred internally from the FLASH 7 to the FPGA 3 and a fifth variation that allows the CPU of the MPU 4 to load the definition data from the on-chip flash memory 29 to the storage circuit of the FPGA 3 This makes it easy to optimize the function settings of the FPGA in terms of using an MPU with a built-in nonvolatile memory and using an FPGA having a volatile memory circuit.

  An electronic device 30 such as a PC (Personal Computer) or a mobile phone in which the semiconductor device 1 is mounted has a communication port 31 for receiving the definition data from the outside as shown in FIG. It becomes easy to deal with corrections.

<Development algorithm>
In designing a semiconductor device equipped with the FPGA 3, when focusing on the above-described physical configuration and functional system configuration, the first to twelfth variations are prepared in the development support system, and variations that meet the design conditions are selected. FIG. 19 illustrates a development support system for that purpose. The development support system includes an IC library (ICL), a PCB library (PCBL), application design data (ADD), and variation data (BDD) that defines the contents of the first to twelfth variations. The analysis unit (AEG) generates a desirable solution for the physical configuration and a desirable solution for the functional system configuration. Regarding the physical configuration, considering the cost, function, ease of handling, etc. within the range that satisfies the design conditions (COND), select a suitable variation from the variations related to the chip arrangement and pin arrangement, and the desired physics accordingly. Design data (DSGN) for specifying a specific configuration is generated. Regarding the functional system configuration, considering the cost, function, ease of handling, etc. within the range that satisfies the design conditions, select a suitable variation from among the variations related to function classification, application model, test method, function definition, and so on. Accordingly, design data (DSGN) that specifies a desired functional system configuration is generated. A plurality of desirable solutions generated by the analysis unit (AEG) may be generated with priorities.

  FIG. 20 illustrates a block diagram of a SIP semiconductor device obtained by the above design method. Here, the definition data is taken into the inside using JTAG from the outside, but naturally it may be loaded from the outside via USB or the like. Here, arithmetic processing functions such as CIF (Camera Interface), GPU (Graphic Processing Unit), and LPC (LCD Panel Controller) are realized in the FPGA, and a memory bus function is realized as a MAC (Memory Access Controller). The FPGA 3 is connected to the MPU 4 via a CBI (CPU Bus Interface).

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

It is explanatory drawing which shows five typical forms of the chip arrangement as a mounting form. It is explanatory drawing which shows another variation of the chip arrangement as a mounting form. It is explanatory drawing which shows another variation of the chip arrangement as a mounting form. It is a bottom view which shows an example of the ball grid array of a semiconductor device. It is explanatory drawing which shows the example of the pin arrangement which arrange | positions the external connection terminal allocated for a connection with a semiconductor device with high use frequency on the outer side of a ball grid array. It is explanatory drawing of the pin arrangement which increases the number of the external connection terminals allocated to a connection with a semiconductor device with high use frequency. It is explanatory drawing which illustrates the arrangement configuration of the terminal for stacks which FPGA has. It is a reference drawing for explaining the arrangement of external terminals of a memory and the arrangement of addresses and data terminals of a microcomputer. It is explanatory drawing which shows the structure which interposes a spacer between FPGA and MPU, and the structure which does not interpose. It is explanatory drawing which shows the concept regarding the function division with respect to FPGA and MPU. It is a function explanatory view showing an example in which a bus for connecting a semiconductor device whose functions are separated is configured with an FPGA. It is function explanatory drawing which shows the example which comprises the bus | bath which connects the semiconductor device by which the function separation was carried out in a package board | substrate. It is explanatory drawing which illustrates the structure in the case of connecting an input / output device to a semiconductor device as an application model. It is explanatory drawing which shows the consideration regarding the mass production test of a semiconductor device. It is explanatory drawing which shows typically the mode of the logic element in the test path | pass and test path which are set when testing FPGA. It is a function explanatory drawing which shows one of the basic forms of the function definition method with respect to FPGA. It is a function explanatory drawing which shows another basic form of the function definition method with respect to FPGA. It is explanatory drawing which showed the application example which receives the definition data of FPGA from a communication port. It is explanatory drawing which illustrates the development support system of the semiconductor device carrying FPGA. FIG. 20 is a block diagram of a SIP semiconductor device obtained by the design method of FIG. 19.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Package substrate 3, 3A-3D FPGA
4 MPU
5 PROM
6 FLASH
7 SDRAM
DESCRIPTION OF SYMBOLS 10 Outer edge side ball electrode 11 Inner edge side ball electrode 13, 15 Ball electrode 14 and 16 with high use frequency Ball electrode 20 with low use frequency 20 First external terminal for external connection 21 Second external connection terminal for stack 25 Bus 26 External input / output interface formed in FPGA 27 Logic element 28 Test path 29 Microcomputer on-chip flash memory 30 Electronic device 31 Communication port

Claims (22)

A semiconductor device comprising a plurality of semiconductor devices on a package substrate,
As at least one semiconductor device, a programmable device in which a logic function by a large number of logic elements is variable according to definition data held by a rewritable memory circuit,
A synchronous DRAM is provided as one of the other semiconductor devices, and the synchronous DRAM is arranged horizontally or in a stack adjacent to the programmable device, and a logical function that becomes an access subject of the synchronous DRAM is assigned to the programmable device. Semiconductor device.   The semiconductor device according to claim 1, further comprising an electrically rewritable nonvolatile memory as another semiconductor device, wherein the definition data is transferred from the nonvolatile memory to a programmable device.   3. A plurality of the programmable devices, wherein memory circuits of some programmable devices are electrically rewritable non-volatile, and memory circuits of the remaining programmable devices are electrically rewritable volatile. Semiconductor device. A processing device is included as another semiconductor device,
The processing device comprises a central processing unit and an electrically writable non-volatile memory,
The semiconductor device according to claim 1, wherein the central processing unit internally transfers the definition data from the nonvolatile memory to the storage circuit. A semiconductor device comprising a plurality of semiconductor devices on a package substrate,
The package substrate has a ball grid array that is concentrically wound in a plurality of rows as external connection electrodes, and the external connection electrodes near the outer peripheral edge of the ball grid array are assigned connections with semiconductor devices that are frequently used. A semiconductor device in which a connection with a semiconductor device that is less frequently used is assigned to an external connection electrode near the inner periphery of the grid array. A semiconductor device comprising a plurality of semiconductor devices on a package substrate,
The package substrate has a ball grid array that is concentrically circulated in a plurality of rows as external connection electrodes, and the number of external connection terminals for signals that are assigned to connection to semiconductor devices that are frequently used is low-use semiconductors A semiconductor device in which the number of external connection terminals for signals assigned to connection with a device is increased. A programmable device in which a logic function by a large number of logic elements is variable according to definition data held by a rewritable memory circuit,
A plurality of first external terminals for mounting on the mounting substrate; and a plurality of second external terminals used for mounting another semiconductor device on the programmable device in a stacked state. A programmable device having an arrangement in which the outer ends are located on three sides of a rectangle. A semiconductor device comprising: a programmable device whose logic function by a large number of logic elements is variable according to definition data held by a rewritable memory circuit; and a processing device having a central processing unit,
An arithmetic processing function is realized in the programmable device,
A semiconductor device that controls an arithmetic processing function of the programmable device in the processing device. A semiconductor device including a programmable device in which a logic function by a large number of logic elements can be changed according to definition data held by a rewritable memory circuit, and a memory,
The memory is a semiconductor device bus-connected to a bus realized in the programmable device.   The semiconductor device according to claim 9, wherein the programmable device constitutes an external input / output interface. A semiconductor device comprising a plurality of semiconductor devices on a package substrate,
As at least one semiconductor device, a programmable device in which a logic function by a large number of logic elements is variable according to definition data held by a rewritable memory circuit,
A memory device is provided as another semiconductor device,
A processing device having a central processing unit as another semiconductor device;
The processing of the programmable device is performed by the processing device,
The semiconductor device performs a test of the memory device by the processing device using a built-in self-test circuit realized in the programmable device. An electronic device using a semiconductor device having a plurality of semiconductor devices on a package substrate,
The semiconductor device includes, as at least one semiconductor device, a programmable device in which logic functions by a large number of logic elements are variable according to definition data held by a rewritable memory circuit,
The electric / electronic device is an electronic device having a communication port for receiving the definition data from the outside. A method for designing a semiconductor device in which a plurality of semiconductor devices are mounted on a package substrate,
As at least one semiconductor device, a programmable device whose logic function by a large number of logic elements is variable according to definition data held by a rewritable memory circuit is used.
Depending on the function assigned to the programmable device, variations can be selectively used,
When a synchronous DRAM is used as one of the other semiconductor devices, and a logical function that is an access main body of the synchronous DRAM is assigned to the programmable device, the selectable variation may be the synchronous device adjacent to the programmable device. A first variation in which DRAMs are arranged horizontally, a second variation in which the programmable device and the synchronous DRAM are stacked, and an electrically rewritable nonvolatile memory as another semiconductor device, A semiconductor device design method comprising: a third variation that enables the definition data to be internally transferred from the nonvolatile memory to the programmable device.   A fourth variation is prepared in which a plurality of programmable devices are used, the memory circuits of some programmable devices are electrically rewritable and non-volatile, and the remaining memory circuits of programmable devices are electrically rewritable and volatile. The method of designing a semiconductor device according to claim 13, which can be performed.   When another processing device is used as another semiconductor device, and the processing device includes a central processing unit and an electrically writable nonvolatile memory, the central processing unit receives the definition data from the nonvolatile memory. 14. The semiconductor device design method according to claim 13, wherein a fifth variation for enabling internal transfer to the memory circuit is prepared.   The package substrate has a ball grid array that is concentrically circulated in multiple rows as external connection electrodes, and the external connection electrodes near the outer periphery of the ball grid array are allocated for connection to frequently used semiconductor devices. 14. The method of designing a semiconductor device according to claim 13, wherein a sixth variation assigned to connection with a semiconductor device having a lower usage frequency is prepared for the external connection electrode near the inner periphery of the array.   The package substrate has a ball grid array that is concentrically wound in a plurality of rows as external connection electrodes, and the number of external connection terminals for signals assigned to connection to semiconductor devices that are frequently used is reduced. 14. The method of designing a semiconductor device according to claim 13, wherein a seventh variation is prepared in which the number of external connection terminals for signals allocated to connection with a device is increased.   The programmable device has a plurality of first external terminals for mounting on the package substrate, and a plurality of second external terminals used for mounting another semiconductor device on the programmable device in a stacked state. The semiconductor device design method according to claim 13, wherein an eighth variation is provided in which a plurality of second external terminals are arranged on three sides of a rectangle.   14. The method of designing a semiconductor device according to claim 13, wherein, when an arithmetic processing function is realized in the programmable device, a ninth variation in which a control function for the arithmetic processing function of the programmable device is assigned to the processing device.   The semiconductor device design method according to claim 13, wherein a tenth variation is provided that realizes a bus in the programmable device and allows the bus to be connected to the bus by another semiconductor.   14. The semiconductor device design method according to claim 13, wherein an eleventh variation for assigning an external input / output interface function to the programmable device is prepared.   14. The semiconductor according to claim 13, wherein a twelfth variation is prepared in which the processing device performs a test of the programmable device and the memory device performs a test using a built-in self-test circuit implemented in the programmable device. Device design method.

Images