JPH07240844A - Image data processing unit and image data processing method - Google Patents

Abstract

PURPOSE:To attain high speed compression processing for image data by providing a variable length coding processor and a pipeline control processor applying pipeline control to the processing the processing unit. CONSTITUTION:The processing unit is provided with a control unit 2 having two processors, a pixel processing unit 3 for DCT and quantization, a moving prediction (or detection) unit 41 and a frame buffer memory 51 or the like storing processed image data. Then the picture element processor executes discrete cosine transformation processing and quantization processing to picture element data sent via a picture element data bus and the variable length coding processor executes the picture element coding processing. Furthermore, the pipeline control processor controls the processing in each processor and pipeline processing in the data transfer via a bus. Thus, the compression processing of picture data is implemented at a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to an image data processing apparatus and an image processing method, and more particularly to an image data processing apparatus and an image data processing method capable of efficiently performing compression and / or expansion of image data at high speed. .

[0002]

BACKGROUND ART Conventionally, the creation of an international standard for compressing and decompressing image data has been performed by the International Organization for Standardization (In
ternational Organization for Standardization; hereinafter referred to as "ISO", International Telegraph and Telephone Advisory Committee (Intern)
ational Telegraph and Telephone Consultative Commi
ttee; hereinafter referred to as “CCITT”, but currently IT
UT, renamed International Electrotechnical Commission (International El
Electrical Committee; hereinafter referred to as "IEC").

Among the international standards, the JPEG standard is I
Joint Photog by SO and CCITT
Created by the Ragic Expert Group, it defines a compression and decompression algorithm for color still images. On the other hand, the MPEG standard is based on the Moving Picture Expert of ISO and IEC.
It is being created by Group and defines compression and decompression algorithms for color video. further,
H. The H.261 standard is a standard being created by CCITT and defines compression and expansion algorithms suitable for video conferences and video telephones.

FIG. 69 is a block diagram showing the main processing in the image compression algorithm recommended by the international standard. Referring to FIG. 69, the image compression processing is
Basically, it includes a predictive coding process, an orthogonal transform process, and a variable length coding process. As can be seen from FIG. 69, JPE
G, MPEG and H.264. The H.261 standards include discrete cosine transform (hereinafter referred to as “DCT”), quantization processing, and Huffman coding processing in image compression processing.

For example, JP for color still image processing
The EG standard includes adaptive DCT processing, quantization processing, DPCM processing and Huffman coding processing as a basic system. The JPEG standard includes adaptive DCT processing, hierarchical coding processing, arithmetic coding processing, and adaptive Huffman coding processing as an extended system.

The MPEG standard for moving image storage processing is
It includes motion compensation / interframe prediction processing, DCT processing, quantization processing, and Huffman coding processing. H.264 for videophone and videoconferencing. 261 standard is motion compensation processing /
It includes inter-frame prediction processing, DCT processing, quantization processing, and Huffman coding processing.

Image compression LS according to the above international standard
The development of I is in progress, and its outline is, for example,
A paper entitled "Image Compression LSI" (Journal of the Television Society, Vol. 46, No. 3, pp. 253-260,
1992). It is pointed out that the present invention can be generally applied to an image data compression device, an image data expansion device and an image data processor for image compression and / or expansion processing according to the above international standard.

FIG. 70 is a block diagram of a conventional image compression / expansion processing apparatus. Referring to FIG. 70, the image compression / expansion processing apparatus includes a digital signal processor (hereinafter referred to as “DSP”) 900 for image data processing.
Image data memory 907 and code data memory 9
08, a display memory 909, and a work memory 910. The DSP 900 is connected to the memories 907 to 910 via the internal bus 940.

FIG. 71 is a block diagram of the DSP 900 shown in FIG. 71, with reference to FIG.
0 is an instruction memory 901 and a program controller 902.
A data memory 903, a data calculator 904, and an external interface 905. System bus 94
1 is a program controller 902, a data memory 903,
Data calculator 904 and external interface 905
Connect between.

In operation, the instruction code stored (or programmed) in instruction memory 901 is read and provided to program controller 902. The program controller 902 decodes a given instruction code and generates various control signals. Data calculator 904
Responds to the control signal given from the program controller 902, receives data from the outside through the data memory 903 and the external interface 905, and executes the operation. The calculation result is stored in the data memory 903 or output via the external interface 905. In this way, the DSP 900 executes the processing according to the instruction code stored in the instruction memory 901.

Next, with reference to FIGS. 70 and 71, the operation in the image data compression process will be described. Here, it is assumed that the image data to be compressed is stored in the image data memory 907. First, the image data stored in the image data memory 907 is
It is transferred to the data memory 903 in the DSP 900. The image data stored in the data memory 903 is subjected to format conversion processing by the data calculator 904. In the format conversion process, for example, the subsample data of the color difference signal or the RGB format data is converted into YUV format data. The converted data is temporarily stored in the data memory 903.
Stored in. The DSP 900 is a data memory 90.
The converted data in 3 is transferred to the image data memory 907.

Next, the DSP 900 uses the data stored in the image data memory 907 to perform an image compression mode determination process. Known image compression modes include an inter-frame compression mode and an intra-frame compression mode. In the inter-frame compression mode, processing such as motion prediction (or detection) is sometimes necessary. The evaluation data for determining the compression mode and the evaluation data for detecting the motion are obtained by executing a difference absolute value sum operation on the image data. When these operations are performed, the DSP 900, like the format conversion process,
The data stored in the image data memory 907 is transferred to the data memory 903, and the data arithmetic unit 904 executes arithmetic processing on the data stored in the data memory 903.

The DSP 900 refers to the mode determination table data stored in the work memory 910 based on the evaluation data obtained by the above operation and / or executes the comparison operation process for the evaluation data. Determines the compression mode.

After the compression mode is determined, the DSP 900
Performs a transform coding process on the image data stored in the image data memory 907. The transform coding process is a process represented by, for example, DCT, and the DSP 900 transfers the data stored in the image data memory 907 to the internal memory 903, and then the data calculator 904 executes the DCT process. The processed data is held in the data memory 903.

Further, the DSP 900 executes variable length coding (or entropy coding) processing. The variable length coding process is known as a code conversion process using, for example, a Huffman code. The DSP 900 executes the variable length coding process on the data stored in the data memory 903 by referring to the code conversion table stored in the work memory 910. After the code conversion, the processed data is transferred from the data memory 903 to the code data memory 908 and stored.

The image data processing for image compression is performed as described above. On the other hand, the image data processing for image decompression is performed in a manner similar to the case of image compression. That is, the data to be image-expanded is once provided to the data memory 903 in the DSP 900, and the data calculator 904 executes the process for image expansion on the stored data.

[0017]

As described above, in the conventional image compression / expansion processing device, the DSP 900 having the single data calculator 904 executes the compression and expansion of the image data. It took a lot of time to process. In addition to this, the DSP 900 has one I / O port for data (ie, external interface 9
Since only 05) is provided, data transfer cannot be performed efficiently in an image compression / expansion processing device that handles a large amount of image data.

The present invention has been made to solve the above problems, and an object thereof is to provide an image data processing apparatus and an image processing method suitable for high speed processing.

[0019]

An image data processing apparatus according to the invention of claim 1 transmits pixel data storage means for storing pixel data to be compressed, and pixel data stored in the pixel data storage means. A pixel data bus and a pixel processor that performs a discrete cosine transform process and a quantization process on pixel data transmitted via the pixel data bus and outputs a pixel code, and a pixel code output from the pixel processor is transmitted. Pixel code bus, variable length coding processor for performing variable length coding processing on pixel code transmitted via the pixel code bus, and outputting variable length code, pixel data bus, pixel processor, pixel code bus And a pipeline control processor for controlling pipeline processing for the variable length coding processor.

According to a second aspect of the present invention, there is provided an image data processing device, wherein variable length code storage means for storing the compressed variable length code and variable length code for transmitting the variable length code stored in the variable length code storage means. A variable-length decoding processor that performs variable-length decoding processing on a bus and a variable-length code transmitted via the variable-length code bus and outputs a pixel code, and a pixel code output from the variable-length decoding processor A pixel code bus for transmitting a pixel code bus, a pixel processor for performing inverse quantization processing and inverse discrete cosine transform processing on the pixel code transmitted via the pixel code bus, and outputting expanded pixel data; A bus, a variable length decoding processor, a pixel code bus and a pipeline control processor for controlling pipeline processing for the pixel processor.

The image data processing apparatus according to the invention of claim 3 executes the discrete cosine transform processing and the quantization processing on the pixel data in the data compression mode, and the inverse quantization processing and the inverse discrete processing on the pixel code in the data expansion mode. Pixel processor for executing cosine transform processing, variable length coding processing for pixel code in data compression mode, and variable length decoding processing for variable length code in data expansion mode, and pixel processor A first data bus for transmitting pixel data and a variable length code between the pixel processor and the variable length processor; a second data bus for transmitting a pixel code between the pixel processor and the variable length processor; Long processor, pipeline for first and second data buses And a pipeline control processor for controlling the process.

An image data processing apparatus according to a fourth aspect of the present invention includes first storage means for storing table data for conversion, second storage means for storing image data to be image processed, and display. It is possible to access the third storage means for storing the image data and the fourth storage means for storing the converted image data. This image data processing apparatus has first to fourth access means for accessing the first to fourth storage means, respectively, and access control for individually controlling the start of an access operation for the first to fourth access means. And means.

According to a fifth aspect of the present invention, there is provided an image data processing device comprising: a control processor for controlling pipeline processing for a plurality of predetermined processes for image data compression and / or image data expansion; And an image processing processor that executes a predetermined one of a plurality of predetermined processes in response to a control signal provided thereto.

An image data processing apparatus according to a sixth aspect of the present invention is a pipe for controlling pipeline processing for discrete cosine transform processing for image data compression and / or image data expansion, quantization processing and variable length data processing. A line control processor and a variable length processor that performs variable length data processing in response to a control signal provided from the pipeline processing control processor are included.

According to a seventh aspect of the present invention, there is provided an image data processing device which comprises a control processor for controlling a predetermined process for image data compression and / or image data decompression and a parallel operation for image data transfer. A plurality of execution instruction means for individually instructing execution of predetermined processing and image data transfer in response to a control signal provided from the control processor.

The image data processing apparatus according to the present invention is provided with a storage means for storing a variable length code corresponding to a combination of run data and level data, the code length data and an equal length code processing flag. Responsive to the run data and the given level data, the reading means for reading the corresponding variable length code, the code length data and the equal length code processing flag from the storage means, the given run data and the given level data With respect to the variable length code, in response to the equal length coding means for performing the coding processing according to a predetermined rule and outputting the corresponding equal length coding, and the equal length coding processing flag output from the reading means. It includes a selecting means for selecting one of the equal-length codes and a code combining means for sequentially combining the output codes output from the selecting means.

The image data processing device according to the invention of claim 9 is provided with a storage means for storing run data, level data and an equal length processing flag corresponding to a variable length code, and a combined variable length code. Extracting means for extracting the variable length code from the variable length code string, and reading means for reading the corresponding run data, level data and equal length processing flag from the storing means in response to the variable length code extracted by the extracting means. An equal-length decoding unit that performs an equal-length decoding process according to a predetermined rule on the variable-length code extracted by the extracting unit and outputs corresponding decoded data,
Selecting means for selecting one of the run data, the level data and the decoded data in response to the equal length processing flag output from the reading means.

An image data processing device according to a tenth aspect of the invention includes n (n ≧ 2) memory cell arrays for storing pixel data for defining pixels in a screen.
The n memory cell arrays are each stored in a corresponding one of the n memory cell arrays in response to the application of one row address signal and one column address signal.
Output pixel data. The n pieces of pixel data define a plurality of pixels vertically arranged on the screen. The image data processing device further includes an address signal generating unit that serially outputs a column address signal for designating pixel data of pixels horizontally arranged on the screen in response to the serial clock signal.

An image data processing device according to the invention of claim 11 includes n (n ≧ 2) memory cell arrays for storing pixel data for defining pixels in a screen.
The n memory cell arrays are each stored in a corresponding one of the n memory cell arrays in response to the application of one row address signal and one column address signal.
Output pixel data. The n pieces of pixel data define a plurality of pixels placed in the horizontal direction on the screen. The image data processing device further includes address signal generating means for serially outputting a column address signal for designating pixel data of pixels vertically arranged on the screen in response to the serial clock signal.

In the image data processing method according to the twelfth aspect of the present invention, a plurality of macroblock data defining pixels forming a screen are encoded under pipeline processing. This image data processing method executes a discrete cosine transform process and a quantization process on macroblock data to generate a pixel code, and a variable length coding process on the generated pixel code to generate a variable length code. And a step of combining the generated variable-length codes to generate a variable-length code string.

In the image data processing method according to the thirteenth aspect of the present invention, a variable length code string including a plurality of variable length codes defining pixels forming a screen is decoded under pipeline processing. This image data processing method includes a step of extracting the variable-length code from a variable-length code string, a step of executing a variable-length decoding process on the extracted variable-length code to generate a pixel code, and an inverse of the pixel code. Performing a quantization process and an inverse discrete cosine transform process to generate macroblock data defining pixels forming a screen.

In the image data processing method according to the fourteenth aspect of the present invention, the first pixel data is mapped in the storage means for storing the plurality of first pixel data defining the pixels in the screen. According to this image data processing method, a first step of determining a plurality of second pixel data included in a rectangular area that is two-dimensionally adjacent and close to a square from the first pixel data, and the second pixel data are combined into one. A second step of giving one address of the storage means as data to the second pixel data;
A third step of transferring the second pixel data from or to the storage means using the address of the pixel data.

According to a fifteenth aspect of the present invention, there is provided a pixel data processing method, wherein the first storage means stores the first and second color difference pixel data associated with each other for defining the pixels in the screen.
And the second color difference pixel data is mapped. In this pixel data processing method, a first step of alternately mapping the first and second color difference pixel data in a transfer unit to a storage unit, and transferring the first or second color difference data in or from a storage unit to the storage unit. A second step of

According to a sixteenth aspect of the present invention, in the image data processing method, the storage means for storing the first and second color difference pixel data associated with each other for defining the pixels in the screen has a first structure.
And the second color difference pixel data is mapped. In this image data processing method, the first step of mapping the third color difference pixel data obtained by combining the first and second pixel data by the same number into the storage means as one data, and the third color difference pixel data as one data, A second step of transferring from or to the storage means.

The image data processing apparatus according to the seventeenth aspect of the present invention transmits first pixel data storage means for storing pixel data to be compressed, and pixel data stored in the first pixel data storage means. The pixel data transmitted via the second pixel data bus and the first pixel data bus are received, the motion prediction reference data is extracted using the transmitted pixel data, and the motion prediction reference data is extracted. Pixel processor having first and second data ports for outputting, second pixel data bus for transmitting motion prediction reference data outputted from the second data port of the pixel processor, and second pixel data bus Second pixel data storage means for storing the motion prediction reference data transmitted via the second pixel data storage means, and the second pixel data storage means for storing the motion prediction reference data stored in the second pixel data storage means. By executing the motion prediction processing using the reference data for motion estimation, a motion prediction unit for generating a motion vector, the first and second pixel data bus,
A pixel processor and a pipeline control processor that controls pipeline processing for the motion estimation unit.

In the image data processing device according to the eighteenth aspect of the present invention, in addition to the configuration of the seventeenth aspect, the pipeline control processor is a system control for outputting output control signals of the first and second data ports of the pixel processor. Further includes a vessel.

An image data processing device according to a nineteenth aspect of the present invention transmits first pixel data storage means for storing pixel data to be compressed and pixel data stored in the first pixel data storage means. A first pixel data bus and pixel data transmitted via the first pixel data bus are received, motion prediction reference data is extracted using the transmitted pixel data, and the extracted motion prediction reference A pixel processor having a first data port for outputting data and a plurality of second data ports for dividing and outputting the extracted reference data for motion prediction, and a pixel processor provided corresponding to each second data port A plurality of second pixel data buses for transmitting the motion prediction reference data output from the second data port, and the second pixel data bus provided for each second data port. A plurality of second pixel data storage means for storing the motion prediction reference data transmitted via the elementary data bus, and a plurality of second pixel data storage means provided corresponding to each second data port. A motion prediction unit that performs motion prediction processing using the motion prediction reference data transmitted via the second data bus, and generates a motion vector; a first pixel data bus, a pixel processor, and a plurality of second A pixel data bus and a pipeline control processor that controls pipeline processing for the plurality of motion prediction units.

The image data processing apparatus according to the twentieth aspect of the present invention transmits first pixel data storage means for storing pixel data to be compressed and pixel data stored in the first pixel data storage means. The first pixel data bus and the pixel data transmitted via the first pixel data bus are received, the motion prediction reference data is extracted using the transmitted pixel data, and the motion prediction reference data is extracted. A pixel processor having a first data port for outputting and a plurality of second data ports for dividing and outputting the reference data for motion prediction according to the type of reference data for motion prediction, and for each second data port A plurality of second pixel data buses that are provided corresponding to each other and transmit the motion prediction reference data output from the second data port, and are provided corresponding to each second data port. A plurality of second pixel data storage means for storing the reference data for motion prediction transmitted via the second pixel data bus, an address bus connected to the plurality of second pixel data storage means, and a second Corresponding to each data port, the motion prediction processing is executed by using the motion prediction reference data stored in the second pixel data storage means and transmitted via the second pixel data bus, Regarding a plurality of motion prediction units that generate a motion vector according to the type of prediction reference data, a first pixel data bus, a pixel processor, a plurality of second pixel data buses, an address bus, and a plurality of motion prediction units And a pipeline control processor for controlling the pipeline processing of the.

An image data processing device according to a twenty-first aspect of the present invention transmits first pixel data storage means for storing pixel data to be compressed and pixel data stored in the first pixel data storage means. The first pixel data bus and the pixel data transmitted via the first pixel data bus are received, the different types of motion prediction reference data are extracted using the transmitted pixel data, and the motion prediction reference data is extracted. A first data port for outputting reference data and a second data port for outputting reference data for motion prediction according to the type of reference data for motion prediction
A plurality of pixel processors each having a data port, and a plurality of second pixel data buses provided corresponding to each pixel processor and transmitting the motion prediction reference data output from the second data port; Second pixel data storage means provided corresponding to each processor and storing the motion prediction reference data transmitted via the second pixel data bus, and provided corresponding to each pixel processor,
A plurality of motion prediction units that perform motion prediction processing using the motion prediction reference data stored in the second pixel data storage means and transmitted via the second pixel data bus; A first pixel data bus, a plurality of pixel processors, a plurality of second pixel data buses, and a pipeline control processor that controls pipeline processing for the plurality of motion prediction units.

In the image data processing apparatus according to the twenty-second aspect of the present invention, in addition to the configurations of the nineteenth to twenty-first aspects, the motion prediction reference data stored in the plurality of second pixel data storage means is a luminance component. Are stored in different second pixel data storage means depending on the types of the color difference component and the color difference component.

The image data processing device according to the twenty-third aspect of the present invention comprises a control processor for controlling a predetermined process for image data compression and / or image data decompression and a parallel operation for image data transfer; Data is transferred between the control processor and the plurality of storage command means for individually instructing execution of predetermined processing and image data transfer in response to a control signal given from the control processor. A second data bus for transferring data between the first data bus and the plurality of execution instruction means
Including data bus.

The image data processing device according to the twenty-fourth aspect of the present invention is a discrete cosine transform process and / or an inverse discrete cosine transform process for image data compression and / or image data decompression, and a quantization process and / or an inverse process. Image processing means for executing quantization processing, at least two interface means provided exclusively for image data, and storage means for storing data for image data compression and / or image data expansion processed by the image processing means. And a data bus for transferring data between the interface means and the storage means.

The image data processing device according to the twenty-fifth aspect of the present invention is a discrete cosine transform process and / or an inverse discrete cosine transform process for image data compression and / or image data decompression, and a quantization process and / or an inverse process. Image processing means for executing quantization processing, at least two interface means provided exclusively for image data, and storage means for storing data for image data compression and / or image data expansion processed by the image processing means. And a plurality of data buses provided for each interface means and transferring data between each of the interface means and the storage means.

[0044]

In the image data processing apparatus according to the present invention, the pixel processor executes the discrete cosine transform processing and the quantization processing on the pixel data transmitted via the pixel data bus, while the variable length coding is performed. A processor performs a variable length coding process on the pixel code transmitted via the pixel code bus. The pipeline control processor is
Since the processing by these processors and the pipeline processing in the data transfer via the bus are controlled, the compression processing of the image data can be performed at high speed.

In the image data processing device according to the second aspect of the present invention, the variable length decoding processor executes the variable length decoding process on the variable length code transmitted via the variable length code bus, while the pixel processor Inverse quantization processing and inverse discrete cosine transform processing are performed on the pixel code transmitted via the pixel code bus. Since the pipeline control processor controls the processing by these processors and the pipeline processing in the data transfer via the bus, the decompression processing of the image data can be performed at high speed.

In the image data processing device according to the third aspect of the present invention, the pipeline control processor controls the pipeline processing for the pixel processor, the variable length processor, and the first and second data buses. And / or the decompression process can be performed at high speed.

In the image data processing device according to the fourth aspect of the invention, the access control means individually controls the start of the access operation for the first to fourth access means. Therefore, since the first to fourth storage means can be individually accessed, the data used in the image data processing can be transferred at high speed, and the image data processing can be executed at high speed.

In the image data processing device according to the fifth aspect of the present invention, the control processor controls the pipeline processing for a plurality of predetermined processings for image data compression and / or image data expansion. Can be done at high speed.

In the image data processing apparatus according to the invention of claim 6, the pipeline processing control processor has a pipeline for discrete cosine transform processing, quantization processing and variable length data processing for image data compression and / or image data expansion. Since the processing is controlled, the image data processing can be performed at high speed.

In the image data processing device according to the seventh aspect of the present invention, the control processor controls a plurality of predetermined processes for image data compression and / or image data expansion and parallel operations for image data transfer. Since the plurality of execution instruction means individually instruct execution of these operations in response to the control signal given from the control processor, the image data processing can be performed at high speed.

In the image data processing device according to the present invention, the selecting means selects one of the variable length code and the equal length code in response to the equal length processing code flag output from the reading means. The determination process by means of is extremely simplified, and image data processing can be performed at high speed.

In the image data processing device according to the invention of claim 9, the selecting means selects one of the run data, the level data and the decoded data in response to the equal length processing flag outputted from the reading means. The determination process by means of is extremely simplified, and image data processing can be performed at high speed.

In the image data processing device according to the tenth aspect of the present invention, n pixel data read from the n memory cell arrays in response to one row address signal and one column address signal are read in the vertical direction on the screen. It defines a plurality of pixels placed in. Since the address signal generating means serially outputs the column address signal in response to the serial clock signal, it is possible to access the pixel data for a desired area in the screen in a short time. Therefore, image data processing can be performed at high speed.

According to the eleventh aspect of the present invention, in the image data processing device, n pixel data read out from the n memory cell arrays in response to one row address signal and one column address signal are horizontally arranged on the screen. It defines a plurality of pixels placed in. Since the address signal generating means serially outputs the column address signal in response to the serial clock signal, it is possible to access the pixel data for a desired area in the screen in a short time. Therefore, image data processing can be performed at high speed.

In the image data processing method according to the twelfth aspect of the invention, all the processing for a plurality of macroblock data is performed under pipeline processing.
The compression processing of image data can be performed at high speed.

In the image data processing method according to the thirteenth aspect of the present invention, since the decoding process for the variable length code string including a plurality of variable length codes is performed under the pipeline process, the image data decompression process is performed at high speed. Can be done.

In the image data processing method according to the fourteenth aspect of the present invention, a plurality of second pixel data which are two-dimensionally adjacent to each other and which are included in a rectangular area close to a square are used as one data and are transferred by giving one address. Therefore, the number of times of transfer when transferring the first pixel data in the rectangular area close to the square is reduced.

In the image data processing method of the fifteenth aspect of the present invention, the first and second color difference pixel data associated with each other are alternately mapped in the transfer unit, and the first or second color difference data is transferred in the transfer unit. Therefore, it is possible to transfer the first and second color difference pixel data within a predetermined range with one address generation.

In the image data processing method according to the sixteenth aspect of the present invention, the third color difference pixel data obtained by combining the same number of first and second color difference pixel data associated with each other is mapped as one data in the storage means, and Since three color difference pixel data are transferred as one data,
It is possible to transfer the first and second color difference pixel data within a predetermined range by generating the address once.

In the image data processing device according to the seventeenth to eighteenth aspects, the pixel processor outputs the motion prediction reference data through the first data port and the second data port, and the first pixel data is output. Storage means and second
The motion prediction reference data stored in the second pixel data storage means and stored in the second pixel storage means are transmitted to the motion prediction unit via the second pixel data bus,
A motion prediction process is executed in the motion prediction unit to generate a motion vector.

In the image data processing device according to the nineteenth to twentieth aspects of the present invention, the pixel processor has a plurality of second data ports, and the plurality of second data ports are provided corresponding to the plurality of second data ports. Second pixel data bus divides and transfers the motion prediction reference data, and the divided motion prediction reference data is stored in the second pixel data storage means connected to each second pixel data bus. Is
A motion prediction process is executed in the motion prediction unit connected to each second pixel data bus to generate a motion vector.

In the image data processing device according to the twenty-first aspect of the present invention, the plurality of pixel processors each have a second data port, and the second pixel data provided corresponding to each second data port. The bus divides and transfers the motion prediction reference data, and the divided motion prediction reference data is stored in the second pixel data storage means connected to each second pixel data bus.
The motion prediction unit connected to the pixel data bus of 1 performs motion prediction processing to generate a motion vector.

In the image data processing device according to the twenty-second aspect of the invention, the plurality of second pixel data storage means store different types of motion prediction reference data according to the difference in the types of the luminance component and the color difference component. .

In the image data processing device of the twenty-third aspect of the invention, the pixel processor controls a plurality of predetermined processes for image data compression and / or image data expansion and image data transfer. The plurality of execution instruction means individually instruct execution of these operations in response to a control signal given from the control processor, and the first and second data buses are provided between the control processor and the plurality of execution instruction means. Since the data transfer can be executed in parallel with the plurality of execution instruction means, the image data processing can be performed at high speed.

In the image data processing device according to the twenty-fourth to twenty-fifth aspects of the present invention, since the data can be transferred in parallel to the external device by at least two interface means, the image data processing can be performed at high speed.

[0066]

The image compression / expansion processing apparatus (or image compression / expansion processing system) showing the first to fifteenth embodiments of the present invention will be described below. First, the system configuration of these embodiments will be described, and then the internal configuration of the system will be described.

1. System Configuration (1) First Embodiment FIG. 1 is a block diagram of an image compression / expansion processing device 101 showing a first embodiment of the present invention. Referring to FIG. 1, the image compression / expansion processing device 101 includes a host computer 9
Host interface (I /
F) Circuit 1, control unit 2 with two processors (not shown), pixel processing unit 3 for DCT and quantization, motion prediction (or detection) unit 41, image to be processed A frame buffer memory 51 for storing data, a buffer memory 6 for storing code data, a work memory 7 for storing table data necessary for various conversion processes,
And an input / output memory 81 for storing image data from the television camera 91 and / or supplying the stored image data to a display device (CRT) 92.

The host bus HB has 24 bits ("2" in the figure).
4b ”) and is provided for data transfer between the host interface circuit 1, the control unit 2, the pixel processing unit 3, the buffer memory 6 and the work memory 7. The pixel data bus PB has a bus width of 32 bits (32b) and is provided for data transfer between the control unit 2, the pixel processing unit 3, the motion prediction unit 41 and the frame buffer memory 51. The code data bus CB has a bus width of 16 bits (16b) and is provided for code data transfer between the control unit 2, the pixel processing unit 3 and the buffer memory 6. I / O bus IOB
Has a bus width of 24 bits (24b) and is provided for data transfer between the control unit 2 and the input / output memory 81.

The host interface circuit 1 is a general-purpose logic LSI (discrete), PLD or F.
It has a logic circuit configured by a programmable logic device such as PGA. The frame buffer memory 5 is mainly provided for temporarily storing image data to be compressed and image data to be referred to. As the frame buffer memory 51, a large capacity memory such as a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous DRAM or a cache DRAM is used.

The buffer memory 6 is provided for temporarily storing bit stream data and run / level data obtained by encoding the image. The buffer memory 6 is a first-in first-out (FIF
O) is composed of memory, but in some cases DRAM
Alternatively, SRAM is used.

The work memory 7 includes DCT / inverse DCT table data, quantization / inverse quantization table data, Huffman table data for variable length processing, programs for processing in the control unit 2 and the pixel processing unit 3 (micro Code), initial setting data, and the like. The work memory 7 is composed of SRAM.

The input / output memory 81 is provided to store image data for the television camera 91 and / or the display device 92. The input / output memory 81 is a video RA
It is composed of M.

The control unit 2 includes a microprocessor (not shown) for overall control and a processor (not shown) for variable length processing. The processor for overall control includes DCT in image compression, quantization, pipeline processing for variable length coding, and variable length decoding in image expansion, inverse quantization and inverse D.
Controls pipeline processing for CT.

The pixel processing unit 3 executes pixel operations such as DCT and quantization in image compression, while inverse quantization and inverse D in image expansion.
Execute CT processing and the like.

The motion prediction unit 41 executes motion detection processing such as interframe prediction in one direction and both directions.

FIG. 2 is a processing diagram showing the image compression processing in the image compression / expansion processing apparatus 101 shown in FIG. FIG. 2 shows, as an example, an encoding method defined in the MPEG standard.

With reference to FIG. 2, the image data ID to be compressed is D through the subtractor 921 and the switch 922.
It is given to the CT processor 923. After the DCT processing, the quantizer 924 performs the quantization processing. The quantized data is supplied to the variable length coding processor 925, subjected to the variable length coding process, and then the coded data is output via the buffer 926 as the compressed image data VD.

On the other hand, the quantized data is also given to the inverse quantizer and the inverse DCT processor, and the inverse quantization processing and the inverse DCT processing for motion prediction are performed. Inverse DCT
The output data of the processor is given to the adder 929.

The image data ID is also given to the motion predictor 930, and the data subjected to the prediction processing is given to the adder 929. The output data of the adder 929 is given to the subtractor 921 and the motion predictor 930 via the switch 931.
By the switching operation by the switching devices 922 and 931, the image compression processing in which the motion prediction is taken into consideration is performed.

FIG. 3 is a processing diagram showing the image expansion processing in the image compression / expansion processing device 101 shown in FIG. Referring to FIG. 3, the variable length code data VD is
It is given to the variable length decoding processor 912 via the buffer 911. After the variable length decoding process, the code data is given to the inverse quantizer 913, and the inverse quantization process is performed.
After the inverse quantization process, the inverse DCT processor 914 performs inverse DC
T processing is performed, and the processed data is given to the adder 915. The adder 915 also performs addition processing on the data subjected to motion prediction processing on the output data, and outputs the expanded image data ID.

The processing shown in FIGS. 2 and 3 is basically defined by the MPEG standard. The image compression / expansion processing is performed by the image compression / expansion processing device 101 shown in FIG. In, it can be efficiently performed under the control of the pipeline processing described later.

(2) Second Embodiment FIG. 4 is a block diagram of an image compression / expansion processing apparatus 102 showing a second embodiment of the present invention. Compared with the image compression / expansion processing apparatus 101 shown in FIG. 1, the image compression / expansion processing apparatus 102 shown in FIG.
Are excluded. That is, in the embodiment shown in FIG.
A moving image decoding process and a still image encoding process and a decoding process may be performed. The moving image decoding process is the reverse process of the encoding process, but does not include the motion prediction process, and a motion decoding process of receiving a motion vector and generating a predicted image is added.

(3) Third Embodiment FIG. 5 is a block diagram of an image compression / expansion processor 103 showing a third embodiment of the present invention. As compared with the image compression / expansion processing apparatus 101 shown in FIG. 1 with reference to FIG. 5, this image compression / expansion processing apparatus 103 includes an input / output memory 82 connected to the pixel data bus PB. That is, the input / output memory 82 is connected to the control unit 2 via the pixel data bus PB.
As a result, in the control unit 2, the input / output memory 82 and the frame buffer memory 6 are mapped on a common address space, and the number of input / output interface circuits (input / output ports) in the control unit 2 is reduced. You can

(4) Fourth Embodiment FIG. 6 is a block diagram of an image compression / expansion processor 104 showing a fourth embodiment of the present invention. Referring to FIG. 6, compared with the image compression / expansion processing apparatus 101 shown in FIG. 1, the image compression / expansion processing apparatus 104 executes motion prediction in the forward direction and the backward direction in parallel (or simultaneously). A bi-directional motion estimation unit 42 is provided. That is, the bidirectional motion prediction unit 42 includes a motion prediction unit 43 for motion prediction processing in the forward direction and a motion prediction unit 44 for motion prediction processing in the backward direction. The motion estimation units 43 and 44 are connected to the pixel data bus PB.

The forward and backward motion prediction processes are performed in parallel using the two motion prediction units 43 and 44.
That is, since they can be executed simultaneously, the bidirectional motion prediction processing can be efficiently performed in a short time.

(5) Fifth Embodiment FIG. 7 is a block diagram of an image compression / expansion processor 105 showing a fifth embodiment of the present invention. Compared with the image compression / expansion processing device 101 shown in FIG.
The decompression processing device 105 includes a motion prediction unit 45 capable of simultaneously performing motion prediction processing in both directions,
There are two frame buffer memories 52 and 53 each connected to the pixel data bus PB. Since the motion prediction unit 45 can execute the bidirectional prediction process at the same time, the bidirectional prediction process can be performed in the time required for one of the previous and the subsequent prediction processes. The motion prediction unit 45 has two input / output ports,
One input / output port is connected to the pixel data bus PB, and the other input / output port is connected to the frame buffer memory 53 via the local bus LB1.

One of the two frame buffer memories 52 and 53 is used as a frame memory for forward motion prediction processing, and the other frame buffer memory is used as a frame memory for backward motion prediction processing. The reference image data is transferred via the pixel data bus PB and the local bus LB1. The template image data and the motion vector data are transferred to the motion prediction unit 45 via the second local bus LB2.
Is transferred to the control unit 2.

(6) Sixth Embodiment FIG. 8 is a block diagram of an image compression / expansion processor 106 showing a sixth embodiment of the present invention. Compared with the image compression / expansion processing device 101 shown in FIG.
The decompression processing device 106 includes a motion prediction unit 46 having two input / output ports. Motion estimation unit 46
Has a first input / output port connected to the pixel data bus PB, while a second input / output port has a local bus LB.
It is connected to the control unit 2 via 3. The motion prediction unit 46 directly gives the motion vector data obtained by the motion prediction processing to the control unit 2 via the local bus LB3. Since the motion vector data is composed of 8-bit signals, the local bus L
B3 has a bus width of 8 bits. Local bus L
Since the motion vector data can be directly given to the control unit 2 via B3, the parallel processing in the image compression / expansion processing device 106 is further improved, and as a result,
The image compression / decompression process can be performed faster and more efficiently.

The image compression / expansion processing devices 102 to 106 shown in FIGS. 4 to 8 basically perform the same operations as the image compression / expansion processing device 101 shown in FIG. That is, in any of the second to sixth embodiments, the image compression / expansion processing shown in FIGS. 2 and 3 is executed under the control for the pipeline processing.
It is pointed out that this allows the image compression / decompression process to be performed quickly and efficiently. The details of the pipeline processing will be described later with reference to FIGS. 11 and 12.

Next, the image data transfer in the image encoding process of the portion which transfers the data via the pixel data bus PB in the image data transfer process of the image compression / expansion processor 106 of the sixth embodiment, and 1 The image data transfer amount when processing the image data of one macroblock will be specifically described.

Here, it is assumed that the image data to be encoded is already held in the frame buffer memory 51. As a premise for obtaining the data transfer amount, the image format is 4: 2: 0, the motion detection range is ± 16 pixels,
The structure is a frame.

Under the control of the control unit 2, each unit outputs image data to the pixel data bus PB and inputs image data from the pixel data bus PB. The operation timing of each unit is also managed by the control unit 2.

First, the original image data is transferred from the control unit 2 to the frame buffer memory 51 via the pixel data bus PB. At this time, the amount of image data transferred is 384 pixels.

Next, the luminance component of the reference image (reproduced image) in the motion search range is transferred from the frame buffer memory 51 to the motion prediction unit 46 via the pixel data bus PB for motion prediction. At this time, the amount of image data to be transferred is 768 pixels for one reference image.
Therefore, in bidirectional prediction, it is necessary to transfer 1536 pixels for two planes.

Next, the luminance component of the image to be coded is transferred from the frame buffer memory 51 to the control unit 2 via the pixel data bus PB for motion estimation. Next, the above-mentioned luminance component is sent from the control unit 2 via the local bus LB3 to the motion prediction unit 4
Transfer to 6. At this time, the amount of image data to be transferred is 2
It has 56 pixels.

When the motion prediction process is completed and the inter-frame prediction is performed by the coding judgment using the result, the predicted image (reproduced image) data is transferred from the frame buffer memory 51 to the pixel data bus PB for the coding process. To the pixel processing unit 3 via. At this time, the amount of image data to be transferred is 4 per predicted image.
It has 51 pixels. Therefore, in bidirectional prediction, it is necessary to transfer 902 pixels for two planes.

Next, the image data to be encoded is transferred from the frame buffer memory 51 to the pixel processing unit 3 via the pixel data bus PB. At this time, the amount of image data to be transferred is 384 pixels.

After the encoding is completed, the reproduced image data regarding the intra-frame encoded image and the one-way predicted image is transferred from the pixel processing unit 3 to the frame buffer memory 51 via the pixel data bus PB. At this time, the amount of image data to be transferred is 384 pixels.

The above-mentioned data transfer amount becomes maximum at the time of bidirectional prediction in which all transfer except transfer of reproduced image data is performed, and becomes 3462 pixels.

Here, when the motion search range is widened to improve the image quality, the amount of image data transfer of the luminance component of the reference image in the motion search range increases. For example, if the motion search range is expanded to ± 32 pixels, it is 128 when unidirectionally predicted.
It is necessary to transfer image data of 0 pixels and 2560 pixels at the time of bidirectional prediction.

In the case of digital image data,
There are different data formats depending on the data amount of the color difference component of the image data. That is, the 4: 4: 4 format in which the original image data amount is maintained, the 4: 2: 2 format in which the color difference component is reduced to half, and the 4: 2: 0 format in which the color difference component is reduced to 1/4. There is. Therefore, when the image format to be handled is changed, the image data transfer amount other than the image data transfer amount related to motion prediction increases. For example, format 4:
In the case of 4: 4, the transfer of the original image data, the transfer of the image data to be encoded to the pixel processing unit, and the transfer of the reproduced image data are doubled to 768 pixels, and the transfer of the predicted image data is predicted. It becomes 867 pixels, which is slightly less than twice as much as one surface of the reference image.

As described above, when the number of pixels of an image to be processed such as a high definition image increases, the time required for processing one macroblock increases. When the system clock is fixed, for example, due to an increase in the data transfer amount when processing one macroblock,
The amount of data transfer that can be processed in a cycle is limited by the performance of the hardware. Therefore, the number of cycles of the system clock increases in order to transfer the data.

As described above, when the amount of data transfer is very large and the amount of data transfer increases as the number of pixels is increased and the image quality is increased, the encoding process of one macroblock is used as a unit. When a pipeline is built, the number of cycles required for the data transfer processing required to execute the encoding operation processing is greater than the number of cycles required for the encoding operation processing, so the data transfer processing limits the overall processing speed. To do. Hereinafter, an image compression / decompression processing device that streamlines the data transfer process and does not limit the overall processing speed by the data transfer speed will be described.

(7) Seventh Embodiment FIG. 83 is a block diagram of an image compression / expansion processing device 107 showing a seventh embodiment of the present invention. In FIG. 83,
The same parts as those in the sixth embodiment shown in FIG. 8 are designated by the same reference numerals and the description thereof will be omitted.

Referring to FIG. 83, pixel data bus P
B has a data width of 32 bits and is provided for data transfer between the control unit 23, the pixel processing unit 33 and the frame buffer memory 51.

The local data bus LDB has a data width of 32 bits, and the pixel processing unit 3
3, provided for data transfer between the motion estimation unit 47 and the local memory 56.

The local memory 56 is provided for temporarily storing the luminance component of the reproduced image data used for motion estimation transferred from the pixel processing unit 33. As the local memory 56, SRAM, D
RAM, synchronous DRAM and cache DRA
A large capacity memory such as M is used.

The microprocessor (not shown) for overall control included in the control unit 23 includes a control unit 23, a frame buffer memory 51,
It controls the transfer of image data between the pixel processing units 33, and further controls the pixel processing units 3
3. Control image data transfer between motion estimation unit 47 and local memory 56.

The pixel processing unit 33 newly has a data output port P2 for image data in addition to the data input / output port P1 connected to the pixel data bus PB. The motion prediction unit 47 and the newly provided local memory 56 are connected to the data output port P2 via the local data bus LDB. The data output port P2 of the pixel processing unit 33, the motion prediction unit 47, and the local memory 56 are controlled by the control unit 23, and transfer image data via the local data bus 61. Also,
The control unit 23 also manages each transfer timing.

The image data handled by the local data bus LDB is the motion prediction reference data (at least the image data) extracted from the image data transferred from the frame buffer memory 51 via the pixel data bus PB by the pixel processing unit 33. Of these, data having information indicating luminance, hereinafter referred to as luminance component).
This reference data is transmitted from the data input / output port P1 via the pixel data bus PB to the frame buffer memory 51.
Is transferred to and stored.

An 8-bit dedicated local bus LB4 is provided between the motion prediction unit 47 and the control unit 23. The motion detection target image data is transmitted from the control unit 23 to the motion prediction unit 4
7 is transferred. The motion vector data indicating the motion detection result is transferred from the motion prediction unit 47 to the control unit 23. The control unit 23, the frame buffer memory 51, and the pixel processing unit 23, which are connected to the pixel data bus PB, generate a predicted image and encode the predicted image based on the above motion vector data. The pixel processing unit 33 outputs the encoded image data to the code bus CB.

Next, with reference to FIG. 83, the image data transfer amount in the image encoding process and the image data transfer amount in processing the image data of one macroblock will be described. Here, the encoding target image data is already held in the frame buffer memory 51, and the luminance component of the reference (reproduction) image necessary for motion detection is already in the local memory 56.
Suppose it is held at. As a premise for obtaining the transfer amount, it is assumed that the image format is 4: 2: 0, the motion detection range is ± 16 pixels, and the structure is a frame.

First, the original image data is transferred from the control unit 23 to the frame buffer memory 51 via the pixel data bus PB. At this time, the amount of image data transferred is 384 pixels.

Next, in order to perform the motion prediction, the luminance component of the motion prediction target image is transferred from the frame buffer memory 51 to the control unit 23 in the pixel data bus PB.
Be transferred through. Further, the luminance component is transferred to the motion detection unit 47 via the local bus LB4. At this time, the amount of image data transferred is 256 pixels.

When the motion prediction process is completed and the interframe prediction is performed by the coding determination using the result, the predicted (reproduced) image is transferred from the frame buffer memory 51 to the pixel processing unit 33 in order to perform the coding process. Transfer via the data bus PB. At this time, the amount of image data transferred is 451 pixels for each predicted image. Therefore, at the time of bidirectional prediction, it is necessary to transfer 902 pixels.

Next, the image data to be encoded is transferred from the frame buffer memory 51 to the pixel processing unit 3
3 through the pixel data bus PB. At this time, the amount of image data transferred is 384 pixels.

In parallel with the above four image data transfer, the luminance component of the image in the motion search range for motion estimation is transferred from the local memory 56 to the motion detection unit 47 via the local data bus LDB. At this time, the amount of image data to be transferred is 768 pixels for each reference image surface. Therefore, in bidirectional prediction, 1536
Pixels need to be transferred.

After the coding is completed, for the intra-frame coded image and the one-way predicted image, the reproduced image data is transferred from the pixel processing unit 33 to the pixel data bus P.
It is transferred to the frame buffer memory 51 via B.
At this time, simultaneously, the luminance component of the reproduced image is transferred to the local memory 56 via the local data bus LDB.

At this time, the control unit 23
The pixel processing unit 33 stores the reproduced image data in an internal reproduced image output memory (for example, FIG.
The port P connected to the pixel data bus PB is synchronized with the output timing from the image memory 335) shown in FIG.
An output control signal for controlling 1 is output. At the same time, the control unit 23 outputs an output control signal for controlling the port P2 connected to the local data bus LDB while the luminance data is being output from the reproduced image output memory.

Further, in the pixel processing 33, according to the instruction from the control unit 23 or the sequence program stored in the internal memory (for example, the internal memory in the controller 319 shown in FIG. 19 described later),
Image data is output from the reproduced image output memory. At this time, the port P1 connected to the pixel data bus PB
Outputs the image data for one macroblock in response to the output control signal output from the control unit 23. At the same time, the port P2 connected to the local data bus LDB outputs only the luminance component of the image data for one macroblock in response to the output control signal output from the control unit 23.

In the above-mentioned reproduction image transfer processing, the transferred image data amount is 384 in the pixel data bus PB.
The number of pixels is 256, and the number of pixels is 256 in the local data bus LDB.

As described above, the pixel processing unit 33 for generating a reproduced image is provided with a data output function to the two data buses, and the local data bus LDB is synchronized with the reproduced image output to the pixel data bus PB. The reproduced image of is being output. Therefore, the control of the reproduced image output memory (not shown) inside the pixel processing unit 33 is shared, and data can be transferred to each port connected to the output of the internal memory only by the 1-bit output control signal. As a result, the data transfer control viewed from the control unit 23 becomes easy, and the bus is disassembled by the control unit 23 except when the reproduced image is transferred, and the parallel processing of the data transfer becomes possible.

The amount of data transfer at this time becomes the maximum in bidirectional prediction, and is 1926 pixels in the pixel data bus PB and 1536 pixels in the local data bus LDB. Therefore, by using the two divided data buses, the amount of data transferred by one bus is reduced as compared with the sixth embodiment, and the data transfer speed is substantially improved.
It is possible to improve the processing speed of the image compression / decompression processing device.

(8) Eighth Embodiment FIG. 84 is a block diagram of the image compression / expansion processing device 108 showing the eighth embodiment of the present invention. In FIG. 84,
The same parts as those of the image compression / expansion processing apparatus shown in FIG.

The pixel processing unit 34 newly has two image data output ports P4 and P5. The image data bus includes a pixel data bus PB, two local data buses LDB1 and LDB2.
3 data buses are provided. Each port P3 to P5
Output control operation of the system controller (eg, system controller 11 shown in FIG. 13 described later) included in the pipeline control processor (eg, overall control processor 11 shown in FIG. 9 described later) in the control unit 24.
This is performed by the output control signal output by 4).

By expanding the function of the apparatus,
When enlarged to 64 pixels, it is 230 even in one-way prediction.
It is necessary to transfer the image data amount of 4 pixels. Hereinafter, description will be made assuming that the motion detection range is expanded to ± 64 pixels and unidirectional prediction is performed. In the case of the sixth embodiment shown in FIG. 8, the image data transfer amount becomes 4230 pixels with the expansion of the motion detection range. On the other hand, the case of the eighth embodiment is as follows. In the case of the eighth embodiment, in order to perform motion estimation, the luminance component of the image in the motion search range is divided into two and transferred using two data buses. That is, the local memory 5
6a to prediction unit 47a local data bus LD
At the same time as 1280 pixels are transferred using B1, 1280 pixels are transferred from the local memory 56b to the motion prediction unit 47b using the local data bus LDB2. At this time, since the data at the data delimiter needs to be transferred to each of the data buses LDB1 and LDB2,
23, which is the amount of data when transferred by one data bus
The total amount of data transferred with two data buses for 04 pixels is 2560 pixels. That is, the pixel data for one macro block (256 pixels) is increased. This is to enable the connection of the respective divided reference data to be recognized when the reference data is divided.

In this case, when the reproduced image is transferred, the reproduced image data is transferred from the pixel processing unit 34 to the frame buffer memory 51 using the pixel data bus PB.
And simultaneously transfer the reproduced image to the local memories 56a and 56b using the local data buses LDB1 and LDB2.

The data transfer amount at this time is 1926 pixels in the pixel data bus PB, and the local data bus LD.
Each of B1 and LDB2 has 1280 pixels. That is, by dividing the image data bus into three, the amount of data to be transferred by one bus is reduced, and the substantial data transfer rate is slightly more than doubled compared with the sixth embodiment, and the image compression / compression is performed.
It is possible to improve the processing speed of the decompression processing device.

(9) Ninth Embodiment FIG. 85 is a block diagram of an image compression / expansion processing apparatus 109 showing a ninth embodiment of the present invention. In FIG. 85,
The same parts as those of the image compression / expansion processing apparatus shown in FIG. 84 are designated by the same reference numerals, and the description thereof will be omitted below.

Referring to FIG. 85, the ninth embodiment is an embodiment using a common address bus AB for local memories 56c and 56d. The address bus AB is connected to the control unit 25, and an address signal is output from the control unit 25.

When the motion search range is set to ± 32 pixels in bidirectional motion prediction as an extended function of the image compression / decompression processing device, it is necessary to transfer 1280 pixels for each predicted image plane. Image data transfer will be described below on the assumption that motion search is performed in a range of ± 32 pixels and bidirectional prediction is performed.

First, the data transfer in the case of an intra-frame coded image will be described. For example, local memory 5
If the reproduced image data stored in the local memory 56d is newer (temporally later) than the reproduced image data stored in 6c, or the first image data is encoded (both local memory 56c and If the data is not stored in 56d), the control unit 2
5, data transfer is performed using the frame buffer memory 51, the pixel processing unit 34, the motion prediction unit 47a, the local memory 56c, the pixel data bus PB, and the local data bus LDB1 as in the seventh embodiment. The luminance signal of the reproduced image is stored in the local memory 56c for use as the motion prediction reference image data. At this time, the control unit 25 selects the local memory 56c by the chip select signal to perform the data write control, and the output port P of the pixel processing unit 34 on the side of the local data bus LDB1.
4 to the output control signal.

Next, data transfer in the case of a one-way predicted image will be described. For example, compared with the reproduced image data stored in the local memory 56d, the local memory 56d
If the reproduced image data stored in c is newer (temporally later), the reproduced image data stored in the local memory 56c is used as forward prediction reference image data, and the motion prediction unit 47a, the local memory 56c, and the local data are stored. The image data in the motion prediction search range is transferred using the bus LDB1. At this time, only when transferring the luminance signal of the reproduced image in the motion prediction search range, the control unit 25 uses the chip select signal to generate the local memory 56.
Data output control is performed by selecting c, and the input control signal of the input port on the side of the local data bus LDB1 of the motion prediction unit 47a is given.

For image transfer other than the above (for example, original image transfer, coding target image transfer for motion prediction, forward prediction image transfer, coding target image transfer and reproduced image transfer), the control unit 25 and the frame buffer are used. The memory 51, the pixel processing unit 34, the local memory 56d, the pixel data bus PB, and the local data bus LDB2 are used to perform the transfer as in the seventh embodiment. At this time, the maximum data transfer amount is 1926 pixels in the bidirectional prediction on the pixel data bus PB,
The local data buses LDB1 and LDB2 have a maximum of 1280 pixels each. Here, the luminance signal of the reproduced image is used as the motion prediction reference image data in the local memory 56.
It is stored in d. At this time, the control unit 25
Selects the local memory 56d by the chip select signal to control data writing only when the luminance signal of the reproduced image is transferred, and the output port P5 of the pixel processing unit 34 on the local data bus LDB2 side is selected.
Give an output signal to. Here, the addressing of the local memory 56d is performed in the same manner as the addressing of the local memory 56c.

Next, data transfer in the case of a bidirectionally predicted image will be described. For example, compared with the reproduced image data stored in the local memory 56c, the local memory 56c
If the reproduced image data stored in d is newer (temporally later), the reproduced image data stored in the local memory 56c is used as the forward prediction reference image data, and the motion prediction unit 47a, the local memory 56c, and the local data are stored. Image transfer within the motion prediction search range is performed using the bus LDB1. At this time, at the same time, the reproduced image stored in the local memory 56d is used as a backward prediction reference image to transfer an image in the motion prediction search range using the motion prediction unit 47b, the local memory 56d and the local data bus LDB2. In this case, the control unit 25 uses the chip select signal only when transferring the luminance signal of the reproduced image in the motion prediction search range.
In order to select 6c and 56d, common address bus AB is used to apply the same address signal to perform common data output control. In addition, the control unit 25,
Input control signals of the input ports on the side of local data buses LDB1 and LDB2 of motion estimation units 47a and 47b are applied, respectively.

Image transfer other than the above (for example, original image transfer, motion prediction encoding target image transfer, forward prediction image transfer, backward prediction image transfer, and encoding target image transfer).
With respect to, the control unit 25, the frame buffer memory 51, the pixel processing unit 34, and the pixel data bus PB are used to transfer the image data as in the seventh embodiment.

Further, the forward motion search range and the backward motion search range for the macro block subject to motion prediction are the same range on the actual screen. Therefore, by performing common addressing on the local memories 56c and 56d, it is possible to transfer the prediction search ranges in both directions using a common address. In other words, except for the chip select signals of the local memories 56c and 56d, the hardware related to the memory control and address generation for the local memories 56c and 56d can be shared, and therefore, compared to the case where an address generator is provided for each memory, The amount of hardware can be reduced without increasing the amount of data transfer.

(10) Tenth Embodiment FIG. 86 is a block diagram of an image compression / expansion processing apparatus 110 showing a tenth embodiment of the present invention. 86, the same parts as those of the image compression / expansion processing apparatus shown in FIG. 85 are designated by the same reference numerals, and the description thereof will be omitted.

Referring to FIG. 86, in the tenth embodiment,
The pixel processing unit 34 shown in FIG.
Pixel processing units 34a and 34b
It is divided into two parts.

As a function expansion of the image compression / expansion processing device, when performing a motion search in a range of ± 32 pixels in bidirectional motion prediction, it is necessary to transfer 1280 pixels per predicted image plane. Image data transfer will be described below on the assumption that motion search is performed in a range of ± 32 pixels and bidirectional prediction is performed.

First, the data transfer in the case of an intra-frame coded image will be described. For example, local memory 5
If the reproduced image data stored in the local memory 56d is newer (temporally later) than the reproduced image data stored in 6c, or the first image data is encoded (both the local memories 56c and 56d). If no data is stored in the control unit 26,
Using the frame buffer memory 51, the pixel processing unit 34, the motion prediction unit 47a, the local memory 56c, the pixel data bus PB, and the local data bus LDB1, data transfer is performed as in the seventh embodiment. The luminance signal of the reproduced image is stored in the local memory 56c for use as motion prediction reference image data. At this time, the control unit 26 controls the data write by selecting the local memory 56c by the chip select signal only when transferring the luminance signal of the reproduced image. The control unit 26 also includes a local data bus L of the pixel processing unit 34a.
An output signal is given to the output port P2a on the DB1 side.

Next, the data transfer in the case of a one-way predicted image will be described. For example, compared with the reproduced image data stored in the local memory 56d, the local memory 56d
If the reproduced image data stored in c is newer (temporally later), the reproduced image data stored in the local memory 56c is used as forward prediction reference image data as the motion prediction unit 47a, the local memory 56c and the local data bus. Image transfer within the motion prediction search range is performed using LDB1. At this time, the control unit 26 controls the data output by selecting the local memory 56c by the chip select signal only when transferring the luminance signal of the reproduced image in the motion prediction search range. Further, the control unit 26 gives an input control signal of the input port of the motion prediction unit 47a on the side of the local data bus LDB1.

Regarding image transfer other than the above (original image transfer, transfer target image transfer for motion prediction, forward predictive image transfer, transfer target image transfer and replay image transfer), the control unit 26 and the frame buffer memory 51. ,
The pixel processing unit 34b, the local memory 56d, the pixel data bus PB and the local data bus LDB2 are used to perform the transfer in the same manner as in the seventh embodiment. The luminance signal of the reproduced image is used as the motion prediction reference image, and thus is stored in the local memory 56d. At this time, the control unit 26 controls the data writing by selecting the local memory 56c by the chip select signal only when transferring the luminance signal of the reproduced image. Also,
The control unit 26 gives an output signal to the output port P2b on the side of the local data bus LDB2 of the pixel processing unit 34b. Here, the addressing of the local memory 56d is performed in the same manner as the addressing of the local memory 56c.

Next, the data transfer in the case of a bidirectionally predicted image will be described. When the reproduced image data stored in the local memory 56d is newer (temporally later) than the reproduced image data stored in the local memory 56c,
The reproduced image data stored in the local memory 56c is used as forward prediction reference image data, and the motion prediction unit 47
a, local memory 56c and local data bus L
Image transfer within the motion prediction search range is performed using DB1.
At this time, at the same time, the reproduced image data stored in the local memory 56d is used as backward prediction reference image data to transfer an image in the motion prediction search range using the motion prediction unit 47b, the local memory 56d and the local data bus LDB2. At this time, since the control unit 26 selects the local memories 56c and 56d by the chip select signal only when transferring the luminance signal of the reproduced image in the motion prediction search range, the same address is used by using the common address bus AB. Apply common data output control. In addition, the control unit 26
Provides input control signals of the input ports on the side of the local data buses LDB1 and LDB2 of the motion prediction units 47a and 47b.

For image transfer other than the above (original image transfer, transfer target image transfer for motion prediction, forward predictive image transfer, backward predictive image transfer and transfer target image transfer), the control unit 26 and the frame buffer are used. Memory 51, pixel processing unit 34a or 3
4b and the pixel data bus PB are used to transfer image data as shown in the seventh embodiment. At this time, the image data is transferred to the two pixel processing units 34a and 34b alternately in units of one macro block, and the processing units 34a or 3 are processed.
In 4b, the encoding operation processing for one macroblock is executed using two macroblock processing times.

Generally, when interframe predictive coding is performed, the amount of calculation in bidirectional prediction is large. In this embodiment,
At the time of bidirectional prediction, image data is divided into two pixel processing units 34a and 34 in units of one macroblock.
b, and the calculation time of the macroblock is substantially given to one pixel processing unit 34a or 34b, so that the calculation time of the pixel processing units 34a and 34b at the time of bidirectional prediction is increased as compared with the ninth embodiment. The expansion effect of is obtained.

(11) Eleventh Embodiment FIG. 87 is a block diagram of an image compression / decompression processing device 111 showing an eleventh embodiment of the present invention. The image compression / decompression processing device shown in FIG. 87 has a configuration in which the motion prediction unit 47b connected to the local data bus LDB2 is removed from the configuration of the eighth embodiment shown in FIG.

In this case, the data transfer processing other than the data transfer processing for transferring the original image data from the control unit 27 to the frame buffer memory 51 is performed as follows by dividing the original image data into the luminance component and the color difference component. .

In the case of the luminance component, the encoding target image is set to the frame buffer memory 51 for the intra-frame encoded image.
To the pixel processing unit 35. The reproduced image is transferred to the frame buffer memory 51 and the local memory 56a.

As for the unidirectional predictive coded image,
On the motion prediction side, the image data in the motion search range is transferred from the local memory 56a to the motion prediction unit 47, and the image data to be encoded is transferred from the frame buffer memory 51 to the control unit 27. On the encoding side, the predicted image data is transferred from the frame buffer memory 51 to the pixel processing unit 35, and the image data to be encoded is transferred from the frame buffer memory 51 to the pixel processing unit 35. The reproduced image data is transferred to the frame buffer memory 51 and the local memory 56a.

Regarding the bidirectional predictive coded image, on the motion predicting side, the image data of the motion search ranges for two planes are transferred from the local memory 56a to the motion predicting unit 47, and the image data to be coded is transferred from the frame buffer memory 51. Motion estimation unit 4 via control unit 27
Transfer to 7. Also, on the encoding side, the two predicted image data are transferred from the frame buffer memory 51 to the pixel processing unit 35, and the image to be encoded is transferred from the frame buffer memory 51 to the pixel processing unit 35.

In the case of the color difference component, for the intra-frame encoded image, the image data to be encoded is transferred from the frame buffer memory 51 to the pixel processing unit 35. The reproduced image data is transferred to the local memory 56e.

For a unidirectional predictive encoded image, the image data to be encoded is transferred from the frame buffer memory 51 to the pixel processing unit 35, and the predictive image data is transferred from the local memory 56e to the pixel processing unit 35. The reproduced image data is transferred to the local memory 56e.

Regarding the bidirectional predictive coded image, the color difference signals of the image to be coded are transferred from the frame buffer memory 51 to the pixel processing unit 35, and the predicted image data of the two planes are transferred from the local memory 56e to the pixel processing unit 35. It For a 4: 4: 4 format image with many color difference components, the image transfer amount in each data bus at the time of bidirectional prediction that maximizes the data transfer amount is estimated as follows.

First, the image compression / compression of the sixth embodiment shown in FIG.
In the decompression processing device, the total data transfer amount transferred through the pixel data bus PB in the above format is 4806 pixels.

However, in the image compression / decompression processing apparatus of the eleventh embodiment shown in FIG. 87, in the above-mentioned 4: 4: 4 format, the pixel data bus PB has 768 pixels of the original image data, and two planes of predicted images. The data luminance component of 578 pixels and the encoded image data of 768 pixels are transferred, and the total data transfer amount is 2114 pixels.

In the local data bus LDB1,
When the motion search range is ± 16 pixels, the data transfer amount is 768 pixels for one plane of the predicted image data, and 1536 pixels for the two predicted image data.

Further, since the local bus LB5 transfers the luminance components of the predicted image data for two planes to the color difference components Cb and Cr by 578 pixels, the total data transfer amount is 1156 pixels.

By encoding each pixel data component as described above and providing the added color difference component bus LB5, the data transfer amount of the pixel data bus PB is reduced. Further, by averaging the data transfer amount in each data bus, the data amount transferred in one data bus is reduced, and the data transfer speed is substantially higher than that in the sixth embodiment shown in FIG. This is 2.2 times higher, and the processing speed of the image compression / decompression processing device can be improved.

(12) Twelfth Embodiment FIG. 88 is a block diagram of an image compression / expansion processor 112 showing a twelfth embodiment of the present invention. In the twelfth embodiment shown in FIG. 88, the pixel processing unit 35 of the eleventh embodiment shown in FIG. 87 is divided into two pixel processing units 35a and 35b, and a luminance component process and a color difference component process are assigned to each. It is a thing.

Therefore, in the twelfth embodiment, the pixel processing units 35a and 35b perform the calculation processing for each component, the calculation amount in one pixel processing unit is reduced, and the processing speed of the image compression / expansion processing apparatus is reduced. It becomes possible to improve.

(13) Thirteenth Embodiment FIG. 89 is a block diagram of an image compression / expansion processing device 113 showing a thirteenth embodiment of the present invention. The thirteenth embodiment has, in addition to the configurations of the eleventh and twelfth embodiments, a configuration capable of coping with the expansion of the motion search range.
Specifically, as the motion prediction reference data, the minimum required luminance component is divided and extracted by the plurality of pixel processing units 36a and 36b from the image data transferred from the frame buffer memory 51. The extracted data is stored in the local memories 56a and 56b via the local data buses LDB1 and LDB2, respectively.
Memorized in. Meanwhile, the pixel processing unit 3
5b extracts from the image data transferred from the frame buffer memory 51 a color difference component not used for motion estimation. The extracted color difference component is stored in the local memory 56e via the local bus LB5.

With the above configuration, the pixel data bus P
The data transfer amount of B is 768 pixels of the original image data, 578 pixels of the luminance component of the predicted image data for two planes, and 768 pixels of the encoded image data, which is 2114 pixels in total.

Further, in the local data buses LDB1 and LDB2, when the motion search range is ± 32 pixels, data of 1280 pixels is transferred respectively.

Further, since the local bus LB5 transfers the luminance component 578 pixels of the prediction image data for two planes to each of the color difference components Cb and Cr, a total of 115 pixels are transferred.
Data of 6 pixels will be transferred.

With the above configuration, when the motion search range is expanded and the image format to be handled is set to 4: 4: 4, the data transfer amount on the pixel data bus PB is reduced and the data transfer amount on each bus is reduced. Can be efficiently divided.

(14) Fourteenth Embodiment FIG. 90 is a block diagram of an image compression / decompression processing device 114 showing a fourteenth embodiment of the present invention. In the fourteenth embodiment, the pixel data bus PB and the local data bus LD
A 32-bit bidirectional tri-state buffer 80 connecting B is added. As shown in FIG. 90, the pixel processing unit 37 includes a local data bus LDB.
It is also possible to use the one that does not have the second data output port connected to. The control unit 29 includes a bidirectional tristate buffer 80, a motion prediction unit 4
7 and local memory 56 operations are also controlled. The reference image data for motion prediction is transferred via the local data bus LDB. The transfer timing at this time is also managed by the control unit 29. The bidirectional tri-state buffer 80 can simultaneously execute the data acquisition and the held data output in synchronization with the clock signal output from the control unit 29.

With reference to FIG. 90, the image data transfer amount in the image encoding process and the image data transfer amount in processing the image data of one macroblock will be described.
Here, it is assumed that the image data to be encoded is already stored in the frame buffer memory 51, and the luminance component of the reference (reproduction) image necessary for motion detection is already stored in the local memory 56. As a premise for obtaining the transfer amount, the image format is 4: 2: 0, the motion detection range is ± 16 pixels, and the structure is a frame.

First, the original image data is transferred from the control unit 29 to the frame buffer memory 51 using the pixel data bus PB. At this time, the amount of image data to be transferred is 384 pixels.

Next, the luminance component of the motion prediction target image for motion prediction is transferred from the frame buffer memory 51 to the control unit 29 using the pixel data bus PB, and further using the dedicated local bus LB4. Transferred to the motion estimation unit 47. At this time,
The amount of image data to be transferred is 256 pixels.

When the motion prediction process is completed and the interframe prediction is used in the coding determination using the result, the predicted (reproduced) image is transferred from the frame buffer memory 51 to the pixel processing unit 3 in order to perform the coding process.
7 through the pixel data bus PB. At this time, the amount of image data to be transferred is 4 per predicted image.
It has 51 pixels. Therefore, in bidirectional prediction, 90
Two pixels of data need to be transferred.

Next, the image to be encoded is transferred from the frame buffer memory 51 to the pixel processing unit 37 using the pixel data bus PB. At this time, the amount of image data to be transferred is 384 pixels.

In parallel with the above-mentioned four image data transfer processes, in order to perform motion estimation, the luminance component of the image in the motion search range is transferred from the local memory 56 to the motion prediction unit 47 using the local data bus LDB. At this time, the amount of image data to be transferred is 76 per reference image.
It has 8 pixels. Therefore, in bidirectional prediction, it is necessary to transfer data of 1536 pixels for two planes.

After the coding is completed, the reproduced image data is transferred from the pixel processing unit 37 to the pixel data bus PB for the intra-frame coded image and the one-way predicted image.
Is transferred to the frame buffer memory 51 by using. At the same time, the reproduced image data is transferred to the bidirectional tristate buffer 80. Further, the reproduced image is transferred from the bidirectional tristate buffer 80 to the local memory 56 via the local data bus LDB with a delay of one system cycle. Control unit 29
Controls the data transfer to the local memory 56 via the bidirectional tristate buffer 80 only when the luminance component of the reproduced image is being transferred. At this time, the amount of image data to be transferred is 384 pixels in the pixel data bus PB and 256 pixels in the local data bus LDB.

As described above, the control unit 29
However, by providing a system controller (not shown) that controls data transfer to the local memory 56 via the bidirectional tri-state buffer 80 only when transferring the luminance component of the reproduced image, the pixel processing is performed. The unit 37 does not have to have a second data output port directly connected to the local data bus LDB,
As in the seventh embodiment shown in FIG. 3, the bus can be divided, and parallel processing of data transfer becomes possible.

At this time, the data transfer amount is the same as that of the seventh embodiment shown in FIG. 83, and becomes the maximum in bidirectional prediction.
Specifically, 1926 pixel data is transferred to the pixel data bus PB, and 1 is transferred to the local data bus LDB.
Data of 536 pixels is transferred. Therefore, by dividing the bus, the amount of data transferred by one bus is reduced, the data transfer speed is substantially improved, and the processing speed of the image compression / expansion processing device can be improved.

(15) Fifteenth Embodiment FIG. 91 is a block diagram of an image compression / expansion processing apparatus 115 showing a fifteenth embodiment of the present invention. The fifteenth embodiment has a configuration in which bit stream data is input and output via the buffer memory 6 and the communication device 94 outside the device. The buffer memory 6 temporarily stores bit stream data and run / level data obtained by encoding pixel data by a variable length processor (not shown) included in the control unit 23.
Therefore, only the bit stream data can be transferred without going through the host computer 93, and the transfer speed can be improved.

That is, in the host computer 93, many complicated processes such as instruction control occur in addition to the data transfer process, and the load on the host computer 93 becomes heavy.
Therefore, the communication device 94 is provided outside the image compression / expansion processing device 115, data can be transferred from the buffer memory 6 to the communication device 94 without passing through the host computer 93, and the load on the host computer 93 does not depend,
Data can be transferred at high speed.

2. Control Unit (1) Control Unit 21 (First Example) FIG. 9 is a block diagram showing an example of the control unit. The control unit 21 shown in FIG. 9 can be applied to the control unit 2 shown in FIGS. 1, 5, 6, 7 and 8.

Referring to FIG. 9, control unit 2
1 includes a processor 11 for overall control including pipeline processing control, a processor 12 for variable length coding and decoding processing, and a motion prediction unit (see FIG. 1).
Control unit 13 for the motion prediction unit 41), the image format conversion unit 14 for image format conversion, and the image data transfer control unit 1 shown in FIG.
5 and an instruction transfer unit 16 for the pixel processing unit (eg unit 3 shown in FIG. 1),
The main port 17 connected to the host bus (bus HB shown in FIG. 1) and the pixel bus (bus P shown in FIG. 1)
B) connected to an image data port 18, a VRAM port 19 connected to an input / output bus (bus IOB shown in FIG. 1), and a code data bus (code bus CB shown in FIG. 1). And a code data port 20.

In FIG. 9, generally, "DT" indicates a data signal, "ADR" indicates an address signal,
“Sc” indicates a control signal.

Each of the units 12 to 16 is connected to the overall control processor 11 via the bus and receives an instruction given from the overall control processor 11. Each unit 12
Nos. 16 to 16 independently perform processing in accordance with the given instruction.

The control unit 13, the format conversion unit 14 and the image data transfer control unit 15 are connected via a bus for pixel data, and the pixel data is transferred under the control of the image data transfer control unit 15. .

The main port 17 is connected to the overall control processor 11 and the variable length processor 12. When data is transferred between the overall control processor 11 and the variable length processor 12 and the buffer memory 6 and the work memory 7 shown in FIG. 1, the data is transferred through the main port 17.

The image data port 18 is connected to the image data transfer control unit 15. The image data transfer control unit 15 and the frame buffer memory 51 shown in FIG.
Data transfer between and is performed via the image data port 18. When the transfer destination of the frame buffer memory 5 is the motion prediction unit 41 or the pixel processing unit 3, the image data port 18 outputs a control signal indicating data validity / invalidity.

The VRAM port 19 is connected to the image format conversion unit 14. Data transfer between the image format conversion unit 14 and the input / output memory 81 shown in FIG. 1 is performed via the VRAM port 19.

Next, the image compression process will be described with reference to FIGS. It is assumed that the image data to be compressed is stored in the frame buffer memory 51 shown in FIG. The overall control processor 11 first transfers image data from the frame buffer memory 51 to the image format conversion unit 14 by giving an image data transfer command to the image data transfer control unit 15. The end of data transfer is notified from the image data transfer control unit 15 to the overall control processor 11.

Next, the overall control processor 11 sends the image format conversion instruction to the image format conversion unit 1.
Give to 4. The image format conversion unit 14 performs arithmetic processing for image format conversion. That is, in the image format conversion unit 14, the color difference signal sub-sample and the RGB format are converted into YU.
Conversion processing to the V format is performed. The image format conversion unit 1 finishes the format conversion process.
4 to notify the overall control processor 11.

Further, the overall control processor 11 gives an image data transfer command to the image data transfer control unit 15 to transfer the converted image data from the image format conversion unit 14 to the frame buffer memory 51.
Transfer to. The end of data transfer is notified from the image data transfer control unit 15 to the overall control processor 11.

In order to execute the processing for motion prediction and coding mode determination, the overall control processor 11 transfers image data for motion prediction processing from the frame buffer memory 51 to the motion prediction control unit 13. This data transfer is performed by giving an image data transfer command from the overall control processor 11 to the image data transfer control unit 15. The end of data transfer is notified from the image data transfer control unit 15 to the overall control processor 11.

If necessary, the overall control processor 11
A data sub-sampling instruction is given to the motion prediction control unit 13, whereby the motion prediction control unit 13 performs sub-sampling of the image data to be motion predicted. The end of the data sub-sampling is notified from the control unit 13 to the overall control processor 11.

Next, the overall control processor 11 gives a motion estimation control unit 13 a mode evaluation value calculation instruction for intraframe coding. The control unit 13 performs a calculation for the evaluation value in the intra-frame coding mode on the motion prediction target data (data subsampled as necessary). The control unit 13 notifies the overall control processor 11 of the end of this calculation.

Further, the overall control processor 11 gives a data transfer instruction to the image data transfer control unit 15,
The image data transfer control unit 15 transfers the image data of the motion search area from the frame buffer memory 51 to the motion prediction unit 41. The end of data transfer is notified from the image data transfer control unit 15 to the overall control processor 11.

Next, the overall control processor 11 gives a motion prediction target data transfer command to the motion prediction unit control unit 13, and the control unit 13 performs motion prediction on the detection target data (data subsampled as necessary). Transfer to unit 41. The end of data transfer is notified from the image data transfer control unit 15 to the overall control processor 11.

After the search target image data and the motion prediction target image data are transferred, the motion prediction unit 41 starts the motion prediction processing, and after a while, the motion prediction result, that is, the motion vector data and the inter-frame code relating to the motion vector. Generated evaluation mode evaluation value data.

After a certain time has passed, the overall control processor 11 gives the motion prediction control unit 13 a command for receiving the motion prediction result, and the control unit 13 sends data indicating the motion prediction result from the motion prediction unit 41. Receive. The control unit 13 notifies the overall control processor 11 of the end of data reception.

Next, the overall control processor 11 causes the intra-frame coding mode evaluation value data obtained by the calculation in the motion prediction control unit 13 and the inter-frame coding mode evaluation value data obtained by the calculation in the motion prediction unit 41. The encoding mode is determined based on
The encoding mode is determined by the buffer memory 6 shown in FIG.
This is performed by referring to the encoding mode determination table data stored in or executing a comparison operation on the evaluation data.

After the coding mode is determined, source coding processing, that is, DCT processing and quantization processing is performed. First, the overall control processor 11 gives an image data transfer command to the image data transfer control unit 15, and the image data transfer control unit 15 transfers the data to be encoded from the frame buffer memory 51 to the pixel processing unit 3. The data transfer is completed by the image data transfer control unit 15 to the overall control processor 11
Will be notified.

Next, the overall control processor 11 gives a source encoding instruction to the pixel processing unit 3 via the pixel processing unit instruction transfer unit 16. The pixel processing unit 3 performs a source coding operation, that is, a DCT operation and a quantization operation, in response to the source coding instruction. Completion of the operation is notified from the pixel processing unit 3 to the overall control processor 11 via the instruction transfer unit 16.

After the source coding operation, that is, the DCT process and the quantization process, the variable length coding process is performed. That is, the overall control processor 11 gives an instruction to the pixel processing unit 3 via the instruction transfer unit 16 to request the transfer of processed data. The pixel processing unit 3 transfers the processed data to the variable length processor 12 in response to this instruction. Instruction transfer unit 1 ends the data transfer.
The pixel processing unit 3 notifies the overall control processor 11 via 6.

Since the variable length coding process, that is, the entropy coding process is performed, the overall control processor 11
Provide entropy coding instructions to variable length processor 12. The variable length processor 12 executes an entropy coding process. In the entropy coding process, code conversion process using Huffman code or the like is performed. That is, the variable-length processor 12 executes the code conversion by referring to the code conversion table data stored in the work memory 7 for the data obtained by the source encoding process. The end of the entropy coding process is notified from the variable length processor 12 to the overall control processor 11.

After the entropy coding process is performed,
The overall control processor 11 provides the variable length processor 12 with an instruction requesting the transfer of processed data. The variable length processor 12 transfers the processed data to the buffer memory 6. The end of data transfer is notified from the variable length processor 12 to the overall control processor 11.

As can be seen from the above description, the image data compression processing is performed independently in each processing unit 13, 14, 15 and 16 in the control unit 21 and in the variable length processor 12 under the overall control by the overall control processor 11. Can be done. That is, the image format conversion processing by the image format conversion unit 14, the motion prediction by the motion prediction unit 41 and the motion prediction unit control unit 13, the arithmetic processing for the coding mode evaluation value, and the image data transfer control unit 1
5, the image data transfer by 5, the source coding operation by the pixel processing unit 3, and the entropy coding operation by the variable length processor 12 can all be executed independently and in parallel. Therefore, the overall control processor 1
1 executes the above processing for each macroblock data of the image under pipeline processing control. The pipeline process of the above process will be described later in detail with reference to FIGS. 11 and 12, but the pipeline process can realize a very efficient image compression process.

Similarly to the image compression processing described above, the image expansion processing is also performed under the overall control of the overall control processor 11.
Each processing in the control unit 21 is performed independently. In the image expansion processing, the code data stored in the buffer memory 6 is inversely converted, and finally the expanded image data is transferred to the input / output memory 81 shown in FIG. 1 via the image format conversion unit 14. To be done.

(2) Control unit 22 (second
Example) FIG. 10 is a block diagram showing another example of the control unit. Control unit 22 shown in FIG.
Is applied as the control unit 22 shown in FIG. Compared to the control unit 21 shown in FIG. 9, the control unit 22 does not include the motion prediction unit control unit 13. That is, since the image compression / expansion processing device 102 shown in FIG. 4 does not require the motion prediction process, the motion prediction unit control unit is excluded from the control unit 22 according to this point.

It is pointed out that the control unit 22 shown in FIG. 10 operates similarly to the control unit 21 shown in FIG. 9, except for the motion prediction process. Therefore, the same advantage as the control unit 21 shown in FIG. 9, that is, each internal unit in the control unit 22 can operate independently and in parallel, and efficient image data compression processing can be performed under pipeline processing control. Can be done.

(3) Pipeline Processing The overall control processor 11 shown in FIG. 9 and FIG.
Pipeline processing is executed in the image compression / expansion processing apparatus as follows.

FIG. 11 is a time chart showing a pipeline process performed under the control of the overall control processor 11 shown in FIG. Referring to FIG. 11, the horizontal axis represents the passage of time and the vertical axis represents the processing steps for image compression. In the image compression processing, one frame data to be processed is divided into a large number of macroblocks MB, and the processing for image compression is performed for each macroblock data. In the example shown in FIG. 11, an example in which 10 pieces of macroblock data MB1 to MB10 are handled is shown.

As an example, a case where one macroblock data MB1 is processed will be described with reference to FIG. First, in the period T1, the RGB data of the macroblock data MB1 is transferred from the input / output memory 81 shown in FIG. 1 to the control unit 2 (step S1). In the period T2, the image format conversion unit 14 shown in FIG. 9 converts the RGB data into YUV data (step S2).

In the period T3, the YUV data is transferred to the frame buffer memory 51 and the image data to be searched is transferred to the control unit 2. At the same time, the search target image data is also transferred to the motion prediction unit 41 via the pixel data bus PB (step S).
3).

In the period T4, the motion prediction unit 41
The motion prediction process is performed (step S4). In the period T5, the control unit 2 performs a coding mode determination process (step S5).

In the period T6, the image data to be encoded is transferred from the frame buffer memory 51 to the pixel processing unit 3, while the reference image data is transferred to the pixel processing unit 3 via the pixel data bus PB (step S6). S6).

In the period T7, the pixel processing unit 3 performs image calculation processing for encoding, that is, DCT processing and quantization processing (step S7). In the period T8, the processed data, that is, the run-level data is transferred to the buffer memory 6 via the code bus CB (step S8).

In the period T9, the variable length coding process is performed by the variable length processor 12 shown in FIG. 9 (step S9). In the period T10, the processed data, that is, the variable length code data is transferred to the buffer memory 6 via the code bus CB (step S1).
0).

As described above, the image compression / expansion processing device 1
In 01, pipeline processing is performed under the control of the overall control processor 11. Therefore, as shown in FIG. 11, the other macroblock data MB2 to MB1.
Also for 0, corresponding processing is sequentially performed in the periods T2 to T10 similarly to the macroblock data MB1.

FIG. 12 shows one period T1 shown in FIG.
It is a parallel operation figure which shows the parallel operation in 0. That is, FIG. 11 shows an operating state of each internal unit in the image compression / expansion processing device 101 and the control unit 21 shown in FIGS. 1 and 9 in the period T10. Referring to FIG. 12, the input / output bus IOB has a tenth macroblock MB10 in the period T10.
RGB data has been transferred (step S1 shown in FIG. 11). The pixel data bus PB executes data transfer for the eighth macroblock MB8 and the fifth macroblock MB5 (steps S3 and S6). The code bus CB includes a third macro block MB3 and a first macro block M.
Data transfer for B1 is being executed (step S
8 and S10).

The overall control processor 11 controls the transfer of RGB data for the tenth macroblock MB10 (step S3), and in parallel with this, the sixth control is performed.
Encoding mode determination processing is performed for the th macroblock MB6 (step S5). In addition to this, the overall control processor 11 controls the macro blocks MB1 to M
Sequence control for B10, that is, control for pipeline processing is performed.

The variable length processor 12 performs the variable length coding process for the second macroblock MB2 (step S9). The instruction transfer unit 16 has a fourth
The image calculation processing control for the th macroblock MB4 is performed (step S7).

The motion prediction unit control unit 13 is
Motion prediction processing control is performed for the seventh macroblock MB7 (step S4). The image data transfer control unit 15 controls data transfer for the eighth macroblock MB8 and the fifth macroblock MB5 (step S8).

The image format conversion unit 14 performs the format conversion process (RGB to YUV) for the ninth macro block MB9 (step S).
2). The pixel processing unit 3 performs image calculation processing on the fourth macroblock MB4 (step S7). The motion prediction unit 4 performs a motion prediction process on the seventh macroblock MB7 (step S4).

(4) Configuration of Internal Units (i) Overall Control Processor 11 (FIG. 13) FIG. 13 is a block diagram of the overall control processor 11 shown in FIG. Referring to FIG. 13, the overall control processor 11 includes an instruction memory 111 and a program controller 112.
A sequence controller / address calculator 113, a system controller 114, a calculation register file 115,
And a data calculator 116. In this figure, "D
"T" indicates data, "ADR" indicates an address signal, "ID" indicates instruction data, "Ssc" indicates a state control signal, and "Sc" indicates a control signal.

(Ii) Motion Prediction Control Unit 13 (FIG. 14) FIG. 14 is a block diagram of the motion prediction control unit 13 shown in FIG. 14, the motion prediction control unit 13 includes a mode / timing controller 131 for the motion prediction unit, an overall controller 132, a vector data processor 133, a motion detection target image data processor 134, Intra-frame coding mode evaluation value calculator 135
Including and

The mode / timing controller 131 outputs the control signal Smc for the motion prediction unit 41.
The vector data processor 133 also includes the motion prediction unit 41.
For outputting the control signal Smc. The vector data processor 133 receives the data Dmr indicating the motion detection result from the motion prediction unit 41. The motion detection target image data processor 134 outputs the motion detection target image data Dmi and the control signal Smc for the motion prediction unit 41. The motion detection target image data processor 134 supplies the pixel data PD to the intra-frame coding mode evaluation value calculator 135.

(Iii) Image Format Conversion Unit 14 (FIG. 15) FIG. 15 is a block diagram of the image format conversion unit 14 shown in FIG. Referring to FIG. 15, the image format conversion unit 14 includes an overall controller 141 and a V controller.
It includes a RAM controller 142, a color converter 143, a UV filter 144, and an image memory 145.

The general controller 141 uses the main data bus M
Data DT and address signal ADR are received via B. The VRAM controller 142 is connected to the VRAM port 19. The image memory 145 receives the pixel data PD via the internal pixel data bus IPB and supplies the stored data.

(Iv) Image data transfer control unit 1
5 (FIG. 16) FIG. 16 shows the image data transfer control unit 1 shown in FIG.
5 is a block diagram of FIG. Referring to FIG. 16, the image data transfer control unit 15 includes an overall controller 151, an image data memory controller 152, and an image data transfer controller 15.
3 and a pixel data bus transfer controller 154.

In FIG. 16, “Simc” indicates an image data memory control signal, “Sptc” indicates an image data transfer control signal for the pixel processing unit 3, and “Smtc” indicates an image for the motion prediction unit 41. 3 shows a data transfer control signal.

(V) Instruction Transfer Unit 16 (FIG. 17) FIG. 17 is a block diagram of the instruction transfer unit 16 shown in FIG. Referring to FIG. 17, the instruction transfer unit 16 for the pixel processing unit 3 includes an overall controller 161, an instruction transfer controller 162, and a status monitor 16.
Including 3 and. The instruction transfer controller 162 outputs the control signal Spc for the pixel processing unit 3.
The state monitor 163 is the pixel processing unit 3
From the status signal Sps. Overall controller 161 receives data DT and address signal ADR via main data bus MB.

As described above, the internal units 13, 14, 15 and 16 shown in FIGS.
After receiving a signal requesting the start of each processing from the overall control processor 11 shown in FIG.
Return to 1. That is, each internal unit 13, 14, 15
It is pointed out that and 16 can individually execute processing in response to the processing start signal from the overall control processor 11. Therefore, under the control of the overall control processor 11, data processing for image compression and image expansion can be efficiently performed by pipeline processing.

(5) Control Unit 200 (Third Example) FIG. 92 is a block diagram showing still another example of the control unit. The control unit 200 shown in FIG. 92 is applied as the control unit shown in FIGS. 1, 5 to 8, and 84 to 91.

Referring to FIG. 92, control unit 200 includes host interface unit 201 connected to host bus HB, overall control unit 202 for performing various controls including pipeline control, and video connected to input / output bus IOB. Codes between the input / output unit 203, the main processor 204 that executes a program written in macro code, the frame memory control unit 205, the motion prediction unit control unit 206 that also controls the motion prediction frame memory, and the pixel processing unit. A code data control unit 207 for handling data, a parameter calculation unit 208, and a variable length processor 209 for variable length code decoding are included.

Further, the control unit 200 is
As the internal bus, the first internal bus 21 connected between the video input / output unit 203 and the frame memory control unit 205.
0, the frame memory control unit 205, the motion prediction unit control unit 206, the second internal bus 211 connected to the parameter calculation unit 208, and the motion prediction unit control unit 212.
Between the frame memory control unit 205 and the third
Internal bus 212, fourth internal bus 21 connected between code data control unit 207 and variable length processor 209
3, main bus 2 connected to all blocks
Including 14.

Next, the configuration and operation of each block will be described. The host interface unit 201 is a control unit that controls data transfer between an external host computer and the control unit 200. Data input or output via the host interface unit 201 is transferred via the main bus 214 connected to each block inside the control unit 200.

The overall control unit 202 is a block which mainly manages each operation timing and pipeline processing in the control unit 200. Overall control unit 20
In image coding, 2 generates an internal sync pulse in picture units or macroblock units based on a basic clock and a sync signal, and manages and transfers main parameters in coding.

The video input / output unit 203 is shown in FIG.
3 has an interface with the input / output memory 81 shown in FIG.
Inside the control unit 200, the frame memory control unit 205 is connected via a first internal bus 210.

The main processor 104 is a block mainly responsible for adaptive processing in encoding, and details thereof will be described later. When competing with the host interface unit 201, the main processor 104 determines that the main bus 2
It becomes the master of 14 and transfers the data of the register / memory in each block.

The frame memory control unit 205 serves as an external interface between the frame buffer memory (for example, the frame buffer memory 51 shown in FIG. 83) and the pixel processing unit (for example, the pixel processing unit 33 shown in FIG. 83). It has a 32-bit interface that serves as a master of the bit pixel data bus (for example, pixel data bus PB shown in FIG. 83). The frame memory control unit 205
A control signal including an address for the frame buffer memory and a control signal for the pixel processing unit are output. The frame memory control unit 205 is connected to the video input / output unit 203 via the first internal bus 210 in the control unit 200, and via the parameter control unit 208, the motion prediction unit control unit 206, and the second internal bus 211. The third internal bus 2 is connected to another interface of the motion prediction unit controller 206.
It is connected via 12.

The motion prediction unit control section 206 uses the motion prediction unit (for example,
It has an interface for outputting a control signal to the motion prediction unit 47) shown in FIG. 83 and an interface for outputting a control signal including an address to a local memory (for example, the local memory 56 shown in FIG. 83). In addition, the motion prediction unit control unit 206 receives template data (image data) between itself and the motion prediction unit.
Bus for transferring parameters such as motion vector and motion vector (for example, local bus LB4 shown in FIG. 83)
Has an interface to. Furthermore, the motion prediction unit control unit 206 is connected to the frame memory control unit 205 and the parameter control unit 208 via the second internal bus 211 in the control unit 200, and connects the frame memory control unit 205 and the third internal bus 212. Connected through.

The code data control unit 207 is connected to a pixel processing unit (eg, pixel processing unit 33 shown in FIG. 83) and a buffer memory (eg, buffer memory 6 shown in FIG. 83) and a code bus (eg, code bus). It has an interface connected to the code bus CB shown in FIG. The code data control unit 207 is connected to the variable length processor 209 via the fourth internal bus 213 inside the control unit 200.

The parameter calculation section 208 is connected to the frame memory control section 205 and the motion prediction unit control section 206 via the second internal bus 211. Template data is input from the frame memory control unit 205 to the parameter calculation unit 208 via the second internal bus 211,
The parameter calculation unit 208 extracts parameters related to the template. The parameter calculation unit 208 has a register for storing the calculation result therein. The calculation result stored in the register can be transferred (read) via the main bus 214 (slave operation).

The variable length processor 209 is connected to the code data control unit 207 via the fourth internal bus 213. The variable-length processor 209 performs variable-length coding processing on the quantization index or run / level type data transferred from the code data control unit 207. The bitstream data generated by the variable length processor 209 is transferred to the frame buffer memory (for example, the frame buffer memory 51 shown in FIG. 83).

Next, the processing contents of each block in the control unit 200 in the image encoding processing will be described in detail with reference to FIGS. 83 and 92.

The control unit 23 has a function of controlling the pixel processing unit 33 and the motion prediction unit 47 and performing an encoding process. Therefore, the following four types of data control are mainly performed.

(1) Acquisition of original image data and storage in frame buffer memory 51 (2) Acquisition of template data for motion estimation and activation of motion estimation unit 47 (3) Acquisition and determination of motion estimation results and pixel processing Activation of Unit 33 (4) Acquisition of Code Data (Quantization Index / Run Level), Variable Length Processing, and Writing to Buffer Memory 6 The above four types of data control will be described below, including the operation of each block.

(I) Acquisition of original image data to writing to frame buffer memory 51 (mapping) Original image data (original image data to be encoded) stored in an external input / output memory is in so-called macroblock units. It is cut out and transferred to the video input / output unit 203.

The video input / output unit 203 internally has a conversion circuit from RGB format to YUV format and a filter circuit, and performs format conversion (for example, RGB → YUV, 4: 2: 2 → 4: 2: 0). Etc.) is performed. The processed data is transferred to the frame memory control unit 205 via the first internal bus 210. The frame memory control unit 205 is the frame memory control unit 20.
Data transferred in a format suitable for the subsequent encoding process is mapped (written) on the frame buffer memory 51 managed by 5. The mapping method here will be described in detail later.

The frame memory control unit 105 takes charge of generating an address for the frame buffer memory 51. The overall control unit 202 manages the control of the frame buffer memory 51 and the timing of data transfer from the video input / output unit 203.

(Ii) Acquisition of template data for motion prediction and control of motion prediction unit The frame memory control unit 205 performs motion prediction for a macroblock to be coded, and therefore image data corresponding to that macroblock Is read from the frame buffer memory 51. This data is called template data. The frame memory control unit 205 transfers the template data to the motion prediction unit control unit 206 and the parameter calculation unit 208.

The motion prediction unit control section 206 transfers the template data to the motion prediction unit 47 via the local bus LB4 and, at the same time, searches the search window data corresponding to the template data in the local memory 56.
To the local data bus LDB. Further, the motion prediction unit control unit 206 inputs a control signal such as start control to the motion prediction unit 47 to start the motion prediction operation for the template data.

Further, the frame memory control unit 205 is
The template data is transferred to the motion prediction unit control unit 206 via the second internal bus 111, and at the same time, transferred to the parameter calculation unit 208. Parameter calculator 20
In 8, the characteristic held by the template data is extracted by a predetermined calculation, and is used later for determination at the time of encoding. The parameters obtained here are the variance (only the luminance signal) of each block (in both field / frame blocking) in the template for activity calculation, the average value and the variance value of the luminance signal of the template macroblock, etc. Intended for what you need.

(Iii) Acquisition and determination of motion estimation result and activation of pixel processing unit After activation of the above motion estimation unit, a few macroblock cycles later, the result of motion estimation, that is, horizontal and vertical directions in each motion estimation mode and directly behind. The motion vector and its evaluation function are taken into the motion prediction unit control unit 206 via the local bus LB4.

The motion prediction unit control section 206 determines the prediction mode and motion vector using the above evaluation function. The determined motion vector is transferred to the frame memory control unit 205 via the third internal bus 212. The frame memory control unit 205 calculates the address of the predicted image based on the input motion vector. The frame memory control unit 205 determines the frame buffer memory 51 and the pixel processing unit 33 based on the calculated address.
To transfer the predicted image data corresponding to the motion vector to the pixel processing unit 33.

Further, the frame memory control unit 205 is
Further, the template data (which needs to be newly transferred because the pipeline is different from the template data described above) is processed in the same manner as above.
3 and activates the pixel processing unit 33, so that the processing after DCT can be performed by the pixel processing unit 33. Here, a command for activation and a parameter (for example, a half-pel filter instruction) necessary for encoding in the pixel processing unit 33 are stored in the pixel via the code data control unit 207 or the host interface unit 201 in the same pipeline. It is set in a predetermined register in the processing unit 33. Pixel processing unit 3
In No. 3, it can be set from both of the above ports.

(Iv) Acquisition of code data and variable length processing and writing to buffer memory The data processed (filtering, DCT, quantization, etc.) by the pixel processing unit 33 is controlled by the overall control unit 202 by the code bus. It is once written in the buffer memory 6 via the CB or is directly transferred to the code data control unit 207 of the control unit 23. In this case, the data format is a quantization index (quantized data) or run level data (the quantization index is converted to a run level).

The code data control unit 207 receives the above data at an arbitrary timing and transfers it to the variable length processor 209 via the fourth internal bus 213. The variable length processor 209 performs so-called Huffman coding processing on this data according to the microprogram and writes the data in the external buffer memory 6. Further, it is also possible to access the table data stored in the work memory 7 at the time of code conversion processing such as Huffman coding.

Next, how the main processor 204 is involved in encoding in the above processing will be described.

When it is desired to perform another determination process other than the determination process performed in the motion prediction unit control unit 206, for example, when the user wants to use his or her own determination method, the following process is performed. The main processor 204 accesses, via the main bus 214, a register that stores a vector and an evaluation value in each prediction mode in the motion prediction unit control unit 206. The vector and the evaluation value are uniquely processed in the macro code and returned to the original register within a fixed time. As a result, application processing such as determination can be performed.

Further, the main processor 204 mainly performs processing in a higher hierarchy than the macro block layer (in the MPEG1 / 2 standard). That is, the main processor 204 is in charge of processing performed in GOP / picture / slice units. For example, the main processor 204 sets the coding parameter of the next picture based on the code amount when the previous picture is coded. The main processor 204 also handles exceptional mode processing such as rate control, synchronous refresh, and forced intra control. The main processing of the macroblock layer is adaptive quantization processing performed based on the calculated activity.

As described above, the main processor 204
Can access the register or the memory of each unit in the control unit 23, so that if it is within an allowable processing step, the register or the memory is referred to and the processing such as the operation is performed. The contents of can be rewritten. Therefore, it is possible to improve the degree of freedom in the encoding process.

As can be seen from the above description of the encoding operation process, the encoding process is performed by the control unit 23.
Under pipeline control by the overall control unit 202 in
It is performed independently in each processing unit. That is,
All of the above four data controls are executed independently and in parallel. Similarly to the above-described encoding process, the image decoding process can also be executed by the blocks in the control unit 23 operating in parallel under the pipeline process of the overall control unit 202.

3. Pixel Processing Unit (1) Pixel Processing Unit 31 (Fig. 18,
FIG. 19) FIG. 18 is a block diagram showing an example of a pixel processing unit. The pixel processing unit 31 shown in FIG. 18 is used as the pixel processing unit 3 shown in FIG. 1, for example.

Referring to FIG. 18, the pixel processing unit 31 includes a host interface (I / F) circuit 311, a local memory group 312, a DCT / ID.
CT calculator 313, quantizer 314, and filter 31
5, a selector bus 316, a code data bus interface circuit 317, a pixel bus interface circuit 318, and a controller 319.

The host interface circuit 311 is provided for data input / output between the host processor, that is, the control unit 2 and the pixel processing unit 31. The pixel bus interface circuit 318 is provided for inputting / outputting image data.
The code data bus interface circuit 317 is provided for inputting / outputting code data.

The DCT / IDCT calculator 313 is
The arithmetic processing and the inverse DCT arithmetic processing are performed. Quantizer 3
14 is provided for performing a quantization operation. The filter 315 is provided to generate reference image data in the motion prediction process. The selector bus 316 is provided for transferring internal data in the pixel processing unit 31. The controller 319 is provided for overall control in the pixel processing unit 31.

FIG. 19 is a more detailed block diagram of the pixel processing unit 31 shown in FIG. The local memory group 312 shown in FIG. 18 includes the image memories 331 to 335 and the data memory 34 shown in FIG.
1, 342, a code data memory 343, and a parameter memory 344. The selector bus 316 shown in FIG. 18 is the selector buses SB1 to SB shown in FIG.
Including B5.

The image memory 331 is provided to store image data to be compressed. The image memories 332 and 333 store the reference image data of the preceding frame and the following frame. The image memory 334 stores the processed reference image data after the filtering process. The image memory 335 stores the image data to be decoded. The code data memory 343 stores the code data after the quantization processing. Parameter memory 344
Stores calculation table data such as a quantization matrix.

The selector bus SB1 has a bus width of 12 bits and transfers the reference image data after filtering. The selector bus SB2 has a bus width of 12 bits and transfers the difference data after the difference calculation process and after the inverse DCT calculation. Selector bus SB3 has 12
It has a bus width of bits and is provided to transfer the DCT coefficients after the DCT operation and after the inverse quantization.
The selector bus SB4 has a bus width of 12 bits and is provided for transferring code data after the inverse quantization process and after zero unpacking. Selector bus S
B5 has a bus width of 16 bits and is provided to transfer parameter data.

(2) Pixel processing unit 3
2 (FIGS. 20 and 21) FIG. 20 is a block diagram showing another example of the pixel processing unit. The pixel processing unit 32 shown in FIG. 20 can also be used as the pixel processing unit 3 shown in FIG. 1, for example.

Referring to FIG. 20, compared with the pixel processing unit 31 shown in FIG. 19, the pixel processing unit 32 further includes a programmable processing unit 320. Programmable processing unit 320 is connected to selector bus 326 and is capable of performing various other operations in accordance with programs stored in unit 320.

For example, the programmable processing unit 320 uses the stored program to perform frequently used operations, that is, addition / subtraction, difference absolute value sum operation, difference absolute value accumulation, difference square sum operation, difference square sum accumulation. , Multiply etc.

FIG. 21 is a more detailed block diagram of the pixel processing unit 32 shown in FIG. As shown in FIG. 21, the added programmable processing unit 320 is connected to the selector buses SB1 to SB5. In addition to this, the programmable processing unit 320 includes a parameter memory 344.
Connected to.

(3) Pixel processing unit 3
Operation of 1, 32 Referring to FIG. 19, the pixel processing unit 31
The operation of will be described. As an example of the operation, MPEG
The storage system moving image coding process in the standard will be described.

Pixel bus interface circuit 318
Receives the image data to be encoded from the frame buffer memory 51 shown in FIG.
It is given to the image memory 331 via. When the motion prediction process is necessary, the reference image data is given to the image memory 332 in the forward prediction process. on the other hand,
In the bidirectional prediction process, the reference image data of the previous frame and the reference image of the subsequent frame are stored in the image memories 332 and 333.
Transferred to.

In the case of forward prediction processing, the data stored in the image memory 332 is given to the filter 315. Filter processing is performed in the filter 315, and the processed reference image data is written in the image memory 334.

In the case of the bidirectional prediction processing, the forward reference image data stored in the image memory 332 is given to the filter 315, while the backward reference image data stored in the image memory 333 is also filtered by the filter 315. Given to. In the filter 315, the given reference image data is subjected to filter processing and interpolation processing, and the generated reference image data is written in the image memory 334.

The difference generator 310 outputs the image data to be encoded stored in the image memory 331 to the selector bus S.
Transfer to B2. In some cases, the difference generator 310 supplies the difference data between the image data to be encoded and the reference image data stored in the image memory 334 to the selector bus SB2.

The DCT / IDCT calculator 313 performs a DCT operation on the pixel data or difference data given via the selector bus SB2 in the encoding process, and transfers the generated DCT coefficient via the selector bus SB3. To do. When the loopback calculation process and the decoding process for encoding are performed, the DCT / IDCT calculator 313 performs an inverse DCT calculation on the DCT coefficient given via the selector bus SB3 to generate pixel data or difference data. To do. The generated data is transferred via the selector bus SB2.

The quantizer 314, in the encoding process,
By referring to the parameter memory 344 for the DCT coefficient given via the selector bus SB3,
Performs a quantization operation. The code data obtained as a result of the quantization operation is transferred to the code data memory 343 via the selector bus SB4. In the loopback calculation process and the decoding process for encoding, the quantizer 314
Performs an inverse quantization operation on the code data given via the selector bus SB4. The DCT coefficient obtained as a result of the inverse quantization operation is transferred via the selector bus SB3.

Code data bus interface circuit 3
Reference numeral 17 denotes a code data memory 34 in the encoding process.
The code data stored in 3 is used for the selector bus SB5.
Receive through. The code data bus interface circuit 317 receives the received code data as it is from the external code data bus, that is, the code bus CB shown in FIG.
Output to. In some cases, it is converted into a run-level code by the code data bus interface circuit 317 and then output to the code bus CB. In the decoding process, the code data bus interface circuit 317
The inverse quantization operation is performed on the code data provided via selector bus SB4. The DCT coefficient obtained as a result of the inverse quantization operation is transferred via the selector bus SB3.

The image decoder 310, in the reference image decoding process and the decoding process for encoding, when the motion prediction process is necessary, the reference image data supplied via the selector bus SB1 and the decoded reference image data. The addition operation result data of the difference data is output, and these data are stored in the image memory 335. On the other hand, when the motion estimation is not required, the decoded image data is output as it is and stored in the image memory 335.

The host interface circuit 331 receives parameters such as an operation command and a quantization matrix for the pixel processing unit 31 via the host bus HB shown in FIG. On the other hand, the host interface circuit 311 uses the internal memories 331 to 3
The data stored in 35 and 341 to 344 and the data held in the internal register are output to the outside.

(4) Processing Flow in Pixel Processing Unit (FIGS. 22 to 25) (i) In the case of a coded intra-frame predicted image according to the MPEG standard FIG. 22 shows the coding in the pixel processing unit 31 shown in FIG. FIG. 6 is an operation flow chart for With reference to FIG. 22, the image data stored in the image memory 331 is given to the difference generator 310. The given data is not processed at all in this case, and the DCT / IDCT calculator 313 is processed via the selector bus SB2.
Given to. After the DCT operation is performed in the operation unit 313, the data indicating the operation result is transferred to the selector bus SB3.
To the quantizer 314 via

The quantizer 314 refers to the parameter memory 344 via the selector bus SB5,
Performs a quantization operation. Data indicating the quantization result, that is, code data is given to the code data memory 343 and stored therein. The data stored in the code data memory 343 is output to the external code bus CB (FIG. 1) via the selector bus SB4 and the code data bus interface circuit 317.

FIG. 23 is an operation flow chart for decoding in the pixel processing unit 31 shown in FIG. Referring to FIG. 23, code data memory 34
The data to be decoded, which is stored in 3, is supplied to the quantizer 314 via the selector bus SB4. The quantizer 314 executes the inverse quantization operation by referring to the parameter memory 344 via the selector bus SB5. The data indicating the inverse quantization calculation result is sent to the DCT / IDCT calculator 31 via the selector bus SB3.
Given to 3.

The calculator 313 executes an inverse DCT calculation on the supplied data. The data showing the calculation result is
It is applied to the decoder 310 via the selector bus SB2. The decoder 310 performs limit processing on the given data, and the processed data is processed by the image memory 335.
Given to and stored there.

(Ii) Case of Encoding Bidirectional Prediction According to MPEG Standard Referring to FIG. 24, the image memory 3 is used in the encoding process.
The forward image data stored in 32 and the backward image data stored in the image memory 333 are provided to the filter 315. The filter 315 executes 1/2 precision image generation processing and pixel interpolation processing for the given data. The processed data is the image memory 3
34 and is stored there.

The data stored in the image memory 334 is applied to the difference generator 310 via the selector bus SB1. On the other hand, the image data to be encoded stored in the image memory 331 is also given to the difference generator 310. The difference generator 310 performs pixel difference calculation on the given data.

DCT / IDCT calculator 313 receives difference data from difference generator 310 via selector bus SB2. The calculator 313 performs a DCT calculation on the received data, and the data indicating the calculation result is given to the quantizer 314 via the selector bus SB3. The quantizer 314 refers to the parameter memory 344 via the selector bus SB5 to perform the quantization operation on the given data. The data indicating the quantization operation result is given to the code data memory 343 via the selector bus SB4 and stored there.

Referring to FIG. 25, in the decoding process,
The data stored in the code data memory 343, that is, the data to be decoded is given to the quantizer 314 via the selector bus SB4. Quantizer 314
Is the parameter memory 34 via the selector bus SB5.
By referring to 4, the quantization process is performed on the given data. The data indicating the quantization processing result is sent to the DCT / IDCT calculator 313 via the selector bus SB3.
Given to.

The computing unit 313 executes inverse DCT processing on the given data. The data indicating the processing result is given to the decoder 310 via the selector bus SB2.
The decoder 310 receives the data stored in the image memory 334 via the selector bus SB1. The decoder 310 executes pixel decoding processing (addition processing) and limit processing based on the supplied data. The processed data is provided to the image memory 335 and stored there.

(5) Pipeline Processing (FIGS. 26 to 29) FIG. 26 is a time chart showing the pipeline processing for encoding in the pixel processing unit 31 shown in FIG. Referring to FIG. 26, operating period A
At, the write data for the image memory 331 is transferred via the internal pixel bus IPB2. Operating period B
At, the write data for the image memory 332 is transferred via the internal pixel bus IPB2. Operating period C
At, the write data for the image memory 333 is transferred via the internal pixel bus IPB2.

In the operation period D, the filter 315 operates. In the operation period E, the DCT / IDCT calculator 313 and the quantizer 314 perform the DCT calculation and the quantization calculation. In the operation period F, the arithmetic unit 3
Inverse quantization operation, inverse DCT operation, and decoding processing are performed by 13, the quantizer 314, and the image decoder 310. In the operation period G, the read operation for the image memory 335 is performed. In the operation period H, the code data bus interface circuit 317 performs run-level packing processing and output processing.

The processing of FIG. 26 is sequentially performed for each macroblock. That is, although FIG. 26 shows only the processing of the image data for one macroblock, the pipeline processing is performed for many macroblocks. The pipeline processing for a plurality of macroblocks will be described below.

FIG. 27 is a time chart showing pipeline processing in intra-frame prediction. With reference to FIG. 27, subscript 0 indicates data processing for the 0th macroblock, and subscript 1 indicates processing for the 1st macroblock.

FIG. 28 is a time chart showing pipeline processing in unidirectional prediction. In addition, FIG.
It is a time chart which shows the pipeline processing in bidirectional prediction.

As can be seen from FIGS. 27 to 29, since data processing for a plurality of macroblocks is also performed in the pixel processing unit 3 under pipeline processing control, data processing is also performed only for the processing in the pixel processing unit 3. Can be performed efficiently. In other words, it is possible to provide a pixel processing unit capable of performing DCT operation and quantization operation at high speed and efficiently.

(6) Pixel processing unit 3
3 FIG. 93 is a block diagram showing still another example of the pixel processing unit. The pixel processing unit 33 shown in FIG. 93 is, for example, shown in FIGS.
9, used as the pixel processing unit shown in FIG. 91.

In FIG. 93, a point different from the pixel processing unit 31 shown in FIG. 18 is that two sets of pixel bus interface circuits 318a and 318b are provided. Since the other points are the same as those of the pixel processing unit 31 shown in FIG. 18, the same portions are denoted by the same reference numerals and the description thereof will be omitted below.

FIG. 94 is a more detailed block diagram of the pixel processing unit 33 shown in FIG. Referring to FIG. 94, pixel buses IPB2a and IPB
2b each have a bus width of 32 bits, and each has a dedicated pixel bus interface circuit 318.
a and 318b and image memories 331 to 333 and 335
It is connected to the. Since the other points are similar to those of the pixel processing unit 31 shown in FIG. 19, the same portions are denoted by the same reference numerals, and the description thereof will be omitted below.

Next, the pixel processing unit 33
The operation of will be described. With reference to FIG. 94, a moving image coding process in the MPEG standard will be described as an example of the operation.

According to the MPEG standard, three types of prediction, that is, forward prediction, backward prediction, and bidirectional prediction are used, and it is necessary to transfer prediction data from the outside according to the type of each prediction. The transfer of the prediction data is performed via one of the pixel bus interface circuits 318a and 318b. Image data to be encoded is also processed through one of the pixel bus interface circuits 318a and 318b. The image compression processing is performed by the filter 325, DCT /
This is performed in the IDCT calculator 313, the quantizer 314, the difference generator and the image decoder 310, and the data is output via the code data bus interface circuit 317. On the other hand, the image locally decoded in the pixel processing unit 33 is transferred to different external devices via both the pixel bus interface circuits 318a and 318b. One of the transferred locally decoded data becomes, for example, the input data of the motion prediction unit 47 shown in FIG. The other of the transferred locally decoded data becomes predicted image data in the next frame processing.

As described above, the pixel processing unit 33 shown in FIG. 94 can simultaneously transfer the locally decoded image data to a plurality of external devices, and further transfer the reference image data from the motion prediction unit to the local memory. , The predicted image data can be transferred from another port. There is also one transfer port for predicted images
It is not fixed to one, and data can be transferred from either port, and the system configuration and data transfer method can be easily changed.

FIG. 95 is a block diagram showing another example of the pixel processing unit 33 shown in FIG. The pixel processing unit 33a shown in FIG.
For example, it is used as the pixel processing unit shown in FIGS. 83 to 89 and 91.

Referring to FIG. 95, in comparison with the pixel processing unit 33 shown in FIG. 94, in the pixel processing unit 33a, the pixel bus IPB2 is connected to two pixel bus interface circuits 318a and 318b, and the internal bus Are commonly used to transfer pixel data. Since the other points are the same as those of the pixel processing unit 33 shown in FIG. 94, description thereof will be omitted below.

Next, the pixel processing unit 33
The operation of a will be described. Referring to FIG. 95, internal pixel bus IPB2 is commonly used. Therefore, when the locally decoded data is simultaneously transferred through the two pixel bus interface circuits 318a and 318b, the same operation as that of the pixel processing unit 33 shown in FIG. 94 is performed.

With the above configuration, the pixel processing unit 33a can transfer the locally decoded data to a plurality of external devices at the same time, and further, while transferring the reference image data from the local memory to the motion prediction unit, Port of the pixel processing unit 35
Data can be transferred to. Further, since the pixel bus IPB2 is commonly used, the circuit area can be reduced, which is suitable for high integration.

[0307] 4. Variable Length Processor In the following description, two system configurations are proposed and processors for realizing the respective system configurations are described.

(1) First System Configuration (FIGS. 30 to 35) FIG. 30 is a block diagram showing a first system configuration for variable length processing. The variable length processor having the system configuration shown in FIG. 30 can be applied to the variable length processor 12 shown in FIG. 9, for example.

Referring to FIG. 30, the first system configuration has a variable length coding table memory 401, a variable length decoding table memory 402, a variable length code string input memory 403, and a variable length code string. It includes an output memory 404, an encoded data input memory 405, and an encoded data output memory 406. The variable length processor 121 is connected to each of the memories 401 to 406 via a bus line BU.

FIG. 31 is a flow chart of the variable length coding process in the first system configuration. Referring to FIG. 31,
The processing for variable length coding will be described below. First, in step 431, the encoded data to be converted is supplied from the encoded data input memory 405 to the internal memory in the variable length processor 121. Here, the encoded data is defined by a combination of "RUN" and "LEVEL". In the following description, encoded data is represented by (RN, LV). The supplied encoded data is supplied to an address generator (not shown) in the variable length processor 121, and the variable length code and its code length are obtained by referring to the variable length encoding table memory 401. The variable length code and the code length are stored in the internal memory in the variable length processor 121.

At step 433, it is judged whether or not the obtained variable length code is an escape code (ESCAPE). When the escape code is obtained, in step 434, the isometric code is generated by combining the escape code and the data (RN, LV). After the generation of the isometric code, the process proceeds to step 43.
Go to 5. On the other hand, when the escape code, that is, the code “000001” is not obtained in step 433, the process proceeds to step 435.

At step 435, a variable length code string is generated by data combination of the variable length codes. After the generation of the variable length code sequence, in step 436, the variable length code sequence is output.

FIG. 32 is a flow chart of the variable length decoding process in the first system configuration. Referring to FIG. 32,
The processing for variable length decoding will be described below.

First, in step 441, the variable length code string input memory 403 shown in FIG. 30 supplies the variable length code string to the variable length processor 121 via the bus line BU. The variable length processor 121, step 442.
At, the leading variable length code is extracted. That is, the head of the next variable length code is recognized from the code length of the immediately preceding variable length code, and 14-bit data, which is the maximum code length of the variable length code, is extracted from the head of the next variable length code.

Next, at step 443, by referring to the decoding table memory 402, the variable length code and the code length, that is, the data (RN, LV) are obtained. That is, from the beginning of the obtained variable length code, 14-bit data, which is the maximum code length of the variable length code, is given to an address generator (not shown), and the address generator refers to the decoding table memory 402. An address signal for generating is generated. The decoding table memory 402 is referred to using this address signal, and the variable length code and its code length are obtained.

At step 444, it is judged if the escape code "000001" is obtained. When the escape code is obtained, in step 445, the escape code "00000" is selected from the variable length code string.
The 16-bit data after "1" is the decoded data (RN, L
V) is extracted. After the processing of step 445,
The process proceeds to step 446. If no escape code is obtained in step 444, the process proceeds to step 446.

At step 446, the decoded data (RN, LV) is output. Next, a data storage structure of data stored in the variable length coding table memory 401 and the variable length decoding table memory 402 shown in FIG. 30 will be described. FIG. 33 is a data storage structure diagram of the variable length coding table memory 401. As shown in FIG. 33, the variable length coding table memory 401 outputs the stored variable length code VC and code length CL by referring to the data (RN, LV). The run data RN has a bit length of 6 bits. The level data LV has a bit length of 10 bits. The variable length code VC has a bit length of 14 bits. The code length data CL has a code length of 4 bits.

FIG. 34 is a data storage structure diagram of the variable length decoding table memory 402. As shown in FIG. 34, the variable length decoding table memory 402 refers to the variable length code VC to obtain the level data L.
V, run data RN and code length data CL are output. The code length data CL has a bit length of 4 bits.

The input data VC used to refer to the variable length decoding table memory 402 has the same bit length as the maximum code length of the variable length code. Therefore, when a code shorter than the maximum code length exists in the upper bits of the input data VC, the decoding result of the upper bits can be preferentially output regardless of any bit pattern in the lower bits. For example, even if the table memory 402 is referred to by using any of the two input data 415 and 417 shown in FIG. 34, the same data 416 and 4 are obtained.
18 is output.

Next, the variable length code string generation processing will be described. FIG. 35 is a processing flow diagram for explaining the variable length code string generation processing. It is assumed that six registers 421 to 426 are prepared in order to generate one variable length code string. It is also assumed that the variable length processor has a data processing band of n bits, and thus each register 421 to 426 has a bit width of n bits.

Referring to FIG. 35, register 421 holds variable length code VC1 and register 422 holds variable length code V1.
It is assumed that the code length k of C1 is held. Register 4
It is assumed that 23 holds the variable length code VC2 and the register 424 holds the code length j of the variable length code VC2.
It is assumed that the register 425 holds the variable length code VC3 and the register 426 holds the code length m of the variable length code VC3.

First, the variable length code VC1 held in the register 421 is given to the register 426. The register 426 MSs each bit of the variable-length code VC1.
Store in order from B. Therefore, register 426
Holds the k-bit variable length code VC1 from the MSB.

Next, at step 427, the code length j of the variable length code VC2 is compared with (nk). j <
In the case of (n−k), the variable length code VC2 held in the register 423 is given to the register 426. The register 426 has a variable length code VC1 followed by a variable length code VC.
Hold 2 The operation in the register 426 is performed by shifting the variable length code VC2 to the LSB side by k bits and then performing accumulation or logical OR processing between the corresponding bits of the variable length codes VC1 and VC2. As a result, the register 426 holds the combined data of (k + j) bits, that is, the variable length code string (VC1 + VC2).

At this stage, the register 426 has (n
-K-j) bit area remains, so register 4
26 is further used to hold the variable length code VC3.

If j> (n−k) in step 427, (n−k) bit data of the variable length code VC2 in the register 423 is held in the register 426. That is, after shifting the variable length code VC2 by k bits, the accumulation or logical sum processing is performed between the variable length codes VC1 and VC2. As a result, the register 426 will be filled with a portion of the k-bit variable length code VC1 and the (n−k) -bit variable length code VC2.

In step 428, the data filled in the register 426 is output. After data output, the variable length code VC2 of (j + k−n) bits left in the register 423 is given to the register 426. The register 426 receives the given data, that is, the variable length code VC.
The remaining 2 bits are held in order from the MSB side.

In this way, the register 426 is filled with the variable length codes sequentially provided, and the filled n-bit data is sequentially output as a variable length code string.

The variable length code string cutout process is performed by repeatedly executing the data shift, the logical operation, the code length count of the variable length code, and the determination process, similarly to the variable length code string generation process described above.

(2) Variable Length Processor (Dedicated Circuit: FIG. 36) FIG. 36 is a block diagram showing a first example of the variable length processor. Referring to FIG. 36, variable length processor 122
Includes an address register 451, a ROM 452, and an output processing circuit 453. These internal circuits 451 and 4
52 and 453 are composed of dedicated circuits.

(3) Variable Length Processor (Digital Signal Processor: FIG. 37) FIG. 37 is a block diagram showing a second example of the variable length processor. The variable length processor 123 is composed of a digital signal processor. Referring to FIG. 37, the variable length processor 123 includes an external interface circuit 461, an ALU 462, a shifter circuit 463, and
A memory 464, an instruction memory 465, and a control circuit 466.
Including and

(4) Variable Length Processor (General Purpose Microprocessor: FIG. 38) FIG. 38 is a block diagram showing a third example of the variable length processor. The variable length processor 124 is composed of a general-purpose microprocessor. Referring to FIG. 38,
The variable length processor 124 includes an execution unit (EU) 471 including a register file 473, a bus interface unit 472 including a relocation register file 474, an ALU 475, and a flag register 476.
A bus interface unit 477, an instruction queue 478, and a control / timing circuit 479.

The variable length processors 122, 123, and 124 shown in FIGS. 36, 37, and 38 all form the first system configuration shown in FIG. 30, and therefore the above-mentioned first system configuration is used. Is processed.

(5) Second System Configuration (FIG. 39) FIG. 39 is a block diagram showing the second system configuration for variable length processing. The system configuration shown in FIG. 39 is
For example, it is formed in the image compression / expansion processing device 101 shown in FIG.

Referring to FIG. 39, work memory 7 includes a variable length coding table memory 481 and a variable length decoding table memory 482. These table memories 481 and 482 are connected to the variable length processor 125 via buses 491 and 492.

The buffer memory 6 includes a variable length code string input memory 483, a variable length code string output memory 484, a coded data input memory 485, and a coded data output memory 486. These code string input memories 483
And output memory 484 is connected to variable length processor 125 via buses 493 and 495. Further, the code string input memory and the code string output memory are the bus 494.
Is connected to the variable length processor 125 and the host interface circuit 1 via.

Encoded data input memory 485 and encoded data output memory 486 include buses 496 and 4
It is connected to the variable length processor 125 via 98. Further, the input memory 485 and the output memory 486 are connected to the variable length processor 125 and the pixel processing unit 3 via the bus 497.

(6) Variable Length Processor (FIG. 40) FIG. 40 is a block diagram of the variable length processor 125 shown in FIG. Therefore, the variable length processor 125 shown in FIG. 40 can be applied to the variable length processor 12 shown in FIG. 9, for example.

Referring to FIG. 40, variable length processor 12
5 is a controller 501, an address generator 502, an external interface circuit 503, and a data calculator 504.
A variable length code string generation / decomposition circuit 505, an external interface circuit 506, and an external interface circuit 5
07 and a data memory 508. These internal circuits 501 to 508 are connected via a first internal bus 509. On the other hand, the external interface circuit 503
The variable length code string generation / decomposition circuit 505 is connected via the second internal bus 510.

External interface circuit 503 is connected to main port 17 shown in FIG. 9 via buses 491 and 492. External interface circuit 506
Are connected to the code data port 20 shown in FIG. 9 via buses 493, 494 and 495.

(I) Address Generator (FIG. 41) FIG. 41 is a block diagram of the address generator 502 shown in FIG. Referring to FIG. 41, the address generator 50
2 is a positive limit value register 520, a negative limit value register 521, a PE mode register 522, a page register 523, and address registers 524 and 52.
5, an escape decoder 526, an escape encoder 527, an escape register 528, a data register 529, a selector circuit 530, a limiter circuit 531, a priority encoder 532, a shifter circuit 533, an external address register 534, and a pipe. It includes line registers 561, 562, 563 and an OR circuit (logical sum processing circuit) 564.

Registers 520 to 525 are connected to first internal bus 509. Selector circuit 530 is connected to first and second internal buses 509 and 510. The data register 529 and the external address register 534 are equivalent to the external interface circuit 5 shown in FIG.
03 is connected.

FIG. 42 is a flow chart of the variable length coding process in the address generator 502 shown in FIG. Although the detailed processing of the address generator 502 will be described later,
First, the basic operation will be described.

Referring to FIG. 42, in step 601, predetermined data is set in registers 520 to 523 shown in FIG. In step 602, the encoded data (RN, LV) is input to the address register 525. Encoded data (RN, LV) is 1 in total
It has 6 bits, the upper 10 bits define the level data LV, and the lower 6 bits define the run data RN. After step 602, step 6
The processes of 03 to 605 and steps 606 to 607 are performed in parallel.

At step 603, the data held in the address register 525 is stored in the limiter circuit 53.
Given to 1. The limiter circuit 531 is provided with the upper 10 bits of the supplied data, that is, the level data L.
V is limited to the range defined by the positive limit value register 520 and the negative limit value register 521. 6-bit level data L as a result of limit processing
A total of 12 bits of encoded data with V and 6 bits of run data RN are obtained.

The 12-bit coded data is OR circuit 5
64 and the given data and page register 5
An OR operation is performed with the data supplied from 23 to generate combined 20-bit data (step 604). The generated data is stored in the external address register 534 (step 605).

On the other hand, in step 606, the encoded data in the register 525 is the escape encoder 52.
7, the equal length code is generated by the escape encoder 527. That is, the equal length code generation process is performed when the encoded data is encoded as the equal length code. In step 607, the generated equal-length code is stored in the escape register 528.

FIG. 43 is a flow chart of the variable length decoding process in the address generator 502 shown in FIG. A basic process for variable length decoding will be described.

Referring to FIG. 43, first, in step 611, predetermined data is set in registers 520 to 523. In step 612, the variable length code string to be decoded is input to the address register 524. The register 524 holds 22 bits from the first bit of the given variable-length code sequence in order from the MSB side. After step 612, steps 613 to 616
And the processing of steps 617 to 618 are performed in parallel.

At step 613, the data held in the address register 524, that is, the variable length code string is given to the priority encoder 532. The priority encoder 532 obtains the number SN of consecutive “0” from the MSB of the given data by calculation.

At step 614, the data in the address register 524 is supplied to the shifter circuit 533.
The shifter circuit 533 responds to the consecutive number SN obtained in step 613, in response to the MS of the given data.
Data of 6 bits lower than the (SN + 1) th position is extracted from B. The extracted data is given to the OR circuit 564.

In step 615, the OR circuit 564
20-bit data is generated. The generated data is the external address register 5
It is stored in 34 (step 616).

On the other hand, in step 617, the data held in the address register 524 is given to the escape decoder 526. Escape decoder 52
6 performs a decoding process by considering that the given data is an equal length code using an escape code.
The decoded data is stored in the escape register 528 (step 618).

(Ii) Variable Length Code Sequence Generation / Decomposition Circuit (FIG. 44) FIG. 44 is a block diagram of the variable length code sequence generation / decomposition circuit 505 shown in FIG. Referring to FIG. 44, the variable-length code string generation / decomposition circuit 505 includes a bus register 536
Barrel shifter (BSFT) 537 and adder 538
, Code length register 539, and code output register 5
40, code input register 541, and FIFO circuit 5
42 and 543 and controller 544. The bus register 536 is connected to the first internal bus 509. The adder 538 is connected to the second internal bus 510. F
The IFO circuits 542 and 543 are connected to the external interface circuit 506 (described later) shown in FIG. 47 via the signal lines 42a to 43c.

FIG. 45 is a flow chart of a variable length coding process in the variable length code string generation / decomposition circuit 505 shown in FIG. First, with reference to FIG. 45, a basic operation in the variable length coding process will be described.

In step 621, the variable length code VC
Are provided to bus register 536 via internal bus 509. The code length data CL of the variable length code VC is given to the adder 538 via the second internal bus 510.

At step 622, the barrel shifter 5
37 combines the old variable length code VC 'that has already been input with the new variable length code VC currently given to generate a variable length code string VCT. In step 623, the adder 538 adds the code length CL of the new variable length code to the cumulatively added code length CLS.

At step 624, the code length sum CLS
Is greater than 8 bits. When CLS ≧ 8, the process proceeds to step 625.

At step 625, the variable length code string V
8-bit data from the first bit of CT is given to the FIFO circuit 542 and stored therein. Step 62
At 6, a new code length sum is determined by performing a subtraction, ie CLS = CLS-8. After step 626, processing returns to step 624.

In step 624, if CLS <8
, The encoding operation ends.

FIG. 46 is a flow chart of a variable length decoding process in the variable length code string generation / decomposition circuit 505 shown in FIG. Referring to FIG. 46, first, in step 631, the variable length code string VCT is placed on the first internal bus 509.
Is given. In step 632, the code length CL of the first variable-length code VC included in the variable-length code string VCT is given to the adder 538 via the second internal bus 510. In step 633, the adder 538 adds the new code length CL to the sum CLS of the old code lengths.

In step 634, the code length sum CLS
Is greater than or equal to 8 bits. CLS ≧
If so, the process proceeds to step 635.

At step 635, one word of data is provided from the variable length code string input memory 483 and combined with the current variable length code string. In step 636, the first 8-bit data from the combined variable length code string is discarded. In step 637, CLS = C
The new code length sum CLS is obtained by executing LS-8.
Is obtained. After the step 637, the process is the step 63.
Return to 4.

In step 634, when CLS <8, this decoding process ends. (Iii) External interface circuit 506 (see FIG.
7) FIG. 47 shows the external interface circuit 5 shown in FIG.
It is a block diagram of 06. 47, external interface circuit 506 includes controller 545 having a DMA function and read access counters 546 and 549.
, Write access counters 547 and 548, subtractors 565 and 566, and comparators 550 and 558.
, Flag generation registers 551 to 554, write data register 556, and read data register 557.
And a selector 555.

The controller 545 controls the signal lines 42b, 42c,
It is connected to the FIFO circuits 542 and 543 shown in FIG. 44 through 43b and 43c. Register 556
Is connected to the FIFO circuit 542 shown in FIG. 44 through the signal line 42a. The register 557 has a signal line 43a.
Is connected to the FIFO circuit 543 shown in FIG. The counters 546 and 547 are connected to the variable length code string input memory 438 and the variable length code string output memory 484 shown in FIG. 39 via the signal line 493. Counters 548 and 549 are shown in FIG.
It is connected to the variable-length code string input memory 483 and the variable-length code string output memory 484 shown in FIG. The selector 555 uses the signal line 495.
Via the variable length code string input memory 483 shown in FIG.
And a variable length code string output memory 484.

The counter 546 counts the number of read accesses to the variable length code string input memory 483 shown in FIG. The counter 547 counts the number of write accesses to the variable length code string output memory 484 shown in FIG. The counter 548 counts the number of write accesses to the variable length code string input memory 483 from other circuits. The counter 549 counts the number of read accesses to the variable length code string output memory 484 from other circuits.

The flag register 551 generates a full flag indicating the full state of the variable length code string input memory 483,
And hold it. The register 552 generates an empty flag indicating the empty state of the variable length code string input memory 483, and holds it. Flag register 553
Generates a full flag indicating the full state of the variable length code string output memory 484 and holds it. Counter 55
4 generates an empty flag indicating the empty state of the variable length code string output memory 484, and holds it.

The comparator 550 outputs the full flag FF1 indicating the full state of the variable length code string input memory 483 or the empty flag EF1 indicating the empty state. The comparator 558 is a full flag FF2 or an empty flag EF indicating the full state of the variable length code string output memory 484.
2 is output.

FIG. 48 is a flow chart of a variable length coding process in the external interface circuit 506 shown in FIG. A basic operation for the variable length coding process will be described with reference to FIG.

In step 641, it is detected whether or not the variable length code string output memory 484 is in the empty state. That is, the empty flag E from the comparator 558.
It is determined whether or not F2 is output. If the empty flag EF2 is not detected, the process proceeds to step 642. If the empty flag EF2 is detected, the process ends.

In step 642, it is detected whether the variable length code string output memory 484 is in the full state.
That is, it is determined whether or not the full flag FF2 is output from the comparator 558. If the full flag FF2 is not detected, the process proceeds to step 643. Full flag F
When F2 is detected, the process ends.

At step 643, the 1-word data stored in the variable length code string output memory 484 is read out and stored in the external variable length code string output memory. In step 644, the write access counter 547 is counted up. After step 644, the process returns to step 641.

FIG. 49 is a flow chart of a variable length decoding process in the external interface circuit 506 shown in FIG. Referring to FIG. 49, first, in step 651, it is detected whether or not the variable length code string input memory 483 is in the full state. That is, it is detected whether the full flag FF1 is output from the comparator 550. If the full flag FF1 is not detected, the process is step 652.
Proceed to. When the full flag FF1 is detected, the processing ends.

At step 652, it is detected whether or not the variable length code string input memory 483 is in the empty state. That is, the empty flag E from the comparator 550
It is detected whether or not F1 is output. If the empty flag EF1 is not detected, the process proceeds to step 653. When the empty flag EF1 is detected, the processing ends.

At step 653, the one-word data stored in the external variable length code string input memory is read and stored in the variable length code string input memory 483.
In step 654, the read access counter 446 for the external variable length code string input memory is counted up. After step 654, the process is step 651.
Return to.

(Iv) More Detailed Description of Variable Length Encoding / Decoding Processing In the following description, the variable length processor 12 shown in FIG.
The variable length encoding / decoding processing in 5 will be described in more detail.

FIG. 50 is a variable length code table used in the processing in the variable length processor 125 shown in FIG. Referring to FIG. 50, the four columns on the left side of the variable length code table are H.264 based on CCITT. 261
It corresponds to the variable length code table in the recommendation. That is, H.264. Run data defined in H.261 (zero run length)
RN, level data (coefficient) LV, code length CL and variable length code VC are described in the four columns on the left side. On the other hand, the three columns on the right side show grouped variable length code tables. That is, the variable length code VC and the code length CL are divided into nine groups GR0 to GR8 in total according to the number of "0" s consecutive from the first bit of the variable length code VC.

For example, the group GR0 includes the variable length code VC whose first bit of the variable length code VC is not "0". The group GR1 includes the variable length code VC in which only the first bit of the variable length code VC is "0". The group GR2 includes the variable length code VC in which the first bit and the next bit of the variable length code VC are "0". Similarly, the group GR8 includes a variable length code VC including eight “0” s from the first bit of the variable length code VC. The variable length code VC and the code length CL grouped in this way are added to the variable length processor 125 as described later.
Used in processing.

First, the variable length coding process will be described. The variable-length coding process is basically the same as that of FIG.
It is executed according to the flow chart shown in FIG. First, FIG.
40 to the data memory 508 in the variable-length processor 125 shown in FIG.
The encoded data, that is, the data (RN, LV) is input to. The input data is the address generator 502.
Address generator 502 generates a table memory address for the variable length coding conversion. In parallel with the generation of the table address, the escape decoder 526 shown in FIG. 41 generates the equal length code using the escape code. The generated equal-length code is given to the escape register 528 and held there. The detailed operation of the address generator 502 will be described later.

Using the table address generated by the address generator 502, the variable length coding table memory 481 is referred to and the stored variable length code V is stored.
C, code length CL and escape flag ESF are read. The variable length code VC and the code length CL are given to the data register 529 shown in FIG. 41 and held there.

After the access to the variable length coding table memory 481 is completed, the data of either the escape register 528 or the data register 529 is output to the variable length code generation / decomposition circuit 505. This selection is performed by the selector circuit 530. That is,
Of the data held in the two registers 528 and 529, the selector 530 selectively outputs one of the data in response to the most significant bit (MSB).

That is, as shown in FIG. 51, the variable length coding table memory 481 stores an escape flag ESF indicating whether or not the coded data in the most significant bit is within the applicable range of the escape code. ing.
Therefore, when the most significant bit of the data given to the data register 529, that is, the flag ESF indicates the application of the escape code, the selector 530 selectively outputs the data held by the data register 529. As a result, it is possible to determine whether or not the escape code needs to be applied to the encoded data only by referring to the variable length encoding table memory 481, and a determination process by the program is required for this determination. I won't.

In addition to this, in the address generator 502 shown in FIG. 41, the variable length coding table memory 481 is used.
Access and access code generation using escape code can be executed in parallel, that is, at the same time,
An increase in processing time due to access to the variable length encoding table memory 481 can be prevented.

The variable length code VC obtained by referring to the variable length coding table memory 481 is transferred to the variable length code generation / decomposition circuit 505 via the first internal bus 509 shown in FIG. On the other hand, the code length CL is the variable length code generation / decomposition circuit 50 via the second internal bus 510.
5 is transferred.

The variable length code generation / decomposition circuit 505 generates a variable length code string VCT from the supplied variable length code VC and its code length CL. The operation of generating the variable length code string will be described later. The generated variable length code string VCT is output to the variable length code string output memory 484 shown in FIG. 39 via the external interface circuit 506. In this way, the variable length coding process is completed.

Next, the variable length decoding process will be described. First, the variable length code string input memory 48 shown in FIG.
The variable-length code sequence is input to the variable-length code sequence generation / decomposition circuit 505 from the external interface circuit 506. The variable-length code string generation / decomposition circuit 505 cuts out a variable-length code to be decoded from the given variable-length code string,
The bits of the variable length code are shifted to the MSB side. The shifted variable length code is transferred to the address generator 502 via the first internal bus 509. Variable length code sequence generation /
Detailed processing in the decomposition circuit 505 will be described later.

The address generator 502 generates a table address for referring to the variable length decoding table memory 482 shown in FIG. 39 in response to the given variable length code. The generated table address is given to the variable length decoding table memory 482 via the external interface circuit 503. As a result, the decoded variable length code, code length data and escape flag ESF are held in the data register 529 shown in FIG. At this time, in parallel with this process, the variable length code is given to the escape code encoder 527, and the equal length code is decoded using the escape code. The data indicating the result is given to the escape register 528 and held there.

As in the case of the variable length coding processing, the variable length decoding table memory 482 is provided with the escape flag E.
I remember the SF. Therefore, the table memory 48
2 is completed, the data register 52
Escape flag ESF in the 9 most significant bits (MSB)
Is retained. In response to the escape flag ESF, one of the data held in the escape register 528 and the data register 529 has the selector 530.
Is selectively output via. The output data is given to the data memory 508 shown in FIG.

On the other hand, the code length data is stored in the second internal bus 51.
It is transferred to the variable length code string generation / decomposition circuit 505 via 0. The variable-length code string generation / decomposition circuit 505 uses the supplied code-length data to perform the cutting process of the next variable-length code. The data indicating the decoding result provided to the data memory 508 is output to the encoded data output memory 486 via the external interface circuit 507. This ends the variable length decoding process.

In the following description, more detailed operation of address generation circuit 502 shown in FIG. 41 will be described.

FIG. 52 is a data format diagram of encoded data in the variable length encoding process. With reference to FIG. 52, the encoded data includes level data LV having 10 bits and run data RN having 6 bits. Therefore, the encoded data has a total bit length of 16 bits.

On the other hand, referring to the four columns on the left side of the variable length code table shown in FIG. 50, the level data LV (this data is defined as absolute value data in the H.261 recommendation) is -15 or It has a value in the range of +15. Data that exceeds this range is H.264. It is supposed to be expressed by an escape code (ESCAPE) in the H.261 recommendation. This means that the level data LV
It means that the number of bits required to express is 5 bits, and a combination of run data and level data can be expressed by a total of 11 bits including run data RN.

Level data LV of +15 or more and -15 or less are subjected to limit processing to +16 and -16, respectively, and therefore level data +16 and -16.
The address containing "" indicates the escape code.
By performing this processing, the address for accessing the variable-length coding table memory is sufficient for a total of 11 bits, and the variable-length coding table memory is configured within the address space of 2k words. be able to.

As described above, the address generator 502 can execute address generation in one pass. Therefore, the limiter 531 shown in FIG.
Of the data held in 5, the level data LV 1
Limit processing for limiting the range of +16 to -16 to 0 bit is performed. Therefore, the positive limit value register 520 shown in FIG. 41 is set to the positive value +16, while the negative limit value register 521 is set to the negative value -16. The limiter 531 performs the above limit processing by referring to the data held in these registers 520 and 521.

As a result of the limit process on the level data, a total of 11-bit combination data is obtained, and an address for referring to the variable length coding table memory 481 is generated using this data.

Next, the address generation circuit 5 shown in FIG.
The decoding operation in 02 will be described.

As shown in the variable length code table of FIG. 50, the variable length codes VC are divided into nine groups GR0 to GR8 in total. In each group, 6 bits are required to define each variable length code. Therefore, in order to configure the decoding table for the variable length code, 4 bits for designating a total of 9 groups and 6 bits for designating the code in each group are required. That is, a total of 10 bits are required as the address of the table for decoding the variable length code. The address generation circuit 502 shown in FIG.
A 0-bit table address can be generated in one pass.

That is, the variable length code to be decoded is given to the address register 524 and held there. The data held by the address register 524 is given to the priority encoder 532, and the number of consecutive “0” from the first bit of the given data is counted. As a result, it is determined which of the groups GR0 to GR8 shown in FIG. 50 contains the data,
The group number is represented by 4-bit data. On the other hand, a 6-bit clipping process of the data after the continuous "0" is performed. The 4-bit group number data and the 6-bit cut-out data form a table address of 10 bits in total, and this table address is given to the external address register 534 and held there.

As described above, by using the address generator 502 shown in FIG. 41, the address space of each of the variable length coding table memory 481 and the variable length decoding table memory 482 can be shortened, Moreover, these processes can be performed by a series of processes.

Next, the variable length code string generation /
The encoding operation in the decomposition circuit 505 will be described.
Code output register 540 includes parallel shift registers 40a-40e each having 8 bits. In the initial state, the code output register 540, the code length register 539, and the FIFO circuit 542 all hold data “0”. The barrel shifter 537 having 40 bits (40b) shifts the input data to the right according to the code length held in the code length register 539.

For example, "001010" is given to the bus register 536 as the first encoded variable length code, while the code length "6" is given to the 5-bit adder 538. At this stage, since the value of the code length register 539 is "0", the data of the bus register 536 passes through the barrel shifter 537 as it is and is given to the code length register 539. In the adder 538, the input data “6” and the data “0” of the code length register 539 are added, and the result data “6” is written in the code length register 539.

Next, as the coded next variable length code, for example, data "00001000" is applied to the bus register 536, while code length "8" is added by the adder 53.
Given to 8. Since the data of the code length register 539 is "6", the data of the bus register 536 is shifted to the right by 6 bits by the barrel shifter 537, and the shifted data is given to the code length register 539. Therefore, the data held in the code length register 539 includes the first variable length code in the first 6 bits and the next variable length code in the 7th bit and thereafter. The adder 538 adds the input data “8” with the data “6” in the code length register 539, and gives the addition result “14” to the code length register 539.

At this stage, since the register 40a in the code output register 540 is filled with the variable length code "00101000", the data in the register 40a is FI.
It is given to the FO circuit 542. Then register 40b
The data inside is transferred to the register 40a. Further, the data in the register 40c is transferred to the register 40b. The same process is repeated, and the last data in the register 40e is transferred to the register 40d. After these transfer processes, "8" which is the code length of the data given to the FIFO circuit 542 is subtracted from the data of the code length register 539. That is, in this example, since the register 539 holds the data “14”, the subtraction result is “6” (=
14-8).

As a result, the data in the code length register 539 indicates the number of bits of the variable length code "001000" stored in the register 40a.
When the next variable length code is input, the input variable length code is shifted to the right by the number of bits of the variable length code stored in the register 40a. Therefore, the next variable length code is stored in the code output register 40 following the variable length code already stored. In this way, the variable-length code and the code length thereof can be used to generate a variable-length code string without requiring a determination process by software.

Next, the decoding operation in the variable length code string generation / decomposition circuit will be described. Code output register 5
Similar to 40, each of the code input registers 541 has eight
Parallel shift registers 41a-4 having bits
Including 1e. In the initial state, the code input register 5
41 and the code length register 539 both hold data “0”. The barrel shifter 537 having 40 bits shifts the input data to the left by the value held in the code length register 539.

First, the first variable length code string is sequentially input to the registers 41a to 41e via the FIFO circuit 543.

When the variable length code is cut out, the data in the code input register 541 is supplied to the bus register 536 via the barrel shifter 537. At this stage, since the data in the code length register 539 is "0", the data in the code input register 541 directly passes through the barrel shifter 537 and is given to the bus register 536. By decoding the data in the bus register 536, data "6" is obtained as its code length, and this code length data is given to the adder 538. Adder 538
Adds the input data "6" to the data "0" in the code length register 539, and the data "6" indicating the result is given to the code length register 539 and held there.

When the next variable length code is cut out, the data in the code input register 541 is supplied to the bus register 536 via the barrel shifter 537. Since the data in the code length register 539 is "6", the data in the code input register 541 is shifted to the left by 6 bits by the barrel shifter 537, and the shifted data is given to the bus register 536. That is, the next variable-length code following the already-decoded variable-length code is obtained in the state of being shifted to the left. As a result of decoding the data in the bus register 536, data “8” is obtained as its code length, and this code length data is input to the adder 538.

The adder 538 adds the input data "8" with the data "6" in the code length register 539, and supplies the data "14" indicating the result to the code length register 539. At this stage, all the contents of the register 41a have been decoded, so the data in the register 40b is transferred to the register 40a. Next, the data in the register 40c is transferred to the register 40b. The same processing is repeated, and finally, the data in the register 40e is stored in the register 4
0d. FI to empty register 40e
The FO circuit 543 provides the next variable length code string.

The data in the code length register 539 is 8
Since the bit decoding process has been completed, "6" is held. Therefore, when the cutting process of the next variable length code is performed, the next variable length code following the already decoded variable length code is obtained in a state of being shifted to the left.

As described above, by using the code length of the decoded variable-length code, the processing for cutting out the variable-length code to be decoded next from the variable-length code string in the state shifted to the left side is performed by software. It can be done without requiring a decision process.

Next, the variable length coding operation in external interface circuit 506 shown in FIG. 47 will be described.

Referring to FIG. 47, controller 545 having a DMA function controls an internal circuit in external interface circuit 506. Counters 548 and 549
Receives a strobe signal for access (read and write) from the host interface circuit 1 to the variable length code string input memory 483 and the variable length code string output memory 484 via the signal line 494. Therefore, the counter 548 counts the number of write accesses to the variable length code string input memory 483 by the host computer.
On the other hand, the counter 549 counts the number of read accesses to the variable length code string output memory 484 by the host computer. Similarly, the counter 546 controls the variable length code string input memory 48 from the external interface circuit 506.
The number of read accesses to 3 is counted. Counter 5
47 counts the number of write accesses from the external interface circuit 506 to the variable length code string output memory 484.

The output data of counters 546 and 548 is applied to subtractor 565 and subjected to the subtraction processing.
The data indicating the subtraction result is the variable length code string input memory 48.
3 indicates the number of words of data stored. The output data of the subtractor 565 is given to the comparator 550.

The comparator 550 receives the word number data in the full state of the variable length code string input memory 483 from the register 551. On the other hand, the comparator 550 is the register 5
From 52, the word number data indicating the empty state of the variable length code string input memory 483 is received. The comparator 550 is
The output data from the subtractor 565 is stored in these registers 55.
1 and 552, and outputs flags FF1 and EF1.

When the output data of the subtracter 565, that is, the difference data is equal to the number of words indicating the full state held in the register 551, the comparator 550 outputs the full flag FF1. On the other hand, when the output data of the subtractor 565 is equal to the number of words indicating the empty state held in the register 552, the comparator 550 outputs the empty flag EF1.

Similarly, the variable-length code string output memory 484 shown in FIG. 39 is also subjected to the same processing as the input memory 483, and the full flag FF2 or empty flag EF2 is output from the comparator 558.

The controller 545 is the FIFO shown in FIG.
Flag output signal 42b from circuit 542 and FIFO
Flag output signal 43b from circuit 543 and comparator 550
And flags FF1, EF1, FF2, and EF2 from 558, and FIFO circuits 542 and 543, respectively.
Data transfer control between the variable length code string output memory 484 and the variable length code string input memory 483 is performed. This data transfer control is performed as follows.

When variable length coding processing is performed, FI
Data transfer is performed between the FO circuit 542 and the variable length code string output memory 484. At this time, in the variable length code string generation / decomposition circuit 505, data transfer control is performed so that the FIFO circuit 542 does not enter the underflow state, that is, the read operation is not caused without storing data. In addition to this, the data transfer control is performed so that the variable length code stream output memory 484 does not overflow, that is, the write operation is not triggered in the variable length code stream output memory 484 even though valid data is stored. Done.

In the variable length decoding process, data transfer is performed between the FIFO circuit 543 and the variable length code string input memory 483. At this time, the FIFO circuit 54
Data transfer control is performed so that 3 does not overflow and the variable length code string output memory 484 does not underflow.

5. Frame Buffer Memory (1) System Configuration (FIGS. 53 and 54) FIG. 53 is a basic configuration diagram of a memory cell array in the frame buffer memory. For example, the frame buffer memory 51 shown in FIG. 1 has the configuration shown in FIG.

Referring to FIG. 53, the frame buffer memory 54 (or 55) is a memory cell array 701 to 732 (or 801 to 83) of 32 planes in total.
2) is provided. When one row address RA and one column address CA are applied, 1-bit data is read (or written) from each of memory cell arrays 701 to 732. For example, when row address RA1 and column address CA1 are applied, a total of 32 bits of data are read from memory cell arrays 701 to 732.

Generally, 8-bit data is required to represent one pixel. Therefore, four pixels PC1 to PC4 can be indicated by a total of 32 bits of data (see FIG. 53). In other words, by supplying one row address RA and one column address CA, the data for the four pixels PC1 to PC4 can be handled.

FIG. 54 is a block diagram of the frame buffer memory. 54, the frame buffer memory 54 (or 55) includes a control circuit 741 and memory cell arrays 701 to 732 (or 801 to 8).
32) is included. Each memory cell array 701 to 732
Are two banks BK1 and B in the case of SDRAM.
It is divided into K2. A sense amplifier 742 and an input / output buffer 743 are provided corresponding to each of the memory cell arrays 701 to 732. Therefore, 32-bit data PD1 to PD32 are read or written in the memory cell arrays 701 to 732.

Control circuit 741 receives address signal ADR and control signal Sc and generates a control signal for accessing memory cell arrays 701 to 732.

(2) Example using DRAM (first example:
55) FIG. 55 shows a frame buffer memory 5 using a DRAM.
4 is a system configuration diagram of FIG. Referring to FIG. 55, the frame buffer memory 54 includes DRAM memory cell arrays 701 to 732 composed of a total of 32 planes. The frame buffer memory 54 uses the address bus AB
The address signal ADR is received from the DRAM controller 740 via. The frame buffer memory 54 is connected to the pixel data bus PB, and data is input / output through the pixel data bus PB.

The DRAM controller 740 is provided in the control unit 2 in the image compression / expansion processing apparatus shown in FIG. 1, for example. That is, the DRAM controller 740 is provided in the overall control processor 11 shown in FIG.

FIG. 56 is a pixel layout diagram showing the relationship between the data stored in the frame buffer memory 54 shown in FIG. 55 and the pixels in the screen. As described above, by applying one row address RA and one column address CA to frame buffer memory 54, 32-bit data for representing four pixels can be accessed. In the system configuration shown in FIG. 55, FIG.
As shown in, one row address and one column address can represent four pixels (for example, PC0 to PC3) in the horizontal direction on the screen SCN.

FIG. 58 is a pixel layout diagram for explaining an addressing signal by DRAM controller 740 shown in FIG. Referring to FIG. 58, the screen SCN is determined by the column address of frame buffer memory 54.
Pixels in the horizontal direction are designated. On the other hand, the pixel in the vertical direction on the screen SCN is designated by the row address signal.
In FIG. 58, ◯ indicates one pixel.

Overall control processor 11 shown in FIG.
Generates a row address signal RA and a column address signal CA according to the stored microprogram. Row and column address signals RA and CA are applied to address bus AB as address signal ADR. The address signal ADR is given to the frame buffer memory 54 via the address bus AB. At the same time, DRAM
The controller 740 outputs a control signal for controlling the frame buffer memory 54. The overall control processor 11 supplies the data to be stored in the data writing to the frame buffer memory 54 via the pixel data bus PB. The overall control processor 11 receives the data stored in the frame buffer memory 54 in the data read operation via the pixel data bus PB.

FIG. 59 shows the frame buffer memory 5 under the control of the DRAM controller 740 shown in FIG.
4 is a time chart showing the read operation of No. 4 in FIG. Referring to FIG. 59, row address strobe signal / RAS falls after row address signal RA1 is applied. After the first column address signal CA1 is applied, the column address strobe signal / CAS falls. In the read operation,
A high level write enable signal / WE is applied. Therefore, stored data PD1 is read from the memory cell (not shown) designated by address signals RA1 and CA1. After data PD1 is read, signal / CAS rises.

After the next column address signal CA2 is applied, the signal / CAS falls again. As a result, data PD2 is read from the memory cell designated by address signals RA1 and CA2. By repeating the same operation, data PD1, PD2, ... Specified by column address signals CA1, CA2, ... Are sequentially output from one row designated by row address signal RA1.

As shown in FIG. 58, the macro block 75
In the screen SCN, 0 is composed of a total of 64 (= 8 × 8) pixels, eight in the horizontal direction and eight in the vertical direction. Therefore, the pixel data in the macro block 750 can be designated by the row address signals RA1 to RA8 and the column address signals CA4, CA5.

Therefore, overall control processor 11 shown in FIG. 55 generates a row address signal and a column address signal according to the stored program as follows.

First, row address signal RA1 is output, and then column address signals CA4 and CA5 are output. Thereby, the pixel data for the first row in the macroblock 750 can be accessed (for example, read). next,
After row address signal RA2 is applied, column address signals CA4 and CA5 are applied sequentially. This causes the data to be accessed for the second row in macroblock 750. Similar operations are performed in macroblock 750.
Up to the 8th row in.

Therefore, in order to access the frame buffer memory 54 with respect to all the pixels in the macro block 750, the row address RA1 is necessary 8 times in total.
Through RA8 and a total of 16 column addresses CA must be provided.

For example, in some cases, 90 ns are required to supply the row address RA, and 120 ns are required to supply the column address CA twice and transfer the data. In this case, 1680 ns (= (90 + 120) × 8) is required to specify one macroblock.

On the other hand, when the motion vector is detected in the motion prediction unit, the macro block 751 as shown in FIG. 58 is required. That is, the pixel data included in the macro block 751 is the row address RA11.
To RA18 and column addresses CA1 to CA3. The pixel data contained in regions 752 and 753 is not needed but is accessed and then discarded to access the data for the pixels in macroblock 751.

Therefore, in order to access the pixel data in the macro block 751, a total of eight row addresses R
It is necessary to provide A and the column address CA a total of 24 times. As a result, for example, a total of 2160 ns is required for access.

(3) Examples Using SDRAM (Second, Third, and Fourth Examples) In the following description, three examples using the synchronous DRAM (hereinafter referred to as "SDRAM") as the frame buffer memory (first Second, third and fourth examples) will be described.

FIG. 60 is a system configuration diagram of the frame buffer memory 55 using SDRAM. Referring to FIG. 60, the frame buffer memory 55 includes memory cell arrays 801 to 832 divided into 32 planes in total.
It is composed of an SDRAM having The overall control processor 11 includes an address generator 840 that generates an address signal ADR for accessing the frame buffer memory 55. The address generator 840 supplies the row address signal RA and the column address signal CA as the address signal ADR to the frame buffer memory 55 via the address bus AB. The data to be accessed is the frame buffer memory 5 via the pixel data bus PB.
Given to 5. The overall control processor 11 uses the system clock signal φs for generating the address signal ADR.
c is provided to the address generator 840.

In operation, the overall control processor 11
Activates the address generator 840 according to the stored program. The address generator 840 outputs an address signal ADR for accessing the SDRAM in the frame buffer memory 55 in response to the system clock signal φsc. The address generator 840 generates the row address signal RA and the column address signal CA in the three modes (second, third and fourth examples) described below.

FIG. 61 is a time chart for explaining the basic operation (read operation in this example) of the SDRAM. Referring to FIG. 61, SDRAM has a system clock signal φsc provided from overall control processor 11.
Be operated in response to. After the row address signal RA1 is fetched in response to the fall of the signal / RAS, the signal / CA
Column address signal CA1 is taken in response to the fall of S. Address generator 840 sequentially outputs column address signals CA1 to CA8 starting from column address signal CA1 in response to system clock signal φsc. These address signals are given to the frame buffer memory 55 via the address bus AB.

Therefore, in the data read operation, S
The stored data PD1 to PD8 are read from the memory cell array in the DRAM. That is, in the example shown in FIG. 61, eight column address signals starting from the column address signal CA1 are generated, so that eight data PD1 to PD8 are read from the row designated by the row address signal RA1. .

(I) Second Example (FIGS. 62 and 63) FIG. 62 is a pixel layout diagram for explaining addressing (second example) by the address generator 840 shown in FIG. As shown in FIG. 62, the screen SCN
The pixels in the horizontal direction are designated by the column address signal CA, while the pixels in the vertical direction are designated by the row address signal RA.

Also in this example, one row address signal RA and one column address signal CA read a total of 32 bits of data from frame buffer memory 55 shown in FIG. Therefore, four pixels can be expressed by 32-bit data. In addition to this, in the second example shown in FIG. 62, as shown in FIG. 57, four pixels (for example, PC0 to PC3) in the vertical direction can be expressed by 32-bit data.

For example, macroblock 860 includes a total of 64 pixels, eight in the horizontal direction and eight in the vertical direction. As an example, addressing of pixel data in the macro block 860 in the read operation is performed as follows.

First, after the row address RA4 is given,
Column address CA1 is applied. The address generator 840 shown in FIG. 60 responds to the system clock signal φsc to the column address C that starts from the column address CA1.
A1 to CA8 are sequentially generated. Therefore, the first half data designated by column addresses CA1 to CA8 are sequentially read from one row designated by row address RA4.

Next, after the row address RA5 is given,
Column address CA1 is applied. Address generator 840
Sequentially outputs column addresses CA1 to CA8 in response to system clock signal φsc. Therefore,
All pixels in the latter half of macroblock 860 can be read.

FIG. 63 is a time chart for explaining the operation of address generator 840 shown in FIG.
To realize the addressing in the mode shown in FIG. 62, the address generator 840 shown in FIG. 60 operates as shown in FIG. 63.

Referring to FIG. 63, row address signal RA4 is taken in response to the fall of signal / RAS, and column address signal CA1 is received in response to the fall of signal / CAS.
Is taken in. The address generator 840 (not shown)
Column address signals CA1 to CA8 (not shown) starting from the fetched column address signal CA1 are sequentially output. These address signals RA4 and CA1 to CA8 are applied to frame buffer memory 55 via address bus AB shown in FIG. as a result,
In the read operation, from the frame buffer memory 55,
The stored data PD1, PD2, ... Are sequentially output.

As described above, the frame buffer memory 5
Since 5 has a total of 32 planes, 1-bit data is read from each of the memory cell arrays 801 to 832. Therefore, one data P shown in FIG.
D1 corresponds to 32-bit data. Therefore, 1
It is pointed out that one data PD1 can represent four pixels in the vertical direction in the screen SCN shown in FIG.

Then, row address signal RA5 is taken in response to the fall of signal / RAS, and column address signal CA1 is taken in response to the fall of signal / CAS. The address generator 840 has address signals CA1 to CA8 (not shown) starting from the column address signal CA1.
Are sequentially output. Therefore, macroblock 860
Data PD11 to PD18 for expressing the latter half of the pixels are sequentially read out.

In this way, one macroblock 860
Row address signal twice (that is, R
A4 and RA5), and the column address signal only needs to be performed twice (CA1 twice), the time required for addressing can be shortened as compared with the example shown in FIG.

For example, 25 is provided for one row address.
In the case where ns is required and 200 ns is required to supply the column address CA and transfer data once, a total of 4 is required.
Addresses can be made in 50 ns.

Another pixel area 862 shown in FIG. 62 shows a pixel area handled in the motion prediction unit. In order to read data for pixels in region 862, column address signal CA11 is applied after row address signal RA1 is applied. Therefore, the row address R
Data for the first one-third pixel in the pixel region 862 is sequentially read from the row designated by A1. For the other pixel regions in pixel region 862 as well, the read operation can be performed in a short time by sequentially applying row address signals RA2 and RA3.

(Ii) Third Example (FIG. 64) FIG. 64 is a time chart showing another example of the operation of the address generator 840 shown in FIG. Referring to FIG. 64, in this example, system clock signal φ is obtained after row address signal RA1 and column address signal CA1 are taken in.
A column address signal CA2 (not shown) is generated by the address generator 840 in response to sc. Therefore, 2
One column address signal CA1 and CA2 is applied to the frame buffer memory 55. As a result, the 32-bit data PD1 designated by the column address CA1 from the row designated by the row address RA1.
And the 32-bit data PD2 designated by the column address CA2 are read.

Since each of the data PD1 and PD2 includes 32-bit data, eight pixels in the horizontal direction can be represented on the screen SCN.

(Iii) Fourth Example (FIG. 65) FIG. 65 is a pixel layout diagram for explaining another example of addressing by the address generator 840 shown in FIG. Referring to FIG. 65, data on pixels in the horizontal direction in the screen SCN is designated by a row address signal, while data on pixels in the vertical direction is designated by a column address signal.

For example, to specify pixel data for macroblock 863, column address signal CA1 is applied after row address signal RA4 is applied. The address generator 840 generates column addresses CA1 to CA8 starting from the column address signal CA1. As a result, the data for the left half pixel in the macroblock 863 is read.

Next, after the row address signal RA5 is applied, the column address signal CA1 is applied. The address generator 840 generates column address signals CA1 to CA8. Therefore, the data for the right half pixel in the macroblock 863 is read.

In the processing in the motion prediction unit, similar addressing is performed on the pixels in the pixel area 865.

As described above, the above-mentioned second, third and fourth
By applying the frame buffer memory 55 using the SDRAM, as shown in the above example, the time required for addressing can be shortened.

(4) Address Generator (FIG. 66) FIG. 66 is a block diagram of the address generator 840 shown in FIG. Referring to FIG. 66, address generator 84
0 is a vertical initial address register 841, a frame size register 842, and a page size register 843.
A horizontal initial address register 844, a horizontal size register 845, registers 846 and 847, a horizontal counter 848, an incrementer 849, a right end detection circuit 850, an output control circuit 851, and a selector 852.
And 853, an adder 854, and a selector 855.

Registers 841 to 845 are assumed to hold respective initial data. Register 84
The initial address held in 1 is output as a row address via the selector 852, the adder 854, and the selector 855. On the other hand, this initial address is given to registers 846 and 847 via selector 852 and adder 854 and held there.

The horizontal initial address held in the register 844 is given to the output control circuit 851 for controlling the bit width via the incrementer 849. The output control circuit 851 outputs the column address, and the column address is output via the selector 855.

The incrementer 859 increments the horizontal address given from the horizontal initial address register 844 every eight cycles of the system clock signal φsc. When the horizontal address exceeds the page size,
The incrementer 849 increments the row address.

The data of register 847 and the data "1" are applied to adder 854, and the addition result is output as a row address, while the addition result is also applied to register 847.

When the right end of the transfer data is detected by the right end detection circuit 850, the data and frame size data held in the register 846 are supplied to the adder 854 via the selectors 852 and 853. The data indicating the addition result is output as a row address via the selector 855 and is also applied to the registers 846 and 847.

FIG. 67 is an address-page correspondence diagram showing the relationship between the row and column addresses output from the address generator 840 shown in FIG. 66 and the page. on the other hand,
FIG. 68 is a page-pixel correspondence diagram showing the relationship between the page shown in FIG. 67 and the pixels in the screen. The frame buffer memory 55 shown in FIG. 60 stores data in the form shown in FIG. The address generator 840 applies the data stored in the frame buffer memory 55 to the screen in the manner shown in FIG. Address generator 840 shown in FIG. 66 generates row address signal RA and column address signal CA such that the addressing in the manner shown in FIGS. 67 and 68 is performed.

(5) Mapping Method Next, a method of mapping each pixel data in the screen in the frame buffer memory will be described. Each of the following methods is performed by, for example, the frame buffer memory 5 shown in FIG.
1 can be applied.

First, a mapping method capable of reducing the number of data transfers will be described. FIG. 72 is a first diagram illustrating a method of mapping pixel data in a screen in the frame buffer memory. In FIG. 72, one address of the frame buffer memory is given with the data area 861 of 2 pixels in the vertical and horizontal directions as one unit. That is, the data area 8 corresponds to one address specified by the row address signal RA and the column address signal CA.
Data for four pixels included in 61 is stored in the frame buffer memory or is read from the frame buffer memory by designating its address, and data is transferred to each block through the pixel data bus. As shown in FIG. 72, for example, a data area 862 composed of 9 pixels in the horizontal direction and 9 pixels in the vertical direction, which is used for motion vector detection processing, is replaced with a data area 861.
When 5 is used as a transfer unit, all pixel data in the data area 862 can be transferred by 5 (horizontal) × 5 (vertical) = 25 times of transfer processing. This is because, for example, as shown in FIG. 58, the number of times of transfer is reduced by two and the data area that does not need to be transferred is compared to the case where a data area composed of four horizontal pixels is used as a transfer unit. 863 will also be reduced. Therefore, by using the above mapping method, the number of transfers is reduced,
Image data transfer processing can be performed at high speed.

Next, transfer of a data area composed of 8 pixels in the horizontal direction and 8 pixels in the vertical direction will be described using the above mapping method. 73 to 76
FIGS. 4A to 4C are first to fourth diagrams illustrating a transfer process of a data area of 8 pixels in the horizontal direction and 8 pixels in the vertical direction. FIGS. When transferring a data area 864 of 8 pixels in the horizontal direction and 8 pixels in the vertical direction, depending on the position of the data area 864, FIG.
There are four possible cases shown in FIGS.

In the case shown in FIG. 73, when each pixel data in the data area 864 is transferred with a data area of 2 pixels in both the horizontal and vertical directions as a transfer unit, 4 (horizontal) × 4 (vertical) = The transfer can be performed 16 times. In the case of FIGS. 74 and 75, the transfer can be performed 20 times, and in the case of FIG. 76,
The transfer can be performed 25 times. Therefore, the average number of transfers required to transfer the data area 864 is 20.25. This is compared with the case where transfer is performed in units of 4 pixels in the horizontal direction shown in FIG.
This reduces the number of transfers about 2 times.

Next, a mapping method will be described in which a data area composed of 4 pixels in the horizontal direction and 2 pixels in the vertical direction is given as one data and one address is given. Figure 7
FIG. 7 is a second diagram illustrating a method of mapping pixel data in the screen in the frame buffer memory. Figure 7
As shown in FIG. 7, one address of the frame buffer memory is given with the data area 865 composed of 4 pixels in the horizontal direction and 2 pixels in the vertical direction as one data. At this time, when the data area 866 composed of 9 pixels in the horizontal direction and 9 pixels in the vertical direction is transferred using the data area 865 as a transfer unit, the required transfer count is 3 (horizontal) × 5.
(Vertical) = 15 times. This reduces the number of times of transfer three times as compared with the case of transferring a data area consisting of 8 pixels in the horizontal direction as a transfer unit as shown in FIG. 58, and also reduces the area 867 in which data transfer is not required. .

Next, the first method for mapping the first and second color difference image data in the frame buffer memory will be described. FIG. 78 is a first diagram for mapping the first and second color difference pixel data in the frame buffer memory.
FIG. 6 is a diagram for explaining the method. Here, the first color difference pixel data is, for example, the color difference pixel data Cb converted from the RGB format to the YUV format, and the second color difference pixel data is the second color difference pixel data Cb.
The color difference pixel data is, for example, similarly converted color difference pixel data Cr. In FIG. 78, one address of the frame buffer memory is given with the data area 868 composed of four pixels in the horizontal direction as one data. Further, the first color difference pixel data 873 and the second color difference pixel data 869 are alternately mapped in the horizontal direction by four pixels each. The first color difference pixel data 873 and the second color difference pixel data 869 have a correlation with each other. For example, in the motion vector detection process, the first and second color difference pixel data 873,
It is necessary to process 869 at the same time, and data transfer is performed at the same time. Therefore, the first color difference pixel data area 872 and the second color difference pixel data area 870 are used as the transfer areas.
When transferring and, the respective data in the data area 871 may be transferred. In this case, since the first color difference pixel data area 872 and the second color difference pixel data area 870 are alternately mapped, by performing address generation once,
Each color difference pixel data in the data area 871 can be transferred, the time required for the address generation calculation can be reduced, and the image data processing can be performed at high speed.

Next, a second method for mapping the first and second color difference pixel data in the frame buffer memory will be described. FIG. 79 shows a second method for mapping the first and second color difference pixel data in the frame buffer memory.
FIG. 6 is a diagram for explaining the method. In FIG. 79, a data area 87 including two horizontal pixels and two vertical pixels.
4 is mapped as one data. Also,
First color difference pixel data 875 and second color difference pixel data 879
And are alternately mapped every two pixels in the horizontal direction. In this case, when the first color difference pixel data area 878 and the second color difference pixel data area 876 are transferred, each data in the data area 877 is transferred using the data area 874 as a transfer unit. Therefore, data can be transferred with one address generation and a small number of data transfers.

Next, a third method for mapping the first and second color difference pixel data in the frame buffer memory will be described. FIG. 80 shows a third example of mapping the first and second color difference pixel data in the frame buffer memory.
FIG. 6 is a diagram for explaining the method. In the example of FIG. 80, one address is given with one data area consisting of four pixels in the horizontal direction. In addition, the first color difference pixel data and the second color difference pixel data are alternately arranged every two pixels in the horizontal direction. Therefore, the data area of four pixels in the horizontal direction to which one address is given includes the first color difference pixel data 880 of two pixels and the second color difference pixel data 881 of two pixels. First color difference pixel data area 88
4 and the second color difference pixel data area 882 are transferred,
Each data in the data area 883 may be transferred by generating the address once. The number of transfers at this time is 5
(Horizontal) × 9 (vertical) = 45 times. For example, the first
When the color-difference pixel data and the second color-difference pixel data are separately mapped in the frame buffer memory and the data area of 4 pixels in the horizontal direction is transferred as the transfer unit as described above,
The number of times required to transfer the first color difference pixel data and the second color difference pixel data similar to that in FIG. 80 is 54 times, and the number of times of transfer is reduced by 9 times by using the third mapping method. .

Next, a fourth method for mapping the first and second color difference pixel data in the frame buffer memory will be described. FIG. 81 shows a fourth example of mapping the first and second color difference pixel data in the frame buffer memory.
FIG. 6 is a diagram for explaining the method. As shown in FIG. 81, a data area composed of 4 pixels in the horizontal direction and 2 pixels in the vertical direction is given as one data, and one address is given to be mapped in the frame buffer memory. Further, the first color difference pixel data and the second color difference pixel data are alternately mapped every two pixels in the horizontal direction. Therefore, the first color difference pixel data 88 of 2 pixels in the horizontal direction and 2 pixels in the vertical direction are included in the data area mapped as one data.
5 and second color difference pixel data 886 of 2 pixels in the horizontal direction and 2 pixels in the vertical direction. First color difference pixel data 889
And the second color difference pixel data 887, each data in the data area 888 may be transferred in a transfer unit of a data area of 4 pixels in the horizontal direction and 2 pixels in the vertical direction. At this time, since the first color difference pixel data and the second color difference pixel data are alternately arranged, the data transfer can be performed by one address generation, and the data transfer can be performed using the rectangular data area as a transfer unit. Since this is done, the number of transfers is reduced.

Next, the effect of using the first to fourth methods of mapping the first and second color difference pixel data in the frame buffer memory will be described.
As an example, description will be made using, for example, the arithmetic processing in the overall control processor 11 shown in FIG. 9 in the bidirectional predictive coding processing. FIG. 82 is a diagram showing the arithmetic processing of the overall control processor at the time of bidirectional predictive coding.

Referring to FIG. 82, in step 891, the first address is generated by the input image write process. This address generation is performed for the luminance pixel data Y, the first color difference pixel data Cb, and the second color difference pixel data Cr. The data here is transferred from the control unit 2 to the frame buffer memory 51 in the image data processing device shown in FIG.

Next, at step 892, the second address generation is executed in the motion prediction read processing.
This process is executed for the luminance pixel data Y, and the data is transferred from the frame buffer memory 51 to the control unit 2.

Next, at step 893, third address generation is executed in the motion search range read processing. Here, the process is executed on the luminance pixel data Y, and the data is transferred from the frame buffer memory 51 to the motion prediction unit 41.

Next, at step 894, a coding mode determination process is performed. Next, in step 895, fourth address generation is executed in the forward prediction image read processing. Here, processing is performed on three types of pixel data Y, Cb, and Cr, and the data is transferred from the frame buffer memory 51 to the pixel processing unit 3.

Next, at step 896, fifth address generation is executed in the backward predicted image read processing. Here, processing is performed on three types of pixel data Y, Cb, and Cr, and the data is transferred from the frame buffer memory 51 to the pixel processing unit 3.

Next, in step 897, sixth address generation is executed in the encoding target image read processing. Here, processing is performed on three types of pixel data Y, Cb, and Cr, and the data is transferred from the frame buffer memory 51 to the pixel processing unit 3.

Regarding the number of calculations in the above-mentioned overall control processor, the first to fourth values shown in FIGS.
The following table shows the results of comparison between the examples and the comparative examples using the above mapping method. Here, the comparative example shows a case where three types of pixel data Y, Cb, and Cr are separately mapped in the frame buffer memory 51, and an address is generated for each pixel data. Further, C in the table below collectively shows the first color difference pixel data Cb and the second color difference pixel data Cr.

[0487]

[Table 1]

From the above table, it can be seen that the number of address generations is reduced by 4 in the embodiment. That is, in the address generation process of the comparative example, three types of pixel data Y and C are used.
It was necessary to perform calculations for each of b and Cr and set each data in the image data transfer control unit 15 shown in FIG. 9 as a resist. On the other hand, in the above-described embodiment, since the addresses of the first color difference pixel data Cb and the second color difference pixel data Cr are collectively generated, it is possible to reduce the calculation time of four times in total and the processing time of the register set. In addition, since the overall control processor needs to perform various processes such as code amount control, various determinations associated with encoding, and other user-specific arithmetic processing, if such arithmetic operations are performed and the number of operations increases. In particular, the reduction of the above address calculation is particularly effective in executing the encoding process in real time.

[0489]

As described above, according to the first aspect of the present invention, the pixel processor for executing the discrete cosine transform processing and the quantization processing and the variable length coding processor for executing the variable length coding processing are provided. Since the pipeline control processor for pipeline controlling the processing of (1) is provided, the image data processing device capable of performing the compression processing of the image data at high speed is obtained.

Further, according to the invention of claim 2, a variable length decoding processor for executing the variable length decoding process and a pixel processor for executing the inverse quantization process and the inverse discrete cosine transform process are provided, and these processes are performed. Since the pipeline control processor for controlling the pipeline is provided, the image data processing device capable of performing the expansion processing of the image data at high speed is obtained.

Furthermore, according to the third aspect of the present invention, the pixel processor, the variable length processor, and the pipeline control processor for controlling the pipeline processing for the first and second data buses are provided. And an image data processing device capable of performing decompression processing at high speed is obtained.

Further, according to the invention of claim 4, there are provided first to fourth access means for respectively accessing the first to fourth storage means, and the access operation to the first to fourth access means is performed. Since the access control means for individually controlling the start is provided, the image data processing device capable of performing the conversion processing of the image data at high speed is obtained.

Further, according to the invention of claim 5, since the control processor for controlling the pipeline processing for a plurality of predetermined processes for image data compression and / or image data expansion is provided, the image data An image data processing device capable of high-speed processing has been obtained.

Furthermore, according to the invention of claim 6, pipeline processing for controlling pipeline processing for discrete cosine transform processing for image data compression and / or image data expansion, quantization processing and variable length data processing. Since the control processor is provided, the image data processing device capable of performing the image data processing at high speed is obtained.

Further, according to the invention of claim 7, there is provided a control processor for controlling a predetermined process for image data compression and / or image data decompression and a parallel operation for image data transfer. Since the plurality of execution instruction means for individually instructing the execution of the predetermined processing and the image data transfer are provided, the image data processing device capable of performing the image data processing at high speed is obtained.

Further, according to the invention of claim 8, the selecting means for selecting one of the variable length code and the equal length code in response to the equal length code processing flag outputted from the reading means is provided. An image data processing device is obtained which can simplify the processing and can perform the compression processing of the image data at high speed.

Further, according to the invention of claim 9, since the selecting means for selecting one of the run data, the level data and the decoded data is provided in response to the equal length processing flag outputted from the reading means, the judgment is made. An image data processing device is obtained which can simplify the processing and can perform the compression processing of the image data at high speed.

Further, according to the invention of claim 10, an address signal for serially outputting a column address signal for designating n pixel data for defining a plurality of pixels vertically arranged on the screen. Since the generating means is provided, the pixel data for a desired area in the screen can be accessed in a short time, and thus an image data processing device capable of performing image data processing at high speed can be obtained.

Further, according to the invention of claim 11, an address signal for serially outputting a column address signal for designating n pixel data for defining a plurality of pixels placed in the horizontal direction on the screen. Since the generating means is provided, the pixel data of a desired area within the screen can be accessed in a short time, and an image data processing device capable of performing image data processing at high speed can be obtained.

Further, according to the twelfth aspect of the invention, since a plurality of macroblock data defining pixels forming a screen are encoded under the pipeline processing, the image data decompression processing can be performed at high speed. An image data processing method capable of performing is obtained.

Further, according to the thirteenth aspect of the invention, since the variable length code string including the plurality of variable length codes defining the pixels forming the screen is decoded under the pipeline processing,
An image data processing method capable of performing the expansion processing of image data at high speed has been obtained.

Furthermore, according to the fourteenth aspect of the present invention, since the number of times of transfer of pixel data can be reduced, an image data processing device capable of performing image data processing at high speed can be obtained.

Further, according to the fifteenth aspect of the present invention, since the first and second color difference pixel data within a predetermined range can be transferred by one-time address generation, the image data processing can be performed at high speed. A data processor is obtained.

Further, according to the sixteenth aspect of the present invention, the first and second color difference pixel data in the predetermined range can be transferred by one time of address generation, so that the image data processing can be performed at high speed. A data processor is obtained.

Furthermore, according to the seventeenth to twenty-second aspects of the present invention, the data transfer amount can be efficiently divided and efficiently transferred, and the data amount transferred by one bus can be reduced. Further, the data transfer speed is improved, and the image data processing device capable of performing the image data processing at high speed is obtained.

Furthermore, according to the twenty-third aspect of the present invention, a control processor for controlling a predetermined process for image data compression and / or image data decompression and a parallel operation for image data transfer is provided and predetermined. A plurality of execution instruction means for individually instructing execution of the processing and image data transfer, and further, a first data bus between the control processor and the plurality of execution instruction means and a first data bus between the plurality of execution instruction means. Since the two data buses are provided, the image data processing is performed in parallel, and the image data processing device capable of performing the image data processing at high speed is obtained.

Further, according to the inventions of claims 24 to 25, at least 2 pixels dedicated to pixel data are provided.
Since the data can be transferred to a plurality of external devices at the same time by one interface means, the image data processing device capable of performing the data transfer in parallel and performing the image data processing at high speed was obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of an image compression / expansion processing device according to a first embodiment of the present invention.

FIG. 2 is a processing diagram showing image compression processing in the image compression / expansion processing apparatus shown in FIG.

FIG. 3 is a processing diagram showing image expansion processing in the image compression / expansion processing apparatus shown in FIG.

FIG. 4 is a block diagram of an image compression / expansion processing apparatus showing a second embodiment of the present invention.

FIG. 5 is a block diagram of an image compression / expansion processing apparatus showing a third embodiment of the present invention.

FIG. 6 is a block diagram of an image compression / expansion processing apparatus showing a fourth embodiment of the present invention.

FIG. 7 is a block diagram of an image compression / expansion processing apparatus showing a fifth embodiment of the present invention.

FIG. 8 is a block diagram of an image compression / expansion processing apparatus showing a sixth embodiment of the present invention.

FIG. 9 is a block diagram showing an example of a control unit.

FIG. 10 is a block diagram showing another example of the control unit.

FIG. 11 is a time chart showing pipeline processing performed under the control of the overall control processor shown in FIG. 9.

FIG. 12 is a parallel operation diagram showing parallel operation in one period T10 shown in FIG.

13 is a block diagram of the overall control processor shown in FIG.

14 is a block diagram of the motion prediction control unit shown in FIG. 9.

15 is a block diagram of the image format conversion unit shown in FIG.

16 is a block diagram of the image data transfer control unit shown in FIG.

17 is a block diagram of the instruction transfer unit shown in FIG. 9. FIG.

FIG. 18 is a block diagram showing an example of a pixel processing unit.

19 is a more detailed block diagram of the pixel processing unit shown in FIG.

FIG. 20 is a block diagram showing another example of a pixel processing unit.

21 is a more detailed block diagram of the pixel processing unit shown in FIG. 20. FIG.

22 is an operational flowchart for encoding (intra-frame prediction) in the pixel processing unit shown in FIG.

23 is an operation flowchart for decoding (intra-frame prediction) in the pixel processing unit shown in FIG.

24 is an operation flowchart for encoding (bidirectional prediction) in the pixel processing unit shown in FIG.

FIG. 25 is an operational flowchart for decoding (bidirectional prediction) in the pixel processing unit shown in FIG.

FIG. 26 is a time chart showing pipeline processing for encoding in the pixel processing unit shown in FIG.

27 is a time chart showing pipeline processing in intra-frame prediction in the pixel processing unit shown in FIG.

28 is a time chart showing pipeline processing in one-way processing in the pixel processing unit shown in FIG.

29 is a time chart showing pipeline processing in bidirectional prediction in the pixel processing unit shown in FIG.

FIG. 30 is a block diagram showing a first system configuration for variable length processing.

31 is a flowchart of the variable length coding process in the first system configuration shown in FIG.

32 is a flowchart of the variable length decoding process in the first system configuration shown in FIG.

33 is a data storage structure diagram of the variable length coding table memory shown in FIG. 30. FIG.

34 is a data storage structure diagram of the variable length decoding table memory shown in FIG. 30. FIG.

[Fig. 35] Fig. 35 is a process flowchart for explaining a process of generating a variable-length code string.

FIG. 36 is a block diagram showing a first example of a variable length processor.

FIG. 37 is a block diagram showing a second example of a variable length processor.

FIG. 38 is a block diagram showing a third example of a variable length processor.

FIG. 39 is a block diagram showing a second system configuration for variable length processing.

40 is a block diagram of the variable length processor shown in FIG. 39. FIG.

41 is a block diagram of the address generator shown in FIG. 40. FIG.

42 is a flow chart of variable-length coding processing in the address generator shown in FIG. 41.

43 is a flowchart of the variable length decoding process in the address generator shown in FIG. 41.

FIG. 44 is a block diagram of the variable-length code string generation / decomposition circuit shown in FIG. 40.

45 is a flowchart of the variable length coding process in the variable length code string generation / decomposition circuit shown in FIG. 44.

FIG. 46 is a flowchart of a variable length decoding process in the variable length code string generation / decomposition circuit shown in FIG. 44.

FIG. 47 is a block diagram of the external interface circuit shown in FIG. 40.

48 is a flowchart of the variable length coding process in the external interface circuit shown in FIG. 47.

49 is a flowchart of a variable length decoding process in the external interface circuit shown in FIG. 47.

50 is a grouped variable length code table used in the variable length processor shown in FIG. 39. FIG.

51 is a data format diagram of data stored in the variable length coding table memory shown in FIG. 39. FIG.

FIG. 52 is a data format diagram of encoded data in variable length encoding processing.

FIG. 53 is a basic configuration diagram of a memory cell array in the frame buffer memory.

FIG. 54 is a block diagram of a frame buffer memory.

FIG. 55 is a system configuration diagram of a frame buffer memory using a DRAM.

FIG. 56 is a pixel layout diagram showing the relationship between the data stored in the frame buffer memory shown in FIG. 55 and the pixels in the screen.

57 is a pixel layout diagram showing a relationship between data stored in the frame buffer memory shown in FIG. 60 and pixels in a screen. FIG.

FIG. 58 is a pixel layout diagram for explaining addressing by the DRAM controller shown in FIG. 55.

59 is a time chart showing a read operation of the frame buffer memory under the control of the DRAM controller shown in FIG. 55.

FIG. 60 is a system configuration diagram of a frame buffer memory using SDRAM.

FIG. 61 is a time chart for explaining the read operation of the SDRAM.

FIG. 62 is a pixel layout diagram for explaining addressing by the address generator shown in FIG. 60.

63 is a time chart for explaining an example of the operation of the address generator shown in FIG. 60. FIG.

64 is a time chart showing another example of the operation of the address generator shown in FIG. 60.

65 is a time chart showing still another example of the operation of the address generator shown in FIG. 60. FIG.

66 is a block diagram of the address generator shown in FIG. 60. FIG.

67 is an address-page correspondence diagram showing the relationship between the row and column addresses output from the address generator shown in FIG. 66 and the page.

68 is a page-pixel correspondence diagram showing the relationship between the page shown in FIG. 67 and the pixels in the screen.

[Fig. 69] Fig. 69 is a block diagram illustrating main processing in an image compression algorithm recommended by an international standard.

FIG. 70 is a block diagram of a conventional image compression / expansion processing device.

71 is a block diagram of the DSP shown in FIG. 70. FIG.

FIG. 72 is a diagram illustrating a first method of mapping pixel data in a screen in a frame buffer memory.

FIG. 73 is a first diagram illustrating a transfer process of a data area of 8 pixels in the horizontal direction and 8 pixels in the vertical direction.

FIG. 74 is a second diagram illustrating a transfer process of a data area of 8 pixels in the horizontal direction and 8 pixels in the vertical direction.

[Fig. 75] Fig. 75 is a third diagram illustrating a transfer process of a data area of 8 pixels in the horizontal direction and 8 pixels in the vertical direction.

FIG. 76 is a fourth diagram illustrating a transfer process of a data area of 8 pixels in the horizontal direction and 8 pixels in the vertical direction.

[Fig. 77] Fig. 77 is a diagram illustrating a second method for mapping pixel data in a screen in a frame buffer memory.

FIG. 78 is a diagram illustrating a first method of mapping first and second color difference pixel data in a frame buffer memory.

FIG. 79 is a diagram illustrating a second method for mapping the first and second color difference pixel data in the frame buffer memory.

FIG. 80 is a diagram illustrating a third method for mapping the first and second color difference pixel data in the frame buffer memory.

FIG. 81 is a diagram illustrating a fourth method of mapping the first and second color difference pixel data in the frame buffer memory.

[Fig. 82] Fig. 82 is a diagram illustrating arithmetic processing of the overall control processor at the time of bidirectional predictive coding.

FIG. 83 is a block diagram of an image compression / expansion processing device showing a seventh embodiment of the present invention.

FIG. 84 is a block diagram of an image compression / decompression processing device showing an eighth embodiment of the present invention.

FIG. 85 is a block diagram of an image compression / decompression processing device showing a ninth embodiment of the present invention.

FIG. 86 is a block diagram of an image compression / decompression processing device showing a tenth embodiment of the present invention.

FIG. 87 is a block diagram of an image compression / decompression processing device showing an eleventh embodiment of the present invention.

FIG. 88 is a block diagram of an image compression / decompression processing device showing a twelfth embodiment of the present invention.

FIG. 89 is a block diagram of an image compression / decompression processing device showing a thirteenth embodiment of the present invention.

FIG. 90 is a block diagram of an image compression / decompression processing device showing a fourteenth embodiment of the present invention.

FIG. 91 is a block diagram of an image compression / decompression processing device showing a fifteenth embodiment of the present invention.

FIG. 92 is a block diagram showing still another example of the control unit.

FIG. 93 is a block diagram showing still another example of a pixel processing unit.

94 is a more detailed first block diagram of the pixel processing unit shown in FIG. 93. FIG.

95 is a more detailed second block diagram of the pixel processing unit shown in FIG. 18. FIG.

[Explanation of symbols]

1 Host Interface Circuit 2, 21, 22 Control Unit 3, 31, 32 Pixel Processing Unit 41-46 Motion Prediction Unit 51-55 Frame Buffer Memory 81, 82 Input / Output Memory 11 Overall Control Processor 12, 121-125 Variable Length Processor 13 Motion prediction control unit 14 Image format conversion unit 15 Image data transfer control unit 16 Pixel processing unit instruction transfer unit 17 Main port 18 Image data port 19 VRAM port 20 Code data port

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Segawa 4-chome, Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Corporation System LSI Development Laboratory (72) Inventor, Kazuya Ishihara 4 Mizuhara, Itami City, Hyogo Prefecture 1-chome, Mitsubishi Electric Corporation System LSI Development Laboratory (72) Inventor Satoshi Kumaki 4-1-1, Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Corporation System-LS Development Laboratory (72) Inventor Mitsuo Hanami 4-1-1 Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Corporation System LSI Development Laboratory

Claims (25)

[Claims] 1. A pixel data storage means for storing pixel data to be compressed, a pixel data bus for transmitting pixel data stored in the pixel data storage means, and a pixel transmitted via the pixel data bus. A pixel processor that performs a discrete cosine transform process and a quantization process on the data and outputs a pixel code, a pixel code bus that transmits the pixel code output from the pixel processor, and a pixel code bus that transmits the pixel code. A variable-length coding processor that executes a variable-length coding process on the pixel code and outputs the variable-length code; and pipes for the pixel data bus, the pixel processor, the pixel code bus, and the variable-length coding processor. An image data processing device including a pipeline control processor for controlling line processing. 2. A variable length code storage means for storing a compressed variable length code, a variable length code bus for transmitting the variable length code stored in the variable length code storage means, and a variable length code bus. The variable-length code transmitted by the variable-length decoding processor for performing a variable-length decoding process and outputting a pixel code, and a pixel code bus for transmitting the pixel code output from the variable-length decoding processor, A pixel processor that performs inverse quantization processing and inverse discrete cosine transform processing on a pixel code transmitted via the pixel code bus and outputs expanded pixel data, the variable length code bus, and the variable length decoding Image data processing device including a pixelization processor, the pixel code bus, and a pipeline control processor that controls pipeline processing for the pixel processor. . 3. A pixel processor that performs discrete cosine transform processing and quantization processing on pixel data in a data compression mode, and inverse quantization processing and inverse discrete cosine transform processing on a pixel code in data expansion mode, and data. A variable-length processor that performs a variable-length coding process on a pixel code in a compression mode and a variable-length decoding process on a variable-length code in a data decompression mode; and a pixel between the pixel processor and the variable-length processor. A first data bus for transmitting data and a variable length code; a second data bus for transmitting a pixel code between the pixel processor and the variable length processor; the pixel processor; the variable length processor; And control pipeline processing for the second data bus. And a pipeline control processor, the image data processing apparatus. 4. A first storage means for storing table data for conversion, a second storage means for storing image data to be image-processed, and a third storage means for storing image data for display. , And an image data processing device capable of accessing a fourth storage means for storing the converted image data, the first storage means accessing the first storage means, and the second storage means. Access means for accessing the third storage means, third access means for accessing the third storage means, fourth access means for accessing the fourth storage means, and first and fourth access means Image data processing device, which includes access control means for individually controlling the start of an access operation to the means. 5. A control processor for controlling pipeline processing for a plurality of predetermined processes for image data compression and / or image data decompression, and the plurality of units in response to a control signal provided from the control processor. 1 of the predetermined processing of
An image data processing device including an image processing processor for executing the image data processing device. 6. A pipeline processing control processor for controlling pipeline processing for discrete cosine transform processing, quantization processing and variable length data processing for image data compression and / or image data expansion, and the pipeline processing control. An image data processing device, comprising: a variable length processor that executes the variable length data processing in response to a control signal given from the processor. 7. Control processors for controlling parallel operations for predetermined processing and image data transfer for image data compression and / or image data decompression, each responsive to a control signal provided by said control processor. And a plurality of execution instruction means for individually instructing execution of the predetermined processing and the image data transfer. 8. A storage means for storing a variable length code corresponding to a combination of run data and level data, the code length data and an equal length code processing flag, and responding to given run data and given level data. Read means for reading the corresponding variable length code, its code length data and equal length code processing flag from the storage means, and the given run data and the given level data, according to a predetermined rule. One of the variable-length code and the equal-length code in response to the equal-length coding processing flag output from the reading means, which executes coding processing and outputs a corresponding equal-length code. An image data processing device, comprising: a selection unit that selects the output code and a code combination unit that sequentially combines the output codes output from the selection unit. 9. A storage means for storing run data, level data and an equal length processing flag corresponding to the variable length code, and extracting the variable length code from a given variable length code string including the combined variable length code. Extracting means, reading means for reading the corresponding run data, level data and equal length processing flag from the storing means in response to the variable length code extracted by the extracting means; and the variable extracted by the extracting means. For long code,
Isometric decoding means for executing a decoding process according to a predetermined rule and outputting the corresponding decoded data; and, in response to an isometric processing flag output from the reading means, the run data and the level data, An image data processing device, comprising: a selection unit that selects one of the decoded data. 10. An n (n ≧ 2) memory cell array for storing pixel data for defining pixels in a screen, wherein the n memory cell arrays include one row address signal and one Responsive to providing a column address signal, each of which outputs n pixel data stored in a corresponding one of the n memory cell arrays, the n pixel data being vertically aligned on a screen. Includes address signal generation means for defining a plurality of placed pixels and serially outputting a column address signal for defining pixel data for pixels placed horizontally in the screen in response to a serial clock signal. , Image data processing device. 11. An n (n ≧ 2) memory cell array for storing pixel data for defining pixels in a screen, wherein the n memory cell arrays include one row address signal and one Responsive to the application of a column address signal, each of which outputs n pixel data stored in a corresponding one of the n memory cell arrays, the n pixel data being horizontally aligned on a screen. Includes address signal generation means for defining a plurality of placed pixels and serially outputting, in response to a serial clock signal, a column address signal for defining pixel data for pixels placed in a vertical direction on the screen. , Image data processing device. 12. An image data processing method for encoding a plurality of macroblock data defining pixels forming a screen under pipeline processing, wherein discrete cosine transform processing and quantization processing are performed on macroblock data. Then, a step of generating a pixel code, a step of performing a variable length coding process on the pixel code generated in the step, a step of generating a variable length code, and combining the variable length code generated in the step,
And a step of generating a variable-length code string. 13. An image data processing method for decoding, under pipeline processing, a variable-length code string including a plurality of variable-length codes that define pixels forming a screen, wherein the variable-length code string is converted to the variable-length code string. A step of extracting a long code; a step of performing a variable length decoding process on the variable length code extracted in the step to generate a pixel code; a step of dequantizing the pixel code generated in the step; Performing discrete cosine transform processing to generate macroblock data defining pixels forming a screen. 14. An image data processing method for mapping the first pixel data to a storage means for storing a plurality of first pixel data defining pixels in a screen, the method being two-dimensional from the first pixel data. A second step of determining a plurality of second pixel data that are adjacent to each other and are included in a rectangular area; and a second step of giving one address of the storage means to the second pixel data by using the second pixel data as one data. An image data processing method comprising: a step; and a third step of transferring the second pixel data from or to the storage means using an address of the second pixel data. 15. A pixel data processing method for mapping the first and second color difference pixel data to a storage means for storing first and second color difference pixel data associated with each other for defining pixels in a screen. A first step of alternately mapping the first and second color difference pixel data in the transfer unit in the transfer unit, and the first or second color difference pixel data in the transfer unit from the storage unit or to the storage unit A second step of transferring, an image data processing method. 16. An image data processing method for mapping the first and second color difference pixel data to a storage means for storing mutually associated first and second color difference pixel data for defining pixels in a screen. A first step of mapping third color difference pixel data, which is the same number of the first and second color difference pixel data, into the storage means as one data; and the storage means as the third color difference pixel data as one data. A second step of transferring from or to the storage means. 17. A first pixel data storage means for storing pixel data to be compressed, a first pixel data bus for transmitting the pixel data stored in the first pixel data storage means, and the first pixel data bus. 1st and 2nd which receives the pixel data transmitted via 1 pixel data bus, extracts the motion prediction reference data using the transmitted pixel data, and outputs the said motion prediction reference data. A pixel processor having a data port, a second pixel data bus for transmitting the motion prediction reference data output from the second data port of the pixel processor, and a second pixel data bus for transmitting the motion prediction reference data. Second pixel data storage means for storing reference data for motion prediction; and motions stored in the second pixel data storage means and transmitted via the second pixel data bus. A motion prediction unit that executes a motion prediction process using prediction reference data to generate a motion vector, and a pipeline process for the first and second pixel data buses, the pixel processor, and the motion prediction unit. And an image data processing device including a pipeline control processor. 18. The pipeline control processor further includes a system controller outputting output control signals of first and second data ports of the pixel processor.
The image data processing device according to claim 17. 19. A first pixel data storage means for storing pixel data to be compressed, a first pixel data bus for transmitting the pixel data stored in the first pixel data storage means, and the first pixel data bus. A first data port for receiving pixel data transmitted via one pixel data bus, extracting motion prediction reference data using the transmitted pixel data, and outputting the motion prediction reference data; A pixel processor having a plurality of second data ports for dividing and outputting the reference data for motion prediction; and a pixel processor provided corresponding to each of the second data ports and output from the second data port. A plurality of second pixel data buses for transmitting reference data for motion prediction, and a plurality of second pixel data buses provided corresponding to each of the second data ports, and transmitted via the second pixel data buses. A plurality of second pixel data storage units for storing reference data for motion prediction; and a second pixel data storage unit provided corresponding to each of the second data ports, stored in the second pixel data storage unit, and the second pixel A plurality of motion prediction units that perform a motion prediction process using the motion prediction reference data transmitted via a data bus to generate motion vectors; the first pixel data bus, the pixel processor, and the plurality of motion estimation units; An image data processing device comprising a second pixel data bus and a pipeline control processor controlling pipeline processing for the plurality of motion prediction units. 20. First pixel data storage means for storing pixel data to be compressed; first pixel data bus for transmitting the pixel data stored in the first pixel data storage means; A first data port for receiving pixel data transmitted via one pixel data bus, extracting motion prediction reference data using the transmitted pixel data, and outputting the motion prediction reference data; A pixel processor having a plurality of second data ports for dividing and outputting the motion prediction reference data according to the type of the motion prediction reference data; and a pixel processor provided corresponding to each of the second data ports. A plurality of second pixel data buses for transmitting the motion prediction reference data output from the second data port, and a plurality of second pixel data buses provided corresponding to each of the second data ports. A plurality of second pixel data storage means for storing motion prediction reference data transmitted via a second pixel data bus, an address bus connected to the plurality of second pixel data storage means, A motion prediction process is performed using the motion prediction reference data that is provided corresponding to each second data port, is stored in the second pixel data storage means, and is transmitted via the second pixel data bus. A plurality of motion prediction units that execute and generate a motion vector according to the type of the motion prediction reference data; the first pixel data bus, the pixel processor, the plurality of second pixel data buses, and the address A bus, and a pipeline control processor that controls pipeline processing for the plurality of motion prediction units,
Image data processing device. 21. First pixel data storage means for storing pixel data to be compressed; first pixel data bus for transmitting the pixel data stored in the first pixel data storage means; A first pixel for receiving pixel data transmitted via one pixel data bus, extracting different types of motion prediction reference data using the transmitted pixel data, and outputting the motion prediction reference data; A plurality of pixel processors each having a data port and a second data port for outputting the reference data for motion prediction according to the type of the reference data for motion prediction; Second
A plurality of second pixel data buses for transmitting the motion prediction reference data output from the data port of the
A plurality of second pixel data storage means for storing the motion prediction reference data transmitted via the pixel data bus, and the second pixel data storage means provided corresponding to each of the pixel processors.
A plurality of motion prediction units that perform motion prediction processing using the motion prediction reference data stored in the pixel data storage unit and transmitted via the second pixel data bus; Image data processing apparatus including a first pixel data bus, the plurality of pixel processors, the plurality of second pixel data buses, and a pipeline control processor that controls pipeline processing for the plurality of motion prediction units. . 22. The motion prediction reference data stored in the plurality of second pixel data storage units are stored in different second pixel data storage units, which differ depending on the type of the luminance component and the color difference component. Claims 19 to 2
1. The image data processing device according to 1. 23. Control processors for controlling predetermined operations for image data compression and / or image data decompression and parallel operations for image data transfer, each responsive to a control signal provided by said control processor. A plurality of execution instruction means for individually instructing execution of the predetermined processing and the image data transfer; and a first data bus for transferring data between the control processor and the plurality of execution instruction means. A second transfer data between the plurality of execution command means
An image data processing device including a data bus. 24. Discrete cosine transform processing and / or inverse discrete cosine transform processing for image data compression and / or image data decompression, and quantization processing and / or
Alternatively, image processing means for performing inverse quantization processing, at least two interface means dedicated to image data, and data for image data compression and / or image data expansion processed by the image processing means are stored. An image data processing device, comprising: a storage unit for storing data; and a data bus for transferring data between the interface unit and the storage unit. 25. Discrete cosine transform processing and / or inverse discrete cosine transform processing for image data compression and / or image data decompression, and quantization processing and / or
Alternatively, image processing means for performing inverse quantization processing, at least two interface means dedicated to image data, and data for image data compression and / or image data expansion processed by the image processing means are stored. And a plurality of data buses provided for each of the interface means for transferring data between each of the interface means and the storage means.