JP2006186346A5 - - Google Patents

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JP2006186346A5
JP2006186346A5 JP2005347517A JP2005347517A JP2006186346A5 JP 2006186346 A5 JP2006186346 A5 JP 2006186346A5 JP 2005347517 A JP2005347517 A JP 2005347517A JP 2005347517 A JP2005347517 A JP 2005347517A JP 2006186346 A5 JP2006186346 A5 JP 2006186346A5
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Japan
Prior art keywords
memory
conductive layer
semiconductor device
organic
layer
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JP2005347517A
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JP4954537B2 (en
JP2006186346A (en
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Priority to JP2005347517A priority Critical patent/JP4954537B2/en
Priority claimed from JP2005347517A external-priority patent/JP4954537B2/en
Publication of JP2006186346A publication Critical patent/JP2006186346A/en
Publication of JP2006186346A5 publication Critical patent/JP2006186346A5/ja
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Claims (14)

複数のメモリセルを含むメモリセルアレイを有する有機メモリと、
前記有機メモリを制御する制御回路と、
アンテナとを有し、
前記複数のメモリセルはそれぞれトランジスタ記憶素子を有し、
前記記憶素子は、第1の導電層と、有機化合物層と、2の導電層とを有し、
前記第2の導電層は、前記複数のメモリセルが有する記憶素子に共通であり、線状に設けられることを特徴とする半導体装置。
An organic memory having a memory cell array including a plurality of memory cells;
A control circuit for controlling the organic memory ;
Has an antenna, a,
Wherein a plurality of memory cells Waso respectively, a transistor and a memory element,
The storage element, possess a first conductive layer, an organic compound layer, a second conductive layer, and
The second conductive layer is common to memory elements included in the plurality of memory cells and is provided in a linear shape .
複数のメモリセルを含むメモリセルアレイを有する有機メモリと、
前記有機メモリを制御する制御回路と、
アンテナとを有し、
前記複数のメモリセルはそれぞれトランジスタ記憶素子を有し、
前記記憶素子は、第1の導電層と、有機化合物層と、2の導電層とを有し、
前記第2の導電層は、前記複数のメモリセルが有する記憶素子に共通であり、線状に設けられ、
前記第1の導電層及び前記第2の導電層の少なくとも一方透光性を有することを特徴とする半導体装置。
An organic memory having a memory cell array including a plurality of memory cells;
A control circuit for controlling the organic memory ;
Has an antenna, a,
Wherein a plurality of memory cells Waso respectively, a transistor and a memory element,
The storage element has a first conductive layer, an organic compound layer, a second conductive layer, and
The second conductive layer is common to storage elements included in the plurality of memory cells, and is provided in a linear shape.
Wherein at least one of the first conductive layer and the second conductive layer, a semiconductor device characterized by having a light-transmitting property.
請求項2において、In claim 2,
前記有機化合物層は、光を照射することによって電気抵抗が変化する材料を用いて設けられることを特徴とする半導体装置。The semiconductor device is characterized in that the organic compound layer is provided using a material whose electrical resistance changes when irradiated with light.
請求項1又は請求項2において、In claim 1 or claim 2,
前記有機化合物層は、前記第1の導電層と前記第2の導電層の間に電位差を生じさせることによって電気抵抗が変化する材料を用いて設けられることを特徴とする半導体装置。The semiconductor device is characterized in that the organic compound layer is provided using a material whose electric resistance is changed by generating a potential difference between the first conductive layer and the second conductive layer.
請求項1又は請求項において、
前記有機化合物層は加熱することによって電気抵抗が変化する材料を用いて設けられることを特徴とする半導体装置。
In claim 1 or claim 2 ,
The organic compound layer, wherein a provided using a material that electrical resistivity I by the heating to Turkey changes.
請求項1乃至請求項5のいずれか一項において、In any one of Claims 1 thru | or 5,
前記第2の導電層は、前記アンテナが設けられている面と同一面上又は平行な面上に設けられることを特徴とする半導体装置。The semiconductor device, wherein the second conductive layer is provided on the same plane or a plane parallel to a plane where the antenna is provided.
請求項1乃至請求項6のいずれか一項において、In any one of Claims 1 thru | or 6,
前記第2の導電層は、くし状に設けられることを特徴とする半導体装置。The semiconductor device, wherein the second conductive layer is provided in a comb shape.
請求項1乃至請求項6のいずれか一項において、In any one of Claims 1 thru | or 6,
前記第2の導電層は、導通した複数の線状の導電層であることを特徴とする半導体装置。The semiconductor device, wherein the second conductive layer is a plurality of conductive linear conductive layers.
請求項1乃至請求項6のいずれか一項において、In any one of Claims 1 thru | or 6,
前記第2の導電層は、はしご型に設けられることを特徴とする半導体装置。The semiconductor device, wherein the second conductive layer is provided in a ladder shape.
請求項1乃至請求項のいずれか一において、
前記有機化合物層は、電子輸送層はホール輸送層であることを特徴とする半導体装置。
In any one of claims 1 to 9,
The organic compound layer, wherein a is also an electron-transporting layer is a hole transport layer.
請求項1乃至請求項10のいずれか一において、
RAM(Dynamic Random Access Memory)、SRAM(Static Random Access Memory)、FeRAM(Ferroelectric Random Access Memory)、マスクROM(Mask Read Only Memory)、PROM(Programmable Read Only Memory)、EPROM(Electrically Programmable Read Only Memory)、EEPROM(Electrically Erasable Read Only Memory)、又はフラッシュメモリを有することを特徴とする半導体装置。
In any one of claims 1 to 10,
D RAM (Dynamic Random Access Memory) , SRAM (Static Random Access Memory), FeRAM (Ferroelectric Random Access Memory), mask ROM (Mask Read Only Memory), PROM (Programmable Read Only Memory), EPROM (Electrically Programmable Read Only Memory) , EEPROM (Electrically Erasable Read Only Memory ), or a semiconductor device characterized by having a flash memory.
請求項1乃至請求項11のいずれか一において、
源回路、クロック発生回路、復調回路、変調回路、命令解析部、又は符号化回路を有することを特徴とする半導体装置。
In any one of claims 1 to 11,
Power circuit, a clock generation circuit, a demodulation circuit, a modulation circuit, the instruction decoder, or a semiconductor device characterized by having the encoding circuits.
請求項1乃至請求項12のいずれか一において、
前記有機メモリと前記アンテナは、ガラス基板上に設けられることを特徴とする半導体装置。
In any one of claims 1 to 12,
The organic memory and the antenna are provided on a glass substrate.
請求項1乃至請求項12のいずれか一において、
前記有機メモリと前記アンテナは、可撓性基板上に設けられることを特徴とする半導体装置。
In any one of claims 1 to 12,
The organic memory and the antenna are provided on a flexible substrate.
JP2005347517A 2004-12-03 2005-12-01 Semiconductor device Expired - Fee Related JP4954537B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005347517A JP4954537B2 (en) 2004-12-03 2005-12-01 Semiconductor device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2004351096 2004-12-03
JP2004351096 2004-12-03
JP2005347517A JP4954537B2 (en) 2004-12-03 2005-12-01 Semiconductor device

Publications (3)

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JP2006186346A JP2006186346A (en) 2006-07-13
JP2006186346A5 true JP2006186346A5 (en) 2008-12-11
JP4954537B2 JP4954537B2 (en) 2012-06-20

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JP2005347517A Expired - Fee Related JP4954537B2 (en) 2004-12-03 2005-12-01 Semiconductor device

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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4974613B2 (en) * 2006-08-29 2012-07-11 株式会社日立製作所 IC memory, access device for IC memory, and validity verification method
CN101529596B (en) * 2006-11-29 2011-12-14 株式会社半导体能源研究所 Device, and method for manufacturing the same
JP2008166420A (en) * 2006-12-27 2008-07-17 Semiconductor Energy Lab Co Ltd Semiconductor device
US8053253B2 (en) * 2008-06-06 2011-11-08 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
CN112786785B (en) * 2021-01-11 2022-09-02 季华实验室 Ultrathin one-dimensional organic single crystal array film and preparation method and application thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02239664A (en) * 1989-03-13 1990-09-21 Olympus Optical Co Ltd Electric memory
JP3090198B2 (en) * 1997-08-21 2000-09-18 日本電気株式会社 Structure of semiconductor device and method of manufacturing the same
JP3217326B2 (en) * 1999-03-19 2001-10-09 富士通株式会社 Ferroelectric memory with electromagnetic shielding structure
JP2001189431A (en) * 1999-12-28 2001-07-10 Seiko Epson Corp Memory cell structure and memory device
US6646912B2 (en) * 2001-06-05 2003-11-11 Hewlett-Packard Development Company, Lp. Non-volatile memory
TWI281748B (en) * 2001-12-18 2007-05-21 Matsushita Electric Ind Co Ltd Non-volatile memory
JP2003229538A (en) * 2002-02-05 2003-08-15 Matsushita Electric Ind Co Ltd Non-volatile memory and manufacturing method thereof
JP4239693B2 (en) * 2002-06-07 2009-03-18 三菱化学株式会社 Information storage device and information storage / reproduction method using the information storage device
JP2004128471A (en) * 2002-08-07 2004-04-22 Canon Inc Nonvolatile memory device
JP4393859B2 (en) * 2002-12-27 2010-01-06 株式会社半導体エネルギー研究所 Method for producing recording medium

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