JP2006179021A - Logic synthesizer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a logic synthesizer capable of preventing unnecessary load distribution and performing load distribution in consideration of the optimal cell arrangement and a wiring area at the time of layout in logic synthesis of LSI design. <P>SOLUTION: A room for improvement in layout remains at the time of logic synthesis by analyzing an RTL (s2), extracting a high fan-out network (s3) and inserting a buffer for a clock tree to be performed at the time of layout into the RTL to the network (s4) and the optimal layout in consideration of the cell arrangement, the wiring area is performed by a layout tool. In addition, since the library is analyzed (s6) and a cell with large drive capacity is not used at the time of logic synthesis (s7), the optimal layout by converging timing is performed by re-mapping a high drive cell to a place where timing is severe at the time of layout. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a logic synthesis device for logic synthesis and layout of LSI (Large Scale Integration) design.

  In the conventional LSI design method, at the stage of logic synthesis, a portion with a large number of fan-outs is buffered for load distribution and proceeds to a layout process.

  Also, at the stage of logic synthesis, high drive cells are mapped to locations where the load is large and processing speed is desired to be high, and the process proceeds to the layout process.

As a similar technique, there is one described in Japanese Patent Application Laid-Open No. 2000-231583 published by NEC Corporation. This is not a technique of replacing logic cells with high drive cells for delay adjustment when performing logic synthesis in consideration of conventional floor plans, but adjusting buffer considering the number of fan-outs based on temporary floor plan information. Is automatically inserted to improve the delay (see, for example, Patent Document 1).
JP 2000-231583 A

  However, even if the conventional method is used, there is no guarantee that the timing is surely converged after the placement and routing at the time of layout. In addition, since a fan-out adjustment buffer is inserted at the time of logic synthesis, wiring efficiency may be deteriorated at the time of layout.

  Therefore, the present invention does not insert a buffer for load distribution at the time of logic synthesis, but analyzes a register transfer level hardware description language: RTL, extracts a high fan-out net, and outputs that net at the time of layout. Insert a buffer for the clock tree to be performed into the RTL.

  Analyzing the library used for logic synthesis and assuming that timing violations remain after layout, cells with large drive capacity are not used during logic synthesis to leave room for timing adjustment. Leave room for improvement in logic synthesis.

  As a result, optimal load distribution in consideration of the cell arrangement and the wiring area is performed by the layout tool, unnecessary load distribution at the time of logic synthesis is prevented, and the problem that the wiring is congested and the layout cannot be solved.

  In addition, high drive cells are not used for logic-synthesizing locations where logic synthesis is used, so they can be used after layout, and by re-mapping high drive cells, wiring can wrap around the layout and converge timing. Solve the problem of being unable to do so.

  In order to solve the above problems, the invention according to claim 1 is an analysis means for analyzing the description of the logic design, an extraction means for extracting a portion where the fan-out number is a predetermined value or more based on the analysis, And an insertion means for inserting a clock tree buffer for adjustment at the time of layout in the extracted portion.

  According to the present invention, an RTL is analyzed, a high fan-out net is extracted, and a buffer for a clock tree to be performed at the time of layout is inserted into the RTL, so there is room for improvement in layout at the time of logic synthesis. Therefore, unnecessary load distribution can be prevented, and load distribution can be performed in consideration of the optimum cell arrangement and wiring area during layout.

  In addition, since the library is analyzed and cells with large drive capability are not used during logic synthesis, high drive cells can be remapped at the timing of layout, and optimal layout with converged timing can be performed. be able to.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

  The processing flow of the present invention is shown in FIG. First, the RTL created by the designer is read into this apparatus (s1). Next, based on the read information, this RTL is analyzed by using Verilog's PLI (Programmable Language Interface) (s2), and a description portion where the fan-out number increases is searched (s3). . A description example in which the number of fan-outs is increased is shown in FIG.

  In FIG. 2, according to the logic in the case statement from the 15th line, the sel [0] and sel [1] signals are the select signals of 64 × 3 multiplexers (FIG. 3). Normally, if logic synthesis is performed as it is, the sel [0] and sel [1] signals must drive 64 × 3 cells, respectively, so the load is distributed based on the load capacity estimated by the floor plan. A tree of buffers is formed (FIG. 4).

  However, this buffering may be unnecessary depending on the layout arrangement. In order to accurately estimate the load capacity, it cannot be determined that the layout is not actually performed, and even if the floor plan is estimated in advance and the load capacity is estimated, it is re-synthesized by RTL correction and re-layout. Each time, the placement can change.

  Further, this unnecessary buffering may increase wiring and cause a problem of wiring congestion. This wiring congestion problem causes an increase in chip size and an increase in delay due to wiring wraparound.

  In order to solve this problem, in the present invention, synthesis is performed such that adjustment is made in the layout without load distribution in the logic synthesis stage. Specifically, as shown in FIG. 5, a buffer for performing a clock tree is inserted into the output of the sel signal (s4). As a result, it is possible to proceed to the layout process without performing unnecessary load distribution at the time of logic synthesis, and it is possible to perform fanout adjustment in consideration of the actual arrangement state at the time of layout. In addition, the buffer tree preferentially inserts an optimum buffer at the time of layout, and solves the problem of unnecessarily load-distributed buffer chains congested with wiring, which has occurred in the conventional method.

  Next, a logic synthesis library corresponding to the technology to be used is read (s5). At this time, the library is analyzed (s6), and a cell having a large drive capability as a logic cell is not used during logic synthesis (s7). The reason is that after the layout, when a delay problem occurs, a cell having a larger drive capability must be mapped. Here, if a cell with the maximum drive capability is used at the time of logic synthesis, it cannot be improved any further and it becomes very difficult to deal with, and in the worst case, it may be a re-layout. Incurs a large increase. This problem can be prevented if a cell having a large drive capability is not used during logic synthesis.

  The above correspondence is performed before logic synthesis, logic synthesis is performed (s8), and a net list is output (s9).

  In the above embodiment, Verilog is taken as an example of HDL language, but similar analysis is possible in other languages.

It is a flowchart which shows one Example of the logic synthesis process which concerns on this invention. It is a figure which shows the RTL description which the number of fan-outs of one Example increases. It is a circuit diagram of one Example. FIG. 3 is a circuit diagram of load distribution according to an embodiment. It is the circuit diagram which made the clock tree of one Example.

Claims (1)

An analysis means for analyzing the description of the logical design;
Extraction means for extracting a location where the fan-out number is equal to or greater than a predetermined value based on the analysis;
Insertion means for inserting a clock tree buffer for adjustment at the time of layout into the extracted portion;
A logic synthesis device for performing LSI logic synthesis, comprising:

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