CN109376467B - Clock tree layout flow method and clock tree deviation compensation device in integrated circuit - Google Patents
Clock tree layout flow method and clock tree deviation compensation device in integrated circuit Download PDFInfo
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Abstract
The invention discloses a clock tree layout process method in an integrated circuit, which specifically comprises the following steps: step 1: layout of a top layer; step 2: a physical implementation of a hard module; and step 3: extracting clock tree information in the hard module; and 4, step 4: acquiring clock tree deviation among hard modules; and 5: inserting a clock tree deviation compensation device into the top module T; step 6: generating a top clock tree in a top module T; and 7: carrying out wiring generation on signal interconnection among the hard modules in the top layer module T; and 8: extracting an interface time sequence model of the hard module when the static time sequence analysis of the whole chip is carried out; and step 9: analyzing the static time sequence of the whole chip; step 10: and (4) physical verification. The invention can reduce the clock tree level and reduce the difficulty of clock tree balance; meanwhile, a clock tree deviation compensation device is provided for the flow method, so that the difficulty of time sequence convergence among the hard modules can be effectively reduced.
Description
Technical Field
The invention belongs to the field of integrated circuit design, and particularly relates to a clock tree layout flow method and a clock tree deviation compensation device in a very large scale integrated circuit.
Background
With the development of the process and the increasing complexity of the function, the integration level of the very large scale integrated circuit is higher and larger, and the scale is larger and larger. The existing EDA tool is limited by the size of the memory and the running speed of the CPU, and has a requirement on the size of the module to be processed. In conventional EDA manufacturers, advanced processes below 28nm, the back-end tool can typically handle two to five million instantiated unit quantities, with the run time typically controlled to within 24 hours. Therefore, to save runtime and increase the number of iterations, most vlsi designs need to adopt a hierarchical physical design: firstly, splitting a design into a plurality of modules, wherein the scale of each module is two million to five million of the number of instantiated units; then, each module is physically designed to form a hard module; and finally, splicing all the hard modules into the whole design. The hierarchical physical design is a method adopted by most designers, and has the advantages that the restriction of EDA tools is avoided, and meanwhile, the hardware modules can be independently and parallelly carried out, so that the progress is accelerated. But this approach requires additional considerations.
Firstly, how to reasonably split the design in a layering way needs to be considered; estimating the size, and dividing the size into reasonable size and shape; and then putting the split hard module at a proper position. A relatively reasonable layout can only be obtained after complicated iteration.
Secondly, the divided hard module interface cannot be combined by logic, namely, the input and the output are required to be both made into a trigger and made out of the trigger. Meanwhile, in order to flexibly repair the interface timing sequence between the hard modules, the optimal situation is that the flow insertion can be carried out between the hard modules without influencing the normal function.
Finally, the clocks need to be balanced in a clock tree at the top level. In the hierarchical physical design, the root of the clock (clock root) is at the top level. Most of the time, a certain clock starts from the top layer and drives a plurality of hard modules simultaneously. There is data interaction both within the hard modules and between the hard modules. In order to meet the timing requirement when data interaction is performed between all memory cells driven by the clock, the clock needs to be balanced, which is called clock tree balancing. Clock tree balancing is made up of a series of clock buffers or inverter pairs, each of which has limited drive capability. Therefore, in order to balance all the memory cells, the clock tree needs to be driven layer by layer, which forms a hierarchy of the clock tree. The more memory cells that are clocked, the more levels. After the clock tree is balanced, the physical distances from the root of the clock to the various memory cells are equidistant. As shown in fig. 1, when the top level performs clock tree balancing, compensation of clock skew is needed to achieve clock tree balancing.
Timing problems are often encountered when clock tree balancing hierarchical physical designs. Firstly, the storage unit load driven by the clock in some hard modules is too large, which results in many clock tree stages and has negative effects on clock tree delay, power consumption, area and other aspects. Secondly, the clock tree levels built inside each hard module by the clock are different, that is, the clock delay difference exists between the hard modules, so that the interface timing sequence between the hard modules is difficult to satisfy. Therefore, the clock tree needs to be adjusted between the hard modules, so that the clock trees of all the hard modules are balanced. In addition, variations in different areas on the chip, such as temperature variations, voltage variations, variations in the width and thickness of interconnection lines, wafer flatness, and the like, are known as on-chip-variations (OCV). Due to the OCV, the static timing analysis calculation process between hard modules is more conservative, and therefore timing convergence is more difficult. In order to reduce the influence of OCV on the timing, it is required that the common part of the clock tree is as close to the memory cell as possible. However, the division of the hard modules makes the common part of the clock tree to exist at the top level, and reduces the common part of the clock tree, so that the common part of the clock is far away from the memory unit.
The traditional hierarchical physical design faces several technical problems to be solved: (1) Clock trees between hard modules need to be balanced at the top level; too many memory cells are clocked. These all result in increased levels of clock trees, which are more delay, power consumption and area intensive. (2) Due to clock tree deviation between the OCV and the hard modules, the effective time window is small, and therefore time and energy are needed to repair the interface time sequence between the hard modules.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a clock tree structure which can reduce the clock tree hierarchy and reduce the difficulty of clock tree balance aiming at the defects in the prior art; meanwhile, a clock tree deviation compensation device is provided for the flow method, so that the difficulty of time sequence convergence among the hard modules can be effectively reduced.
The technical scheme adopted by the invention for solving the technical problem is as follows:
a method for clock tree layout flow in an integrated circuit is provided, which comprises the following steps:
step 1: the layout of the top layer, the top layer in the integrated circuit is reasonably divided and placed by the hard modules, and the distribution planning of the power supply is carried out at the same time; each hard module is marked as B1, B2, …, bn, and the top module is marked as T;
step 2: the physical realization of the hard module, planning the placement and power distribution of macro cells in the hard module, placing standard cells, and generating and balancing a clock tree in the hard module;
and step 3: clock tree information in the hard modules is extracted, clock tree delay information of each hard module is extracted through reports and scripts, and the clock tree delay information is marked as CTSB1, CTSB2, … and CTSBn.
And 4, step 4: acquiring clock tree deviation between the hard modules, namely calculating the difference value of clock tree delay between every two hard modules to obtain a clock tree deviation value, wherein the clock tree deviation values of the hard modules B1 and B2 are recorded as SkewB1B2= CTSB1-CTSB2, and if the clock tree delay of the CTSB1 is greater than the clock tree delay of the CTSB2, the clock tree deviation value is a positive value; otherwise, it is a negative value.
And 5: inserting a clock tree deviation compensation device into the top module T, selecting a proper clock tree deviation compensation device according to the clock deviation value obtained in the step 4, and placing the clock tree deviation compensation device on the edge of the hard module with the shorter clock tree in the two hard modules;
step 6: generating a top clock tree in a top module T, taking a clock input point of a hard module as a negligible point, not balancing the clock tree part of the T, and only meeting the requirements of DRC;
and 7: carrying out wiring generation on signal interconnection among the hard modules in the top layer module T;
and 8: extracting an interface time sequence model of the hard module when the static time sequence analysis of the whole chip is carried out;
and step 9: performing static time sequence analysis on the whole chip, and finely adjusting the clock tree and the clock tree deviation compensation device according to the result;
step 10: and physical verification, namely, carrying out physical inspection on the whole chip and repairing the places which do not meet the rules.
In connection with the above technical solution, the method further comprises:
step 11: a GDSII (Graphic Database System II) Database was generated.
Step 12: production, packaging and testing of chips.
By the technical scheme, when the whole chip is subjected to static time sequence analysis, the static voltage drop is ensured to be less than 3-5%, and the dynamic voltage drop is ensured to be less than 10-15%.
According to the technical scheme, static time sequence analysis is carried out through a PrimeTime tool, and the PrimeTime tool is a software tool of Synopsys.
And performing physical verification through Calibre which is a software tool according to the technical scheme.
In the above technical solution, if the clock tree deviation value SkewB1B2 of the hard modules B1 and B2 is greater than one clock cycle, a P1 path from the hard module B1 to B2 may have a timing violation of setup time, and a P2 path from the hard module B2 to B1 may have a timing violation of hold time; if the time sequence of the setup time is illegal, adjusting the clock tree through a clock tree deviation compensation device to repair; if the time sequence of the holding time is violated, the clock tree is adjusted by increasing the delay of the data path or by the clock tree deviation compensation device for repairing.
According to the technical scheme, the clock tree deviation compensation device comprises a time sequence violation establishing circuit and a time sequence violation keeping circuit, wherein the time sequence violation establishing circuit comprises a plurality of first CELL units, and the time sequence violation keeping circuit comprises a second CELL unit and a plurality of third CELL units;
the first CELL CELL comprises a configurable clock buffer and an edge flip-flop;
the second CELL CELL comprises an active low latch;
the third CELL includes a clock buffer, an edge flip-flop, and an active low latch.
In connection with the above technical solution, the delay value of the clock buffer is 1/4 of the clock period, and the edge flip-flop is an edge flip-flop with an effective clock rising edge.
The invention has the following beneficial effects: the invention can carry out integral design during the initial clock tree planning, can effectively reduce the clock tree hierarchy and reduce the difficulty of clock tree balance; the clock tree deviation compensation device can effectively reduce the difficulty of timing sequence convergence between hard modules. By the invention, the time sequence convergence period can be accelerated, and the time for the chip to appear on the market can be shortened.
Drawings
The invention will be further described with reference to the accompanying drawings and examples, in which:
FIG. 1 is a schematic of clock skew compensation;
FIG. 2 is a flow chart of a clock tree layout flow method in an integrated circuit;
FIG. 3 is a schematic diagram of a clock tree deviation compensation apparatus according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of CELL1 according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of CELL2 according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of CELL3 according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a CTSADJ according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of SETUP _ DESKEWER according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of HOLD _ DESKEWER according to an embodiment of the present invention;
FIG. 10 is an original diagram of path P1 from B1 to B2 according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of path P1 of B1 to B2 of FIG. 10 after passing through the deviation compensation device;
FIG. 12 is a diagram of the original path P2 from B2 to B1 according to another embodiment of the present invention;
fig. 13 is a schematic diagram of a path P2 from B2 to B1 after passing through the deviation compensation device in fig. 12.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The clock tree layout flow method in the integrated circuit of the embodiment of the invention, as shown in fig. 2, specifically includes the following steps:
step 1: and (6) top layer layout. Firstly, dividing and placing hard modules on a top layer, and performing multiple iteration and test processes to ensure that wiring congestion and timing sequence violation cannot occur in subsequent layout and wiring processes; meanwhile, the distribution planning of the power supply is well done, and the voltage drop is ensured to be within a certain range, such as the static voltage drop is ensured to be less than 3% -5%, and the dynamic voltage drop is ensured to be less than 10% -15%. Each hard module is denoted as B1, B2, …, bn, and the top module is denoted as T. T is not required to have any standard unit except a hard module, and only has an interconnection signal wire.
Step 2: physical implementation of the hard module. Placing macro units in the hard module and planning power distribution; placing standard units; balancing and generating a hard module clock tree; wiring actions and physical verification and repair of hard modules. All processes need to take into account various factors in power supply, congestion, power consumption, timing, area and performance.
And step 3: clock tree information of the hard module is extracted. Clock tree delay information of each hard module is extracted through reports and scripts. The clock tree delay information is denoted as CTSB1, CTSB2, …, CTSBn.
And 4, step 4: and acquiring clock tree deviation among the hard modules (assuming that the hard modules have data transmission among each other). And calculating the difference value of the clock tree delay between every two hard modules to obtain the clock tree deviation value. The clock tree deviation values for hard blocks B1 and B2 are denoted as SkewB1B2= CTSB1-CTSB2. A positive value if the clock tree delay of CTSB1 is greater than the clock tree delay of CTSB 2; otherwise, it is a negative value.
And 5: a clock tree skew compensation device (the clock skew compensation device is described in detail later) is inserted in T. And 4, selecting a proper clock tree deviation compensation device according to the clock deviation value obtained in the step 4. Usually the clock tree deviation compensation means is placed near the hard module output interface where the clock tree is shorter of the two hard modules.
Step 6: the generation of the top-level clock tree is performed in T. The clock input point of the hard module is regarded as a negligible point, the clock tree part of T does not need to be balanced, and the requirement of DRC (Design rule check) only needs to be met.
And 7: the wiring is generated in T. And carrying out routing generation on signal interconnection among the hard modules in the T.
And 8: and extracting an interface timing model of the hard module. In performing a static timing analysis of the entire chip, an interface timing model may be used. Because the interface time sequence model data of the hard module is small, the occupied memory is small, the running speed of the EDA software can be accelerated, and the running time is shortened.
And step 9: and (4) performing static timing analysis on the whole chip. And performing static time sequence analysis on the whole chip, and finely adjusting the clock tree and the clock tree deviation compensation device according to the result. Static timing analysis may be performed using PrimeTime (Note that PrimeTime is a software tool for Synopsys).
Step 10: and (5) physical verification. Physical checks such as DRC (Design Rule Check), ERC (Electrical Rule Check), LVS (Layout letters), ANT (Antenna) and the like are carried out on the brand-new tablet, and the sites which do not meet the rules are repaired. Such as physical verification by Calibre (note: calibre is a software tool from Mentor corporation).
Step 11: a GDSII (Graphic Database System II) Database was generated.
Step 12: production, packaging and testing.
In steps 3, 4,5, 6 of the present invention, clock tree balancing is not required from the clock tree generated on T to each hard module. The selection of the clock tree deviation compensation device depends on the clock tree delay deviation value between the two hard modules. The clock tree deviation compensation device needs to be placed at the hard module edge where the clock tree delay is small.
As shown, the hard modules B1 and B2 are clock tree deviation compensated by the clock tree deviation compensation means.
According to the layout flow of the clock tree, after the step 1-4, skewB1B2= CTSB1-CTSB2 is obtained. The signal from B1 to B2 is passed as P1; the signal from B2 to B1 is passed as P2. Neither P1 nor P2 has combinational logic, only wired. Since CTSB1> CTSB2, P1 is prone to timing violations of setup time requirements and P2 is prone to timing violations of hold time. In general, ideally, if SkewB1B2 is less than one clock cycle, no timing violation will occur on P1 path and a hold time timing violation will occur on P2; if SkewB1B2 is greater than one clock cycle, the P1 path may experience a setup time timing violation and P2 may experience a hold time timing violation. Timing violations of setup time occur and must be repaired by adjusting the clock tree. If the time sequence of the holding time is violated, the data path delay can be increased or the clock tree can be adjusted to repair the violation. If the clock tree bias is small, the cost of adjusting the clock tree is relatively small. But the clocktree is large and needs to be repaired at great expense. In the invention, the time sequence violation of the setup time of the P1 path can be adjusted by the clock tree deviation compensation device, and the time sequence violation of the hold time of the P2 path can be adjusted by the clock tree deviation compensation device.
The clock tree deviation compensation device has two functions: (1) The clock tree deviation in the B1 to B2 direction is compensated, and the clock tree deviation is recorded as a SETUP _ DESKEWER part, so that the establishment time sequence violation occurring in the P1 type can be repaired; (2) The clock tree deviation for compensating the direction from B2 to B1, which is referred to as HOLD _ DESKEWER, can repair the HOLD time timing violation occurring in the P2 type. The two parts form a complete compensation circuit. It is composed of three basic elements: the CTSADKn is composed of a configurable clock buffer, and is configured to be a 1/4 delay value of a clock cycle under the default condition, and the configuration can be adjusted and fine-tuned according to the specific condition; fn is an edge flip-flop for which the rising edge of the clock is valid; ln is an active low latch. (n =0/1/2/…/…).
The clock tree deviation compensation device comprises a time sequence violation establishing circuit and a time sequence violation keeping circuit, wherein the time sequence violation establishing circuit comprises a plurality of first CELL units CELL1, and the time sequence violation keeping circuit comprises a second CELL unit CELL2 and a plurality of third CELL units CELL3;
CELL1, as shown: including a D-FLOP (edge flip-FLOP) and a CTSADJ (configurable clock buffer).
CELL2, shown in FIG. 5: including an active low Latch.
CELL3, shown in FIG. 6: including an active low Latch, a D-FLOP and a CTSADJ.
Configurable clock buffer CTSADJ, as shown in fig. 7: the device consists of a four-to-one MUX and four delay buffers of CTS. Each delay buffer delays 1/8cycle under normal conditions. Default condition S1S0=2' b10.
As shown in fig. 8, the n CELLs 1 constitute a SETUP _ DESKEWER (SETUP time timing violation circuit).
As shown in fig. 9, 1 CELL2 and n CELL3 constitute HOLD _ DESKEWER (HOLD time timing violation circuit).
In one embodiment of the present invention: path P1 from B1 to B2, as shown in fig. 10.
And according to the step 3, extracting the clock tree delay information of the B1 and the B2, and recording the clock tree delay information as CTSB1 and CTSB2.
According to step 4, calculating the clock delay difference between B1 and B2 to obtain a clock tree deviation value, which is recorded as SkewB1B2= CTSB1-CTSB2. The configuration mode is carried out according to two conditions:
case 1: if 0 and are woven SkewB1B2 and woven 1cycle, ideally there is no timing violation by SETUP or HOLD.
Case 2: if SkewB1B2 is greater than 1cycle, ideally, there is a timing violation of SETUP. It is necessary to insert SETUP _ deskey for compensation of clock skew. If (n/4) cycle < SkewB1B2< ((n + 4)/4) cycle, then n CELLs 1 need to be configured; CTSADJ is the default configuration. For example: cycle =5ns, skewb1b2=8ns, then n =3, i.e. 3 CELL1 are required to constitute SETUP _ DESKEWER.
According to step 5, the clock tree deviation compensator SETUP _ DESKEWER is inserted in T, as shown in fig. 11.
In another embodiment of the present invention: path P2 from B2 to B1, as shown in fig. 12. The usual way is to increase the data path delay for repair. Here, clock tree compensation is performed not in a conventional manner, but using HOLD _ deskey.
And according to the step 3, extracting the clock tree delay information of the B1 and the B2, and recording the clock tree delay information as CTSB1 and CTSB2.
According to step 4, calculating the clock delay difference between B1 and B2 to obtain a clock tree deviation value, which is recorded as SkewB1B2= CTSB1-CTSB2. The configuration mode is carried out according to two conditions:
case 1: if 0< -SkewB1B2 < -1/2 cycle, ideally, HOLD timing violations exist. HOLD _ deskey needs to be inserted for clock tree bias compensation. HOLD _ deskey is configured as one CELL2.
Case 2: if 0< -SkewB1B2 < -3/4 cycle, ideally, there is timing violation of HOLD. HOLD _ deskey needs to be inserted for clock skew compensation. HOLD _ deskey is configured as 1 CELL2 and 1 CELL3.CTSADJ is the default configuration.
Case 3: if ((n-4)/4) _ cycle < SkewB1B2< (n/4) _ cycle (n =4,5, …), there is a timing violation by HOLD. HOLD _ deskey needs to be inserted for clock skew compensation. HOLD _ DESKEWER is configured as 1 CELL2 and n-1 CELL3.CTSADJ is the default configuration.
According to step 5, the clock tree deviation compensation means HOLD _ DESKEWER is inserted in T, as shown in fig. 13.
In summary, the clock tree layout flow method provided by the invention can reduce the clock tree levels and reduce the difficulty of clock tree balance; meanwhile, a clock tree deviation compensation device is provided for the flow method, so that the difficulty of time sequence convergence among the hard modules can be effectively reduced.
It will be understood that modifications and variations can be made by persons skilled in the art in light of the above teachings and all such modifications and variations are intended to be included within the scope of the invention as defined in the appended claims.
Claims (8)
1. A clock tree layout flow method in an integrated circuit is characterized by comprising the following steps:
step 1: the layout of the top layer, the top layer in the integrated circuit is reasonably divided and placed by the hard modules, and the distribution planning of the power supply is carried out at the same time; each hard module is marked as B1, B2, …, bn, and the top module is marked as T;
and 2, step: the physical realization of the hard module, planning the placement and power distribution of macro cells inside the hard module, placing standard cells, and generating and balancing a clock tree in the hard module;
and step 3: extracting clock tree information in the hard modules, extracting clock tree delay information of each hard module through reports and scripts, and recording the clock tree delay information as CTSB1, CTSB2, … and CTSBn;
and 4, step 4: acquiring clock tree deviation between the hard modules, namely calculating the difference value of clock tree delay between every two hard modules to obtain a clock tree deviation value, wherein the clock tree deviation values of the hard modules B1 and B2 are recorded as SkewB1B2= CTSB1-CTSB2, and if the clock tree delay of the CTSB1 is greater than the clock tree delay of the CTSB2, the clock tree deviation value is a positive value; otherwise, the value is a negative value;
and 5: inserting a clock tree deviation compensation device into the top module T, selecting a proper clock tree deviation compensation device according to the clock deviation value obtained in the step (4), and placing the clock tree deviation compensation device on the hard module edge with the shorter clock tree in the two hard modules;
step 6: generating a top clock tree in a top module T, taking a clock input point of a hard module as a negligible point, not balancing the clock tree part of the T, and only meeting the requirements of DRC;
and 7: carrying out wiring generation on signal interconnection among all the hard modules in the top layer module T;
and 8: extracting an interface time sequence model of the hard module when the static time sequence analysis of the whole chip is carried out;
and step 9: performing static time sequence analysis on the whole chip, and finely adjusting the clock tree and the clock tree deviation compensation device according to the result;
step 10: and physical verification, namely, carrying out physical inspection on the whole chip and repairing the places which do not meet the rules.
2. The method of claim 1, further comprising:
step 11: generating a GDSII database;
step 12: production, packaging and testing of chips.
3. The method of claim 1, wherein a static timing analysis of the entire chip is performed to ensure that the static voltage drop is less than 3% -5% and the dynamic voltage drop is less than 10% -15%.
4. The method of claim 1, wherein the static timing analysis is performed by a PrimeTime tool, the PrimeTime tool being a Synopsys software tool.
5. The method of claim 1, wherein the physical verification is performed by Calibre, which is a software tool.
6. The method of claim 1, wherein if the deviation value SkewB1B2 of the clock tree of the hard blocks B1 and B2 is greater than one clock cycle, a timing violation of setup time occurs in the P1 path from the hard blocks B1 to B2, and a timing violation of hold time occurs in the P2 path from the hard blocks B2 to B1; if the time sequence of the set-up time is violated, adjusting the clock tree by the clock tree deviation compensation device to repair; if the time sequence of the holding time is violated, the clock tree is adjusted by increasing the delay of the data path or by the clock tree deviation compensation device for repairing.
7. The method of claim 1, wherein the clock tree bias compensation apparatus comprises a setup time timing violation circuit and a hold time timing violation circuit, the time timing violation circuit comprising a first plurality of CELL units, the hold time timing violation circuit comprising a second CELL unit and a third plurality of CELL units;
the first CELL CELL comprises a configurable clock buffer and an edge flip-flop;
the second CELL CELL comprises an active low latch;
the third CELL includes a clock buffer, an edge flip-flop, and an active low latch.
8. The method as claimed in claim 7, wherein the delay value of the clock buffer is 1/4 of the clock period, and the edge flip-flop is an edge flip-flop whose clock rising edge is valid.
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| CN110619137B (en) * | 2019-06-25 | 2022-12-02 | 眸芯科技（上海）有限公司 | Time sequence analysis method aiming at voltage drop and application |
| CN111046624A (en) * | 2019-12-17 | 2020-04-21 | 天津飞腾信息技术有限公司 | Method, device, equipment and medium for constructing chip module interface clock structure |
| CN111753480B (en) * | 2020-07-01 | 2022-05-31 | 无锡中微亿芯有限公司 | Multi-die FPGA for implementing clock tree by using active silicon connection layer |
| CN111931453A (en) * | 2020-07-15 | 2020-11-13 | 深圳市紫光同创电子有限公司 | Data path repairing method, FPGA circuit and FPGA circuit design device |
| CN112115676B (en) * | 2020-09-29 | 2021-10-26 | 飞腾信息技术有限公司 | Static voltage drop repairing method, device, equipment and storage medium |
| CN113177383B (en) * | 2021-04-29 | 2023-01-31 | 飞腾信息技术有限公司 | Clock design method based on dummy |
| CN116167331B (en) * | 2023-04-26 | 2023-07-28 | 瀚博半导体(上海)有限公司 | Method for constructing clock tree, clock tree and chip |
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