JP2006174132A - Semiconductor apparatus and its redundancy relief method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve yield and reliability of a large-scale semiconductor apparatus easily. <P>SOLUTION: When the timing becomes one of current measurement by a control signal S(i) from a control circuit 108, resting power source current value of each of dividing logical circuit blocks 105<SB>1</SB>to 105<SB>r-1</SB>is measured. Then, the control circuit 108 compares the resting power source current value of the dividing logical circuit blocks 105<SB>1</SB>to 105<SB>r-1</SB>with a reference value and when the resting power source current exceeds the reference value, a decision signal (i) is set to an Lo level. On the other hand, when the resting power source current does not exceed the reference value, the decision signal (i) is set to a Hi level. Switch control signals R(1) to R(r) are outputted to selectors 106<SB>2</SB>to 106<SB>r</SB>and 107<SB>1</SB>to 107<SB>r-1</SB>so that a defective block where the decision signal (i) is at the Lo level is replaced by a redundancy circuit block 105<SB>r</SB>, connection of an input output bus is switched, and power feeding to the defective block is stopped. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a redundant relief method thereof.

  As a logic circuit redundancy repair method, for example, a computer system employs a multiprocessor system in which a plurality of processors are connected, and a processor that detects an error by a program and processes an error in the logic circuit is replaced. (For example, see Patent Document 1).

In this multiprocessor system, it is possible to replace a processor in which an error has occurred with a normal processor by providing an interface that allows the access of each processor to be selected simultaneously or individually.
Japanese Patent Publication No. 7-92791

  However, with the progress of miniaturization technology, the degree of integration of semiconductor devices has become very large, but the multiprocessor method is too large as a redundancy method for semiconductor devices, and considering the impact of layout, Realization is extremely difficult.

  Even if the multiprocessor system can be realized, if the yield reduction due to the size of integration exceeds the yield improvement due to redundancy, the effect to be applied is lost. Moderate circuit block redundancy is required, but control by a program becomes impossible.

  In addition, a method in which a test is performed in advance, such as a method used in a memory, and a faulty circuit block is replaced with a normal circuit block by an irreversible method (for example, a fuse, a nonvolatile memory, etc.) is also conceivable. However, the irreversible replacement method has a large scale in terms of layout and may require a special manufacturing method. In addition, since a redundant repair method is determined by performing an inspection first, it becomes impossible to cope with a change with time.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device capable of easily improving the yield and reliability of a large-scale semiconductor device and a redundant relief method thereof. To do.

  In order to solve this problem, a semiconductor device according to the present invention includes a plurality of divided logic circuit blocks each having an independent power supply source, and an independent power supply source in the same power source separation unit as the plurality of divided logic circuit blocks. The configuration includes the above redundant circuit block, and a control circuit that controls to replace one or more divided logic circuit blocks of the plurality of divided logic circuit blocks with the redundant circuit block.

  In particular, the plurality of divided logic circuit blocks have a configuration in which a logic circuit that performs arithmetic processing on a signal of a plurality of bits is divided so that power is separated for each arbitrary bit unit, and power supply sources are independent from each other. .

  Further, the control circuit measures the quiescent power supply current of each divided logic circuit block from which power is separated, and if there is a defective block with a large current, the power supply of the defective block is set to the ground level, and the redundant circuit block A configuration is adopted in which control is performed to replace the redundant circuit block by supplying power.

  Further, the control circuit makes the power of each of the plurality of divided logic circuit blocks separated from the power source independent from a power supply source by a MOS switch, and when there is an invalid block among the plurality of divided logic circuit blocks, A configuration is adopted in which control is performed to replace the redundant circuit block.

  Further, the control circuit determines whether or not there is a defective block having a large current by measuring the quiescent power supply current of each of the plurality of divided logic circuit blocks separated in power supply while switching each block with a MOS switch. When there is a defective block with a large current, the enable signal of the defective block is set to the non-selection level, and the enable signal of the redundant circuit block is set to the selection level to control the replacement with the redundant circuit block. Take.

  The semiconductor device according to the present invention includes a plurality of divided logic circuit blocks whose power supply sources are independent by MOS switches, and one or more redundant power sources that are independent in the same power source separation unit as the plurality of divided logic circuit blocks. A circuit block and a minute current flowing through the plurality of divided logic circuit blocks are measured to determine whether the block is an effective block or an invalid block. If there is an invalid block, control is performed to replace the redundant circuit block. And a control circuit.

  In particular, the plurality of divided logic circuit blocks divide a logic circuit for arithmetic processing of a signal of a plurality of bits so as to separate the power supply for each arbitrary bit unit, and the power supply sources are independent by MOS switches, Take the configuration.

  In addition, the control circuit measures the quiescent power supply current of each of the plurality of divided logical blocks separated from each other by a MOS switch at any timing when the power is turned on or the device is operated. When there is a defective block with a large current, the enable signal of the defective block is set to a non-selection level, and the enable signal of the redundant circuit block is set to a selection level to control to replace the redundant circuit block. Take.

  The redundant repair method for a semiconductor device according to the present invention measures the quiescent power supply current of each of a plurality of divided logic circuit blocks whose power supply sources are independent, and if there is a defective block with a large current, A method is adopted in which the power supply is set to the ground level and control is performed so that the power supply source is replaced with one or more redundant circuit blocks independent in the same power source separation unit as the plurality of divided logic circuit blocks.

  According to the present invention, one or more divided logic circuit blocks among a plurality of divided logic circuit blocks each having an independent power supply source are separated from each other in the same power source separation unit as the plurality of divided logic circuit blocks. Since replacement with a redundant circuit block, for example, it becomes possible to divide a logic circuit such as a CPU or a DSP into a bitwise division logic circuit block or a functional block, which is frequently repeated, and to repair it as a redundant object. The yield and reliability of a scaled semiconductor device can be easily improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a semiconductor device according to an embodiment of the present invention. In this embodiment mode, a configuration example in which part of a logic circuit in a semiconductor device is made redundant is shown. That is, the logic circuit block is divided into a logic circuit block that is not made redundant and a logic circuit block that is made redundant, and the logic circuit block that is made redundant is divided into bit-wise division logic circuit blocks and functional blocks, and In the figure, one or more redundant circuits are provided, and each block is configured to be able to independently control on / off of the power supply path of each other.

  In FIG. 1, non-redundant logic circuit blocks (hereinafter referred to as “normal blocks”) 101 and 102 are provided with input / output terminals 103 and 104, respectively. A logic circuit block interposed between the normal block 101 and the normal block 102 is made redundant for each bit or each functional block.

In the example shown in FIG. 1, one or more of the logical circuit blocks to be made redundant includes a divided logical circuit block (Block (1) to Block (r)) 105 _r (r is an arbitrary natural number). It is composed of _{(r-1)) 105 1~r} -1. Each of the divided logic circuit blocks 1051 to _r-1 has the same configuration as shown in FIG.

And dividing logic circuit block (Block (1) ~Block (r -1)) 105 1~r-1 and the redundant circuit blocks _{(Block (r)) 105 r} , between the normal block 101, respectively, Selectors (Selectors) _{1062- r} and _1071-r-1 for switching the input / output data buses are arranged.

Here, the divided logic circuit blocks (Block (1) to Block (r−1)) 105 1 to r ₋₁ and the redundant circuit block (Block (r)) 105 _r are arranged between the normal block 101. Between the selectors 106 2 to _r , the divided logic circuit blocks (Block (1) to Block (r−1)) 105 1 to r ₋₁ and the redundant circuit block (Block (r)) 105 _r and the normal block 102 As shown in FIG. 1, the selectors 107 ₁ to _r-1 that are arranged are arranged in a relationship shifted to one adjacent block opposite to each other in the redundant logic at the time of abnormality in the division logic circuit. block (block (1) ~Block (r -1)) 105 1~r and redundant circuit blocks (block (r)) of the input bus switching selection in 105 _r , The switching selection and output bus in order to allow each other opposite directions.

Control circuit 108, dividing logic circuit block (Block (1) ~Block (r -1)) 105 1~r and redundant circuit blocks (Block (r)) 105 individually control signals to _r S (1) ~ S (r) is given, and each power supply control, current measurement, determination flip-flop set, and the like are performed. Dividing logic circuit block (Block (1) ~Block (r -1)) 105 1~r-1 and the redundant circuit blocks (Block _(r)) 105 r, respectively, the determination of the flip-flop to the control circuit 108 Determination signals J (1) to J (r) indicating the state are given.

Then, the control circuit 108 individually _gives control signals R (2) to R (r) to the selectors 106 ₂ to r based on the determination signals J (1) to J (r), respectively, and the selectors 107 _{1 to} 107 _{1 The} control signals R (1), R (2),... are individually applied to _r , and the divided logic circuit blocks 105 1 to _r and the redundant circuit block (Block (r)) 105 _r and the normal blocks 101 and 102 Controls switching of input / output data bus connections between

2 shows a specific configuration example of the divided logic circuit blocks (Block (1) to Block (r-1)) 105 1 to r _-1 and the redundant circuit block (Block (r)) 105 _{r shown} in FIG. FIG. 2 is a specific configuration example of the divided logic circuit blocks (Block (1) to Block (r-1)) 105 1 to r _-1 and the redundant circuit block (Block (r)) 105 _{r shown} in FIG. A certain logic circuit block (Block (i)) 200 includes a unit logic circuit block 201 divided into bits or function blocks, a power switch 202, a current measurement switch 203, and a determination result holding unit 204. I have. Moreover, all the divided logic circuit blocks, namely dividing logic circuit block (Block (1) ~Block (r -1)) 105 1~r-1 and the redundant circuit blocks (Block (r)) current measurements that are shared by 105 _r A circuit 205 is provided. Note that i = 1 to r.

  An input bus 211 and an output bus 212 are drawn from the unit logic circuit block 201. The unit logic circuit block 201 is connected to the power supply line of the power supply (VD) 206 through the power switch 202 and the current measurement switch 203. The unit logic circuit block 201 and each divided logic circuit block (Block (i) ) 200 is connected by a separate power supply line, and power supply can be turned on / off for each divided logic circuit block (Block (i)) 200.

  The power switch 202 includes an NMOS transistor 221 and a PMOS transistor 222 provided between the power supply line of the power supply (VD) 206 and the power supply terminal of the unit logic circuit block 201, and an inverter 223. A control signal S (i) from the control circuit 108 is applied to the gate electrode of the NMOS transistor 221 and the input terminal of the inverter 223. The output terminal of the inverter 223 is connected to the gate electrode of the PMOS transistor 222.

  The control signal S (i) is a signal that defines a current measurement mode 301 and a normal mode 302 as shown in FIG. The control signal S (i) is at the Hi level in the normal mode 302, but in the current measurement mode 301, the control signal S (i) is at the Lo level only at the current measurement timing of the divided logic circuit block (Block (i)) 200. It is Hi level in a period other than the timing.

  Accordingly, in a period other than the current measurement timing, both transistors, that is, the NMOS transistor 221 and the PMOS transistor 222 are in the on operation state, so that the operating power is supplied to the unit logic circuit block 201, and both transistors are in the off operation at the current measurement timing. Therefore, the operation power supply to the unit logic circuit block 201 is cut off.

  The current measurement switch 203 includes NMOS transistors 231 and 232. The NMOS transistor 231 is provided between the power supply line of the power supply (VD) 206 and the current measurement terminal of the unit logic circuit block 201. The NMOS transistor 232 is provided between the current measurement terminal of the unit logic circuit block 201 and the current measurement circuit 205. The gate electrodes of the two NMOS transistors 231 and 232 are connected to the output terminal of the inverter 223 in the power switch 202.

  That is, the NMOS transistors 231 and 232 are both turned on at the current measurement timing when the control signal S (i) is at the Lo level.

  Thus, at the current measurement timing, the divided logic circuit block (Block (i)) 200 becomes active when the operation power is supplied to the current measurement terminal of the unit logic circuit block 201 via the NMOS transistor 231. Then, a test pattern is given to the unit logic circuit block 201 from the input bus 211, and a minute current (static power supply current) flowing through the NMOS transistor 231 is transmitted to the current measurement circuit 205 via the NMOS transistor 232. That is, a well-known IDDQ test is performed.

  The determination result holding unit 204 includes a determination flip-flop 241 and an AND circuit 242. The control signal S (i) is applied to one input terminal of the AND circuit 242, and the output signal of the current measuring circuit 205 is applied to the other input terminal. The determination flip-flop 241 takes in the output of the AND circuit 242 input to the data input terminal D in accordance with the clock CLK from the control circuit 108, and supplies the determination signal J (i) from the data output terminal Q to the control circuit 108. ing.

  The current measurement circuit 205 measures a minute current from the current measurement switch 203, compares the value with a reference value, sets the output to the Hi level when normal below the reference value, and outputs when the abnormality exceeds the reference value. To Lo level.

  Since the output of the current measurement circuit 205 is given to the other input terminal of the AND circuit 242, the judgment result holding unit 204 gives the judgment signal J (i) at the Hi level to the control circuit 108 in the normal state, and the abnormality is detected. Sometimes the Lo level determination signal J (i) is supplied to the control circuit 108.

  Next, with reference to FIG. 3, a redundant relief operation realized by the semiconductor device configured as described above will be described.

  FIG. 3 is a time chart for explaining the redundant relief operation.

In Figure 3, from the control circuit 108 divides the logic circuit blocks (Block (1) ~Block (r -1)) 105 applied to the _{1 to r-1} control signals S (1) ~S (r) , dividing logic circuit block (Block (1) to Block (r-1)) 105 ₁ to r-1 to determination signals J (1) to J (r) given to the control circuit 108, and the control circuit 108 to selectors 106 ₂ to r ₁ , 107 _{1 The} switching control signals R (1) to R (r) given to _.about.r-1 .

Then, in the current measurement mode 301 defined by the control signals S (1) to S (r), the control signals S (1) to S (r) sequentially reach the current measurement timing (Lo level), and the current measurement circuit 205 dividing logic circuit block (block ₍₁₎₎ 105 1 from the redundant circuit blocks (block (r)) in turn current value determination towards the 105 _r done by.

Each dividing logic circuit block (Block (1) ~Block (r -1)) 105 1~r-1, the result of the determination current value, if normal, Hi level is set to determine the flip-flop 241, the abnormality If so, the Lo level is set in the decision flip-flop 241. This is the content of the determination signals J (1) to J (r).

As a result, the defective block can be surely replaced with the redundant circuit block (Block (r)) 105 _r , and the normal block and the defective block can be automatically discriminated sequentially.

Here, the case shown in FIG. 3 shows a case where there is an abnormality in the divided logic circuit 105 ₂ (block Block (2)) and the determination signal J (2) does not become Hi level.

When all of the determination signals J (1) to J (r) are at the Hi level, the control circuit 108 determines that each divided logic circuit block (Block (1) to Block (r−1)) 105 1 to r _−1. Is normal, the switching control signals R (1) to R (r) given to the selectors 106 _{2 to} r ₁ and 107 ₁ to r−1 are all set to the Lo level. Output bus of each divided logic circuit blocks (Block (1) ~Block (r -1))) 105 1~r-1 is maintained to the original connection state.

On the other hand, when the determination signal J (i) of a certain divided logic circuit block (Block (i)) 105 _i is at the Lo level, the control circuit 108 displays the corresponding divided logic circuit block 105 _i (Block (i)). Redundant circuit block (Block (r)) 105 _r is replaced with redundant relief measures.

That is, in the example shown in FIG. 3, divided since the logic circuit block (Block (2)) 105 ₂ is abnormal, dividing logic circuit block (Block (2)) after the 105 _second input bus adjacent divided logic connected to a circuit block (block ₍₃₎₎ 105 3, adjacent dividing logic circuit block (block ₍₃₎₎ 105 3 of the input bus, the next adjacent divided logic circuit blocks (block ₍₄₎₎ 105 4 that The switching control signal (i) for the selectors 106 2 to _r and 107 ₁ to _r−1 after the divided logic circuit block Block (2) is set to the Hi level so that the connection is shifted in order. To do.

  At this time, the control circuit 108 performs control so that the output bus is shifted and connected in the direction opposite to the shift direction of the input bus.

Further, the control circuit 108 becomes abnormal dividing logic circuit block (Block (2)) the power supply line to 105 ₂ for example, such as lowering the ground level, divided logic circuit blocks (Block (2)) 105 ₂ The power supply to the power supply is also stopped, and control is performed so that no abnormal current flows.

Thus, in the present embodiment, a plurality of divided power source is independent logic blocks (Block (1) ~Block (r -1)) 105 1 or more dividing logic of _{1 to r-1} If there is an abnormality in the circuit block, the plurality of dividing logic circuit block (block (1) ~Block (r -1)) 105 redundant circuit _{blocks 1 to r-1} and the power supply source in the same power supply separate units independent (Block (r)) 105 _r can be substituted.

  As a result, for example, a logic circuit such as a CPU or a DSP can be relieved as a redundant target by dividing it into bitwise divisional circuit blocks or functional blocks with many repetitions. The yield and reliability can be easily improved.

  If a supplementary explanation is added to the design guideline of the semiconductor device according to the present invention, it is necessary to increase the effectiveness in consideration of the scale of the redundancy target circuit in order to make the logic circuit redundant. Therefore, in a CPU or DSP that performs processing in bit units that are frequently repeated even in a logic circuit, the redundancy efficiency increases when the logic circuit blocks are divided into bit-by-bit division logic circuit blocks to be redundant. For this reason, the number of bits to be redundant is set by carefully considering beforehand whether to perform block division for each bit or block division for a plurality of bits depending on the bit configuration of the target circuit. In this case, it is fully considered that it is effective to provide a redundant circuit for an important circuit.

  Then, the power supply of such a circuit block is made independent from each other, and the quiescent power supply current is measured for each divided logic circuit block. If the current value is larger than the reference value, the circuit block is regarded as a redundant circuit block. Replace. In this case, when replacing a relatively large divisional logic circuit block, the power supply terminals are also made independent, power supply wiring is performed in advance for the necessary divisional logic circuit block, and the power supply for unnecessary divisional logic circuit blocks is at the ground level. Can be taken. This method cannot cope with changes over time, but is effective depending on the scale and measurement accuracy of the LSI. In this case, there is an advantage that a current measuring circuit is not required for an unnecessary divided logic circuit block.

  Further, a switch for switching between operation power supply and current measurement power supply is inserted between the power supply line separated for each divided logic circuit block and each divided logic circuit block, and each divided logic circuit block Enable automatic current measurement in sequence. That is, when the current measurement mode is entered, the circuit is switched to supply of the current measurement power source and the circuit blocks are sequentially activated to perform current measurement. If there is a problem, a determination flag assigned to each divided logic circuit block is set. At this time, an error signal is output when the determination flag is set more than the number of redundant circuit blocks.

  By this method, the redundancy efficiency of the logic circuit is improved, and it becomes possible to perform redundancy relief when a problem occurs by self-scanning even after incorporation into the device. It goes without saying that it is necessary to fully consider what method should be adopted according to the goals of semiconductor integration scale, yield, reliability, and the like.

  According to the semiconductor device and the redundancy repair method thereof according to the present invention, one or more divided logic circuit blocks out of a plurality of divided logic circuit blocks each having an independent power supply source have the same power supply as the plurality of divided logic circuit blocks. Since the power supply source is replaced with an independent redundant circuit block in a separation unit, for example, a logic circuit such as a CPU or a DSP is divided into redundant bit-wise division logic circuit blocks or functional blocks for redundancy. It is possible to relieve the target, and it is possible to easily improve the yield and reliability of a large-scale semiconductor device, which is useful.

1 is a block diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention. The figure which shows the specific structural example of the division | segmentation logic circuit block shown in FIG. 1 is a time chart for explaining a redundant relief operation realized in the semiconductor device shown in FIG.

Explanation of symbols

101,102 Normal block (logic circuit block without redundancy)
103, 104 Input / output terminals 105 _{1- r -1} divided logic circuit block 105 _r redundant circuit block 106 _{2- r} , 107 _{1- r -1} data bus selector (Selector)
108 control circuit 200 i (i = 1 to r) -th divided logic circuit block (Block (i)) 105 _i
201 unit logic circuit block 202 power switch 203 current measurement switch 204 determination result holding unit 205 current measurement circuit 221, 231, 232 NMOS transistor 222 PMOS transistor 223 inverter 241 determination flip-flop 242 AND circuit

Claims (9)

A plurality of divided logic circuit blocks each having an independent power supply source;
One or more redundant circuit blocks having independent power supply sources in the same power source separation unit as the plurality of divided logic circuit blocks;
A control circuit that controls to replace one or more of the plurality of divided logic circuit blocks with the redundant circuit block;
A semiconductor device comprising: The semiconductor device according to claim 1,
The plurality of divided logic circuit blocks are:
Dividing a logic circuit for arithmetic processing of a multi-bit signal so as to separate the power for each arbitrary bit unit, and the power supply sources are independent,
A semiconductor device. The semiconductor device according to claim 1 or 2,
The control circuit includes:
By measuring the quiescent power supply current of each of the divided logic circuit blocks separated from the power source, if there is a defective block with a large current, the power of the defective block is set to the ground level, and the power of the redundant circuit block is supplied. Control to replace with redundant circuit block,
A semiconductor device. The semiconductor device according to claim 1 or 2,
The control circuit includes:
The power supply of each of the plurality of divided logical circuit blocks separated from the power source is made independent from a power supply source by a MOS switch, and when there is an invalid block among the plurality of divided logical circuit blocks, the redundant circuit block is replaced. To control,
A semiconductor device. The semiconductor device according to claim 3 or 4,
The control circuit includes:
Measure the quiescent power supply current of each of the plurality of divided logic circuit blocks separated by power supply for each block with a MOS switch to determine whether there is a defective block with a large current. If present, the enable signal of the defective block is set to a non-selection level and the enable signal of the redundant circuit block is set to a selection level to control the replacement with the redundant circuit block.
A semiconductor device. A plurality of divided logic circuit blocks whose power supply sources are independent by MOS switches;
One or more redundant circuit blocks having independent power supply sources in the same power source separation unit as the plurality of divided logic circuit blocks;
Measuring a minute current flowing through the plurality of divided logic circuit blocks to determine whether it is an effective block or an invalid block, and if there is an invalid block, a control circuit that controls to replace the redundant circuit block;
A semiconductor device comprising: The semiconductor device according to claim 6.
The plurality of divided logic circuit blocks are:
Dividing a logic circuit that performs arithmetic processing on a signal of a plurality of bits so as to separate the power supply for each arbitrary bit unit, and the power supply sources are independent by MOS switches,
A semiconductor device. The semiconductor device according to claim 6 or 7,
The control circuit includes:
Measure the quiescent power supply current of each of the plurality of divided logical blocks separated at power supply at each timing when the device is powered on or when the device is operating, by switching each block using a MOS switch, and a defective block with a lot of current Is present, control to replace the redundant circuit block by setting the enable signal of the defective block to the non-selection level and setting the enable signal of the redundant circuit block to the selection level,
A semiconductor device. Measure the quiescent power supply current of each of the plurality of divided logic circuit blocks whose power supply sources are independent, and if there is a defective block with a large current, the power of the defective block is set to the ground level,
Control to replace one or more redundant circuit blocks with independent power supply sources in the same power source separation unit as the plurality of divided logic circuit blocks.
A redundant relief method in a semiconductor device.

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