JP2010041705A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure where the relief of redundancy is carried out in a logic region of a semiconductor device. <P>SOLUTION: There is provided a semiconductor device 1 with a logic region 2. The semiconductor device 1 is equipped with a plurality of basic cells 21 which have the same structures and are provided in the logic region 2, redundant cells 22 with the same structures as those of the plurality of basic cells 21, an input selector 23 for switching a signal input to each of a plurality of basic cells 21 and the redundant cells 22, and an output selector 24 for switching a signal output from each of a plurality of basic cells 21 and the redundant cells 22. Furthermore, the semiconductor device 1 switches at least one of the input and output selectors 23, 24 to cause the redundant cells 22 to function to relieve a faulty cell among the plurality of basic cells 21. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and particularly relates to a semiconductor device having a logic region.

  In a semiconductor device, redundant relief is performed in order to improve the yield. For example, in Patent Document 1, in the two circuits A and B separated by the power source, when the circuit A has a half short / half open abnormality, the current supply source of the circuit A is cut off using a fuse, and the circuit A A redundant relief method for replacing B is performed. In Patent Document 2, a redundant relief method is performed by separating one of redundant logic circuits (not necessarily having the same function) from a memory by a fuse or a switch (transistor) and connecting the other to the memory. Further, Patent Document 3 discloses a configuration that prevents leakage current in a defective block of an arithmetic processing unit having a plurality of arithmetic blocks by packaging for cutting the defective block.

JP 2007-201166 A JP 2004-048618 A JP 2006-310663 A

  However, conventional redundancy relief relates to memories such as SRAM and flash, and efforts have been made to improve yield by redundancy relief of memories in semiconductor devices. For this reason, in a semiconductor device including a logic region, redundancy repair was not performed in the logic region. Therefore, even in a semiconductor device having no defect in the memory region, a defect is determined if there is a defect in the logic region, and the yield is increased. There was a problem of lowering.

  In view of the above, an object of the present invention is to provide a configuration for performing redundant relief in a logic region of a semiconductor device.

  A solving means according to one embodiment of the present invention is a semiconductor device having a logic region. The semiconductor device is input to each of the plurality of basic cells having the same configuration provided in the logic region, the redundant cell having the same configuration as the plurality of basic cells, and the plurality of basic cells and the redundant cell. And an output selector for switching signals output from each of the basic cell and the redundant cell. Further, the semiconductor device switches at least one of the input selector and the output selector to function the redundant cell and repair the failed cell among the plurality of basic cells.

  In the semiconductor device described in one embodiment of the present invention, at least one of the input selector and the output selector is switched to function a redundant cell and repair a failed cell among a plurality of basic cells. Since it is possible to perform redundant relief against a failure, the yield can be improved.

(Embodiment 1)
FIG. 1 shows a schematic diagram of a semiconductor device according to the present embodiment. A semiconductor device 1 shown in FIG. 1 is an SOC (System On a Chip), and includes a logic area 2, a memory area 3, and an analog area 4. Further, the semiconductor device 1 shown in FIG. 1 includes an IO region 5 for connecting the logic region 2, the memory region 3, and the analog region 4 to an external device. In the semiconductor device according to the present embodiment, the yield of the entire semiconductor device 1 is improved by adopting a configuration for relieving logic defects in the logic region 2.

  FIG. 1 is a schematic diagram of a configuration for relieving a logic defect. A plurality of basic cells 21 having the same configuration, a redundant cell 22 having the same configuration as the basic cell 21, An input selector 23 that switches a signal input to each of the cell 21 and the redundant cell 22 and an output selector 24 that switches a signal output from each of the basic cell 21 and the redundant cell 23 are provided. A plurality of basic cells 21 having the same configuration and redundant cells 22 having the same configuration as the basic cell 21 are collectively referred to as a repair target group 25. When there is a logic defect in the basic cell 21 in the same repair target group 25, the basic cell 21 becomes the failed cell 26. The input selector 23 and the output selector 24 are switched so that the redundant cell 22 in the same repair target group 25 can be used instead of the failed cell 26.

  The failure determination is performed by performing failure analysis on a chip that has failed during the shipping test. In addition, when the failed cell 26 is not the basic cell 21 included in the repair target group 25 and does not have the redundant cell 22, it is not a target for redundant repair. In addition, in order to replace the failed cell 26 with the redundant cell 22, it is necessary to switch the input path and the output path with the input selector 23 and the output selector 24. The control terminals of these selectors employ registers or fuses and are logically fixed. The This logically fixed information is written as a program for redundant relief in the flash memory or the like in the semiconductor device 1, and the information is read from the flash memory or the like at the time of relief.

  Further, the redundant relief configuration according to the present embodiment will be specifically described. FIG. 2 shows a circuit diagram of one redundant relief configuration formed in the logic region 2 according to the present embodiment. In FIG. 2, the flip-flops U0 to U2 are the basic cells 21 and the number of basic cells in the repair target group 25 is three. It is assumed that the redundant cell 22 prepared for repairing the flip-flops U0 to U2 is the flip-flop U3, and the flip-flops U0 to U3 are one repair target group 25. A selector U4 is provided as an input selector 23 for switching the input path of the relief target group 25. Further, the selector U5 as the output selector 24 for switching the output path of the flip-flop U0, the selector U6 as the output selector 24 for switching the output path of the flip-flop U1, and the output selector 24 for switching the output path of the flip-flop U2. A selector U7 is provided.

  If the result of the shipment test and failure analysis reveals that there is a failure in the flip-flop U0, the flip-flop U0 (failure cell 26) is replaced with the flip-flop U3 (redundant cell 22). For this purpose, the control pin of the selector U4 is set to switch the input path so that the propagation signal DA0 to the original flip-flop U0 flows to the flip-flop U3 (redundant cell 22). That is, the selector U4 has the logic of the control pin so that the signal from the terminal D0 becomes the output of the terminal Y. When the fault cell 26 is the flip-flop U1, the signal from the terminal D1 is the output of the terminal Y, and when the fault cell 26 is the flip-flop U2, the signal from the terminal D2 is the output of the terminal Y.

  Furthermore, it is necessary to switch the output path in order to propagate the calculation result performed by the flip-flop U3 of the redundant cell 22, and the control pin of the selector U5 is switched among the selectors U5, U6, and U7 that are the output selector 24. That is, the input pin of the selector U5 is changed from “0” to “1”, and the input pins of the other selectors U6 and U7 remain “0”. 0 '. When the fault cell 26 is the flip-flop U1, the control pin logic (SEL) '0, 1, 0' and when the fault cell 26 is the flip-flop U2, the control pin logic (SEL) '0, 0, 1 ', respectively.

  In addition to the propagation signals DA0 to DA2, a clock signal CLK and a reset signal RST are supplied to the flip-flops U0, U1 and U2, respectively. The output destinations of the selectors U5, U6, U7 are combination logic. FIG. 3 illustrates a path after the failed cell 26 is switched to the redundant cell 22. In FIG. 3, the route after switching is indicated by a bold line, and the route before switching is indicated by a broken line.

  FIG. 4 is a conceptual diagram in which the control pin of the input selector 23 is fixed to fix the input / output path. In FIG. 4, the setting value of the input selector 23 for fixing the input / output path of the specified failed cell 26 is stored on the flash memory 31. The input selector 23 using this set value is an 8-to-1 selector that selects one signal from the eight terminals D0 to D7 and outputs it from the terminal Y. When the power is turned on, the set value is loaded into each register connected to the select pin of the input selector 23 based on the set value stored on the flash memory 31, and the control pin is fixed. The same applies to the output path, and the output selector 24 is provided with eight 2-to-1 selectors for selecting and outputting one signal from two terminals, based on the set value stored in the flash memory 31. Thus, the control pin of the 2to1 selector is fixed. In FIG. 4, since the method of fixing the input selector 23 and the output selector 24 is a register, the above operation occurs for each power source On. When it is desired to eliminate such an operation, the input selector 23 and the output selector 24 may employ a fuse and fix the control pin without using a register.

  As described above, in the semiconductor device according to the present embodiment, even when the flip-flop U0 has a defect (for example, 0 stuck-at fault) and cannot subsequently propagate logic, it is treated as a defective product. It can be relieved by the cell 22 and the yield can be improved.

(Embodiment 2)
In the first embodiment, the basic cell 21 is described as a flip-flop. However, the present invention is not limited to this and may have other configurations. Specifically, in the circuit diagram shown in FIG. 5, the basic cell 21 is an inverter. Therefore, in the case of FIG. 5, the redundant cell 22 is also an inverter. Since the configuration and operation other than the basic cell 21 are the same as the configuration shown in FIG.

  In the circuit diagram shown in FIG. 6, the basic cell 21 is a NAND circuit that is a logic circuit. Therefore, in the case of FIG. 6, the redundant cell 22 is also a NAND circuit. Since the configuration and operation other than the basic cell 21 are the same as the configuration shown in FIG. However, in the case of a NAND circuit, since there are two input propagation signals (DA01, DA02, etc.), the input selector 23 is also composed of two selectors U4A and U4B.

  Further, in the circuit diagram shown in FIG. 7, the basic cell 21 is a scan register. Therefore, in the case of FIG. 7, the redundant cell 22 is also a scan register. Since the configuration and operation other than the basic cell 21 are the same as the configuration shown in FIG. 2, the same components are denoted by the same reference numerals and detailed description thereof is omitted. However, in the case of the scan register, since the input propagation signals are two (DA01, DA02, etc.), the input selector 23 is composed of two selectors U4D and U4SI.

  As described above, even if the basic cell 21 is a macro cell such as an inverter, NAND, or scan FF as in the semiconductor device according to the present embodiment, the redundant cell 22 can be used for repair, thereby improving the yield. be able to.

(Embodiment 3)
In the first and second embodiments, the basic cell 21 is described as a macro cell such as a flip-flop. However, the present invention is not limited to this and may have other configurations. Specifically, the circuit diagram shown in FIG. 8 shows a case where the basic cell 21 is an arithmetic unit. Therefore, in the case of FIG. 8, the redundant cell 22 is also an arithmetic unit.

  In the circuit diagram shown in FIG. 8, the arithmetic units U0 to U2 to which two 8-bit signals as the basic cell 21 are input (DA01, DA02, etc.) and the arithmetic unit U3 of the redundant cell 22 are combined into one repair target group. 25. In order to switch the input path of the relief target group 25, selectors U4A [7: 0] and U4B [7: 0] are provided as input selectors 23 that can switch 8-bit signals. In addition, when the computing unit U0 that outputs the 8-bit computation result fails, in order to switch to the output path from the computing unit U3, the selector U5 [7: 0] is used as the output selector 24 that can switch the 8-bit signal. I have. Similarly, when the arithmetic unit U1 that outputs the 8-bit arithmetic result fails, the selector U6 [7: 0] is output as the output selector 24 for switching to the output path from the arithmetic unit U3, and the 8-bit arithmetic result is output. A selector U7 [7: 0] is provided as an output selector 24 for switching to the output path from the computing unit U3 when the computing unit U2 to be malfunctioned.

  If it is found from the results of the shipment test and failure analysis that there is a failure in the arithmetic unit U0, the arithmetic unit U0 (failure cell 26) is replaced with the arithmetic unit U3 (redundant cell 22). For this purpose, selectors U4A [7: 0] and UB [7: 0] are used to switch the input path so that the propagation signals DA01 and DA02 to the original arithmetic unit U0 flow to the arithmetic unit U3 (redundant cell 22). Set the control pin. That is, the selector U4AB [7: 0] has the logic of the control pin so that the signal from the terminal D0 becomes the output of the terminal Y, respectively.

  Further, it is necessary to switch the output path in order to propagate the result of the operation performed by the arithmetic unit U3 of the redundant cell 22, and the selectors U5 [7: 0], U6 [7: 0], U7 [7 which are the output selectors 24 are required. : 0], the control pin of the selector U5 [7: 0] is switched. That is, the input pin of the selector U5 [7: 0] is changed from “00000000” to “11111111”, and the input pins of the other selectors U6 [7: 0] and U7 [7: 0] are left as “00000000”. Become.

  As described above, even if the basic cell 21 is an arithmetic unit as in the semiconductor device according to the present embodiment, it can be relieved by the redundant cell 22, so that the yield can be improved. In addition, the signal which the basic cell 21 processes with an arithmetic unit is not restricted to 8 bits.

(Embodiment 4)
In the first and second embodiments, the basic cell 21 is described as a macro cell such as a flip-flop or an arithmetic unit. However, the present invention is not limited to this and may have other configurations. Specifically, in the circuit diagram shown in FIG. 9, the basic cell 21 is a logic cone. Therefore, in the case of FIG. 9, the redundant cell 22 is also a logic cone. The logic cone is a combinational logic of multiple inputs and one output in which an input is an output terminal of a flip-flop or a primary input and an output is a data terminal of the flip-flop or a primary output.

  In the circuit diagram shown in FIG. 9, the logic cone LC <b> 0 as the basic cell 21 and the logic cone LC <b> 1 of the redundant cell 22 are set as one repair target group 25. The logic cone LC1 of the redundant cell 22 is a clone circuit to which the same input signal as that of the logic cone LC0 of the basic cell 21 is input. In the redundant relief configuration according to the present embodiment, the same logic is directly connected to the redundant cell 22 because the input selector supplies the same logic to all the input paths. Further, a selector U0 of an output selector 24 is provided to select a path from the logic cone LC1 of the redundant cell 22 as an output path instead of the logic cone LC0 that is the repaired failure cell 26. Other configurations and operations are the same as those shown in FIG. 2, and thus detailed description thereof is omitted.

  As described above, even if the basic cell 21 is a logic cone as in the semiconductor device according to the present embodiment, it can be relieved by the redundant cell 22, so that the yield can be improved.

(Embodiment 5)
In the first and second embodiments, the basic cell 21 is described as a macro cell such as a flip-flop. However, the present invention is not limited to this and may have other configurations. Specifically, the circuit diagram shown in FIG. 10 shows a case where the basic cell 21 is a macro block. Therefore, in the case of FIG. 10, the redundant cell 22 is also a macroblock. Note that a macroblock is a logical assembly at a functional level, and a difference from a logic cone is that a storage element may be included therein or multiple outputs may be used.

  In the circuit diagram shown in FIG. 10, the macroblock MB0 as the basic cell 21 and the macroblock MB1 of the redundant cell 22 are set as one repair target group 25. The macroblock MB1 of the redundant cell 22 is a clone circuit to which the same input signal as that of the macroblock MB0 of the basic cell 21 is input. In the redundant relief configuration according to the present embodiment, the same logic is directly connected to the redundant cell 22 because the input selector supplies the same logic to all the input paths. Further, in place of the macroblock MB0 that is the failure cell 26 to be repaired, the selector U0 [*, 0] of the output selector 24 that selects the path from the macroblock MB1 of the redundant cell 22 as the output path (multiple bit correspondence: * = Arbitrary integer). Other configurations and operations are the same as those shown in FIG. 2, and thus detailed description thereof is omitted.

  As described above, even if the basic cell 21 is a macro block as in the semiconductor device according to the present embodiment, it can be repaired by the redundant cell 22, so that the yield can be improved.

(Embodiment 6)
In the semiconductor device according to the present embodiment, an example in which the repair target group 25 is arrayed is shown. The semiconductor device illustrated in FIG. 11 is an example of a semiconductor device according to this embodiment. In the semiconductor device shown in FIG. 11, the basic cell 21 is a flip-flop, eight basic cells 21 including the repair target group 25, and one redundant cell 22. As the repair target group 25 is arrayed, the input selector 23 and the output selector 24 for switching input / output paths are also optimally arranged in the vicinity of the repair target group 25. Furthermore, in the semiconductor device shown in FIG. 11, the degree of integration is further improved by arranging eight identical repair target groups 25 in parallel.

  Then, the input selector 23 and the output selector 24 switch the input / output path in order to identify the fault cell 26 in each repair target group 25 and use the redundant cell 22 instead of the fault cell 26. The operation for switching the input / output path is the same as that described in the first embodiment, and thus detailed description thereof is omitted.

  As described above, in the semiconductor device according to the present embodiment, the repair target group 25 is arrayed and the plurality of basic cells 21 and the redundant cells 22 are arranged in the vicinity. Not only can the area be increased, but the skew can be reduced by using equal-length wiring or the like, and the influence on the timing after redundancy relief can be minimized. Furthermore, in the present embodiment, by arranging the repair target groups 25 in parallel, the degree of integration can be increased by resource sharing or the like, and the influence of the area penalty can be reduced.

(Embodiment 7)
In the sixth embodiment, the repair target groups 25 are arrayed, and the same repair target groups 25 are arranged in parallel. The semiconductor device according to this embodiment has a configuration in which an area penalty is suppressed by reducing resources (registers) for controlling an input path and an output path. FIG. 12 shows an example of a semiconductor device according to this embodiment.

  In the semiconductor device shown in FIG. 11, the input path is controlled using the eight input selectors 23 corresponding to each of the eight repair target groups 25. This input selector 23 is an 8to1 selector, and it is necessary to spend three registers to fix the value of the control signal (3 bits each) for one 8-to1 selector. For this reason, in the semiconductor device shown in FIG. 11, since eight repair target groups 25 are provided, 8 * 3 = 24 registers are required.

  However, in the semiconductor device according to the present embodiment, as shown in FIG. 12, the eight input selectors 23 share a register for fixing the value of the control signal of each selector (three registers), and each relief target group 25 Are configured to relieve only the same topology. That is, as shown in FIG. 12, when a basic cell 21 of a certain repair target group 25 becomes a failed cell 26, the failed cell 26 is changed to a redundant cell 22 and is also located in the same row as the failed cell 26. The redundant cell 22 is also changed in the basic cell 21 of the repair target group 25. By sacrificing the degree of relief freedom of each relief target group 25, the number of registers required for controlling the input path is reduced from 24 to 3.

  Similarly, the output selector 24 for setting the output path also shares the control signal (1 bit for each), thereby reducing the number of registers for controlling the output path to eight. In other words, the number of registers for controlling 64 output paths in FIG. 11 is 8 in FIG.

  As described above, in the semiconductor device according to the present embodiment, the array is multiplexed and the wiring to the input selector 23 and the output selector 24 is shared, so that two or more failures except for the same topology (row) can be obtained. Instead of sacrificing the degree of freedom that it cannot be rescued, it is possible to reduce resources for controlling the input / output path and reduce an area penalty for redundant relief.

(Embodiment 8)
The semiconductor device according to the above-described embodiment has a configuration in which power is supplied regardless of whether the redundant cell 22 is used. However, the semiconductor device according to the present embodiment is configured to provide a switch that cuts off the power supply to the redundant cells 22 in the repair target group 25 that need not be repaired. FIG. 13 shows a redundant cell 22 in which the basic cell is assumed to be an inverter, and a switch SW is provided on the path from the power source and the path to the ground.

  In the redundant cell 22 shown in FIG. 13, when there is no failure cell 26 in the repair target group 25 and it is not necessary to use it, the power supply path and the path to the ground can be cut off by turning off the switch SW. it can.

  As described above, in the semiconductor device according to the present embodiment, the redundant cell 22 is provided with the switch SW that cuts off the power supply and the path to the ground, thereby preventing extra leakage current and interfering with other logic. It can prevent the adverse effects of.

(Embodiment 9)
In the eighth embodiment, the switch SW that can cut the path from the power supply and the path to the ground is provided in each redundant cell 22. However, the failed cell 26 rescued by the redundant cell 22 is in a non-functional state but remains energized. Therefore, in the eighth embodiment, an extra leakage current may occur in the failed cell 26.

  Therefore, in the semiconductor device according to the present embodiment, the switch SW that can cut the path from the power source and the path to the ground is provided in the basic cell 21 as well as the redundant cell 22 shown in FIG. That is, in the present embodiment, the switch SW is also applied to all the basic cells 21 in the repair target group 25. For this reason, in the present embodiment, the switch SW is also provided in the failed basic cell 21 (failed cell 26). Therefore, by turning off the switch SW of the basic cell 21, supply of power to the failed cell 26 is performed. The route and the route to the ground can be cut off.

  As described above, in the semiconductor device according to this embodiment, by providing the switch SW that cuts off the power supply and the path to the ground in the basic cell 21, the power supply of the failed cell 26 and the path to the ground can be cut off. It is possible to prevent extra leakage current and to prevent adverse effects such as interference with other logic.

(Embodiment 10)
In the first embodiment, the redundant repair configuration in which all the basic cells 21 in the repair target group 25 are repaired by the redundant cells 22 has been described. However, the redundant repair configuration of the semiconductor device according to the present invention is not limited to this, and a redundant repair configuration in which each basic cell 21 is repaired by the adjacent basic cell 21 and redundant cell 22 may be used. By adopting the redundant relief configuration, timing overhead can be reduced. FIG. 14 shows a circuit configuration of the semiconductor device according to the present embodiment. In the semiconductor device shown in FIG. 14, the flip-flop is the basic cell 21 and the number of basic cells 21 in the repair target group 25 is three.

  First, in the semiconductor device shown in FIG. 14, a flip-flop U3 that is a redundant cell 22 is provided in addition to the flip-flops U0, U1, and U2 that are basic cells 21, and the flip-flops U0 to U3 are set as one repair target group 25. . An input selector 23 is provided to switch the input path of the relief target group 25. However, unlike the selector U4 shown in FIG. 2, selectors S1 and S2 are provided. Here, the selector S1 switches between the propagation signal DA0 and the propagation signal DA1 input to the flip-flop U1. The selector S2 switches between the propagation signal DA1 and the propagation signal DA2 input to the flip-flop U2. Further, in the redundant cell 22 shown in FIG. 14, only the propagation signal DA2 is input.

  Therefore, the semiconductor device shown in FIG. 14 does not replace the failed basic cell 21 (failed cell 26) in the redundant cell 22, but replaces it with the adjacent basic cell 21 or redundant cell 22. For example, when it is found that the flip-flop U0 has a failure, the function of the flip-flop U0 is performed by the flip-flop U1 by switching the propagation signal DA0 to be supplied to the flip-flop U1 using the selector S1. Similarly, the function of the flip-flop U1 is performed by the flip-flop U2 by switching the propagation signal DA1 to be supplied to the flip-flop U2 using the selector S2. Further, the function of the flip-flop U2 is performed by the flip-flop U3 which is the redundant cell 22. As a result, the flip-flop U0 which is the failure cell 26 is redundantly remedied. FIG. 15 illustrates a path in the case where the flip-flop U0 which is the failure cell 26 is redundantly repaired. In FIG. 15, the route after switching is indicated by a bold line, and the route before switching is indicated by a broken line.

  The logic of the selectors S1 and S2, which are the input selector 23, is S1, S2 = 0, 0 as described above when the flip-flop U0 is the failed cell 26, and S1, S2 when the flip-flop U1 is the failed cell 26. When the flip-flop U2 is the fault cell 26, S1, S2 = 1,-. Here, '-' indicates that the logic of the selectors S1 and S2 is not questioned. Further, the output selector 24 for controlling the output path shown in FIG. 14 is the same as the output selector 24 shown in FIG.

  As described above, in the semiconductor device according to the present embodiment, the failed cell 26 is switched to the adjacent basic cell 21, and the switched basic cell 21 is sequentially switched to the adjacent basic cell 21 or the redundant cell 22 for relief. In addition to the effects described in the first embodiment, it is possible to distribute the fan-out of the redundant cells 22 and delete the wiring necessary for redundancy relief, thereby minimizing the influence on the timing.

(Embodiment 11)
The semiconductor device according to the above-described embodiment has a feature that the basic cell 21, the redundant cell 22, and a selector for switching them are held as a set as a redundant relief configuration. Therefore, in the semiconductor device according to the present embodiment, a description will be given of making the redundancy repair configuration a hard macro by using the feature of the configuration. The circuit diagram shown in FIG. 16 has the same configuration as the semiconductor device shown in FIG. The circuit diagram shown in FIG. 16 shows a cell HM1 in which the set of the flip-flop U0 and the selector U5 is made into a hard macro, and a cell HM2 in which the set of the flip-flop U2 and the selectors S2 and U5 is made into a hard macro. ing.

  When the hard macro is formed in the unit shown in the cell HM1, even if the redundant cell 22 shown in FIG. 2 is a shared repair method for repairing all the basic cells 21, the adjacent basic cells 21 shown in FIG. Alternatively, the present invention can be applied to any of the adjacent repair methods for repairing with the redundant cell 22. On the other hand, when the hard macro is formed in the unit shown in the cell HM2, it can be applied only to the adjacent repair method.

  The hard macro cell HM1 functions as a normal flip-flop when the select signal S is “0”, and receives the input signal QI without synchronizing with the clock signal CLK when the select signal S is “1”. This is combinational logic that is output as is.

  On the other hand, in the hard macro cell HM2, the select signal S is composed of 2 bits, the select signal S [1] corresponds to the input select, and the select signal S [0] corresponds to the output select. Therefore, the cell HM2 functions as a normal multiplexer flip-flop when the select signal S [0] is “0”, and is input without being synchronized with the clock signal CLK when the select signal S [0] is “1”. This is combinational logic for outputting the processed signal QI as it is. The cell HM2 is supplied with the propagation signal DA0 when the select signal S [1] is “0”, and is supplied with the propagation signal D1 when the select signal S [1] is “1”.

  Also, in the cell HM2 shown in FIG. 16, the actual select signal S [1: 0] cannot be 00. That is, in the cell HM2 shown in FIG. 16, the select signal S [1: 0] is always 10 when there is no relief, and the select signal S [1: 0] is always 01 when there is relief. Therefore, the cell HM2 can be configured as shown in FIG. 17 using the above relationship. That is, the cell HM2 shown in FIG. 17 controls the selector S2 by inverting the signal SD for controlling the selector S1 with the inverter 170 and supplying the inverted signal as the signal SQ to the selector S2. Therefore, the configuration of the cell HM2 illustrated in FIG. 17 can be reduced compared to the cell HM2 illustrated in FIG. 17 is a data path (signal SD = 1, signal SQ = 0, output of Q ′ = D, output of Q = D) when there is no relief in the cell HM2, and a broken line path is shown in FIG. This is a data path with relief when the flip-flop U0 fails (signal SD = 0, signal SQ = 1, Q ′ output = D ′, Q output = QI).

  As described above, in the semiconductor device according to the present embodiment, by making the configuration essential for redundancy relief into a hard macro, in addition to increasing the degree of integration and reducing the area, the influence on timing can be minimized. it can.

(Embodiment 12)
In the semiconductor device according to the present embodiment, a scan flip-flop used for facilitating circuit testing, a selector for switching data input and scan input before the scan flip-flop, a relief target By utilizing the feature of having a selector for switching the scan cell to a redundant cell, these are converted into a hard macro. That is, the semiconductor device according to the present embodiment includes a hard macro cell in which a redundant scan cell with an input / output switching function is compactly converted into a hard macro.

  FIG. 18 shows a circuit configuration of the semiconductor device according to the present embodiment. The circuit shown in FIG. 18 includes a selector 231 that switches the input to the flip-flop in place of the input selector 23 in the circuit configuration shown in FIG. 14, and a selector 232 that switches between a data input and a scan input. The selector 232 includes a selector S01 that switches between a data input propagation signal DA0 and a scan input signal sc0, a selector S02 that switches between a data input propagation signal DA1 and a scan input signal sc1, and a data input propagation signal DA2. There is a selector S03 for switching the scan input signal sc2. On the other hand, the selector 231 includes a selector S11 that switches between an external signal and an output signal from the selector S01, a selector S12 that switches between an output signal from the selector S01 and an output signal from the selector S02, an output signal from the selector S02, and an output from the selector S03. There is a selector S13 that switches between signals, and a selector S14 that switches between the output signal of the selector S03 and an external signal.

  Further, in the circuit shown in FIG. 18, the selector S02, the selector S12, the flip-flop U1, and the selector U6 are implemented as a hard macro as the hard macro cell HM3 that can be applied to the adjacent relief system. The hard macro cell HM3 operates as follows. First, in the normal mode (signal SM = 0) in which there is no failure in the flip-flop and the selectors S01 to S03 select the data input, the bold path shown in FIG. 18 is the data flow. In other words, the path for receiving the propagation signal DA1 at the D pin, taking it into the flip-flop U1, and outputting it to the next combination circuit via the Q pin is the data flow of the propagation signal DA1. At this time, the signal (signal SM) input to the SM pin is 0, the signal (signal SD) input to the SD pin is 1, and the signal (signal SQ) input to the SQ pin is 0, so that the clock signal Is Rise, the flip-flop U1 takes in the propagation signal DA1 and the signal output from the Q pin and the Q ′ pin is input to the D pin to become a signal (propagation signal DA1).

  On the other hand, in the normal mode (signal SM = 0) in which the flip-flop U0 fails and the selectors S01 to S03 select the data input, the broken line path shown in FIG. 18 is the relief data flow. In other words, the path for receiving the propagation signal DA0 at the D 'pin, fetching it into the flip-flop U1, and outputting it to the next combination circuit via the Q' pin is the relief data flow of the propagation signal DA0. At this time, the signal (signal SM) input to the SM pin is 0, the signal (signal SD) input to the SD pin is 0, and the signal (signal SQ) input to the SQ pin is 1, so that the clock signal Is Rise, the flip-flop U1 takes in the propagation signal DA0 and the signal output from the Q ′ pin is input to the D ′ pin to become a signal (propagation signal DA0). At this time, the signal output from the Q pin is input to the QI pin and becomes a signal (signal QI).

  Next, the operation in the scan mode (signal SM = 1) in which the selectors S01 to S03 select the scan input will be described with reference to FIG. First, when there is no failure in the flip-flop and the selectors S01 to S03 are in the scan mode (signal SM = 1) for selecting data input, the bold path shown in FIG. 19 is the scan flow. In other words, the scan flow is a path that receives the signal (signal SI) of the previous scanout sc1 at the SI pin, takes it into the flip-flop U1, and outputs it from the scanout sc2 to the next stage via the Q pin. At this time, the signal (signal SM) input to the SM pin is 1, the signal (signal SD) input to the SD pin is 1, and the signal (signal SQ) input to the SQ pin is 0, so that the clock signal Is Rise, the flip-flop U1 takes in the signal SI and the signal output from the Q pin and the Q ′ pin becomes the signal SI.

  On the other hand, in the scan mode (signal SM = 1) in which the flip-flop U0 fails and the selectors S01 to S03 select the data input, the broken line path shown in FIG. 19 is the relief scan flow. That is, the path for receiving the signal (signal D ′) of the previous scanout sc0 at the D ′ pin and fetching it into the flip-flop U1 and outputting from the scanout sc1 to the next stage via the Q ′ pin is the relief scan flow. At this time, the signal (signal SM) input to the SM pin is 1, the signal (signal SD) input to the SD pin is 0, and the signal (signal SQ) input to the SQ pin is 1, so that the clock signal Is Rise, the flip-flop U1 takes in the signal D 'and the signal output from the Q' pin becomes the signal D '. At this time, the signal output from the Q pin is input to the QI pin and becomes a signal (signal QI).

  As described above, in the semiconductor device according to the present embodiment, the area is reduced by integrating the selectors 231 and 24 for switching to the redundant cell 25 and the selector 232 for switching to the scan operation into a hard macro, The area penalty can be reduced and the manufacturing cost can be reduced.

  Note that the circuit configuration that forms a hard macro in the semiconductor device according to the present invention is not limited to the circuit configuration illustrated in FIGS. 18 and 19, and can be applied to the circuit configurations described in other embodiments.

(Embodiment 13)
FIG. 20A shows a hard-redundant redundancy relief basic circuit used in the semiconductor device according to the present embodiment, and FIG. 20B shows a truth table thereof. The basic circuit for redundant repair made into a hard macro shown in FIG. 20A includes a selector USM.1 for repairing the flip-flop UR by the adjacent repair system. It has USD and USQ. The selector USM switches between a signal (signal D) input from the D pin and a signal (signal SI) input from the SI pin based on the signal (signal SM) input to the SM pin. Further, the selector USD outputs an output signal (signal D or signal SI) of the selector USM and a signal (signal RDI) output from the selector USM of the adjacent circuit based on a signal (signal SD) input to the SD pin. Switch. Note that the output signal (signal D or signal SI) of the selector USM is also output as a signal RDO for the selector USD of the adjacent circuit.

  Further, the output signal (signal D, signal SI or signal RDI) of the selector USM is processed by the flip-flop UR and output to the selector USQ. The output signal of the flip-flop UR is also output as a signal RQO for the selector USQ of the adjacent circuit. The selector USQ switches between the output signal of the flip-flop UR and the signal (signal RQI) output from the flip-flop UR of the adjacent circuit based on the signal (signal SQ) input to the SQ pin, and from the Q pin. Output as signal Q.

  Next, the operation of the circuit shown in FIG. 20A will be specifically described using the truth values shown in FIG. First, in the normal mode of the signal SM = 0, when the signal SI = 0 and the signal SQ = 0, the signal Q = the signal RDI, when the signal SI = 0 and the signal SQ = 1, the signal Q = the signal RQI, and the signal SI = 1 and signal SQ = 0, signal Q = signal D, and signal SI = 1 and signal SQ = 1, signal Q = signal RQI. On the other hand, in the scan mode with the signal SM = 1, when the signal SI = 0 and the signal SQ = 0, the signal Q = the signal RDI, and when the signal SI = 0 and the signal SQ = 1, the signal Q = the signal RQI, and the signal SI = 1 and signal SQ = 0, signal Q = signal SI, and signal SI = 1 and signal SQ = 1, signal Q = signal RQI. It is assumed that the clock signal input to the flip-flop UR is rise regardless of the mode of the signal SM. In this way, in the circuit shown in FIG. 20A, by controlling the signal SI and the signal SQ, the signal (signal D, signal SI) input to its own circuit and the signal from the adjacent circuit (signal RDI, The path can be selected so that the signal can be output from the Q pin that switches between the signal RQI). In the circuit shown in FIG. 20A, the selector USM. By sharing a part of USD and USQ with those in the scan mode, circuit duplication required for redundancy relief is reduced.

  Next, FIG. 21 shows a circuit of the semiconductor device according to the present embodiment configured by using a plurality of hard macro circuits shown in FIG. The circuit shown in FIG. 21 has three hard macro circuits HM shown in FIG. 20A, and has the same configuration as the flip-flops U0, U1, U2 of the basic cell 21 to be repaired. The 22 flip-flops U3 are collectively set as a relief target group 25. The selector USM shown in FIG. 20A corresponds to the selector 232 in FIG. 21, and a selector S01 that switches between the data input propagation signal DA0 and the scan input signal sc0, and the data input propagation signal DA1 and the scan. There is a selector S02 that switches between the input signal sc1 and a selector S03 that switches between the data input propagation signal DA2 and the scan input signal sc2.

  The selector USD shown in FIG. 20A corresponds to the selector 231 in FIG. 21, and selects the selector S11 that switches between the external signal RDI and the output signal of the selector S01, and the external signal RDI and the output signal of the selector S02. There is a selector S12 for switching, and a selector S13 for switching between the external signal RDI and the output signal of the selector S03. Here, the external signal RDI is a signal RDO of the adjacent circuit HM when the hard macro 3 is adjacent to the circuit HM, and an arbitrary signal is a signal input from outside the circuit when it does not exist. is there.

  Furthermore, the selector USQ shown in FIG. 20A corresponds to the selector 24 in FIG. 21, and a selector U5 for switching between the external signal RQI and the output signal of the flip-flop U0, the external signal RQI and the output signal of the flip-flop U1. And a selector U7 for switching between the external signal RQI and the output signal of the flip-flop U2. Here, the external signal RQI is the signal RQO of the adjacent circuit HM or the output signal of the flip-flop.

  Next, the operation of the circuit shown in FIG. 21 will be described. First, in the normal mode (signal SM = 0) in which the flip-flops U0 to U2 have no failure and the selectors S01 to S03 select the data input, the path of the propagation signal DA1 is the thick line path (data flow) shown in FIG. It becomes. In other words, the path for receiving the propagation signal DA1 at the D pin, taking it into the flip-flop U1, and outputting it to the next combination circuit via the Q pin is the data flow of the propagation signal DA1. At this time, the signal (signal SM) input to the SM pin is 0, the signal (signal SD) input to the SD pin is 1, and the signal (signal SQ) input to the SQ pin is 0, so that the clock signal Is Rise, the flip-flop U1 takes in the propagation signal DA1 and the signal output from the Q pin is input to the D pin and becomes a signal (propagation signal DA1).

  On the other hand, in the normal mode (signal SM = 0) in which the flip-flop U0 fails and the selectors S01 to S03 select data input, the path of the propagation signal DA0 is the broken line path (relief data flow) shown in FIG. Become. That is, the selector S12 is switched to take the propagation signal DA0 into the flip-flop U1 as the signal RDI and output to the next combination circuit through the selector U5 is the relief data flow of the propagation signal DA0. At this time, the signal (signal SM) input to the SM pin is 0, the signal (signal SD) input to the SD pin is 0, and the signal (signal SQ) input to the SQ pin is 1, so that the clock signal Is Rise, the flip-flop U1 takes in the propagation signal DA0 and the signal output from the selector U5 is input to the selector S01 and becomes a signal (propagation signal DA0). At this time, the signal output from the selector U6 is the output signal of the flip-flop U2, the signal output from the selector U7 is the output signal of the flip-flop U3, and there is no signal passing through the failed flip-flop U0. .

  Next, the operation in the scan mode (signal SM = 1) in which the selectors S01 to S03 select the scan input will be described with reference to FIG. First, when there is no failure in the flip-flops U0 to U2 and the selectors S01 to S03 are in the scan mode (signal SM = 1) to select the data input, the signal path of the scan-out sc1 in the previous stage is the thick line path shown in FIG. (Scan flow). That is, the scan flow is a path that receives the signal (signal SI) of the previous scan-out sc1 at the SI pin, takes it into the flip-flop U1, and outputs it from the scan-out sc2 to the next stage via the Q pin. At this time, the signal (signal SM) input to the SM pin is 1, the signal (signal SD) input to the SD pin is 1, and the signal (signal SQ) input to the SQ pin is 0, so that the clock signal Is Rise, the signal that the flip-flop U1 takes in the signal SI and outputs from the Q pin becomes the signal SI of the next stage.

  On the other hand, in the scan mode (signal SM = 1) in which the flip-flop U0 fails and the selectors S01 to S03 select the data input, the signal path of the scan-out sc0 in the previous stage is a broken-line path (relief scan) shown in FIG. Flow). In other words, the relief scan flow is a path in which the signal of the previous scan-out sc0 received by the selector S01 is taken into the flip-flop U1 and output from the scan-out sc1 to the next stage via the selector U5. At this time, the signal (signal SM) input to the SM pin is 1, the signal (signal SD) input to the SD pin is 0, and the signal (signal SQ) input to the SQ pin is 1, so that the clock signal Is Rise, the flip-flop U1 takes in the output signal of the selector S01 and the signal output from the selector U5 becomes the signal of the scan-out sc0 in the previous stage. At this time, the signal output from the selector U6 is the output signal of the flip-flop U2, the signal output from the selector U7 is the output signal of the flip-flop U3, and there is no signal passing through the failed flip-flop U0. .

  As described above, in the semiconductor device according to the present embodiment, by sharing a part of the selector with that in the scan mode, the area penalty can be reduced and the manufacturing cost can be suppressed.

(Embodiment 14)
In the semiconductor device according to the present embodiment, the area of the entire circuit is reduced by relaxing the design rule of the relief target group 25 or the redundant cell 22 from the design rule of other parts (changing the design rule so as to increase the degree of integration). As a result, an increase in area due to logic redundancy relief is reduced. When it is assumed that the repair target group 25 or the redundant cell 22 is the hard macro of FIG. 21, the design rule for the flip-flop in the hard macro is relaxed from the design rule of the other part to increase the degree of integration. The entire area can be compressed.

  Specifically, a design rule applied to the repair target group 25 or the redundant cell 22 will be described. FIG. 23 shows an example of design rule relaxation. In the layout shown in FIG. 23, the circuit area is reduced by applying design rules that are more relaxed than the design rules of other portions. Normally, a margin considering the lithography and OPC (Optical Proximity Correction) is imposed on the design rule. However, the design rule applied to the repair target group 25 or the redundant cell 22 according to the present embodiment has a defect density. By allowing the increase or by imposing some restrictions on the cell layout, the number of places where the margin is imposed is reduced, and for example, the design rule is reduced to that of an SRAM (hereinafter referred to as the Push rule). The degree of integration is increased.

  As a Push rule, a contact distance between contact holes CO or vias V indicated by an arrow A in FIG. 23, a space amount between metal wirings M1 and M2 indicated by an arrow B, and a space amount between polysilicon wirings P indicated by an arrow C are as follows. The cell width is reduced by packing. In the design rule applied to the relief target group 25 or the redundant cell 22 according to the present embodiment, the rule at that location is reduced by about 10% compared to the design rule of other portions. Further, in the semiconductor device, it is basically the cell row direction (direction in which cells are arranged next to each other) that affects the circuit occupation area. Accordingly, the amount of space between the PMOS and NMOS indicated by the arrow D in FIG. 23, the amount of protrusion of the polysilicon wiring P from the P-type diffusion layer PD indicated by the arrow E, and the N-type diffusion layer ND as in the arrow E Although the protruding amount of the polysilicon wiring P can be considered, these rules are portions that affect the cell height and are not directly reflected in the reduction of the chip area.

  As above. In the relief target group 25 or the redundant cell 22 according to the present embodiment, the design rule to be applied is more relaxed than the design rule to be applied to other parts (for example, the design rule for the flip-flop is changed to a design rule similar to that of an SRAM) The area occupied by the circuit can be reduced, and the number of chips including the logic redundancy relief mechanism per wafer can be increased. In addition, since the logic circuit designed with the relaxed design rule as in this embodiment can be relieved by this relief mechanism even if the defect density is increased if it is a single defect, the semiconductor device according to this embodiment The number of defective chips does not increase, leading to an increase in non-defective chips, and the wafer manufacturing cost can be reduced. Note that the relaxation of the design rule applied to the repair target group 25 or the redundant cell 22 according to the present embodiment can be similarly applied to the configurations of the other embodiments.

(Embodiment 15)
In this embodiment mode, a design flow used for the semiconductor device described in Embodiment Modes 1 to 13 is described. FIG. 24 shows a design flow according to the present embodiment. In the design flow shown in FIG. 24, it is assumed that flip-flops in the logic area are to be repaired.

  First, in step S1, logic synthesis of a logic area including a flip-flop to be repaired is performed. In general logic synthesis, assuming that a flip-flop is converted to a scan flip-flop, synthesis is performed in consideration of a delay difference for the replacement. Therefore, when flip-flops are to be repaired as in this embodiment, it is conceivable to use the flip-flops of the redundant cells 22 shown in FIG. 21 and the like instead of the scan flip-flops. Then, it is necessary to perform logic synthesis in consideration of the delay difference for the replacement.

  Next, in step S2, a relief target group is formed by providing a redundancy relief flip-flop for the flip-flop included in the logic area for the netlist after logic synthesis. Note that the flip-flop includes a scan flip-flop.

  Next, in step S3, placement / wiring processing is performed so that the repair target group is placed as close as possible so that timing mismatch does not occur during redundancy repair. In step S3, the newly generated wiring length for the purpose of redundancy relief is also minimized.

  Next, in step S4, a normal scan test is performed on the logic circuit. In the test, failure analysis is performed on the failed cell in step S5. The type and location of the failed cell are specified by the failure analysis performed in step S5.

  In step S6, based on the type of the failed cell specified in step S5, it is determined whether or not the failed cell is a flip-flop. In other words, in step S6, if the failure cell is not a flip-flop that is a repair target, it cannot be repaired, so it is determined as a defective chip. If the fault cell is a flip-flop included in the repair target group, the repair is performed. Proceed to step S7.

  In step S7, the register connected to the control signal of the selector is fixed by writing the location of the failed cell in the flash memory as a relief program or by cutting the fuse corresponding to the location of the failed cell. The flip-flop is redundantly repaired by controlling the selector based on the register fixed in step S7 (step S8). A specific relief method in step S8 is performed using the method described in the first to thirteenth embodiments.

  As described above, by using the design flow according to the present embodiment, the flip-flops included in the logic area can be reliably relieved, so that the wafer manufacturing cost per good product can be kept low. Also, the design flow according to the present embodiment is very simple, so there is almost no overhead to TAT (Turn Around Time) of the design.

(Embodiment 16)
In step S1 of the fifteenth embodiment, in order to replace the scan flip-flop with the redundant flip-flop, it has been described that the logic synthesis is performed in consideration of the delay difference for the replacement. As described above, when logic synthesis is performed in consideration of the delay difference for replacement in advance, the speed performance of the logic circuit is slightly deteriorated.

  Therefore, in step S1 in the design flow of the present embodiment, when a scan flip-flop is replaced with a redundant relief flip-flop, a scan flip-flop having no timing margin in the replacement delay difference is replaced with a redundant relief flip-flop. By not doing so, the number of non-defective products per wafer can be increased without degrading the speed performance of the logic circuit.

  For example, FIG. 25 shows the timing slack distribution of a scan flip-flop in which the delay difference for replacement generated when replacing the scan flip-flop with a redundancy relief flip-flop is 2 ns or more, or a scan flip-flop of a certain design. In such a case, the scan flip-flop having no 2 ns timing slack is not replaced with a redundancy relief flip-flop. In the timing slack distribution shown in FIG. 25, the scan flip-flop having no 2 ns timing slack is 0.006%, and a scan flip-flop other than this scan flip-flop is replaced with a redundant relief flip-flop. .

  Since the design flow according to the present embodiment is the same as that of the fifteenth embodiment except for step S1, detailed description thereof is omitted.

  As described above, in the design flow according to the present embodiment, a timing critical scan flip-flop such as a scan flip-flop having a predetermined delay difference or a scan flip-flop having no predetermined timing slack (predetermined Therefore, the number of non-defective products per wafer can be increased without deteriorating the product performance.

1 is a schematic diagram of a semiconductor device according to a first embodiment of the present invention. 1 is a circuit diagram showing a redundant relief configuration of a semiconductor device according to a first embodiment of the present invention. FIG. It is a figure which shows the path | route of the redundant relief of the semiconductor device which concerns on Embodiment 1 of this invention. It is a figure for demonstrating the selector of the semiconductor device which concerns on Embodiment 1 of this invention. It is a circuit diagram which shows the structure of the redundant relief of the semiconductor device concerning Embodiment 2 of this invention. It is a circuit diagram which shows the structure of the redundant relief of another semiconductor device which concerns on Embodiment 2 of this invention. It is a circuit diagram which shows the structure of the redundant relief of another semiconductor device which concerns on Embodiment 2 of this invention. It is a circuit diagram which shows the structure of the redundant relief of the semiconductor device which concerns on Embodiment 3 of this invention. It is a circuit diagram which shows the structure of the redundant relief of the semiconductor device which concerns on Embodiment 4 of this invention. It is a circuit diagram which shows the structure of the redundant relief of the semiconductor device which concerns on Embodiment 5 of this invention. It is the schematic which shows the structure of the redundant relief of the semiconductor device which concerns on Embodiment 6 of this invention. It is the schematic which shows the structure of the redundant relief of the semiconductor device which concerns on Embodiment 7 of this invention. It is a circuit diagram which shows the redundant cell of the semiconductor device which concerns on Embodiment 8 of this invention. It is a circuit diagram which shows the structure of the redundant relief of the semiconductor device concerning Embodiment 10 of this invention. It is a figure which shows the path | route of the redundant relief of the semiconductor device based on Embodiment 10 of this invention. It is a circuit diagram which shows the structure of the redundant relief of the semiconductor device concerning Embodiment 11 of this invention. It is a circuit diagram which shows the structure of the redundant relief of another semiconductor device based on Embodiment 11 of this invention. It is a circuit diagram which shows the structure of the redundant relief of the semiconductor device concerning Embodiment 12 of this invention. It is a circuit diagram which shows the structure of the redundant relief of the semiconductor device concerning Embodiment 12 of this invention. It is the circuit diagram made into the hard macro which shows the structure of the redundant relief of the semiconductor device based on Embodiment 13 of this invention. It is a circuit diagram which shows the structure of the redundant relief of the semiconductor device which concerns on Embodiment 13 of this invention. It is a circuit diagram which shows the structure of the redundant relief of the semiconductor device which concerns on Embodiment 13 of this invention. FIG. 38 is a circuit layout diagram showing a redundant relief configuration of a semiconductor device according to Embodiment 14 of the present invention; It is a design flowchart of the semiconductor device concerning Embodiment 15 of this invention. It is a figure which shows the timing slack distribution of the flip-flop which comprises the semiconductor device concerning Embodiment 16 of this invention.

Explanation of symbols

  1 semiconductor device, 2 logic area, 3 memory area, 4 analog area, 5 IO area, 21 basic cell, 22 redundant cell, 23 input selector, 24 output selector, 25 rescue target group, 26 failed cell.

Claims (13)

A semiconductor device having a logic region,
A plurality of basic cells having the same configuration provided in the logic region;
A redundant cell having the same configuration as the plurality of basic cells;
An input selector that switches a signal input to each of the plurality of basic cells and the redundant cells;
An output selector that switches a signal output from each of the basic cell and the redundant cell;
A semiconductor device, wherein at least one of the input selector and the output selector is switched to function the redundant cell and to repair a failed cell among the plurality of basic cells. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the input selector and the output selector directly switch between a failed cell of the plurality of basic cells and the redundant cell to rescue. The semiconductor device according to claim 1,
The input selector and the output selector switch a failed cell out of the plurality of basic cells to an adjacent cell, and sequentially switch the switched cell to the adjacent plurality of basic cells or the redundant cell to rescue. A semiconductor device. A semiconductor device according to any one of claims 1 to 3,
A semiconductor device, wherein one of the plurality of basic cells and at least one of the input selector and the output selector connected to the cell are made into one hard macro. The semiconductor device according to claim 4,
A switching selector for switching between data input and scan input;
A semiconductor device characterized in that the switching selector is also made into one hard macro. A semiconductor device according to any one of claims 1 to 5,
A semiconductor device, wherein the plurality of basic cells and the redundant cells having the same configuration are arrayed, and the input selector and the output selector are arranged in the vicinity of the array. The semiconductor device according to claim 6,
A semiconductor device, wherein the array is multiplexed and wirings to the input selector and the output selector are shared. A semiconductor device according to any one of claims 1 to 7,
Further comprising a switch between at least one of the plurality of basic cells and the redundant cell and a power source,
A semiconductor device characterized in that the power is turned off by turning off at least one of the failed cells among the plurality of basic cells and the redundant cells not necessary for repair. A semiconductor device according to any one of claims 1 to 8,
The semiconductor device, wherein the plurality of basic cells and the redundant cells are a macro cell, an arithmetic unit, a logic cone, and a macro block. A semiconductor device according to any one of claims 1 to 9,
The semiconductor device, wherein the input selector includes a configuration for supplying the same signal to each of a plurality of basic cells and the redundant cells. A semiconductor device according to any one of claims 1 to 10,
The design rule applied to the redundant cell or the plurality of basic cells to be repaired of the redundant cell is relaxed compared to the design rule applied to other parts in the logic region. Semiconductor device. A semiconductor device according to any one of claims 1 to 11,
2. The semiconductor device according to claim 1, wherein the redundant cell is arranged in the vicinity of the plurality of basic cells to be repaired by the redundant cell. A semiconductor device according to any one of claims 1 to 12,
The semiconductor device according to claim 1, wherein only the basic cells other than a predetermined timing condition among the plurality of basic cells are to be repaired.

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