JP2006173542A - Automatic design method of semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the degree of freedom at the time of designing of a semiconductor integrated circuit in its entirety in a method of automatic design of the integrated circuit having a macro block. <P>SOLUTION: A lower layer power source wire 11 and a lower layer grounding wire 12 are arranged on a hard macro 10 which is the macro block of the semiconductor integrated circuit by using the lowermost wiring layer of several wiring layers constituting the semiconductor integrated circuit. Then upper layer power source wires 41 and 51 and upper layer grounding wires 42 and 52 which come into contact with the lower layer power source wire 11 and the lower layer grounding wire 12 are arranged along the edges of the hard macro 10 by using either of the several wiring layers except the lowermost layer. Then a cell 10C is arranged in a region surrounded by the upper layer power source wires 41 and 51 and the upper layer grounding wires 42 and 52 of the hard macro 10. Then ports 20 are arranged at an edge of the hard macro 10 by using either of the wiring layers except the lowermost layer of the several wiring layers and the wiring layers of the upper layer power source wires 41 and 51 and the upper layer grounding wires 42 and 52. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an automatic design method for a semiconductor integrated circuit, and more particularly to an automatic design method for a macro block of a semiconductor integrated circuit in which a plurality of wiring layers are stacked.

  In recent years, with the miniaturization and multifunctionalization of mobile phones and digital cameras, semiconductor integrated circuits mounted on them have been highly integrated and multi-layered. As such a semiconductor integrated circuit, a system large scale integration (LSI) having a plurality of functional blocks on the same semiconductor chip is known.

  Highly integrated and multi-layered semiconductor integrated circuits such as system LSIs are designed through automatic design by a CAD (Computer Aided Design) system using an electronic computer, that is, functional design, logical design, layout design, etc. The In the function design, a desired semiconductor integrated circuit function is specified by a hardware description language, and in the logic design, logic circuit data is generated by performing logic synthesis so as to realize the function specified in the function design. In layout design, a logic circuit is laid out on a semiconductor chip based on logic circuit data logically synthesized in the logic design.

  In the layout design, for the purpose of shortening the design period, a hard macro (Hard Macro), which is a macro block of the semiconductor integrated circuit, is designed, and the hard macro is arranged in the semiconductor integrated circuit as necessary. . Since the hard macro has been adjusted for the layout and the timing for the signal delay, it is not necessary to optimize the layout and timing again after the hard macro is arranged in the semiconductor integrated circuit. Therefore, the design period of the semiconductor integrated circuit can be shortened.

  Next, the outline of the hard macro designed in the layout design of the automatic design of the semiconductor integrated circuit according to the conventional example will be described with reference to the drawings. FIG. 3 is a plan view for explaining an automatic design method of a semiconductor integrated circuit according to a conventional example. The finally designed semiconductor integrated circuit has a multilayer structure composed of a plurality of wiring layers, and the hard macro designed here has the same multilayer wiring structure. For example, the plurality of wiring layers are assumed to be five layers, and each wiring layer is referred to as a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer.

  As shown in FIG. 3, the lower layer power line 211 and the lower layer ground line 212 are arranged in the hard macro 210 using the first metal layer. A port 220 using the first metal layer is disposed at the end of the hard macro 210. The port 220 is an external input / output wiring that connects the inside and the outside of the hard macro 210.

  Further, upper power supply lines 241 and 251 and upper layer ground lines 242 and 252 using, for example, a fourth metal layer and a fifth metal layer are arranged along the end portion of the hard macro 210. The fourth metal layer and the fifth metal layer constituting the upper power supply lines 241 and 251 are connected via the contact CT so that they have the same potential. Similarly, the fourth metal layer and the fifth metal layer constituting the upper layer ground lines 242 and 252 are connected via the contact CT.

  Further, the lower layer power line 211 and the upper layer power lines 241 and 251 are connected via the contact CT so that they have the same potential. Similarly, the ground line 212 and the upper layer ground lines 242 and 252 are connected via a contact CT. In the region of the hard macro 210 surrounded by the upper layer power supply lines 241 and 251 and the upper layer ground lines 242 and 252, one or more cells 210 </ b> C are arranged.

In addition, as a related technical document, the following patent documents are mentioned, for example.
Japanese Patent Laid-Open No. 2004-288685

  In the design of the hard macro 210 as described above, a new cell using the first metal layer is added to the end of the hard macro 210, that is, below the upper power supply lines 241 and 251 and the upper ground lines 242 and 252. May be placed. This new cell is a cell required when the hard macro 210 is arranged on the semiconductor integrated circuit according to the use of the semiconductor integrated circuit.

  However, in the automatic design method for a semiconductor integrated circuit according to the conventional example, since the port 220 is formed at the end of the hard macro 210 using the first metal layer, the first metal layer is used at that location. It has been extremely difficult to add and arrange new cells. Alternatively, the number of new cells that can be placed at the location is limited. That is, the degree of freedom in designing the entire semiconductor integrated circuit using the hard macro 210 is limited.

  Therefore, the present invention aims to improve the degree of freedom in designing the entire semiconductor integrated circuit using the block in the method of automatically designing a semiconductor integrated circuit having a hard macro, that is, a macroized block.

  An automatic design method for a semiconductor integrated circuit according to the present invention has been made in view of the above-described problems, and is an automatic design method for a macro block of a semiconductor integrated circuit formed by laminating a plurality of wiring layers. , Has the following characteristics.

  That is, in the method for automatically designing a semiconductor integrated circuit according to the present invention, a step of arranging a first power line and a ground line in the block using a lowermost wiring layer of a plurality of wiring layers, and an end of the block Arranging a second power supply line and a ground line in contact with the first power supply line and the ground line using any one of the wiring layers excluding the lowermost layer among the plurality of wiring layers along the portion; A step of disposing a first cell in a region surrounded by a second power line and a ground line of the block; and a lowermost layer of the plurality of wiring layers, and a second power line and a ground at an end of the block And arranging an external input / output wiring by using any wiring layer other than the wiring layer of the line.

  In addition to the above steps, the method for automatically designing a semiconductor integrated circuit according to the present invention uses the lowermost layer of the plurality of wiring layers at the end of the block corresponding to the lower part of the second power supply line and the ground line. The second cell is arranged. Here, the second cell is, for example, a bypass capacitor cell in which a capacitor configuration circuit is inserted between the first power supply line and the ground line.

  According to the semiconductor integrated circuit automatic design method of the present invention, the external input / output wiring (that is, the port) forms the semiconductor integrated circuit at the end of the macro block (that is, the hard macro) of the semiconductor integrated circuit. The wiring layers are arranged using any wiring layer except the lowest layer (that is, the first metal layer) among the plurality of wiring layers. Therefore, a new cell using the lowermost wiring layer can be added and arranged at the location. In addition, the number of the new cells that can be arranged at the location can be increased. That is, the degree of freedom in designing the entire semiconductor integrated circuit using the macro-ized block of the semiconductor integrated circuit is improved.

  Next, a method for automatically designing a semiconductor integrated circuit according to an embodiment of the present invention will be described. The automatic design method of this embodiment is an automatic design method of a macro block of a semiconductor integrated circuit, that is, a hard macro. The automatic design method according to the present embodiment is an automatic layout design method after function design and logic design. Functional design and logical design are performed in the same manner as in the conventional example. Also, the semiconductor integrated circuit automatic design method according to the embodiment of the present invention is performed by a CAD (Computer Aided Design) system using an electronic computer.

  In addition, a macro block designed by the semiconductor integrated circuit automatic design method according to the present embodiment, that is, a hard macro, has a multilayer wiring structure in which a plurality of wiring layers are stacked on a semiconductor chip. In the present embodiment, for example, the plurality of wiring layers are assumed to be five layers, and each wiring layer is referred to as a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer. To.

  Next, a method for automatically designing a semiconductor integrated circuit according to the present embodiment will be described with reference to the drawings. FIG. 1 is a plan view for explaining an automatic design method for a semiconductor integrated circuit according to the present embodiment. FIG. 1 schematically shows a planar layout of a macro block of a semiconductor integrated circuit automatically designed by a CAD system, that is, a hard macro. FIG. 2 is a conceptual diagram illustrating a bypass capacitor cell arranged in a hard macro designed by the semiconductor integrated circuit automatic design method of the present embodiment.

  First, although not shown in the figure, a database comprising cell pattern information (a circuit group data group of each cell) which is a unit block of a circuit constituting a semiconductor integrated circuit, that is, a cell library, and a connection relation between the cells. A database consisting of the circuit connection information shown, that is, a net list is prepared. Then, circuit pattern information and circuit connection information are read from the cell library and net list.

  As shown in FIG. 1, the lower layer power line 11 and the lower layer ground line 12, which are the power line and the ground line of the semiconductor integrated circuit, are preferably parallel to a predetermined position of the hard macro 10 using the first metal layer. To place.

  Next, the upper power supply line 41 using the fourth metal layer and the upper power supply line 51 using the fifth metal layer are arranged along the end of the hard macro 10 so as to go around the end. . At the intersection of the fourth metal layer and the fifth metal layer constituting the upper power supply lines 41 and 51, a contact CT for connecting these layers so as to have the same potential is disposed. Thus, the upper power supply lines 41 and 51 are arranged in a ring shape on the hard macro 10.

  Further, along the end portion of the hard macro 10, an upper layer ground line 42 using the fourth metal layer and an upper layer ground line 52 using the fifth metal layer are disposed adjacent to the upper layer power supply lines 41 and 51. . At the intersection of the fourth metal layer and the fifth metal layer constituting the upper ground lines 42 and 52, a contact CT for connecting these layers so as to have the same potential is disposed. Thus, the upper layer ground wires 42 and 52 are arranged in a ring shape on the hard macro 10.

  Furthermore, at the intersection of the first metal layer constituting the lower layer power supply line 11 and the fourth metal layer or the fifth metal layer constituting the upper layer power supply lines 41 and 51, these layers are connected to have the same potential. The contact CT to be arranged is arranged. Similarly, at the intersection of the first metal layer constituting the lower layer ground line 12 and the fourth metal layer or the fifth metal layer constituting the upper layer ground lines 42 and 52, these layers are set to the same potential. A contact CT to be connected is arranged.

  The upper layer power supply lines 41 and 51 and the upper layer ground lines 42 and 52 may be arranged using wirings other than the fourth metal layer and the fifth metal layer. That is, the upper layer power supply lines 41 and 51 and the upper layer ground lines 42 and 52 are arranged by using any one of the plurality of wiring layers constituting the semiconductor integrated circuit (that is, the hard macro 10) except for the lowest layer. May be.

  Next, based on the circuit pattern information read from a cell library (not shown) in a predetermined area of the hard macro 10 surrounded by the upper layer power supply lines 41 and 51 and the upper layer ground lines 42 and 52 arranged in a ring shape, One or a plurality of cells 10C are arranged. The cell 10C is, for example, a memory cell, a standard cell that is a unit block of a logic circuit including a standardized basic logic gate or a combination thereof.

  Next, at the end of the hard macro 10, a port is formed using any of the wiring layers except the lowermost layer of the plurality of wiring layers and the wiring layers of the upper power supply lines 41 and 51 and the upper ground lines 42 and 52. 20 is arranged. That is, in the present embodiment, the port 20 is disposed at the end of the hard macro 10 located below the upper power supply lines 41 and 51 and the upper ground lines 42 and 52 using the second metal layer or the third metal layer. Is done. One end of the port 20 is connected to the cell 10C. The other end of the port 20 is used for input / output with the outside of the hard macro 10.

  When there are more than five wiring layers constituting the semiconductor integrated circuit, the port 20 is arranged using a wiring layer of a second metal layer or more, preferably a third metal layer or more. However, the wiring layer used for the upper layer power line and the upper layer ground line is excluded.

  In this way, by arranging the port 20 without using the lowermost layer among the plurality of wiring layers, that is, the first metal layer, in the plurality of wiring layers as seen in the conventional example. The lowermost layer, that is, the region occupied by the port using the first metal layer can be used for wiring or cell arrangement other than the port.

  Next, a new cell using the lowermost layer, that is, the first metal layer is disposed at the end of the hard macro 10 corresponding to the lower layer of the upper layer power supply lines 41 and 51 and the upper layer ground lines 42 and 52.

  Here, the new cell using the first metal layer is a cell required when the hard macro 10 is arranged on the semiconductor integrated circuit in accordance with the application of the semiconductor integrated circuit. In the present embodiment, although not particularly limited, for example, the bypass capacitor cell 70 is disposed using the first metal layer. As shown in the conceptual diagram of FIG. 2, the bypass capacitor cell 70 is a cell in which a predetermined capacitance configuration circuit 80 is inserted between the first metal layers constituting the lower layer power line 11 and the lower layer ground line 12. Have.

  The predetermined capacitance configuration circuit is formed, for example, by disposing a polysilicon layer between the lower layer power line 11 and a semiconductor substrate (not shown) and between the lower layer ground line 12 and a semiconductor substrate (not shown). The capacitor 90 is formed between the lower layer power line 11 and the lower layer ground line 12.

  Next, based on the circuit connection information read from the net list (not shown), the lower layer power line 11 and the lower layer ground line 12, the upper layer power lines 41 and 51 and the upper layer ground lines 42 and 52, or the port 20 and the cell 10C Wirings (not shown) that connect the two are arranged. In addition, when there are a plurality of cells 10C, wiring (not shown) for connecting the cells to be connected to each other is arranged. Thereafter, after adjusting a predetermined layout, adjusting a signal delay timing, and the like, the layout is determined.

  As described above, according to the automatic design method for a semiconductor integrated circuit of the present invention, the plurality of wiring layers are formed at the end portions of the hard macro 10 corresponding to the lower portions of the upper power supply lines 41 and 51 and the upper layer ground lines 42 and 52. It is possible to easily add and arrange a new cell using the lowermost layer, that is, the first metal layer. In addition, the number of new cells using the first metal layer that can be arranged in the place can be increased as compared with the conventional example. That is, the degree of freedom in designing the entire semiconductor integrated circuit using the hard macro 10, that is, the macroized block of the semiconductor integrated circuit is improved.

It is a top view explaining the automatic design method of the semiconductor integrated circuit which concerns on embodiment of this invention. It is a conceptual diagram explaining a bypass capacitor cell. It is a top view explaining the automatic design method of the semiconductor integrated circuit concerning a prior art example.

Explanation of symbols

10, 210 Hard macro 10C, 210C Cell 11, 211 Lower layer power line 12, 212 Lower layer ground line 20, 220 Port 41, 51, 241, 251 Upper layer power line 42, 52, 242, 252 Upper layer ground line 70 Bypass capacitor cell 80 Capacitance configuration circuit 90 Capacitance CT contact

Claims (3)

A method for automatically designing a macro block of a semiconductor integrated circuit in which a plurality of wiring layers are laminated,
Disposing a first power line and a ground line in the block using a lowermost wiring layer of the plurality of wiring layers;
A second power supply line and a ground line that are in contact with the first power supply line and the ground line by using any one of the wiring layers except for the lowest layer among the plurality of wiring layers along the end of the block. Placing a step;
Disposing a first cell in a region surrounded by the second power line and ground line of the block;
A step of arranging an external input / output wiring at one end of the block using any wiring layer other than a lowermost layer of the plurality of wiring layers and a wiring layer of the second power supply line and the ground line; And a method for automatically designing a semiconductor integrated circuit. 2. The second cell is disposed at an end portion of the block corresponding to a lower side of the second power supply line and the ground line by using a lowermost layer among the plurality of wiring layers. Method for automatically designing semiconductor integrated circuits. 3. The method of automatically designing a semiconductor integrated circuit according to claim 2, wherein the second cell is a bypass capacitor cell in which a capacitor circuit is inserted between the first power supply line and the ground line.

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