JP2006165085A - Method of automatically designing semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of automatically designing semiconductor integrated circuit by which the time required for design can be shortened to the utmost. <P>SOLUTION: In the method of automatically designing a semiconductor integrated circuit constituted by laminating a plurality of wiring layers upon another, an I/O cell 11, a memory cell 12, and a standard cell 13 are arranged on a semiconductor chip 10. Then, before arranging wiring among the cells 11, 12, and 13 to be connected to each other, dummy cells 14 using some wiring layer of the plurality of wiring layers constituting the semiconductor integrated circuit except the lowest wiring layer are arranged among the cells 11, 12, and 13. Thereafter, a plurality of wiring 15 is arranged by using different wiring layers by arranging the wiring 15 through the dummy cells 14. When the wiring 15 is arranged in this way, the distance between parallelly adjacent wiring 15 in a plane of the same wiring layer can be shortened to the utmost. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an automatic design method for a semiconductor integrated circuit, and more particularly to an automatic design method for a semiconductor integrated circuit in which cells and wirings are arranged on a semiconductor chip.

  In recent years, with the increase in the scale of semiconductor integrated circuits such as those found in LSI (Large Scale Integration), the tendency of higher density and multilayering of cells and wirings constituting the semiconductor integrated circuits is increasing. Such a semiconductor integrated circuit is designed through automatic design by a CAD (Computer Aided Design) system using an electronic computer, that is, functional design, logical design, layout design, and the like. In the function design, a desired semiconductor integrated circuit function is specified by a hardware description language, and in the logic design, logic circuit data is generated by performing logic synthesis so as to realize the function specified in the function design. In layout design, a logic circuit is laid out on a semiconductor chip based on logic circuit data logically synthesized in the logic design.

  Next, an outline of an example of a conventional layout design in an automatic design method of a semiconductor integrated circuit using an electronic computer will be described with reference to the drawings. FIG. 4 is a flowchart for explaining an automatic designing method of a semiconductor integrated circuit according to a conventional example. As shown in FIG. 4, first, a cell library which is a database composed of circuit pattern information (circuit pattern data group of each cell) of cells constituting a semiconductor integrated circuit (unit blocks of circuits constituting the semiconductor integrated circuit) And a net list which is a database composed of circuit connection information between the cells.

  In step B1, circuit pattern information and circuit connection information are read from the cell library and netlist. Next, in step B2, a plurality of cells are arranged in a predetermined region of the semiconductor chip based on the read circuit pattern information. In step B3, wiring is arranged so as to connect the cells based on the circuit connection information.

  Next, in step B4, the wiring length of the wiring is adjusted to a predetermined length or less so that the so-called process antenna effect does not occur in the wiring connected to the gate electrode constituting the transistor in a certain cell. To do.

  Here, the process antenna effect means that when a wiring connected to a gate electrode constituting a transistor has a long wiring length, charges are accumulated in the gate electrode through the wiring in, for example, an etching process when manufacturing a semiconductor integrated circuit. This is a phenomenon in which the dielectric breakdown of the gate insulating film occurs due to the charge.

  Further, in step B5, signal integrity (Signal Integrity), which is signal timing integrity in the semiconductor integrated circuit, is analyzed. If the desired signal consistency cannot be obtained, the wiring is adjusted (moving the arrangement position, etc.) in step B6. If the desired signal consistency cannot be obtained despite the adjustment of the wiring, a buffer for adjusting the delay time of the signal is inserted into the wiring.

  Such signal integrity analysis and buffer insertion for adjusting the wiring and signal delay time, that is, step B5 and step B6 are repeated until the desired signal integrity is obtained.

  Next, an outline of a planar layout of a semiconductor integrated circuit designed by the above-described conventional semiconductor integrated circuit automatic design method will be described with reference to the drawings. FIG. 5 is a schematic plan view of a semiconductor integrated circuit designed by a conventional semiconductor integrated circuit automatic design method.

  As shown in FIG. 5, an I / O (Input / Output) cell 21, which is an input / output port, is disposed at the end of the semiconductor chip 20. A plurality of memory cells 22 and standard cells 23 are arranged in a predetermined region of the semiconductor chip 20. Here, the standard cell 23 is a unit block of a logic circuit composed of standardized basic logic gates and combinations thereof. And wiring 25 which connects them between each above-mentioned cell is arranged. In addition, a NAND circuit, a NOR circuit, an FF circuit, a buffer 26, and the like that form logic in the standard cell region are arranged at one end of the wiring connected to the standard cell 23.

In addition, as a related technical document, the following patent documents are mentioned, for example.
Japanese Patent Laid-Open No. 2004-288685

  However, according to the semiconductor integrated circuit automatic design method according to the conventional example described above, when the density of the semiconductor integrated circuit is increased, the interval in which the adjacent wirings 25 are arranged in parallel with each other at a narrow interval becomes long. was there. In this case, as shown in FIG. 5, as the section of the wirings arranged in parallel with each other becomes longer, a larger parasitic capacitance 30 exists between the adjacent wirings. The parasitic capacitance 30 induces a voltage change, that is, crosstalk, that causes distortion of a signal propagating through the wiring between the adjacent wirings. This crosstalk causes a logic error and an increase in signal delay time, leading to deterioration in signal integrity and malfunction of the semiconductor integrated circuit.

  In order to eliminate the degradation of the signal integrity of the semiconductor integrated circuit, etc., the signal integrity of the designed semiconductor integrated circuit is analyzed using a dedicated analysis tool, and the distance between the wirings where the crosstalk is caused is determined. The layout of the wiring is adjusted so as to increase. Alternatively, the buffer 26 for adjusting the delay time of the signal is arranged. In order to perform such signal consistency analysis and wiring adjustment, as a result, there has been a problem that the time required for designing a semiconductor integrated circuit increases.

  Therefore, the present invention provides a method for automatically designing a semiconductor integrated circuit in which the time spent for designing is shortened as much as possible.

  An automatic design method for a semiconductor integrated circuit according to the present invention has been made in view of the above-mentioned problems, and is an automatic design method for a semiconductor integrated circuit in which a plurality of wiring layers are stacked, and has the following characteristics. . That is, in the semiconductor integrated circuit automatic design method of the present invention, the lowermost layer in the plurality of wiring layers is removed between the step of arranging the plurality of cells constituting the semiconductor integrated circuit and the cells to be connected to each other. A dummy cell having any wiring layer, an input terminal, and an output terminal is arranged, and the cells are connected via the input terminal and the output terminal of the dummy cell arranged between the cells to be connected to each other. Thus, the method includes a step of arranging a wiring using a wiring layer in the same layer as the wiring layer in which the dummy cell is arranged.

  Further, in the method for automatically designing a semiconductor integrated circuit according to the present invention, after the step of arranging the wiring, the step of erasing the dummy cell and the two terminals of the wiring connected to the input terminal and the output terminal of the dummy cell are short-circuited. Rewiring processing, and adjusting the wiring length so that the wiring length between cells of the rewiring processing is less than a predetermined length not affected by the process antenna effect; It is characterized by including.

  Here, the step of disposing the dummy cell includes a step of randomly selecting any one of the wiring layers excluding the lowermost layer among the plurality of wiring layers, a step of disposing a dummy cell using the selected wiring layer, including.

  Alternatively, the step of arranging the dummy cells includes a step of predicting wiring connecting between cells to be connected to each other, and a step of arranging a plurality of wiring layers so that wirings scheduled to be adjacent in plan are different from each other. A step of selecting one of the wiring layers excluding the lowermost layer, and a step of arranging a dummy cell using the selected wiring layer.

  Furthermore, the method for automatically designing a semiconductor integrated circuit according to the present invention includes a step of acquiring connection information indicating a connection relationship between the dummy cell and the plurality of cells before arranging the dummy cell.

  According to the semiconductor integrated circuit automatic design method of the present invention, before arranging wiring between cells to be connected to each other, the lowermost layer among the plurality of wiring layers constituting the semiconductor integrated circuit is arranged between the cells. A dummy cell using any one of the wiring layers except for was placed. Then, by arranging the wiring via this dummy cell, a plurality of wirings are arranged using different wiring layers.

  Thereby, the distance at which the wirings of the same wiring layer are arranged adjacent to each other in parallel is shortened as compared with the conventional example. That is, it is possible to suppress the parasitic capacitance as small as possible between the wirings adjacent in parallel as in the conventional example. Therefore, it is possible to suppress the crosstalk between the wirings due to the parasitic capacitance as compared with the conventional example. Accordingly, the time required to eliminate the signal integrity degradation due to crosstalk is shortened compared to the conventional example. As a result, the time spent for the automatic design of the semiconductor integrated circuit can be reduced as much as possible.

  Next, a method for automatically designing a semiconductor integrated circuit according to an embodiment of the present invention will be described. The automatic design method of this embodiment is an automatic layout design method after function design and logic design. Functional design and logical design are performed in the same manner as in the conventional example. Also, the semiconductor integrated circuit automatic design method according to the embodiment of the present invention is performed by a CAD (Computer Aided Design) system using an electronic computer. The semiconductor integrated circuit designed by the semiconductor integrated circuit automatic design method according to the present embodiment has a multilayer wiring structure in which a plurality of wiring layers are stacked on a semiconductor chip.

  Next, a method for automatically designing a semiconductor integrated circuit according to the present embodiment will be described with reference to the drawings. FIG. 1 is a flowchart illustrating an automatic design method for a semiconductor integrated circuit according to this embodiment. 2 and 3 are schematic plan views for explaining an automatic design method of a semiconductor integrated circuit according to the embodiment of the present invention. 2 and 3 schematically show a layout on a semiconductor chip automatically designed by a CAD system.

  First, as shown in FIG. 1, a database consisting of circuit pattern information (a data group of circuit patterns of each cell) which is a unit block of a circuit constituting a semiconductor integrated circuit, that is, a cell library, and between the cells. A database consisting of circuit connection information, that is, a net list is prepared.

  Then, as shown in FIGS. 1 and 2, in step A1, circuit pattern information and circuit connection information are read from the cell library and net list. Next, in step A2, a plurality of cells are arranged in a predetermined region of the semiconductor chip based on the read circuit pattern information. That is, an I / O (Input / Output) cell 11 that is an input / output port is disposed at the end of the semiconductor chip 10.

  A plurality of memory cells 12 and standard cells 13 are arranged in a predetermined region of the semiconductor chip 10. Here, the standard cell 13 is a unit block of a logic circuit composed of standardized basic logic gates and combinations thereof. The standard cell 13 includes an electronic element such as a transistor (not shown). In FIG. 2, it is assumed that a plurality of standard cells 13 are arranged in a predetermined standard cell region.

  Next, in step A3, dummy cells are arranged between cells that are to be connected to each other. That is, a dummy cell 14 having no logic function is arranged between the I / O cell 11 and the standard cell 13 and between the memory cell 12 and the standard cell 13. The dummy cell 14 has an input terminal 14A and an output terminal 14B, and is arranged using any wiring layer except for the lowest layer among a plurality of wiring layers constituting the semiconductor chip 10 having a multilayer wiring structure. For example, when the semiconductor integrated circuit has a multilayer structure composed of five wiring layers, the dummy cells 14 are arranged using any one of the second and higher wiring layers.

  Here, the step A3 of arranging the dummy cell 14 is performed through the following steps. That is, first, any wiring layer excluding the lowermost layer among the plurality of wiring layers constituting the semiconductor chip 10 having the multilayer wiring structure is selected at random. Thereafter, dummy cells 14 using the selected wiring layer are arranged. Thus, the plurality of dummy cells 14 are arranged using different wiring layers.

  Or step A3 which arrange | positions the said dummy cell 14 may be performed through the step shown next. That is, first, the layout of wirings connecting between cells to be connected to each other (between the I / O cell 11 and the standard cell 13 or between the memory cell 12 and the standard cell 13) is predicted. Then, one of the wiring layers excluding the lowermost layer among the plurality of wiring layers is selected so that the wirings scheduled to be arranged adjacent to each other are different from each other. Thereafter, dummy cells 14 using the selected wiring layer are arranged. Thus, the plurality of dummy cells 14 are arranged using different wiring layers.

  In addition, before the dummy cell 14 is arranged, a step of adding the circuit connection information read in step A1 to the dummy cell 14, the I / O cell 11, the memory cell 12, and the standard cell 13 is included.

  Next, in step A4, based on the circuit connection information, wiring is arranged so as to connect cells that are to be connected to each other. That is, the wiring 15 is disposed between the I / O cell 11 and the standard cell 13 and between the memory cell 12 and the standard cell 13. Here, the wiring 15 connects the cells via the dummy cell 14 arranged in step A3 (once it is input to the input terminal 14A of the dummy cell 14 and then output from the output terminal 14B). Arranged. That is, the wiring 15 that connects the cells is arranged using a wiring layer that is the same layer as the wiring layer constituting the dummy cell 14. Note that the lowest layer among the plurality of wiring layers constituting the semiconductor chip 10, that is, the first wiring layer is used as a power supply line of a semiconductor integrated circuit, for example.

  With such an arrangement of the wirings 15, the wirings 15 arranged adjacent to each other in plan are arranged using wiring layers that are as different as possible. In other words, the distance at which the wires 15 using the same wiring layer are arranged adjacent to each other in parallel is shortened as compared with the conventional example. That is, it is possible to suppress the parasitic capacitance as small as possible between wirings arranged adjacent to each other in parallel as in the conventional example. Therefore, it is possible to suppress the crosstalk between the wirings due to the parasitic capacitance as compared with the conventional example. Accordingly, the time required to eliminate the signal integrity degradation due to crosstalk is shortened compared to the conventional example. As a result, the time spent for the automatic design of the semiconductor integrated circuit can be reduced as much as possible.

  Further, the wiring length of the wiring 15 is not more than a predetermined length so that the so-called process antenna effect does not occur in the wiring 15 connected to a gate electrode (not shown) constituting a transistor (not shown) in a certain standard cell 13. Adjust so that

  Here, the process antenna effect means that when the wiring 15 connected to the gate electrode constituting the transistor has a long wiring length, the gate electrode is charged through the wiring 15 in, for example, an etching process when manufacturing a semiconductor integrated circuit. Is accumulated, and the electric breakdown causes breakdown of the gate insulating film.

  However, when adjusting the wiring length of the wiring 15 to be a predetermined length or less so that the process antenna effect does not occur, the CAD system uses an algorithm for detecting the length of the wiring connecting the cells. Therefore, the length of the wiring connecting the dummy cell 14 and the standard cell 13 is detected. Therefore, the adjustment of the wiring length to cope with the process antenna effect without detecting the length of the wiring from a certain cell to the gate electrode constituting the transistor (not shown) in the standard cell 13 that should be detected. Is not done accurately.

  Therefore, in the present invention, the wiring length adjusted to deal with the process antenna effect is performed through the following steps on the wiring 15 arranged by the above-described steps. That is, as shown in FIGS. 1 and 3, in step A5, the dummy cell 14 arranged in step A3 is removed.

  Next, in step A6, rewiring processing is performed so as to short-circuit the connection points 15A and 15B of the wiring 15 connected to the input terminal 14A and the output terminal 14B of the dummy cell 14. That is, the rewiring 17 is disposed between the connection points 15A and 15B of the wiring 15.

  In step A7, the wiring length is adjusted for the wiring 15 including the rewiring 17 to cope with the process antenna effect. That is, by the rewiring process, the length of a wiring from a certain cell to a gate electrode constituting a transistor (not shown) in the standard cell 13 is normally detected, and the wiring length for dealing with the process antenna effect is detected. Adjustment is performed normally.

  Furthermore, the following steps may be added. That is, in step A8, signal consistency in the semiconductor integrated circuit is analyzed. If the desired signal consistency cannot be obtained, the wiring 15 is adjusted (such as moving the arrangement position) in step A9. If the desired signal consistency cannot be obtained despite the adjustment of the wiring 15, a buffer 16 for adjusting the delay time of the signal is inserted into the wiring 15.

  Such signal consistency analysis, wiring adjustment and buffer insertion, that is, Step A8 and Step A9 are repeated until the desired signal consistency is obtained.

  Here, in the present invention, as described above, the crosstalk is suppressed to be lower than that of the conventional example. For this reason, it is possible to minimize the number of repetitions of the signal matching analysis, the wiring adjustment and the buffer insertion, that is, the loop processing composed of step A8 and step A9, as compared with the conventional example. As a result, the time spent for the automatic design of the semiconductor integrated circuit can be reduced as much as possible.

It is a flowchart explaining the automatic design method of the semiconductor integrated circuit which concerns on embodiment of this invention. 1 is a schematic plan view illustrating an automatic design method for a semiconductor integrated circuit according to an embodiment of the present invention. 1 is a schematic plan view illustrating an automatic design method for a semiconductor integrated circuit according to an embodiment of the present invention. It is a flowchart explaining the automatic design method of a semiconductor integrated circuit. It is a schematic plan view of a semiconductor integrated circuit designed by an automatic designing method for a semiconductor integrated circuit according to a conventional example.

Explanation of symbols

10, 20 Semiconductor chip 11, 21 I / O cell 12, 22 Memory cell 13, 23 Standard cell 14 Dummy cell 14A Input terminal 14B Output terminal 15 Wiring 15A, 15B Connection point 17 Rewiring 26 Buffer 30 Parasitic capacitance

Claims (5)

An automatic design method of a semiconductor integrated circuit formed by laminating a plurality of wiring layers,
Disposing a plurality of cells constituting the semiconductor integrated circuit;
Arranging a dummy cell having any wiring layer except the lowest layer of the plurality of wiring layers, an input terminal, and an output terminal between cells to be connected to each other;
Wiring in the same layer as the wiring layer in which the dummy cells are arranged so as to connect the cells via the input terminal and the output terminal of the dummy cells arranged between the cells to be connected to each other A method of automatically designing a semiconductor integrated circuit, comprising: arranging a wiring using a layer. After placing the wiring,
Erasing the dummy cell;
Rewiring process to short-circuit the two terminals of the wiring connected to the input terminal and the output terminal of the dummy cell;
Adjusting the wiring length so that the wiring length between the cells of the wiring subjected to rewiring processing is not more than a predetermined length not affected by the process antenna effect. 2. A method for automatically designing a semiconductor integrated circuit according to claim 1. The step of arranging the dummy cells includes:
Randomly selecting any wiring layer except the lowest layer among the plurality of wiring layers;
2. The method for automatically designing a semiconductor integrated circuit according to claim 1, further comprising the step of arranging a dummy cell using the selected wiring layer. The step of arranging the dummy cells includes:
Predicting wiring connecting the cells that are to be connected to each other;
Selecting one of the wiring layers excluding the lowermost layer of the plurality of wiring layers so that the wirings scheduled to be adjacent in a plane are different from each other;
2. The method for automatically designing a semiconductor integrated circuit according to claim 1, further comprising the step of arranging a dummy cell using the selected wiring layer. 2. The method for automatically designing a semiconductor integrated circuit according to claim 1, further comprising the step of obtaining connection information indicating a connection relationship between the dummy cell and the plurality of cells before arranging the dummy cell.

Images