JP2006173144A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is highly reliable by using a protective diode so as not to degrade the characteristic of the semiconductor device, as well as to prevent the occurrence of plasma charging damage in the plasma process of a wiring formation step. <P>SOLUTION: A semiconductor element having a gate insulating film 6 and a gate electrode 7 is formed on a semiconductor substrate 1, and a first wiring 16A connected electrically with the gate electrode 7 and a second wiring 16B connected electrically with the semiconductor substrate 1 are formed at any space in a second interlayer insulating film 14 formed on the semiconductor element. The upper layer of the second interlayer insulating film 14 is formed of a silicon nitride film 13, which is an insulator displaying conductivity in a plasma atmosphere. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device that is not easily damaged in a plasma process during manufacturing, and a manufacturing method thereof.

  In recent years, high integration in semiconductor integrated circuit devices has greatly advanced, and in order to cope with high integration, elements such as transistors have been miniaturized and high performance has been achieved, and the thickness of the gate insulating film has been reduced. Tend to be. On the other hand, with the miniaturization of elements, a plasma process for performing processing in a plasma atmosphere is also frequently used in the wiring process. In addition, with the increase in performance of elements, the introduction of copper (Cu) wiring is progressing, and with the introduction of Cu wiring, a plasma process is increasingly used in the wiring process.

  As described above, the gate insulating film is thinned and the plasma process is frequently used in the wiring process, so that plasma charge damage, which is a device damage due to plasma, has become obvious and has been greatly closed up. (For example, see Non-Patent Document 1).

  Due to the plasma charging damage, various defects with deterioration of device characteristics occur, and in particular, deterioration of the reliability of the gate insulating film is a serious problem. For example, a conductive part such as a wiring exposed on the surface of a semiconductor device being formed in a plasma atmosphere serves as an antenna, and captures charged particles such as ions and electrons in the plasma. The charges trapped in the conductive portion are accumulated in the gate electrode through the wiring, and an electric field is generated in the gate insulating film provided between the gate electrode and the semiconductor substrate. When this electric field exceeds a certain level, a current flows through the gate insulating film, which causes deterioration of the gate insulating film.

  In a copper (Cu) wiring process using a damascene structure, a tantalum (Ta) / tantalum nitride (TaN) film is used as a barrier film in order to improve adhesion between Cu and an interlayer insulating film or an inter-wiring insulating film. It has been. Since the Ta / TaN film is formed by plasma, charging damage is likely to occur. (For example, refer nonpatent literature 2.).

  In order to prevent such deterioration of the gate insulating film due to charging damage, a method using a bypass protective diode is known. Hereinafter, an example of a method for reducing plasma charging damage using a conventional protection diode will be described.

  FIG. 21 shows a main part of a method of manufacturing a semiconductor device having a conventional Cu wiring in the order of steps. As shown in FIG. 21A, a MIS (Metal Insulator Semiconductor) transistor having a gate insulating film 106 and a gate electrode 108 on a substrate 101 made of p-type silicon is separated from the MIS transistor by element isolation 102. A protection diode composed of the n-type diffusion layer 105 is formed. Next, after forming a first interlayer insulating film 107 covering the MIS transistor, a contact plug 111 that penetrates the first interlayer insulating film 107 and is electrically connected to the gate electrode 108 is formed. In addition, a contact plug 112 that penetrates the first interlayer insulating film 107 and is electrically connected to the diffusion layer 105 is formed.

  Next, after depositing an etching stopper 109 and a second interlayer insulating film 110 on the first interlayer insulating film 107, the second interlayer insulating film 110 and the etching stopper 109 are selectively etched, A groove portion where the contact plug 111 and the contact plug 112 are exposed is formed.

Next, as shown in FIG. 21B, a barrier film 113 made of Ta / TaN having a thickness of 20 nm is formed on the bottom and side surfaces of the trench and on the second interlayer insulating film 110. The barrier film 113 is formed by sputtering using plasma, and the general discharge power is 1.5 kW and the discharge time is 20 seconds. Since the negative charge generated in this plasma process flows to the protective diode via the contact plug 112, no current flows through the gate insulating film 106. Therefore, the MIS transistor can be protected from plasma charging damage.
K. Noguchi et al., “IEEE Proc. Int. Rel. Phys. Symp.”, 1994, p.232 G. Van den bosch et al., “6th Int. Symp. On Plasma Process-Induced Damage”, 2001, p.8 S. Krishnan et al., “Proc. Int. Rel. Phys. Symp.”, 1998, p.302 S. Lee et al., “1st Int. Conference on Integrated Circuit Design and Technology”, 2004, p.342

  However, in the conventional method of providing a protection diode to avoid plasma charging damage, the protection diode remains connected even after the semiconductor device is completed. The semiconductor element is miniaturized, and the performance of the semiconductor device is greatly deteriorated by a slight increase in leakage current. Therefore, an increase in leakage current due to the protection diode is a problem that cannot be ignored.

  In the plasma process, the gate electrode may be negatively charged or positively charged (see Non-Patent Document 3, for example). However, since the protection diode can only flow current in one direction, for example, in the case of FIG. 21, the protection diode does not function in the state where the gate electrode 108 is positively charged, and the gate insulating film 106 There is a problem that current flows.

  In addition to the step of forming the barrier film 113, there are various plasma processes such as a step of further forming an etching stopper film and an upper interlayer insulating film on the copper wiring in order to form an upper wiring. In these processes, it is reported that a charging current flows by plasma as in the barrier film forming process (see, for example, Non-Patent Document 4). However, these processes are not considered in the conventional method, and there is a problem that plasma charging damage that occurs in these processes cannot be prevented.

  The present invention solves the above-mentioned conventional problems, prevents the occurrence of plasma charging damage in the plasma process of the wiring formation process without deteriorating the characteristics of the semiconductor device by the protection diode, and a highly reliable semiconductor device and It aims at enabling it to realize the manufacturing method.

  In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising a step of forming a plasma-responsive insulating film that exhibits conductivity by receiving light from plasma, and in the processing in a plasma atmosphere. Only the current path for releasing the charge from the plasma is formed.

  Specifically, a first method for manufacturing a semiconductor device according to the present invention includes a step (a) of forming a semiconductor element having an insulating film and an electrode formed on the insulating film on a semiconductor substrate; Forming a first insulating film laminate including a plasma-responsive insulating film made of an insulating material by receiving light from plasma on the element; and a first insulating film Forming a first wiring electrically connected to the electrode and a second wiring electrically connected to the semiconductor substrate and insulated from the first wiring so as to be exposed on the upper surface of the stacked body; (C) and a step (d) of forming a second insulating film stack in a plasma atmosphere on the first insulating film stack on which the first wiring and the second wiring are formed. The first wiring and the second wiring are in contact with the plasma-responsive insulating film. Is formed, in the step (d), the charges first wiring is captured, characterized in that it is released into the semiconductor substrate through the plasma response insulating film and the second wiring.

  According to the first method for manufacturing a semiconductor device, in the step of forming the second insulating film stack in the plasma atmosphere, the charge captured by the first wiring is applied to the plasma-responsive insulating film and the second wiring. The plasma charging current does not flow from the electrode to the substrate through the insulating film when the insulating film is formed on the wiring connected to the electrode using plasma. The insulating film is not deteriorated by plasma charging damage. In addition, when light from plasma does not enter the plasma-responsive insulating film, the first wiring and the second wiring are insulated from each other, so that the leakage current does not increase after the semiconductor device is completed. .

  In the first method for manufacturing a semiconductor device, the step (c) includes forming the first groove portion and the second groove portion on the first insulating film stacked body at a distance from each other, and then forming the first groove portion. Preferably, the first wiring is formed in the groove and the second wiring is formed in the formed second groove. With such a configuration, metal wiring can be reliably formed by a damascene process.

  In this case, in the step (c), a first conductive film electrically connected to the electrode and a second conductive film electrically connected to the semiconductor substrate are respectively connected to the first groove portion and the second groove portion. Including a step of forming in a plasma atmosphere, wherein the first conductive film and the second conductive film are formed to be in contact with the plasma-responsive insulating film, and when the first conductive film is formed in step (c). In addition, the charge captured by the first conductive film is preferably released to the semiconductor substrate through the plasma-responsive insulating film and the second conductive film. With such a configuration, it is possible to prevent the occurrence of plasma charging damage in the step of forming the barrier film of the metal wiring.

  In this case, the first conductive film and the second conductive film are preferably a single layer film made of tantalum or tantalum nitride, or a laminated film made of tantalum and tantalum nitride. With such a configuration, the first wiring and the second wiring can be reliably formed by a damascene process.

  In the first method for manufacturing a semiconductor device, a third groove is formed on the second insulating film stack, and then the third groove is electrically connected to the first wiring in the formed third groove. A step (e) of forming a wiring, and a step (f) of forming a third insulating film stack in a plasma atmosphere on the second insulating film stack on which the third wiring is formed. In the step (e), the charge captured by the third wiring is preferably released to the semiconductor substrate through the first wiring, the plasma-responsive insulating film, and the second wiring. With such a configuration, it is possible to prevent plasma charging damage from occurring when the upper layer wiring is formed.

  In the first method for manufacturing a semiconductor device, the step (e) includes a step of forming a via hole that exposes the first wiring in the second insulating film stack by plasma etching. In the step of forming the via hole, The charge captured by one wiring is preferably released to the semiconductor substrate through the plasma-responsive insulating film and the second wiring. With such a configuration, it is possible to prevent the occurrence of plasma charging damage when forming a via hole.

  In the first method for manufacturing a semiconductor device, the step (e) includes a step of forming a third conductive film in a plasma atmosphere at least on the bottom and side walls of the via hole. In the step of forming the third conductive film, The charge captured by the third conductive film when the third conductive film is formed is preferably released to the semiconductor substrate through the first wiring, the plasma-responsive insulating film, and the second wiring. By adopting such a configuration, it is possible to prevent plasma charging damage from occurring when the barrier film of the metal wiring is formed. In this case, the third conductive film is preferably a single layer film made of tantalum or tantalum nitride or a laminated film made of tantalum and tantalum nitride.

  In the first method for manufacturing a semiconductor device, a fourth groove portion is formed on the second insulating film stacked body at a distance from the third groove portion, and then the electrically floating dummy wiring is connected to the first semiconductor device. And a step (g) of forming in the groove portion of 4 in the second insulating film laminate, the region above the plasma-responsive insulating film formed in the region between the first wiring and the second wiring In this case, it is preferable not to form a dummy wiring. With such a configuration, when forming the upper layer wiring, it is possible to reliably release charges through the plasma-responsive insulating film and prevent the occurrence of plasma charging damage.

  According to a first method for manufacturing a semiconductor device, a fourth wiring that is adjacent to a first wiring and is electrically floating, a semiconductor that is adjacent to the fourth wiring, and a semiconductor The method further includes a step (j) of forming a fifth wiring electrically connected to the substrate, wherein the fourth wiring and the fifth wiring are formed in contact with the plasma-responsive insulating film, and the step (d) ), The charge captured by the fourth wiring is preferably released to the semiconductor substrate through the plasma-responsive insulating film and the fifth wiring. With this configuration, it is possible to reliably prevent plasma charging damage from being caused by the floating wiring.

  In the first method for manufacturing a semiconductor device, the plasma-responsive insulating film is preferably made of an insulator having a higher refractive index than silicon dioxide. In this case, the insulator having a higher refractive index than silicon dioxide is preferably silicon nitride. With such a configuration, it is possible to reliably release the plasma charging current to the substrate in the plasma atmosphere.

  In the first method for manufacturing a semiconductor device, the first insulating film stack includes a film made of silicon dioxide, and the plasma-responsive insulating film is formed by irradiating the film made of silicon dioxide with nitrogen plasma. Is preferred. With such a configuration, a plasma-responsive inter-insulating film can be reliably formed.

The first method for manufacturing a semiconductor device preferably further includes a step (h) of forming an impurity diffusion layer in a region electrically connected to the second wiring in the semiconductor substrate.
With such a configuration, the resistance of the semiconductor substrate can be reduced and the charge can be easily released, so that the occurrence of plasma charging damage can be reliably prevented.

  In the first method for manufacturing a semiconductor device, in the step (c), a plurality of second groove portions are formed after forming a plurality of second groove portions spaced apart from each other on the first insulating film stack. Preferably, the step is a step of forming a plurality of second wirings each insulated from the first wiring. With such a configuration, even when a large plasma charging current is generated, the plasma charging current can be reliably released to the substrate.

  In this case, it is preferable that the semiconductor substrate further includes a step (i) of forming a diode in a region electrically connected to each second wiring in the semiconductor substrate. In the step (i), the diode forms at least one element in which current flows from the second wiring toward the semiconductor substrate and another element in which current flows from the semiconductor substrate to the second wiring. It is preferable to do. With such a configuration, both positive and negative charges can be reliably released to the substrate.

  In the first method for manufacturing a semiconductor device, the second insulating film stack preferably includes an interlayer insulating film having a low dielectric constant and an etching stopper film having an etching rate different from that of the interlayer insulating film. The etching stopper layer is preferably made of carbon-containing silicon oxide. With this configuration, the upper layer wiring can be reliably formed.

  In the first method for manufacturing a semiconductor device, the insulating film may be a capacitive insulating film, and may be a gate insulating film or a capacitive insulating film.

  A second semiconductor device manufacturing method according to the present invention includes a semiconductor element forming step of forming a semiconductor element having an insulating film and an electrode formed on the insulating film on the semiconductor substrate; Forming an insulating film stack on the insulating film stack, forming a first groove and a second groove on the upper portion of the insulating film stack, and then forming an electrode on the formed first groove Forming a first wiring electrically connected to the semiconductor substrate, and forming a second wiring electrically connected to the semiconductor substrate in the formed second groove, the wiring forming process comprising: (A) forming a first conductive film on the insulating film stack, and forming the first groove and the second groove on the insulating film stack on which the first conductive film is formed. The second groove electrically connected to the electrodes in the first groove and the second groove respectively. A step (b) of forming a third conductive film electrically connected to the electric film and the semiconductor substrate in a plasma atmosphere; and a step (c) of removing the first conductive film after the step (b). The second conductive film and the third conductive film are formed in contact with the first conductive film, and the second conductive film is formed when the second conductive film is formed in the step (b). The charge trapped by is released to the semiconductor substrate through the first conductive film and the third conductive film.

  According to the second method for manufacturing a semiconductor device, the second conductive film and the third conductive film are formed in contact with the first conductive film, so that the second conductive film is formed when the second conductive film is formed. The charge captured by the second conductive film is released to the semiconductor substrate through the first conductive film and the third conductive film. Therefore, the charging current can be surely released to the substrate in the barrier film forming step in the damascene process, and as a result, the occurrence of plasma charging damage can be prevented. In addition, since the first conductive film is removed, the first wiring and the second wiring are insulated when the semiconductor device is completed, so that an increase in leakage current can be prevented. .

  In the second method for manufacturing a semiconductor device, the first conductive film is preferably a single layer film made of tantalum or tantalum nitride or a laminated film made of tantalum and tantalum nitride, and step (c) The conductive film is preferably removed by a chemical mechanical polishing method.

  In the second method for manufacturing a semiconductor device, the insulating film may be a capacitive insulating film, and may be a gate insulating film or a capacitive insulating film.

  A semiconductor device according to the present invention is formed so as to cover a semiconductor element on a semiconductor substrate, and a semiconductor element having an insulating film formed on the semiconductor substrate and an electrode formed on the insulating film. A first insulating film stack including a plasma-responsive insulating film made of an insulator that exhibits conductivity when receiving light from plasma, and is formed on the first insulating film stack and electrically connected to the electrode A first wiring; and a second wiring that is provided in a peripheral portion of the first wiring in the first insulating film stack and is electrically connected to the semiconductor substrate. The first wiring and the second wiring The wiring is in contact with the plasma-responsive insulating film.

  According to the semiconductor device of the present invention, since the first wiring and the second wiring are in contact with the plasma-responsive insulating film, the first wiring connected to the electrode in the plasma processing step when manufacturing the semiconductor device. Since a current path is formed between the wiring and the substrate, the charging current can be diverted to the substrate by bypassing the insulating film, and in the completed semiconductor device, the electrode and the substrate are insulated. Leakage current will not increase.

  In the semiconductor device of the present invention, the plasma-responsive insulating film is preferably made of an insulator having a higher refractive index than silicon dioxide. Further, the insulator having a higher refractive index than silicon dioxide is preferably silicon nitride. With such a configuration, the plasma-responsive insulating film can be reliably formed.

  In the semiconductor device of the present invention, the top surfaces of the first wiring and the second wiring and the top surface of the plasma-responsive insulating film are preferably the same surface. With such a configuration, a current can be reliably passed between the first wiring and the second wiring during plasma irradiation. In addition, since the plasma-responsive insulating film can have a function as a CMP stopper, the structure can be simplified.

  The semiconductor device of the present invention includes a second insulating film stack covering the first wiring and the second wiring, and a second insulating film formed on the second insulating film stack and electrically connected to the first wiring. 3 and a plurality of dummy wirings formed in the second insulating film stack and electrically floating, and the first wiring and the second wiring in the second insulating film stack It is preferable that no dummy wiring is formed in a region above the plasma-responsive insulating film formed therebetween. By adopting such a configuration, it is possible to reliably obtain a semiconductor device that is not subject to plasma charging damage even when the upper wiring is formed.

  In the semiconductor device of the present invention, the first insulating film may be a gate insulating film or a capacitive insulating film.

  In the semiconductor device of the present invention, an impurity diffusion layer is preferably formed in a region of the semiconductor substrate where the second wiring is electrically connected. With such a configuration, it is possible to reduce the resistance of a current path formed during plasma irradiation.

  In the semiconductor device of the present invention, it is preferable that the second wiring includes a plurality of wirings, and the plurality of second wirings are formed in a peripheral portion of the first wiring. With such a configuration, it is possible to reliably prevent the occurrence of plasma charging damage even when a large plasma charging current is generated.

  In the semiconductor device of the present invention, a diode is formed in a region where each second wiring in the semiconductor substrate is electrically connected, and the diode has a current flowing from the second wiring toward the semiconductor substrate. It is preferable that at least one element and another element through which current flows from the semiconductor substrate toward the second wiring are formed. By adopting such a configuration, the charging current can be surely released to the substrate when either positive or negative charge occurs.

  In the semiconductor device of the present invention, the fourth insulating film stack is formed adjacent to the first wiring and is not electrically connected to the wiring formed below the first wiring. And a plurality of fifth wirings formed adjacent to the fourth wiring in the interlayer insulating film and electrically connected to the semiconductor substrate. The fourth wiring and the fifth wiring each have a plasma response. It is preferable to be in contact with the conductive insulating film. With such a configuration, it is possible to reliably prevent plasma charging damage from occurring in the semiconductor element due to the floating wiring.

  The present invention can realize a highly reliable semiconductor device and a method for manufacturing the same by preventing the occurrence of plasma charging damage in the plasma process of the wiring forming process without degrading the characteristics of the semiconductor device by the protective diode.

(First embodiment)
A semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to the drawings. 1 to 5 show cross-sectional states in the respective steps of the semiconductor device manufacturing method of the present embodiment.

  As shown in FIG. 1, according to a known method, a MIS (Metal Insulator Semiconductor) transistor and a protection diode separated from each other by element isolation 2 in a p-type active (p-well) region 3 formed in a p-type semiconductor substrate 1 Then, a first interlayer insulating film 10 is formed on the substrate 1.

Here, the MIS transistor includes a source 4A and a drain 4B each formed of an n-type diffusion layer and spaced apart from the p-well 3. A gate insulating film 6 having a thickness of 2.2 nm is formed in a region across the source 4A and the drain 4B on the substrate 1. A gate electrode 7 made of n ⁺ polysilicon is formed on the gate insulating film 6, and the side surfaces of the gate insulating film 6 and the gate electrode 7 are covered with a sidewall insulating film 8. The protection diode includes an n-type diffusion layer 4 </ b> C formed in the p-well 3.

  Subsequently, a contact plug 9A that penetrates the first interlayer insulating film 10 and is electrically connected to the gate electrode 7 of the MIS transistor and a contact plug 9B that is electrically connected to the diffusion layer 4C of the protective diode are formed. .

Next, an etching stopper film 11 made of SiN is formed on the first interlayer insulating film 10. Subsequently, a second interlayer insulating film 14 is formed on the etching stopper film 11. In the present embodiment, the second interlayer insulating film 14 is formed by sequentially depositing a SiO ₂ film 12 and a SiN film 13 having a thickness of 20 nm by a chemical vapor deposition (CVD) method.

  Next, as shown in FIG. 2, the second interlayer insulating film 14 is etched to form a first wiring formation groove 14a in which the contact plug 9A is exposed and a second wiring formation in which the contact plug 9B is exposed. The groove portion 14b is formed.

  Next, as shown in FIG. 3, after removing the etching stopper film 11 from the bottom surfaces of the groove portions 14a and 14b, the barrier film 15 made of Ta / TaN and having a thickness of several nm is formed on the bottom surfaces of the groove portions 11a and 11b. It is deposited on the side surface and the second interlayer insulating film 14 by sputtering using plasma.

  Next, as shown in FIG. 4, a Cu film is embedded in the groove 11a and the groove 11b, and then planarized by a chemical mechanical polishing (CMP) method to form the first wiring 16A and the second wiring 16B. . At this time, the barrier film 15 formed on the second interlayer insulating film 14 is removed. In this case, since the SiN film 13 is polished as a CMP stopper, the upper surfaces of the first wiring 16A, the second wiring 16B, and the SiN film 13 are the same surface.

Next, as shown in FIG. 5, a carbon-containing silicon oxide film (SiOC) is formed on the first wiring 16A, the second wiring 16B, and the second interlayer insulating film 14 in order to form a second-layer wiring. After the etching stopper film 17 made of is formed, a second interlayer insulating film 18 made of SiO ₂ is formed. Thereafter, wiring is formed on the second layer in the same manner as the first layer, and further upper wiring is formed as necessary. The second and subsequent interlayer insulating films 18 may be low-k films such as SiO ₂ containing fluorine ions. Note that description of wirings connected to the source and drain of the MIS transistor is omitted.

  Hereinafter, the principle of protecting the gate insulating film in the method for manufacturing the semiconductor device of this embodiment will be described. As shown in FIG. 4, in the semiconductor device of this embodiment, the first wiring 16A connected to the gate electrode 7 of the MIS transistor and the second wiring 16B connected to the diffusion layer 4C of the protection diode are the second Insulated by the interlayer insulating film 14. Therefore, normally, no current flows through the protection diode, and the protection diode does not affect the characteristics of the completed semiconductor device.

On the other hand, in the present embodiment, the second interlayer insulating film 14 is formed of the SiO ₂ film 12 and the SiN film 13. SiN is an insulator having an energy gap Eg of about 7 eV. However, it has been experimentally clarified that the SiN film is a plasma-responsive insulating material that exhibits conductivity when high-energy light from the plasma is incident in the plasma process.

  In the semiconductor device of this embodiment, when light from plasma is incident on the SiN film 13 between the first wiring 16A and the second wiring 16B in the plasma process, the SiN film 13 exhibits conductivity, and the first A current flows between the wiring 16A and the second wiring 16A. Therefore, in the plasma process, the gate electrode 7 of the MIS transistor and the diffusion layer 4C of the protection diode are electrically connected, so that a current can flow from the gate electrode 7 to the substrate 1 without passing through the gate insulating film 6. . As a result, it is possible to prevent plasma charging damage in which the gate insulating film 6 is destroyed by the charge generated in the plasma process.

  For example, the etching stopper film 17 made of SiOC shown in FIG. 5 is usually formed by a plasma CVD method. At this time, charges from the plasma are captured by the wiring 16A, and the potential of the wiring 16A rises. However, since current flows between the first wiring 16A and the second wiring 16B through the SiN film 13 when plasma is irradiated, the charge generated by the plasma is insulated from the first wiring 16A by gate insulation. Instead of flowing to the substrate 1 through the film 6, it flows to the substrate 1 through the second wiring 16B and the protective diode.

The same effect can be obtained when the second interlayer insulating film 18 made of SiO ₂ is formed on the etching stopper film 17 by using plasma CVD. Further, when the second layer wiring is formed, the interlayer insulating film 18 is etched to form a groove, and charges generated during this etching can be released to the substrate 1 in the same manner. .

  When the barrier film 15 is formed by sputtering using plasma, the first wiring 16A and the second wiring 16B are not yet formed. However, since the barrier film 15 is made of Ta / TaN and is conductive, when the contact plug 9A and the contact plug 9B are electrically connected by the barrier film 15, the charge can be released through the protective diode. it can.

  However, when the barrier film 15 is deposited by the sputtering method, the coverage is poor, so that the film thickness is reduced particularly in the upper corner portion of the second interlayer insulating film 14, and the barrier film 15 and the groove portion formed in the groove portion 14a. There is a possibility that the barrier film 15 formed on 14b is not electrically connected. In this case, since the charging current captured in the trench 14a flows to the substrate 1 through the gate insulating film 6, the gate insulating film 6 is deteriorated.

  In the present embodiment, since the SiN film 13 having plasma responsiveness is provided on the interlayer insulating film 14, even when the coverage of the barrier film 15 is poor, the charging current generated at the time of plasma irradiation Can flow to the protective diode.

  Although an example in which one second wiring 16B is provided adjacent to the first wiring 16A has been shown, a plurality of second wirings 16B are provided in the periphery of the first wiring 16A as shown in FIG. May be. By doing so, the gate insulating film 6 is not damaged even when a large charging current is generated.

  When the plurality of second wirings 16B are provided, the second wirings 16B and the second wirings 16B and the first wirings 16A are insulated when plasma is not irradiated. Each protection diode connected to the second wiring 16B can be set to an arbitrary polarity. Thereby, even when the gate electrode 7 is positively charged or negatively charged, the charging current is released to the substrate 1 through the protective diode. In this case, if the adjacent second wirings 16B are connected to the protection diodes having the opposite polarities, the current paths can be balanced. Further, it is not necessary to connect all the second wirings 16B to the protection diode, and the second wirings that are required depending on the magnitude of the current that must be bypassed determined by the area of the first wiring 16A and the like. Only 16B needs to be connected to the protection diode.

  Furthermore, the second wiring 16B of this embodiment may be directly connected to the p-well 3 of the substrate 1 instead of the protective diode. In this way, the step of forming the protection diode can be omitted. Further, charging damage can be prevented even when the gate electrode 7 is charged positively or negatively. Even in this case, after the semiconductor device is completed, the first wiring 16A and the second wiring 16B are insulated from each other, so that the leakage current of the semiconductor device does not increase. In this case, the resistance of the current path can be further reduced by introducing a high-concentration p-type impurity into a region to which the p-well contact plug 9B is connected.

FIG. 7 shows the evaluation result of the semiconductor device of this embodiment. In FIG. 7, the horizontal axis indicates the value of the gate leakage current that is an index of the quality of the gate insulating film, and the vertical axis indicates the cumulative frequency. Note that the gate length, the gate width, and the thickness of the gate insulating film of the transistor used for measurement were 1.0 μm, 0.2 μm, and 2.2 nm, respectively, and the voltage applied to the gate was 1.2 V. Further, four second wirings 16B are provided per 10,000 μm ^{2 in} the area of the first wiring 16A connected to the gate electrode, and the second wirings 16B are alternately connected to protective diodes having different polarities.

  As shown in FIG. 7, in the case where the protective diodes indicated by ◯ in the figure are not provided, the graph is not a straight line, the leakage current is increased, and the gate insulating film is deteriorated. it is obvious. Further, when only the n-type protection diode indicated by Δ is provided, an increase in leakage current is suppressed considerably, but a defect still occurs. On the other hand, in the semiconductor device provided with both the n-type protection diode and the p-type protection diode indicated by □, the graph was a clean straight line, and no deterioration of the gate insulating film was observed.

  Although an example in which an n-channel transistor is formed has been described in this embodiment, a p-channel transistor can be formed in the same manner. FIG. 8 shows an evaluation result when a p-channel transistor is formed. In this case as well, as in the case of the n-channel transistor, the wiring electrically connected to the gate electrode and the dummy wiring connected to the protective diode are connected by a plasma-responsive insulating film, whereby gate insulation is achieved. The deterioration of the film could be completely prevented. Note that the gate length, the gate width, and the thickness of the gate insulating film of the transistor used for the measurement were 2.6 μm, 0.5 μm, and 2.2 nm, respectively, and the voltage applied to the gate was −1.2V.

In this embodiment, SiN is used as the plasma-responsive insulating film. However, any insulator that can flow current when receiving high-energy light from plasma is used, and is more refractory than SiO _2. An insulator having a high rate can be used similarly. The film thickness of the plasma-responsive insulating film may be arbitrarily changed.

(One modification of the first embodiment)
A method for manufacturing a semiconductor device according to a modification of the first embodiment will be described below with reference to the drawings. FIG. 9 is a diagram showing a cross-sectional state in one step of the manufacturing method of the semiconductor device of the present modification.

Until the etching stopper 11 shown in FIG. 9 is formed, since it is the same as that of the first embodiment, the description is omitted. In the present embodiment, after the second interlayer insulating film 14 made of SiO ₂ is formed on the etching stopper 11, the second interlayer insulating film 14 is irradiated with plasma containing nitrogen gas to obtain the second interlayer insulating film 14. A SiN film 14 A is formed on the surface of the interlayer insulating film 14. As a result, the second interlayer insulating film 14 whose surface is a plasma-responsive insulating film is obtained.

  After forming the second interlayer insulating film 14, the first wiring 16A, the second wiring 16B, and the like are formed in the same manner as in the first embodiment to form a semiconductor device.

  FIG. 10 shows the result of evaluating the characteristics of the gate insulating film of the semiconductor device thus obtained. As with the semiconductor device of the first embodiment, the semiconductor device formed by the method shown in this modification does not show deterioration of the gate insulating film, and it is clear that plasma charging damage can be prevented.

  In this modification, the plasma containing nitrogen gas was formed under the condition of a discharge voltage of 2 kW at a pressure of 10 Torr, and the plasma treatment time was 30 seconds.

(Second Embodiment)
A semiconductor device and a manufacturing method thereof according to the second embodiment of the present invention will be described below with reference to the drawings. 11 to 15 show cross-sectional states in the respective steps of the semiconductor device manufacturing method of the present embodiment. In FIG. 11 to FIG. 15, the same components as those in FIG. 1 to FIG.

  As shown in FIG. 11, in the same manner as in the first embodiment, a MIS transistor and a protection diode are formed on a p-type semiconductor substrate 1, and a first interlayer insulating film 10 covering the MIS transistor and the protection diode is formed. An etching stopper 11 is formed on the substrate.

Next, a second interlayer insulating film 14 made of SiO ₂ is formed on the etching stopper 11. Subsequently, a TaN film 24 is formed on the second interlayer insulating film 14 by the CVD method.

  Next, as shown in FIG. 12, the TaN film 24 and the second interlayer insulating film 14 are etched to form the groove 14a and the groove 14b.

  Next, as shown in FIG. 13, after removing the etching stopper 11 on the bottom surface of the groove 14a and the groove 14b, a barrier film 15 made of Ta / TaN is formed by sputtering.

  Next, as shown in FIG. 14, a Cu film is formed on the groove 14a and the groove 14b by a plating method, and then polished by a CMP method to expose the barrier film 15.

  Next, as shown in FIG. 15, the barrier film 15 and the TaN film 24 formed on the second interlayer insulating film 14 are further removed by CMP. Thereafter, in the same manner as in the first embodiment, upper layer wiring is formed as necessary.

  According to the semiconductor device manufacturing method of the present embodiment, the barrier film 15 is formed by the sputtering method in the state where the conductive TaN film is formed on the second interlayer insulating film 14. For this reason, even when the barrier film 15 is formed by a sputtering method with poor coverage, the groove portion 14a and the groove portion 14b can be made conductive. Therefore, since the charge current when forming the barrier film 15 can be released to the protection diode, it is possible to prevent the gate insulating film 6 from being deteriorated due to charging damage.

  Further, since the TaN film 24 is removed after the Cu wiring is formed, the first wiring 16A and the second wiring 16B are insulated in the completed semiconductor device. Therefore, there is no leakage due to the protective diode. Also in the semiconductor device of this embodiment, a plurality of protection diodes having different polarities can be provided as in the first embodiment. Therefore, charging damage does not occur when the gate electrode 7 is positively charged or negatively charged. It is also possible to connect the contact plug 9B directly to the substrate without providing a protective diode. Further, since SiN is not used for the interlayer insulating film 14, there is an advantage that wiring delay hardly occurs.

  FIG. 16 shows the results of evaluating the characteristics of the gate insulating film of the semiconductor device of this embodiment. As shown in FIG. 16, the value of the gate current and the cumulative defect rate show a good linear relationship, and it is clear that the gate insulating film is not deteriorated even in the semiconductor device of this embodiment.

(Third embodiment)
A semiconductor device according to the third embodiment of the present invention will be described below with reference to the drawings. FIGS. 17A and 17B show the semiconductor device of the present embodiment, where FIG. 17A shows a planar state viewed from above, and FIG. 17B shows a cross-section taken along line XVIIb-XVIIb in FIG. Indicates the state. In FIG. 17, the same components as those in FIG.

  As shown in FIG. 17, in the semiconductor device of this embodiment, wiring is further formed in the upper layer of the semiconductor device of the first embodiment. An etching stopper 17 made of SiOC and a third interlayer insulating film 18 are formed on the second interlayer insulating film 14 on which the first wiring 16A and the second wiring 16B are formed. Further, an etching stopper 33 made of SiOC and an interlayer insulating film 34 of the fourth layer are formed.

  A third wiring 36A having a dual damascene structure is formed in the third interlayer insulating film 18 and the fourth interlayer insulating film 34, and is electrically connected to the first wiring 16A. In addition, a dummy wiring 36B insulated from the third wiring 36A is formed in the interlayer insulating film 34. The dummy wiring 36B is a dummy wiring in CMP and is electrically floating.

  When the third wiring 36A is formed, a plasma process such as formation of a groove portion for embedding the third wiring 36A and formation of a barrier film 36 made of a Ta / TaN film is required. At this time, electric charges from the plasma are captured by the third wiring 36A, and a current flows through the first wiring 16A that is electrically connected to the third wiring 36A. However, since the upper layer of the second interlayer insulating film 14 formed between the first wiring 16A and the second wiring 16B is the plasma-responsive SiN film 13, the first wiring 16A and the first wiring 16A are not exposed during plasma irradiation. Since the second wiring 16B is in a conductive state, the charging current flows not to the gate insulating film 6 but to the protection diode.

  However, if the CMP dummy wiring 36B is formed above the region sandwiched between the first wiring 16A and the second wiring 16B, high energy light from the plasma will not reach the SiN film 13. The first wiring 16A and the second wiring 16B remain in an insulated state, the charging current flows to the gate insulating film 6, and the gate insulating film 6 deteriorates.

  In order to prevent this, the semiconductor device of this embodiment is provided with a region 30 that prohibits the formation of the dummy wiring 36B above the region sandwiched between the first wiring 16A and the second wiring 16B. The high energy light from the plasma is not blocked by 36B.

  FIG. 18 shows the result of evaluating the characteristics of the gate insulating film of the semiconductor device of this embodiment. As shown in FIG. 18, the value of the gate current and the cumulative defect rate show a good linear relationship, and it is clear that the gate insulating film is not deteriorated even in the semiconductor device of this embodiment.

  In this embodiment, the case where the second-layer wiring is formed has been described, but the present invention can also be applied to the case where an upper-layer wiring is formed.

  In addition, the dummy wiring pattern is usually automatically calculated by a computer. By applying the information of the prohibited area of this embodiment to this calculation program, the dummy wiring pattern is sandwiched between the first layer wiring and the dummy wiring. It is possible to easily prevent the dummy wiring from being formed in the upper part of the region.

(Fourth embodiment)
A semiconductor device and a manufacturing method thereof according to the fourth embodiment of the present invention will be described below with reference to the drawings. FIGS. 19A and 19B show the semiconductor device of the present embodiment in the process of being formed. FIG. 19A shows a planar configuration viewed from above, and FIG. 19B shows the XIXb-XIXb line of FIG. The state of the cross section in is shown. In FIG. 19, the same components as those of FIG.

  As shown in FIG. 19, in the semiconductor device of this embodiment, the first wiring 56 </ b> A and the second wiring embedded in the second interlayer insulating film 14 formed on the semiconductor substrate 1 are insulated from each other. A wiring 56B, a third wiring 56C, and a fourth wiring 56D are formed.

  The first wiring 56A and the third wiring 56C are formed in parallel with each other at a distance from each other, and face the side opposite to the side facing the third wiring 56C of the first wiring 56A. Thus, a plurality of second wirings 56B are formed. In addition, a plurality of fourth wirings 56D are formed facing the side opposite to the side facing the first wiring 56A of the third wiring 56C.

  The first wiring 56A is electrically connected to the gate electrode 7 through the contact plug 9A, and the third wiring 56C is a wiring that is connected when an upper layer wiring is formed, and is currently electrically connected. It is in a floating state. The second wiring 56B and the fourth wiring 56D are electrically connected to the diffusion layer 4C of the protective diode via the contact plug 9B. The adjacent second wiring 56B and the adjacent fourth wiring 56D are connected to protection diodes having different polarities.

  In the next step, when an etching stopper made of, for example, SiOC is formed on the second interlayer insulating film 14 using plasma, electric charges due to the plasma are captured by the first wiring 56A and the third wiring 56C. The The electric charge captured by the first wiring 56A is released to the protection diode through the second wiring 56B.

  On the other hand, the charge captured by the third wiring 56C flows to the first wiring 56A when there is no fourth wiring 56D or when the fourth wiring 56D is in an electrically floating state. Since the charge trapped in the wiring increases in accordance with the area of the wiring, when all of the charge trapped in the third wiring 56C flows to the first wiring 56A, the capacity of the second wiring 56B is exceeded. Then, a current flows through the gate insulating film 6 and the gate insulating film 6 is deteriorated.

  Further, since the current flowing through the SiN film 13 is very small even during plasma irradiation, if the potential difference between the first wiring 56A and the third wiring 56C increases, the dielectric breakdown of the second interlayer insulating film 14 occurs. As a result, the semiconductor device is destroyed.

  In order to prevent this, in the present embodiment, a plurality of fourth wirings 56D connected to the protection diode are provided around the third wiring 56C in a floating state. As a result, the charges trapped in the third wiring 56C flow in a distributed manner in the fourth wirings 56D, so that no current flows through the first wiring 56A. Further, a high voltage is locally applied to the second interlayer insulating film 14 so that dielectric breakdown does not occur.

  20A and 20B show the characteristics of the gate insulating film of the semiconductor device of the present embodiment and the conventional semiconductor device in which the fourth wiring 56D is in an electrically floating state, respectively. In FIG. 20, the horizontal axis indicates the gate voltage, the vertical axis indicates the value of the leakage current, and the measurement results for 25 transistors are shown.

  As shown in FIG. 20B, when the fourth wiring 56D formed in the periphery of the third wiring 56C is in an electrically floating state, variation in the value of the leakage current is recognized. This indicates that the gate insulating film 6 has deteriorated due to plasma charging damage. On the other hand, as shown in FIG. 20A, when the fourth wiring 56D was connected to the protective diode, no variation was observed in the value of the leakage current, and no deterioration was observed in the gate insulating film 6.

  In the present embodiment, the second wiring 56B and the fourth wiring 56D are connected to the diffusion layer 4C of the protective diode, but may be directly connected to the semiconductor substrate 1 without forming a diode.

  In the first to fourth embodiments of the present invention, the example in which the MIS transistor is formed as the semiconductor element and the gate insulating film is protected is shown. When an element is formed, the capacitor insulating film can be protected.

  The present invention can prevent the occurrence of plasma charging damage in the plasma process of the wiring formation process without deteriorating the characteristics of the semiconductor device due to the protective diode, and can realize a highly reliable semiconductor device and its manufacturing method. This is useful for a semiconductor device with reduced damage in a plasma process, a manufacturing method thereof, and the like.

It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a top view which shows an example of a structure of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a graph which shows the evaluation result of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a graph which shows the evaluation result of the semiconductor device which concerns on another example of the 1st Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on the modification of the 1st Embodiment of this invention. It is a graph which shows the evaluation result of the semiconductor device which concerns on the modification of the 1st Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a graph which shows the evaluation result of the semiconductor device which concerns on the 2nd Embodiment of this invention. (A) And (b) shows the semiconductor device which concerns on the 3rd Embodiment of this invention, (a) is the top view seen from the top, (b) is in the XVIIb-XVIIb line | wire of (a). It is sectional drawing. It is a graph which shows the evaluation result of the semiconductor device which concerns on the 3rd Embodiment of this invention. (A) And (b) shows the semiconductor device which concerns on 4th Embodiment of this invention, (a) is the top view seen from the top, (b) is the cross section in the XIXb-XIXb line | wire of (a) FIG. It is a graph which shows the evaluation result of the semiconductor device which concerns on the 4th Embodiment of this invention. It is sectional drawing which shows the principal part of the manufacturing process of the semiconductor device which concerns on a prior art example in process order.

Explanation of symbols

1 p-type silicon substrate 2 element isolation 3 active region (p well),
4 n-type source and drain layer 5 n-type diffusion layer 6 gate insulating film 7 gate electrode,
8 sidewall oxide film,
9A First contact plug 9B Second contact plug 10 First interlayer insulating film 11 Etching stopper film 12 Silicon oxide (SiO ₂ ) film 13 Silicon nitride (SiN) film 14 Second interlayer insulating film 14A SiN film 14a First 1 trench 14b 2nd trench 15 Barrier film 16A 1st interconnect 16B 2nd interconnect 17 Etching stopper film 18 Interlayer insulating film 24 TaN film 30 Dummy formation prohibition region 33 Etching stopper film 34 Interlayer insulating film 36A Third interconnect 36B dummy wiring 56A first wiring 56B second wiring 56C third wiring 56D fourth wiring

Claims (37)

Forming a semiconductor element having an insulating film and an electrode formed on the insulating film on a semiconductor substrate;
Forming a first insulating film stack including a plasma-responsive insulating film made of an insulating material by receiving light from plasma on the semiconductor element;
The first wiring electrically connected to the electrode and the semiconductor substrate are electrically connected and insulated from the first wiring so as to be exposed on the upper surface of the first insulating film stack. Forming a second wiring to be performed (c);
A step (d) of forming a second insulating film laminate in a plasma atmosphere on the first insulating film laminate on which the first wiring and the second wiring are formed;
The first wiring and the second wiring are formed in contact with the plasma-responsive insulating film,
In the step (d), the charge captured by the first wiring is released to the semiconductor substrate through the plasma-responsive insulating film and the second wiring.   In the step (c), a first groove and a second groove are formed at an interval above the first insulating film stack, and then the first wiring is formed in the formed first groove. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the second wiring is formed in the formed second groove portion. In the step (c), a first conductive film electrically connected to the electrode and a second conductive film electrically connected to the semiconductor substrate are respectively connected to the first groove portion and the second groove portion. Including a step of forming in a plasma atmosphere,
The first conductive film and the second conductive film are formed in contact with the plasma-responsive insulating film,
In the step (c), the charge captured by the first conductive film when forming the first conductive film is transferred to the semiconductor substrate through the plasma-responsive insulating film and the second conductive film. The method of manufacturing a semiconductor device according to claim 2, wherein the semiconductor device is escaped.   The semiconductor device according to claim 3, wherein the first conductive film and the second conductive film are a single layer film made of tantalum or tantalum nitride, or a laminated film made of tantalum and tantalum nitride. Method. Forming a third groove on the second insulating film stack and then forming a third wiring electrically connected to the first wiring in the formed third groove (e); When,
A step (f) of forming the third insulating film stack in a plasma atmosphere on the second insulating film stack on which the third wiring is formed;
In the step (e), the charge captured by the third wiring is released to the semiconductor substrate through the first wiring, the plasma-responsive insulating film, and the second wiring. The method for manufacturing a semiconductor device according to claim 1, wherein: The step (e) includes forming a via hole that exposes the first wiring in the second insulating film stack by plasma etching,
The charge formed by the first wiring in the step of forming the via hole is released to the semiconductor substrate through the plasma-responsive insulating film and the second wiring. Semiconductor device manufacturing method. The step (e) includes a step of forming a third conductive film in a plasma atmosphere at least on the bottom and side walls of the via hole,
In the step of forming the third conductive film, the charge captured by the third conductive film when the third conductive film is formed is the first wiring, the plasma-responsive insulating film, and the first The method of manufacturing a semiconductor device according to claim 6, wherein the semiconductor substrate is escaped to the semiconductor substrate through two wirings.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the third conductive film is a single layer film made of tantalum or tantalum nitride, or a laminated film made of tantalum and tantalum nitride. Forming an electrically floating dummy wiring in the fourth groove portion after forming a fourth groove portion spaced apart from the third groove portion on the second insulating film stack; (G)
Do not form the dummy wiring in a region above the plasma-responsive insulating film formed in a region between the first wiring and the second wiring in the second insulating film laminate. The method of manufacturing a semiconductor device according to claim 5, wherein: The first insulating film stack is adjacent to the first wiring and electrically floating, and is electrically insulated from the semiconductor substrate and adjacent to the fourth wiring. A step (j) of forming a fifth wiring connected to
The fourth wiring and the fifth wiring are formed in contact with the plasma-responsive insulating film,
10. The charge captured by the fourth wiring in the step (d) is released to the semiconductor substrate through the plasma-responsive insulating film and the fifth wiring. A manufacturing method of a semiconductor device given in any 1 paragraph.   The method of manufacturing a semiconductor device according to claim 1, wherein the plasma-responsive insulating film is made of an insulator having a higher refractive index than silicon dioxide.   The method of manufacturing a semiconductor device according to claim 11, wherein the insulator having a higher refractive index than silicon dioxide is silicon nitride. The first insulating film stack includes a film made of silicon dioxide,
The method of manufacturing a semiconductor device according to claim 12, wherein the plasma-responsive insulating film is formed by irradiating the film made of silicon dioxide with nitrogen plasma.   14. The method according to claim 1, further comprising a step (h) of forming an impurity diffusion layer in a region electrically connected to the second wiring in the semiconductor substrate. The manufacturing method of the semiconductor device of description.   In the step (c), a plurality of the second groove portions are formed at an interval from each other on the upper portion of the first insulating film stack, and then the plurality of second groove portions formed are respectively connected to the first groove portions. The method for manufacturing a semiconductor device according to claim 2, wherein the method is a step of forming a plurality of the second wirings insulated from the wirings.   The method of manufacturing a semiconductor device according to claim 15, further comprising a step (i) of forming a diode in each region electrically connected to each of the second wirings in the semiconductor substrate. .   In the step (i), the diode includes one element in which current flows from the second wiring toward the semiconductor substrate, and another element in which current flows from the semiconductor substrate to the second wiring. The method of manufacturing a semiconductor device according to claim 16, wherein at least one is formed.   18. The semiconductor device according to claim 1, wherein the second insulating film laminate includes an interlayer insulating film having a low dielectric constant and an etching stopper film having an etching rate different from that of the interlayer insulating film. Manufacturing method.   The method of manufacturing a semiconductor device according to claim 18, wherein the etching stopper layer is made of carbon-containing silicon oxide.   The method for manufacturing a semiconductor device according to claim 1, wherein the insulating film is a gate insulating film.   The method for manufacturing a semiconductor device according to claim 1, wherein the insulating film is a capacitive insulating film. Forming a semiconductor element having an insulating film and an electrode formed on the insulating film on the semiconductor substrate; and
An insulating film laminate forming step of forming an insulating film laminate on the semiconductor substrate;
A first groove and a second groove are formed on the insulating film stack at a distance from each other, and then a first wiring electrically connected to the electrode is formed in the formed first groove. And a wiring forming step of forming a second wiring electrically connected to the semiconductor substrate in the formed second groove portion,
The wiring formation step includes
A step (a) of forming a first conductive film on the insulating film laminate;
The first groove portion and the second groove portion are formed in the insulating film laminated body on which the first conductive film is formed, and then electrically connected to the electrode in the formed first groove portion and second groove portion, respectively. Forming a second conductive film and a third conductive film electrically connected to the semiconductor substrate in a plasma atmosphere (b);
And (c) removing the first conductive film after the step (b),
The second conductive film and the third conductive film are formed in contact with the first conductive film,
In the step (b), the charge captured by the second conductive film when forming the second conductive film is transferred to the semiconductor substrate through the first conductive film and the third conductive film. A method of manufacturing a semiconductor device, wherein the semiconductor device is released.   23. The method of manufacturing a semiconductor device according to claim 22, wherein the first conductive film is a single layer film made of tantalum or tantalum nitride, or a laminated film made of tantalum and tantalum nitride.   24. The method of manufacturing a semiconductor device according to claim 22, wherein the step (c) is a step of removing the first conductive film by a chemical mechanical polishing method.   25. The method of manufacturing a semiconductor device according to claim 22, wherein the insulating film is a gate insulating film.   25. The method of manufacturing a semiconductor device according to claim 22, wherein the insulating film is a capacitive insulating film. A semiconductor element having an insulating film formed on a semiconductor substrate and an electrode formed on the insulating film;
A first insulating film stack including a plasma-responsive insulating film formed of an insulator that exhibits conductivity when receiving light from plasma formed on the semiconductor substrate so as to cover the semiconductor element;
A first wiring formed in the first insulating film stack and electrically connected to the electrode;
A second wiring provided in a peripheral portion of the first wiring in the first insulating film laminate and electrically connected to the semiconductor substrate;
The semiconductor device, wherein the first wiring and the second wiring are in contact with the plasma-responsive insulating film.   28. The semiconductor device according to claim 27, wherein the plasma-responsive insulating film is made of an insulator having a higher refractive index than silicon dioxide.   29. The semiconductor device according to claim 28, wherein the insulator having a higher refractive index than silicon dioxide is silicon nitride.   30. The semiconductor device according to claim 27, wherein an upper surface of the first wiring and the second wiring and an upper surface of the plasma-responsive insulating film are the same surface. A second insulating film laminate covering the first wiring and the second wiring;
A third wiring formed in the second insulating film stack and electrically connected to the first wiring;
A plurality of dummy wirings formed in the second insulating film stack and electrically floating;
The dummy wiring is not formed in a region above the plasma-responsive insulating film formed between the first wiring and the second wiring in the second insulating film laminate. 31. The semiconductor device according to claim 27, wherein the semiconductor device is characterized in that:   32. The semiconductor device according to claim 27, wherein the insulating film is a gate insulating film.   32. The semiconductor device according to claim 27, wherein the insulating film is a capacitive insulating film.   34. The semiconductor device according to claim 27, wherein an impurity diffusion layer is formed in a region of the semiconductor substrate where the second wiring is electrically connected.   The said 2nd wiring consists of a some wiring, The said some 2nd wiring is formed in the peripheral part of the said 1st wiring, The any one of Claims 27-34 characterized by the above-mentioned. A semiconductor device according to 1. A diode is formed in each region of the semiconductor substrate where the second wirings are electrically connected.
The diode includes at least one element in which current flows from the second wiring toward the semiconductor substrate and another element in which current flows from the semiconductor substrate toward the second wiring. 36. The semiconductor device according to claim 35, wherein: A fourth wiring that is formed adjacent to the first wiring in the first insulating film stack and is not electrically connected to a wiring formed in a layer lower than the first wiring;
A plurality of fifth wirings formed adjacent to the fourth wiring in the interlayer insulating film and electrically connected to the semiconductor substrate;
37. The semiconductor device according to claim 27, wherein the fourth wiring and the fifth wiring are in contact with the plasma-responsive insulating film.

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