JP2005150396A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method capable of restraining plasma charging damage in a plasma process. <P>SOLUTION: A MOS transistor and protective diodes A, B having different polarities are formed on a p-type silicon substrate 1 beforehand. Thereafter, a first insulating film 7, a stopper film 8, and a second insulating film 10 are formed in sequence on the p-type silicon substrate 1, and to the second insulating film 10 there are connected through etching a first trench 15a and a second trench 15b both for forming metal wiring. Further, a third trench having its depth shallower than these trenches is formed. Thereafter, a barrier film 13 is formed by a plasma process, and a charging current generated at that time is led to earth potential through either the protective diode A or B. Thereafter, a Cu layer 14 is formed on the barrier film 13, and CMP is made until the third trench 15c disappears. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device using plasma processing and a semiconductor device manufactured thereby.

  In recent years, high integration has been greatly progressed in a semiconductor device including a semiconductor integrated circuit. In particular, in MIS (Metal Insulated semiconductor) type semiconductor devices, in order to cope with high integration, elements such as transistors are miniaturized and enhanced in performance, and further miniaturization and higher performance are required. It has been.

  Further, in such a wiring formation process of a semiconductor device, the use of a plasma process typified by plasma CVD or plasma etching is increasing. Furthermore, the plasma process is frequently used not only at the time of etching but also at the time of film formation. From this point of view, the use of the plasma process tends to increase year by year. This is because the heat treatment amount is limited in terms of impurity diffusion and heat resistance of the metal wiring material in the wiring formation process of the semiconductor device, and the heat treatment amount can be reduced by the plasma process.

  However, as the use of plasma processes increases, device damage due to plasma processes has become apparent. This is mainly called “plasma charging damage” and has been greatly increased in recent years (see, for example, Non-Patent Document 1).

  A semiconductor device that has been subjected to such plasma charging damage is a defective product because the device characteristics deteriorate. In the problem of plasma charging damage, particularly, deterioration of reliability in the gate insulating film is a serious problem.

  For example, in recent years, copper (Cu) wiring may be introduced to improve performance. In this case, the damascene method is used for forming the Cu wiring. In the Cu wiring forming process using the damascene method, a conductive barrier film (Ta / TaN) is used to improve the adhesion between the Cu layer and the interlayer insulating film (or inter-wiring insulating film). Film) is formed.

  However, since the barrier film is formed by a plasma process and the barrier film is electrically connected to the gate insulating film, it is considered that plasma charging damage is likely to occur when the barrier film is formed ( For example, refer nonpatent literature 2.). In this case, the gate insulating film under the barrier film is easily destroyed.

  In order to solve such problems, conventionally, a wiring formation method has been proposed in which a protective diode is provided on a semiconductor substrate in advance, thereby suppressing plasma charging damage (see, for example, Patent Document 1). According to this method, since the charging current that causes plasma charging damage is released to the installation potential via the protective diode, the charging current is suppressed from being applied to the gate insulating film, and the gate insulating film is destroyed. Is avoided.

  Here, taking a wiring forming method using the damascene method as an example, a wiring forming method for preventing plasma charging by a protective diode will be described with reference to FIGS. 12 and 13. 12 and 13 are cross-sectional views showing a process for forming a conventional damascene structure. 12 (a) to 12 (c) show a series of main processes, and FIGS. 13 (d) to 13 (e) show a series of main processes following the process shown in FIG. Yes. FIG. 13 (e) also shows the semiconductor device according to the first embodiment of the present invention.

  First, as shown in FIG. 12A, an interlayer insulating film 107 (400 nm), a silicon nitride film (40 nm) 109, and a wiring are formed on a p-type silicon substrate 101 on which an n-channel MOS transistor and a protection diode are formed. After the interlayer insulating film (200 nm) 110 is sequentially formed, these are etched to form a trench 115 for metal wiring. The trench 115 has a rectangular parallelepiped shape. The silicon nitride film 109 functions as a stopper when the trench 115 is etched.

In the example of FIGS. 12 and 13, the n-channel MOS transistor and the protection diode are separated by element isolation 102. The n-channel MOS transistor includes a p-well 103 formed in the p-type silicon substrate 101, a gate insulating film (NO / O ₂ oxynitride film: film thickness 2.2 nm) 106, a gate electrode 108, a p-type A source (n +) region 104a and a drain (n +) region 104b provided in the surface layer portion of the silicon substrate 101, and a sidewall 112 formed of a silicon oxide film are included.

  The protection diode is configured by a p-well 103 formed inside the p-type silicon substrate 101 and an n-type diffusion layer 105 provided in the surface layer portion of the p-type silicon substrate 101. In FIGS. 12 and 13, reference numerals 111a and 111b denote tungsten (W) plug electrodes. Plug electrode 111 a is connected to gate electrode 108, and plug electrode 111 b is connected to n-type diffusion layer 105.

  Next, as shown in FIGS. 12B and 12C, a barrier film (20 nm) 113 is formed by a plasma process so that the trench 115 and the inter-wiring insulating film 110 are covered. 12 and 13, the barrier film 113 is a Ta / TaN film, the discharge power during the plasma process is set to 1.5 kW, and the discharge time is set to 20 seconds.

  At this time, as can be seen from FIGS. 12B and 12C, the step portion 116 is formed in the inter-wiring insulating film 110 by the trench 115, and the coverage state of the barrier film 113 in the step portion 116 is poor. Therefore, the barrier film 113 is first formed on the upper surface of the inter-wiring insulating film 110 and the bottom surface of the trench 115.

  At this time, if the protective diode is not formed, the barrier film 113 (the barrier film on the bottom surface of the trench 115) electrically connected to the gate electrode 108 is electrically separated from the other barrier films. As shown by the arrow, the charging current flows to the gate electrode 108 and destroys the gate insulating film 106. However, in the example of FIG. 12, since the protection diode is provided, the charging current is set via the protection diode. Escape to potential. As a result, destruction of the gate insulating film 106 is avoided.

  However, when the transistor formed on the silicon substrate 101 is an n-channel MOS transistor as shown in FIG. 1, the diffusion layer 105 constituting the protective diode connected thereto is n-type. Therefore, since the rectification direction of the protection diode is n + / p, if the gate electrode 108 is charged with a positive charge as shown in FIG. 12B, the protection diode does not function and the charging current is It flows to the insulating film 106 (see, for example, Non-Patent Document 3).

In this case, a Cu layer (500 nm) 114 is formed as shown in FIG. 13D with the gate insulating film 106 being destroyed, and further, Cu wiring is formed by CMP as shown in FIG. 13E. The semiconductor device is finally completed, but the semiconductor device is a defective product due to the breakdown of the gate insulating film 106.
Japanese Patent Laid-Open No. 10-173157 H. H. Shin et al., “Thickness dependence and other effects on oxide and interface damage by plasma processing”, (Issue Country: USA), Eye Triple E (IEEE), p. 272, 1993 G. G. Van den bosch et al., “Plasma charging damage issues in copper single and dual damascene, oxide and low-k dielectric. interconnects) "(Issuing country: USA), American Vacuum Society (AVS), p. 8, 2001 S. Krishnan et al., “Antenna Protection Strategy for Ultra-thin Gate MOSFETs”, (Issue Country: USA), I Triplex (IEEE), p. 302, 1998

  As described above, in the wiring forming method using the conventional damascene method shown in FIG. 12, the charging damage can be avoided only when the direction of the charging current coincides with the rectification direction of the protective diode. The possibility that the insulating film is destroyed is considered extremely high.

  An object of the present invention is to provide a semiconductor device capable of solving the above-described problems and suppressing plasma charging damage in a plasma process, and a manufacturing method thereof.

  In order to achieve the above object, a first method of manufacturing a semiconductor device according to the present invention includes: (a) a first insulating film covering a semiconductor substrate on which a MOS transistor and a diode are formed; And (b) etching the second insulating film to form a trench for forming a metal wiring electrically connected to the MOS transistor and the diode. (C) forming a barrier film containing tantalum on the side and bottom surfaces of the trench by a plasma process, and further forming a metal film on the barrier film; and (d) performing CMP on the metal film. A method of manufacturing a semiconductor device, wherein two types of diodes having different polarities are formed on the semiconductor substrate. In the step (b), the first trench for forming the metal wiring electrically connected to the gate electrode of the MOS transistor and the metal wiring electrically connected to the active regions of the two types of diodes A second trench for formation, and a third trench connecting the first trench and the second trench and formed shallower than the first and second trenches, and In the step (d), the CMP is performed until at least the third trench disappears.

  In order to achieve the above object, a method for manufacturing a second semiconductor device according to the present invention includes: (a) a first insulating film covering a semiconductor substrate on which a MOS transistor and a diode are formed; And (b) etching the second insulating film to form a trench for forming a metal wiring electrically connected to the MOS transistor and the diode. (C) forming a barrier film containing tantalum on the side and bottom surfaces of the trench by a plasma process, and further forming a metal film on the barrier film; and (d) performing CMP on the metal film. And forming a metal wiring, wherein the third insulation covers at least the side surface of the trench before the step (c) is performed. It is formed and by etching the third insulating film, and having a step of forming a sidewall protection film on a side surface of the trench.

  In order to achieve the above object, a third method of manufacturing a semiconductor device according to the present invention includes: (a) a first insulating film covering a semiconductor substrate on which a MOS transistor and a diode are formed; And (b) etching the second insulating film to form a trench for forming a metal wiring electrically connected to the MOS transistor and the diode. (C) forming a barrier film containing tantalum on the side and bottom surfaces of the trench by a plasma process, and further forming a metal film on the barrier film; and (d) performing CMP on the metal film. A method of manufacturing a semiconductor device, wherein two types of diodes having different polarities are formed on the semiconductor substrate. By the step (d), the first metal wiring electrically connected to the gate electrode of the MOS transistor, the second metal wiring electrically connected to the active region of the two types of diodes, A third metal wiring is formed that electrically connects the first metal wiring and the second metal wiring and has a lower surface positioned higher than the lower surfaces of the first and second metal wirings. As described above, the trench is formed in the step (b), and in the step (d), the CMP electrically separates at least the first metal wiring and the second metal wiring. It is performed until it is done.

  In order to achieve the above object, a fourth method of manufacturing a semiconductor device according to the present invention includes: (a) a first insulating film covering a semiconductor substrate on which a MOS transistor and a diode are formed; And (b) etching the second insulating film to form a trench for forming a metal wiring electrically connected to the MOS transistor and the diode. (C) forming a barrier film containing tantalum on the side and bottom surfaces of the trench by a plasma process, and further forming a metal film on the barrier film; and (d) performing CMP on the metal film. A method of manufacturing a semiconductor device including at least a step of forming a metal wiring, wherein a side surface of the trench is formed in a thickness direction of the semiconductor substrate before the step (b) is performed. So as to be inclined in a range of 5 degrees to 20 degrees with respect, and having a step of forming an etching pattern for forming the trench.

  In order to achieve the above object, a first semiconductor device according to the present invention includes a semiconductor substrate on which a MOS transistor and a diode are formed, a first insulating film covering the MOS transistor and the diode, and the first semiconductor device. A semiconductor device having at least a second insulating film formed on an upper layer of the insulating film and a metal wiring electrically connected to the MOS transistor and the diode, wherein the metal wiring is A side wall protective film having a multilayer structure embedded in a trench formed in an insulating film and having at least a layer containing tantalum and having a curved surface on the metal wiring side is provided on a side surface of the trench. It is provided.

  To achieve the above object, a second semiconductor device according to the present invention includes a semiconductor substrate on which a MOS transistor and a diode are formed, a first insulating film covering the MOS transistor and the diode, and the first insulation. A semiconductor device having at least a second insulating film formed on an upper layer of the film and a metal wiring electrically connected to the MOS transistor and the diode, wherein the metal wiring is the second insulating film And having a multilayer structure having at least a layer containing tantalum, and the side surface of the trench is inclined in a range of 5 degrees to 20 degrees with respect to the thickness direction of the semiconductor substrate. It is characterized by that.

  With the above characteristics, according to the semiconductor device manufacturing method and the semiconductor device of the present invention, it is possible to suppress the charging current generated by the plasma in the wiring forming process from being applied to the gate insulating film. Suppression can be achieved. For this reason, it is possible to reduce the defect rate and improve the reliability of the semiconductor device.

  In the first method for fabricating a semiconductor device of the present invention, the third trench has an etching rate in a region where the third trench is formed, and a region where the first and second trenches are formed. It is preferable that the first and second trenches be shallower than the first etching rate.

  The etching rate in the region where the third trench is formed by the RIE-Lag phenomenon generated by making the width of the third trench narrower than the width of the first and second trenches is as follows. The etching rate is preferably slower than the etching rate in the region where the first and second trenches are formed.

  In the second method for manufacturing a semiconductor device and the first semiconductor device of the present invention, the formation of the trench has a value obtained by dividing the thickness of the second insulating film by the width of the trench from 2. It is preferable to be carried out so as to be small. Furthermore, it is preferable that the third insulating film is a silicon insulating film or a silicon nitride film containing at least oxygen.

  Furthermore, in the third semiconductor device manufacturing method, the second semiconductor device manufacturing method, and the semiconductor device of the present invention, two types of diodes having different polarities are formed on the semiconductor substrate, and the metal It is also possible to adopt a mode in which the wiring is electrically connected to the active regions of the two types of diodes.

  Hereinafter, a method for manufacturing a semiconductor device and a semiconductor device according to the present invention will be described with reference to the drawings. Note that the semiconductor device manufacturing method and the semiconductor device of the present invention are not limited to the following embodiments, and can be implemented in various modes without departing from the scope of the invention.

(Embodiment 1)
A semiconductor device manufacturing method and a semiconductor device according to a first embodiment of the present invention will be described below with reference to FIGS. 1 and 2 are partial cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment of the present invention. 1 (a) to 1 (c) show a series of main processes, and FIGS. 2 (d) to 2 (f) show a series of main processes following the process shown in FIG. Yes. FIG. 2 (f) also shows the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a perspective view showing a trench formed in the step shown in FIG.

  First, as shown in FIG. 1A, on a p-type silicon substrate 1 on which an n-channel MOS transistor and two protection diodes A and B are formed, a first insulating film 7 covering these and a stopper A film 9 and a second insulating film 10 are sequentially formed. Further, the second insulating film 10 is etched to form a trench 15 for forming a metal wiring. Further, in FIG. 1A, the stopper film 9 is exposed on the bottom surface of the trench 15, but the stopper film 9 is removed by etching before the step shown in FIG.

In FIG. 1 and FIG. 2, the n-channel MOS transistor and the protection diodes A and B are separated by element isolation 2. The n-channel MOS transistor includes a p-well 3 formed inside a p-type silicon substrate 1, a gate insulating film (NO / O ₂ oxynitride film: film thickness 2.2 nm) 6, and a gate electrode formed of n + polySi. 8, a source (n +) region 4 a and a drain (n +) region 4 b provided in the surface layer portion of the p-type silicon substrate 1, a sidewall (side wall protective film) 12 formed by etching back a silicon oxide film, It is constituted by.

  The protection diode A is composed of a p-well 3 formed inside the p-type silicon substrate 1 and an n-type diffusion layer 5 provided in a surface layer portion of the p-type silicon substrate 1. On the other hand, the protection diode B is composed of an n-well 21 formed by separating the element from the p-well 3 and a p + type diffusion layer 22 provided near the surface layer of the portion where the n-well 21 is provided. The protection diodes A and B have different polarities (rectification directions).

  In FIGS. 1 and 2, reference numerals 11a to 11c denote tungsten (W) plug electrodes. One end of the plug electrode 11 a is connected to the gate electrode 8, and the other end is exposed on the upper surface of the first insulating film 7. One end of the plug electrode 11 b is connected to the n-type diffusion layer 5 of the protection diode A, and the other end is exposed on the upper surface of the first insulating film 7. One end of the plug electrode 11 c is connected to the p + -type diffusion layer 22 of the protection diode B, and the other end is exposed on the upper surface of the first insulating film 7.

  1 and 2, the first insulating film 7 is an interlayer insulating film having a thickness of 400 nm, and the second insulating film 10 is an inter-wiring insulating film having a thickness of 200 nm. The stopper film 9 is a silicon nitride film having a thickness of 40 nm and functions as a stopper when the trench 15 is etched.

  Further, as shown in FIG. 3, the trench 15 formed in FIG. 1A includes a first trench 15a, a second trench 15b, and a third trench 15c. The first trench 15a is located immediately above the plug electrode 11a, and the metal wiring formed by the first trench 15a is electrically connected to the gate electrode of the n-channel MOS transistor.

  The second trench 15b is located immediately above both the plug electrodes 11b and 11c, and the metal wiring formed by the second trench 15b is electrically connected to the active regions of the protection diodes A and B having different polarities. Connected to.

  Further, the third trench 15c is formed so as to connect the first trench 15a and the second trench 15b, and the metal wiring formed by the third trench 15c is formed by the first trench. The metal wiring to be formed is electrically connected to the metal wiring formed by the second trench.

  As shown in FIG. 3, the width W3 of the third trench 15c is narrower than the width W1 of the first trench 15a and the width W2 of the second trench 15b. Therefore, due to the RIE-Lag phenomenon caused by etching, the etching rate in the region where the third trench 15c is formed is higher than the etching rate in the region where the first trench 15a and the second trench 15b are formed. Become slow.

  Here, the RIE-lag phenomenon will be described with reference to FIG. FIG. 4 is a diagram showing the relationship between the etching width and the width of the trench for forming the wiring. As shown in FIG. 4, when the trench width becomes 0.12 μm or less, the etching rate rapidly decreases. Further, when the trench width is 0.10 μm, the etching rate is reduced to about 60% as compared with the case of 0.12 μm. As a result, as shown in FIGS. 1A and 3, the depth x of the third trench 15c is shallower than the depth y of the first trench 15a and the second trench 15b.

  Next, when the stopper film 9 is removed and one end of the interlayer insulating film 7 and the plug electrodes 11a to 11c is exposed, a conductive barrier film 13 is formed as shown in FIGS. The The barrier film 13 is formed in order to improve the adhesion between the Cu layer 14 to be formed later and the interlayer insulating film 7, and is a film containing tantalum (Ta) such as a Ta / TaN film.

  The barrier film 13 is formed by a plasma process in the same manner as the steps shown in FIGS. 12B and 12C in the prior art. Further, in the example shown in FIG. 1B, since the coverage of the barrier film 13 in the stepped portion 16 is poor, the barrier film 13 is first formed of the upper surface of the second insulating film 10 and the bottom surface of the trench 15 (plug). And the upper surface of the first insulating film from which the electrodes 11a to 11c are exposed.

  Since the step portion 17 between the first trench 15 a and the second trench 15 b and the third trench 15 c is smaller than the step portion 16, the step portion 17 has a barrier similar to the bottom surface of the trench 15. A film 13 is formed. In this case, the protection diodes A and B are electrically connected to the n-channel MOS transistor.

  For this reason, also in the first embodiment, the charging current due to plasma goes to the barrier film 13 formed on the bottom surface of the trench 15 as in the example shown in FIG. However, in the first embodiment, unlike the conventional example, protective diodes A and B having different polarities are provided under the same trench.

  Therefore, when the gate electrode 8 is charged with a positive charge, the charging current flows to the protective diode B (p + type diffusion layer 22). When the gate electrode 8 is charged with a negative charge, the charging current is It flows to the protection diode A (n-type diffusion layer 5). That is, according to the first embodiment, unlike the example shown in FIG. 12 in the prior art, charging current in either direction flows to the protection diode and does not flow to the gate insulating film 6. Further, it is possible to reduce the deterioration of the characteristics of the semiconductor device due to the breakdown of the gate insulating film 6.

  Thereafter, as shown in FIG. 1D, a Cu layer 14 for forming a metal wiring is formed by electroplating. Further, CMP is performed as shown in FIG. Further, CMP is performed until the third trench 15c disappears as shown in FIG.

  As a result, the metal wiring 18a is formed in the first trench 15a and the metal wiring 18b is formed in the second trench 15b, and the semiconductor device according to the first embodiment shown in FIG. 1 (f) is obtained. In the first embodiment, an inter-wiring insulating film or a metal wiring may be further provided on the upper layer of the metal wirings 18a and 18b to form a multilayer wiring.

  Further, as can be seen from FIG. 1 (f), in the semiconductor device according to the first embodiment, the metal wiring 18a electrically connected to the protection diodes A and B and the n-channel MOS transistor are connected. Since the barrier film 13 formed on the bottom surface is removed by the disappearance of the third trench 15c, the metal wiring 18b is electrically isolated.

  That is, according to the first embodiment, unlike the example shown in FIG. 13E in the prior art, the protection diode and the transistor can be electrically separated in the completed semiconductor device. For this reason, it is possible to prevent the protection diode from affecting the operation of the semiconductor device.

  Here, with reference to FIG. 5, the semiconductor device according to the first embodiment is compared with the conventional semiconductor device shown in FIG. FIG. 5 is a graph showing an electrical characteristic evaluation between the semiconductor device in the first embodiment and the conventional semiconductor device. Specifically, FIG. 5 shows the measurement result of the gate leakage current value in an n-channel MOS transistor array (channel width W / channel length L = 1 / 0.1 × 0.01 K). The results shown in FIG. 5 are obtained from an in-plane 78-chip wafer.

In FIG. 5, the horizontal axis indicates the gate current density [A / cm ² ] when a gate voltage of 1.2 V is applied. The vertical axis represents the cumulative failure probability when a Gaussian distribution is assumed.

  As can be seen from FIG. 5, the gate leakage current value is increased in the conventional semiconductor device as compared with the semiconductor device in the first embodiment. This indicates that the device characteristics of the conventional semiconductor device are deteriorated due to plasma charging damage as compared with the semiconductor device of the first embodiment. That is, FIG. 5 suggests that the plasma charging damage can be reduced according to the first embodiment as compared with the conventional case.

  In the example shown in FIGS. 1 and 2, the barrier film 13 is formed between the Cu layer 14 and the interlayer insulating film 7, but the barrier film 13 may not be formed in some cases. An example in which the barrier film 13 is not formed will be described with reference to FIG. FIG. 6 is a partial cross-sectional view showing another example of the method for manufacturing a semiconductor device according to the first embodiment of the present invention, and FIGS. 6A to 6C show a series of main steps. .

  The process shown in FIG. 6A is the same as the process shown in FIG. Also in the example of FIG. 6A, the trench 15 is formed in the second insulating film 10 (see FIG. 3). After the step shown in FIG. 6A, a Cu layer 14 is formed by electroplating as shown in FIG. 6B.

  Thereafter, as shown in FIG. 6C, as in the steps shown in FIGS. 1D and 1F, CMP is performed until the third trench 15c disappears, and metal wirings 18a and 18b are formed. Is done. Thus, in the example of FIG. 6, unlike the example shown in FIG. 1, since the plasma process is not performed, the gate insulating film 6 is not destroyed by plasma charging damage.

  However, in the CMP process, charges are charged between the CMP polishing pad and the Cu layer 14 in order to rotate the CMP polishing pad at high speed. In addition, when the charged charge increases, in this case as well as in the case of the plasma process, a charging current flows and the gate insulating film 6 may be destroyed. That is, in the example of FIG. 6, no charging current is generated by plasma, but there is a possibility that a charging current is generated by charging.

  However, also in the example of FIG. 6, protection diodes A and B having different polarities are provided, and the n-channel MOS transistor is connected to the protection diodes A and B by the Cu layer 14.

  For this reason, the charging current due to charging also flows to the diffusion layer of either the protective diode A or B, similarly to the charging current due to the plasma process shown in FIG. Therefore, in the example of FIG. 6, the gate insulating film 6 is suppressed from being destroyed by the charging current due to charging. This also applies to the examples shown in FIGS.

  In the first embodiment, the connection between the protective diode and the transistor and the metal wiring uses the plug electrodes 11a to 11c formed of tungsten. However, the present invention is not limited to this mode. . In the present invention, a dual damascene structure can be employed instead of providing the plug electrodes 11a to 11c, and the same effect can be obtained in this case.

(Embodiment 2)
Next, a semiconductor device manufacturing method and a semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS. FIG. 7 is a partial cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention, and FIGS. 7A to 7D show a series of main steps. FIG. 7D also shows the semiconductor device according to the second embodiment of the present invention. In FIG. 7, the same components as those shown in FIGS. 1 and 2 are denoted by the same reference numerals.

  First, as shown in FIG. 7A, on a p-type silicon substrate 1 on which an n-channel MOS transistor and a protection diode A are formed, a first insulating film 7, a stopper film 9 covering these, A second insulating film 10 is sequentially formed. Further, the second insulating film 10 is etched to form a trench 32 for forming a metal wiring.

  The process shown in FIG. 7A is performed in the same manner as the process shown in FIG. 12A in the prior art, except that the stopper film 9 on the bottom surface of the trench 32 is not removed by etching in this process. In FIG. 7A, the shape of the trench 32 is a rectangular parallelepiped.

  In the second embodiment, the width of the trench 32 is obtained by dividing the thickness of the second insulating film 10 by this (the thickness of the second insulating film 10 / the width of the trench 32). It is set to be smaller than 2. This is because if the obtained value is 2 or more, it becomes difficult to embed a Cu layer 14 described later.

  Next, unlike the conventional example, in the second embodiment, as shown in FIG. 7B, the side wall similar to the side wall 12 provided on the side surface of the trench 32 is also provided on the side surface of the trench 32. (Sidewall protective film) 31 is formed. Specifically, first, a third insulating film (not shown) is formed inside the trench 32. Next, this is etched back to form sidewalls 31.

  The third insulating film is etched until the stopper film 9 is exposed. In the example of FIG. 7, a silicon insulating film containing at least oxygen typified by a silicon oxide film is used as the third insulating film forming the side wall. However, other examples include silicon nitride films.

  Next, as shown in FIG. 7C, after the stopper film 9 on the bottom surface portion of the trench 32 is removed by etching to expose the end portions of the plug electrodes 11a and 11b, the barrier film 13 is formed. Also in the step shown in FIG. 7C, the barrier film 13 is formed by the plasma process in the same manner as the steps shown in FIGS. 1B and 1C.

  For this reason, also in the second embodiment, the charging current due to the plasma when forming the barrier film 13 is directed to the barrier film 13 as in the example shown in FIG.

  However, in the second embodiment, the sidewall 31 is formed on the side surface of the trench 32 as described above, and the outer surface of the sidewall 31 (the surface on which the barrier film 13 is formed) is a curved surface. Further, this surface is gentler than the step portion 116 shown in FIG. 12 in the prior art, and has a shape in which the barrier film 13 is easily formed.

  Therefore, the formation of the barrier film 13 proceeds substantially simultaneously on the upper surface of the second insulating film 10, the bottom surface of the trench 32, and the outer surface of the sidewall. For this reason, unlike the example shown in FIG. 12B in the prior art, the barrier film 13 electrically connected to the gate electrode 8 (the barrier film formed on the bottom surface of the trench 32) is used as another barrier film. On the other hand, an electrically separated state is avoided.

  As a result, when the direction of the charging current coincides with the rectification direction of the protection diode A, the charging current is released to the ground potential by the protection diode A. On the other hand, when the direction of the charging current does not coincide with the rectification direction of the protection diode A, the charging current passes through the barrier film on the second insulating film 10 as indicated by an arrow and the rectification direction is the same. To a protective diode (not shown) and thereby escaped to ground potential.

  The other protection diode is a diode that is not electrically connected to the protection diode A by a metal wiring formed in the trench 32, and is, for example, a p-channel provided in another region on the silicon substrate 1. A protection diode connected to the MOS transistor.

  As described above, in the second embodiment, as in the first embodiment, unlike the example shown in FIG. 12 in the prior art, the charging current in either direction flows to the protection diode, and the gate Since it does not flow to the insulating film 6, it is possible to reduce the deterioration of the characteristics of the semiconductor device due to the breakdown of the gate insulating film 6.

  Thereafter, as shown in FIG. 7D, a Cu layer 14 for forming a metal wiring is formed by electroplating, and further CMP is performed to complete the semiconductor device according to the second embodiment. In the second embodiment, a multilayer wiring can be formed by further providing an inter-wiring insulating film or a metal wiring. Also in the second embodiment, similarly to the first embodiment, a protection diode B having a polarity different from that of the protection diode A and electrically connected to the protection diode A by a metal wiring can be provided.

  Here, with reference to FIG. 8, the semiconductor device according to the second embodiment is compared with the conventional semiconductor device shown in FIG. FIG. 8 is a graph showing reliability evaluation between the semiconductor device in the second embodiment and a conventional semiconductor device.

  In FIG. 8, the horizontal axis indicates the lifetime [s] during the constant voltage TDDB test, which is an index of the reliability lifetime. The vertical axis represents the cumulative failure rate when the Weibull distribution is assumed. In FIG. 8, the device structure is the same as the example of FIG. The stress current value is set to 3.0V.

  As can be seen from FIG. 8, when the cumulative defect rate is the same, the semiconductor device in the present embodiment 2 (“●” in FIG. 8) is different from the conventional semiconductor device (“□” in FIG. 8). Life is getting longer. Thus, according to the second embodiment, plasma charging damage can be reduced as compared with the conventional example.

(Embodiment 3)
Next, a semiconductor device manufacturing method and a semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS. FIG. 9 is a partial cross-sectional view showing a method for manufacturing a semiconductor device according to the third embodiment of the present invention, and FIGS. 9A to 9C show a series of main steps. FIG. 10 is a perspective view showing a trench formed in the step shown in FIG. FIG. 9C also shows the semiconductor device according to the second embodiment of the present invention. In FIGS. 9 and 10, the same components as those shown in FIGS. 1 and 2 are denoted by the same reference numerals.

  First, as shown in FIG. 9A, on a p-type silicon substrate 1 on which an n-channel MOS transistor and a protection diode A are formed, a first insulating film 7, a stopper film 9, and Two insulating films 10 are sequentially formed. Further, the second insulating film 10 is etched to form a trench 41 for forming a metal wiring.

  The process shown in FIG. 8A is performed in the same manner as the process shown in FIG. 12A in the prior art, but in the third embodiment, as can be seen from FIG. Is formed to be inclined.

  Further, in general, in dry etching, the side surface of the trench in the longitudinal direction is inclined as shown in FIGS. 9 and 10 due to the influence of etching by-products, but the inclination angle (based on the thickness direction of the silicon substrate 1) The angle θ is usually about 0 to 4 degrees. Furthermore, with this degree of inclination, the barrier film 13 is first formed on the upper surface of the inter-wiring insulating film 10 and the bottom surface of the trench 41 as shown in FIG. It is hard to be inclined on the side.

  On the other hand, in the present third embodiment, the inclination angle of the side surface of the trench 41 is 5 ° to 20 ° in order to efficiently discharge the current to the outside of the trench when the coverage characteristic of the barrier film 13 and the metal wiring are formed. Is set to degrees.

  Therefore, also in the third embodiment, as in the second embodiment, the side surface of the trench 41 is gentler than the step portion 116 shown in FIG. 12 in the prior art, and the barrier film 13 is formed. Easy to shape. Therefore, as shown in FIG. 9B, when the barrier film 13 is formed by the plasma process, the barrier film 13 is formed almost simultaneously on the upper surface of the second insulating film 10, the bottom surface of the trench 41, and the side surfaces. Will progress.

  Therefore, also in the third embodiment, the barrier film 13 electrically connected to the gate electrode 8 is electrically isolated from the other barrier films as shown in FIG. Since the state is avoided, as in the second embodiment, the charging current flows to the protection diode regardless of the direction. Therefore, characteristic deterioration of the semiconductor device due to the breakdown of the gate insulating film 6 can be reduced.

  In the third embodiment, the inclination angle θ on the side surface of the trench 41 is adjusted by setting the pattern shape for forming the trench 41. Specifically, as shown in FIG. 10, the putter shape is set so that, for example, the value of WL / WT is in the range of 50 to 100 so that the trench length WL is sufficiently longer than the trench width WT. Is done by doing. In the example of FIG. 10, the trench length WL is set to 10 μm, the trench width WT is set to 0.2 μm, and WL / WT is set to 50.

Further, in order to set the inclination angle θ of the side surface of the trench 41 within the above range, the etching for forming the trench 41 is performed by setting the flow rate of CF ₄ gas to 3.5 × 10 ⁻³ [l / min] (35 sccm), CHF. _{3 The} gas flow rate is set to 9.0 × 10 ⁻³ [l / min] (90 sccm), the pressure is set to 1.33 [Pa] (10 mTorr), the discharge power is set to 1 kW, and an inductively coupled plasma apparatus is used. It has been broken.

  When the step shown in FIG. 9B is completed, as shown in FIG. 9C, a Cu layer 14 for forming a metal wiring is formed by electroplating, and further CMP is performed, so that the third embodiment is performed. The semiconductor device is completed. In the third embodiment, a multilayer wiring can be formed by further providing an inter-wiring insulating film or a metal wiring. Also in the third embodiment, similarly to the first embodiment, a protection diode B having a polarity different from that of the protection diode A and electrically connected to the protection diode A by a metal wiring can be provided.

  Here, with reference to FIG. 11, the semiconductor device according to the third embodiment is compared with the conventional semiconductor device shown in FIG. FIG. 11 is a graph showing evaluation of electrical characteristics of the semiconductor device according to the third embodiment and a conventional semiconductor device. The graph shown in FIG. 11 is obtained under the same conditions as in FIG.

Also in FIG. 11, the horizontal axis represents the gate current density [A / cm ² ] when a gate voltage of 1.2 V is applied. The vertical axis represents the cumulative failure probability when a Gaussian distribution is assumed.

  As can be seen from FIG. 11, the gate leakage current value is increased in the conventional semiconductor device as compared with the semiconductor device in the third embodiment. This indicates that the device characteristics of the conventional semiconductor device are degraded due to plasma charging damage as compared with the semiconductor device of the third embodiment. That is, FIG. 11 suggests that the plasma charging damage can be reduced according to the first embodiment as compared with the conventional case.

  The method for manufacturing a semiconductor device and the semiconductor device according to the present invention suppress charging damage of the semiconductor device due to the plasma process, and are useful for improving the reliability of the semiconductor device.

FIG. 1 is a partial cross-sectional view showing a method for manufacturing a semiconductor device in Embodiment 1 of the present invention, and FIGS. 1A to 1C show a series of main steps. FIG. 2D is a partial cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and FIGS. 2D to 2F illustrate a series of main steps subsequent to the step illustrated in FIG. 1. . It is a perspective view which shows the trench formed at the process shown to Fig.1 (a). It is a figure which shows the relationship between the etching width | variety and the width | variety of the trench for wiring formation. 5 is a graph showing an electrical characteristic evaluation between the semiconductor device in the first embodiment and a conventional semiconductor device. FIG. 6 is a partial cross-sectional view showing another example of the method for manufacturing a semiconductor device in the first embodiment of the present invention, and FIGS. 6A to 6C show a series of main steps. FIG. 7A is a partial cross-sectional view showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention, and FIGS. 7A to 7D show a series of main steps. 10 is a graph showing reliability evaluation between the semiconductor device in the second embodiment and a conventional semiconductor device. FIG. 9A is a partial cross-sectional view showing a method for manufacturing a semiconductor device in a third embodiment of the present invention, and FIGS. 9A to 9C show a series of main steps. It is a perspective view which shows the trench formed at the process shown to Fig.9 (a). 10 is a graph showing an evaluation of electrical characteristics between the semiconductor device in the third embodiment and a conventional semiconductor device. It is sectional drawing which shows the formation process of the conventional damascene structure, and Fig.12 (a)-FIG.12 (c) have shown a series of main processes. It is sectional drawing which shows the formation process of the conventional damascene structure, and FIG.13 (d)-FIG.13 (e) have shown the series of main processes following the process shown in FIG.

Explanation of symbols

1 p-type silicon substrate 2 element isolation 3 p-well (active region in which a transistor is formed)
4a source (n +) region 4b drain (n +) region 5 n-type diffusion layer 6 gate oxide film (2.2 nm)
7 First insulating film (interlayer insulating film (400 nm))
8 Gate electrode,
9 Stopper film (silicon nitride film)
10 Second insulating film (inter-wiring insulating film)
11a, 11b, 11c Plug electrode 12 Side wall 13 Barrier film (Ta / TaN film (20 nm))
14 Cu layer (500 nm)
15, 32, 41 Trench 15a First trench 15b Second trench 15c Third trench 16 Stepped portion 17 on the side of the trench Stepped portion 18a between the first trench and the second and third trenches, 18b metal wiring 21 n well 22 p + type diffusion layer 31 sidewalls A and B formed in the trench protection diode

Claims (15)

(A) a step of sequentially forming a first insulating film and a second insulating film covering the semiconductor substrate on which the MOS transistor and the diode are formed; and (b) etching into the second insulating film. (C) forming a trench for forming a metal wiring electrically connected to the MOS transistor and the diode, and (c) forming a barrier film containing tantalum on a side surface and a bottom surface of the trench by a plasma process. Forming a metal film on the barrier film; and (d) a method of manufacturing a semiconductor device including at least a step of forming a metal wiring by performing CMP on the metal film,
Two types of diodes having different polarities are formed on the semiconductor substrate,
In the step (b), a first trench for forming a metal wiring electrically connected to the gate electrode of the MOS transistor, and a metal wiring electrically connected to the active regions of the two types of diodes A second trench for forming the first trench and a third trench connected to the first trench and the second trench and formed shallower than the first and second trenches,
In the step (d), the CMP is performed until at least the third trench disappears.   The third trench causes the etching rate in the region where the third trench is formed to be slower than the etching rate in the region where the first and second trenches are formed, thereby allowing the first and The method of manufacturing a semiconductor device according to claim 1, wherein the method is formed shallower than the second trench.   The etching rate in the region where the third trench is formed by the RIE-Lag phenomenon generated by making the width of the third trench narrower than the width of the first and second trenches is the first rate. 3. The method for manufacturing a semiconductor device according to claim 2, wherein the etching rate is slower than an etching rate in a region where the second trench is formed. (A) a step of sequentially forming a first insulating film and a second insulating film covering the semiconductor substrate on which the MOS transistor and the diode are formed; and (b) etching into the second insulating film. And forming a trench for forming a metal wiring electrically connected to the MOS transistor and the diode, and (c) forming a barrier film containing tantalum on a side surface and a bottom surface of the trench by a plasma process. Forming a metal film on the barrier film; and (d) a method of manufacturing a semiconductor device including at least a step of forming a metal wiring by performing CMP on the metal film,
Before the step (c) is performed, a third insulating film that covers at least the side surface of the trench is formed, and the third insulating film is etched back to form a sidewall protective film on the side surface of the trench. A method for manufacturing a semiconductor device, comprising: a step.   The method of manufacturing a semiconductor device according to claim 4, wherein the trench is formed so that a value obtained by dividing the thickness of the second insulating film by the width of the trench is smaller than 2. 6. Two types of diodes having different polarities are formed on the semiconductor substrate,
5. The method of manufacturing a semiconductor device according to claim 4, wherein the trench is formed so that a metal wiring formed thereby is electrically connected to an active region of the two types of diodes.   The method for manufacturing a semiconductor device according to claim 4, wherein the third insulating film is a silicon insulating film or a silicon nitride film containing at least oxygen. (A) a step of sequentially forming a first insulating film and a second insulating film covering the semiconductor substrate on which the MOS transistor and the diode are formed; and (b) etching into the second insulating film. (C) forming a trench for forming a metal wiring electrically connected to the MOS transistor and the diode, and (c) forming a barrier film containing tantalum on a side surface and a bottom surface of the trench by a plasma process. Forming a metal film on the barrier film; and (d) a method of manufacturing a semiconductor device including at least a step of forming a metal wiring by performing CMP on the metal film,
Two types of diodes having different polarities are formed on the semiconductor substrate,
A first metal wiring electrically connected to the gate electrode of the MOS transistor and a second metal wiring electrically connected to an active region of the two types of diodes by the step (d); A third metal wiring that electrically connects the first metal wiring and the second metal wiring and has a lower surface positioned higher than the lower surfaces of the first and second metal wirings is formed. As described above, the trench is formed in the step (b),
In the step (d), the CMP is performed until at least the first metal wiring and the second metal wiring are electrically separated from each other. (A) a step of sequentially forming a first insulating film and a second insulating film covering the semiconductor substrate on which the MOS transistor and the diode are formed; and (b) etching into the second insulating film. And forming a trench for forming a metal wiring electrically connected to the MOS transistor and the diode, and (c) forming a barrier film containing tantalum on a side surface and a bottom surface of the trench by a plasma process. Forming a metal film on the barrier film; and (d) a method of manufacturing a semiconductor device including at least a step of forming a metal wiring by performing CMP on the metal film,
Before the step (b) is performed, an etching pattern for forming the trench is formed so that the side surface of the trench is inclined within a range of 5 degrees to 20 degrees with respect to the thickness direction of the semiconductor substrate. A method for manufacturing a semiconductor device, comprising the step of: Two types of diodes having different polarities are formed on the semiconductor substrate,
10. The method of manufacturing a semiconductor device according to claim 9, wherein the trench is formed so that a metal wiring formed thereby is electrically connected to an active region of the two types of diodes. A semiconductor substrate on which a MOS transistor and a diode are formed; a first insulating film covering the MOS transistor and the diode; a second insulating film formed on an upper layer of the first insulating film; and the MOS transistor And a semiconductor device having at least a metal wiring electrically connected to the diode,
The metal wiring has a multilayer structure embedded in a trench formed in the second insulating film and having at least a layer containing tantalum,
A side wall of the trench is provided with a side wall protective film having a curved surface on the metal wiring side.   12. The semiconductor device according to claim 11, wherein the width of the trench is set so that a value obtained by dividing the thickness of the second insulating film by the width of the trench is smaller than 2. Two types of diodes having different polarities are formed on the semiconductor substrate,
The semiconductor device according to claim 11, wherein the metal wiring is electrically connected to active regions of the two types of diodes. A semiconductor substrate on which a MOS transistor and a diode are formed; a first insulating film covering the MOS transistor and the diode; a second insulating film formed on an upper layer of the first insulating film; and the MOS transistor And a semiconductor device having at least a metal wiring electrically connected to the diode,
The metal wiring has a multilayer structure embedded in a trench formed in the second insulating film and having at least a layer containing tantalum,
A side surface of the trench is inclined in a range of 5 degrees to 20 degrees with respect to a thickness direction of the semiconductor substrate. Two types of diodes having different polarities are formed on the semiconductor substrate,
The semiconductor device according to claim 14, wherein the metal wiring is electrically connected to active regions of the two types of diodes.

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