JP2013016721A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent increase in resistivity of wiring caused by charge transfer in high density between a floating wiring and washing water.SOLUTION: In a manufacturing process performed by a semiconductor manufacturing apparatus, a connection via PL2 that electrically functions and a dummy via DP2 that does not electrically functions are formed on a top face of a first layer wiring L1 that is a floating copper wiring insulated from a semiconductor substrate 1S and the like, and connected with each other. Because of this, when charge accumulated on the first layer wiring L1 transfers in a cleaning process after forming a via hole for forming the connection via PL2 on the top face of the first layer wiring L1, the charge is prevented from concentrating only on a bottom of the via hole for forming the connection via PL2 by dispersing the charge also on the via hole for forming the dummy via DP2.

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to the manufacture of a semiconductor device including a wiring having a laminated structure.

  In recent years, as the miniaturization of a semiconductor device progresses, the wiring width in the semiconductor device is narrowed, and the width of the via for electrically connecting the lower layer wiring and the upper layer wiring is becoming smaller. For wiring of semiconductor devices, wiring having copper (Cu) as a main conductor is often used.

  In Patent Document 1 (Japanese Patent Laid-Open No. 2009-60034), a dummy via that does not contribute to electrical connection is provided in addition to the via that connects the lower layer wiring and the upper layer wiring in order to prevent the occurrence of disconnection failure of the via. It is described that it is connected to the upper part of the lower layer wiring. Here, by forming the width of the dummy via narrower than the width of the electrically functioning via, a void is easily formed at the bottom of the dummy via, and the void is formed at the bottom of the electrically functioning via. Is preventing. Patent Document 1 does not describe whether the lower layer wiring is in a floating state in which it is not connected to a substrate or another wiring.

  In Patent Document 2 (Japanese Patent Laid-Open No. 2010-34216), a dummy wiring that does not function electrically is formed adjacent to an electrically functioning wiring, and via holes are formed on the wiring and the dummy wiring, respectively. It is described that the formation increases the number of reaction points on the surface of the wiring due to the charge accumulated in each wiring, and the charge is dispersed to prevent the formation of oxide on the surface of the wiring.

JP 2009-60034 A JP 2010-34216 A

  In recent years, the number of in-vehicle semiconductor devices has been increasing, and these in-vehicle semiconductor devices are required to have a defect rate close to zero from the viewpoint of safety. However, an increase in the resistance of the connection via due to the wiring formation has been confirmed in the in-vehicle semiconductor device, and it is an important issue to prevent the occurrence of this defect.

  When forming a lower layer wiring in contact with the bottom of a via constituting such a semiconductor device, or a gate electrode connected to the lower layer wiring, the wiring is formed on a substrate or other wiring before the via is formed. May be in a floating state that is not electrically connected to. For example, when forming a via on a wiring, after depositing an insulating film on the upper part of the floating wiring as described above, a via hole exposing the upper surface of the wiring is opened by an etching method, and the via is embedded in the via hole. Form with. At this time, after the via hole is formed and before the via is formed, in order to remove residues generated by the etching process in which the via hole is formed, cleaning with a chemical solution and pure water (ultra pure water) are performed. It is necessary to sequentially perform cleaning (rinse cleaning) using

  A charge is accumulated in the wiring in a floating state insulated from other conductors by performing a semiconductor process such as dry etching. After that, when the electric charge accumulated in the wiring moves in the cleaning water used for the rinse cleaning, the copper constituting the wiring in the vicinity of the bottom of the via hole is melted, and a part of the wiring disappears and the wiring is cut off. There is a problem that the semiconductor device does not operate normally. This leads to a decrease in the reliability of the semiconductor device.

  Similarly, after a contact plug mainly including tungsten (W) or the like is formed on a wiring in a floating state, the wiring is charged when an upper layer wiring including copper or the like is formed on the contact plug. A large charge escapes to the upper layer wiring through the contact plug. At this time, if a large current flows through the contact plug, a high-resistance layer is formed between the contact plug and the upper wiring, and some of the contact plugs formed on the wafer Since the resistance value of the semiconductor device increases, there arises a problem that the performance of the semiconductor device varies.

  An object of the present invention is to prevent a part of wiring containing copper from disappearing.

  Another object of the present invention is to prevent an increase in wiring resistance.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to a preferred embodiment of the present invention electrically functions on the upper surface of a first layer wiring that is a copper wiring that is in a floating state insulated from a semiconductor substrate or the like during the manufacturing process of the semiconductor manufacturing apparatus. The connection via and the dummy via which does not function electrically are connected to each other. Accordingly, when the charge accumulated in the first layer wiring moves into the cleaning water during the cleaning step after forming the via hole for forming the connection via on the upper surface of the first layer wiring, the charge is used for forming the dummy via. Also, the charge is prevented from concentrating only at the bottom of the via hole for forming the connection via.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  It is possible to prevent a part of the wiring containing copper from disappearing.

  In addition, an increase in wiring resistance can be prevented.

It is sectional drawing which shows the semiconductor device which is Embodiment 1 of this invention. It is sectional drawing which shows the modification of the semiconductor device which is Embodiment 1 of this invention. 7 is a cross-sectional view for illustrating a manufacturing step of the semiconductor device of the first embodiment. FIG. FIG. 4 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 3; FIG. 5 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; FIG. 6 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; FIG. 7 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 6; FIG. 8 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7; FIG. 9 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 8; FIG. 10 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 9; FIG. 11 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 10; FIG. 12 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; FIG. 13 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12; FIG. 14 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 13; FIG. 15 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 14; FIG. 16 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 15; FIG. 17 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 16; FIG. 18 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 17; FIG. 19 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 18; FIG. 20 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 19; FIG. 21 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 20; FIG. 22 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 21; FIG. 23 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 22; FIG. 24 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 23; FIG. 25 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 24; FIG. 26 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 25; FIG. 27 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 26; FIG. 28 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 27; FIG. 29 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 28; FIG. 30 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 29; It is sectional drawing which shows the semiconductor device which is Embodiment 2 of this invention. It is sectional drawing which shows the modification of the semiconductor device which is Embodiment 2 of this invention. It is sectional drawing of the semiconductor device which is a comparative example. It is sectional drawing of the semiconductor device which is a comparative example. It is the graph which showed the relationship of the contact resistance of a contact plug and wiring. It is the graph which showed the relationship of the contact resistance of a contact plug and wiring. It is the graph which showed the relationship between the length of wiring, and the length of a void. It is the graph which showed the relationship between the length of wiring, and defect incidence.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

(Embodiment 1)
The semiconductor device of this embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view of the semiconductor device of the present embodiment, which is a cross-sectional view in a plane perpendicular to the main surface of the semiconductor substrate 1S. FIG. 1 shows a plurality of MISFETs (Metal Insulator Semiconductor Field Effect Transistors) formed on the main surface of the semiconductor substrate 1S, wirings for supplying a predetermined potential to each MISFET, vias and contact plugs, An interlayer insulating film for embedding them is shown.

  In FIG. 1, MISFETs Q1 and Q2 are formed on a semiconductor substrate 1S made of silicon single crystal. Each of the MISFETs Q1 and Q2 shown in FIG. 1 is formed in an active region isolated by an element isolation region, and has, for example, the following configuration. Specifically, a plurality of p wells PW having a p-type conductivity are formed in the active region isolated by the element isolation region, and the MISFET Q1 or MISFET Q2 is formed on the plurality of p wells PW. The MISFETs Q1 and Q2 are n-channel MISFETs having a gate electrode made of, for example, a polysilicon film formed on a main surface of the semiconductor substrate 1S through a gate insulating film made of a silicon oxide film. . The MISFET Q1 has a gate electrode G1, and the MISFET Q2 has a gate electrode G2.

  Side walls including, for example, a silicon oxide film are formed on the side walls on both sides of the gate electrode, and an impurity diffusion region having a shallow n-type conductivity is aligned with the gate electrode in the semiconductor substrate 1S below the side wall. Is formed. Outside the shallow impurity diffusion region, an impurity diffusion region having an n-type conductivity and deeper than the shallow impurity diffusion region is formed in alignment with the sidewall. Hereinafter, the n-type deep impurity diffusion layer is referred to as an n-type diffusion layer NS. The pair of shallow impurity diffusion regions and the pair of n-type diffusion layers NS form source and drain regions of the MISFETs Q1 and Q2, respectively. Both the shallow impurity diffusion region and the n-type diffusion layer NS have an n-type conductivity, and impurities are introduced into the n-type diffusion layer NS at a higher concentration than the shallow impurity diffusion layer. As described above, the MISFETs Q1 and Q2 are formed on the semiconductor substrate 1S.

  In other regions on the semiconductor substrate 1S, a p-well PW is formed on the main surface of the semiconductor substrate 1S, and a p-type impurity diffusion region having an impurity concentration higher than that of the p-well PW is formed on the upper surface of the p-well PW. A p-type diffusion layer PS is formed. The MISFETs Q1, Q2 and the p-type diffusion layer PS are separated by an element isolation region formed on the main surface of the semiconductor substrate 1S.

  As shown in FIG. 1, a contact interlayer insulating film CIL is formed on the semiconductor substrate 1S on which the MISFETs Q1 and Q2 and the p-type diffusion layer PS are formed so as to cover the MISFETs Q1 and Q2. The contact interlayer insulating film CIL is provided on, for example, an ozone TEOS film formed by a thermal CVD (Chemical Vapor Deposition) method using ozone and TEOS (Tetra Ethyl Ortho Silicate) as raw materials. It is formed of a laminated film with a plasma TEOS film formed by a plasma CVD method using TEOS as a raw material.

A plurality of plugs (contact plugs) PL1 that penetrate through the contact interlayer insulating film CIL and reach the source region, drain region, gate electrode, or p-type diffusion layer PS of the MISFETs Q1 and Q2 are formed. The plug PL1 includes a barrier conductor film made of, for example, a titanium / titanium nitride film (hereinafter, the titanium / titanium nitride film indicates a film formed of a titanium film and a titanium nitride film provided on the titanium film), The tungsten film formed on the barrier conductor film is buried in a contact hole penetrating the contact interlayer insulating film CIL. The titanium / titanium nitride film is a film provided to prevent tungsten constituting the tungsten film from diffusing into silicon, and WF ₆ (tungsten fluoride) at the time of forming the tungsten film is used. This is to prevent the fluorine attack from damaging the contact interlayer insulating film CIL or the semiconductor substrate 1S in the CVD method for reduction treatment. The contact interlayer insulating film CIL may be formed of any one of a silicon oxide film (SiO ₂ film), a SiOF film, or a silicon nitride film.

  A plurality of first layer wirings L1 are formed on the contact interlayer insulating film CIL. Specifically, the first layer wiring L1 is formed so as to be embedded in the interlayer insulating film IL1 formed on the contact interlayer insulating film CIL on which the plug PL1 is formed, and the first layer wiring L1 is formed in the interlayer insulating film IL1. It is formed in contact with. The interlayer insulating film IL1 and the first layer wiring L1 have the same film thickness (height), and their upper surfaces are flat and located at the same height. That is, the first layer wiring L1 is formed so as to penetrate the interlayer insulating film IL1. The interlayer insulating film IL1 is composed of, for example, a Low-k film having a relative dielectric constant lower than that of the passivation film PAS formed in the upper layer of the semiconductor substrate 1S, and is composed of, for example, a SiOC film.

  The first layer wiring L1 is an interlayer insulating film after a film (hereinafter referred to as a copper film) mainly composed of copper (Cu) is buried in a wiring groove that penetrates the interlayer insulating film IL1 and exposes the plug PL1 at the bottom. This is a damascene wiring formed by polishing and removing the copper film on IL1. At this time, the first layer wiring L1 is formed in the lower portion of the wiring trench, and at the same time, a via which is a connection portion for electrically connecting the first layer wiring L1 and the lower conductor film (for example, the plug PL1) is formed. Not. That is, the first layer wiring L1 is a single damascene wiring formed by a single damascene method. Although not shown in FIG. 1, a barrier conductor film containing tantalum (Ta) or the like is formed between the inner wall and bottom of the wiring groove and the copper film, as in the plug described above. In the present application, the layer including the first layer wiring L1 and the interlayer insulating film IL1 in the same layer as the first layer wiring L1 may be referred to as a first fine layer. Although not shown, it is assumed that there is an etching stopper film made of silicon nitride or the like between the contact interlayer insulating film CIL and the interlayer insulating film IL1.

  Here, the wiring in the case where only the wiring is formed in the same layer of the insulating film by using the damascene method is referred to as single damascene wiring. Also, the method of forming the integrated wiring and via by filling the wiring groove and via hole opened in the insulating film using the damascene method in the same process and simultaneously forming the wiring and via is called the dual damascene method. And

  In the figure, the plug PL1 is connected to the gate electrode G1 of the MISFET Q1, and the plug PL1 is connected to the n-type diffusion layer NS that is the source / drain region of the MISFET Q2. In other regions not shown, the gate of the MISFET Q2 is connected. A plug is connected to the electrode G2, and the plug is connected to the n-type diffusion layer NS which is the source / drain region of the MISFET Q1. Although not shown, a metal silicide layer made of, for example, nickel silicide is formed on the upper surfaces of the gate electrodes G1, G2, the n-type diffusion layer NS, and the p-type diffusion layer PS, and the gate electrodes G1, G2 The contact resistance between the n-type diffusion layer NS and the p-type diffusion layer PS and the plug PL1 above them is reduced.

  On the interlayer insulating film IL1 on which the first layer wiring L1 is formed, an interlayer insulating film IL2 and a plurality of second layer wirings L2 in contact with the interlayer insulating film IL2 are formed. Specifically, a barrier insulating film BI1 is formed on the interlayer insulating film IL1 on which the first layer wiring L1 is formed, and an interlayer insulating film IL2 is formed on the barrier insulating film BI1. The barrier insulating film BI1 is made of, for example, a laminated film of a SiCN film and a SiOC film provided on the SiCN film, a SiC film, an amorphous carbon film, a boron fluoride film, or a SiN film. The barrier insulating film BI1 and the interlayer insulating film IL2 are formed so that a plurality of second layer wirings L2 and a plurality of connection vias PL2 which are damascene wirings are embedded. The second layer wiring L2 is electrically connected to the first layer wiring L1 through the connection via PL2. The second layer wiring L2 and the connection via PL2 are made of, for example, a metal film mainly composed of copper. The barrier insulating film BI1 is formed between a metal wiring mainly made of copper (for example, the first layer wiring L1) and an interlayer insulating film (for example, the interlayer insulating film IL2), and metal ions in the metal wiring are formed in the interlayer insulating film. It is a film having a function of preventing diffusion into the inside.

  The second layer wiring L2 is formed in a wiring groove formed in the interlayer insulating film IL2, and the connection via PL2 is formed in a via hole penetrating from the bottom of the wiring groove formed in the interlayer insulating film IL2 to the first layer wiring L1. It is a conductor film made of a copper film embedded by the same process. Specifically, a copper film is formed on the interlayer insulating film IL2 in which the plurality of wiring grooves and the plurality of via holes are formed, thereby filling the plurality of wiring grooves and the plurality of via holes with the copper film. Thereafter, the copper film on the interlayer insulating film IL2 is polished and removed to form a plurality of second layer wirings L2 and a plurality of connection vias PL2. That is, the second layer wiring L2 and the connection via PL2 are formed by a dual damascene method.

  On the upper surface of the first layer wiring L1 connected to the gate electrode G1 of the MISFET Q1 via the plug PL1, in addition to the connection via PL2, the dummy via DP2 having the same structure as the connection via PL2 is formed in contact with the dummy via. A dummy wiring D2 formed in the same manner as the second layer wiring L2 is formed on DP2. The dummy via DP2 and the dummy wiring D2 are made of a copper film formed by using the dual damascene method in the same process as the connection via PL2 and the second layer wiring L2, and have a structure in which the wiring and the connection via are integrated. ing. However, the second-layer wiring L2 is connected to the upper-layer wiring via an upper-layer connection via PL3 connected to the upper surface thereof, and is used as a part of the circuit of the semiconductor device, whereas the dummy wiring D2 has a conductive surface on the upper surface. And is connected only to the first layer wiring L1 through the dummy via DP2. That is, the dummy wiring D2 is electrically connected to the first layer wiring L1 through the dummy via DP2, but is not electrically functioning in the semiconductor device shown in FIG. The dummy via DP2 and the connection via PL2 are electrically connected to the gate electrode G1 made of a polysilicon film via the first layer wiring L1 and the plug PL1.

  Further, the second layer wiring L2 electrically connected to the n-type diffusion layer NS of the MISFET Q2 is other than the first layer wiring L1 via vias connected to the upper surface or the lower surface in other regions not shown. And functions as part of a circuit for supplying a predetermined potential to the MISFET Q2. The width of the dummy via DP2 in the direction along the main surface of the semiconductor substrate 1S is the same as that of the connection via PL2 in the same layer in the same direction. That is, the dummy via DP2 and the connection via PL2 are formed according to the same rule (standard), have the same diameter (diameter), and have the same shape. Therefore, the area where the dummy via DP2 and the first layer wiring L1 are in contact with the area where the connection via PL2 and the first layer wiring L1 are in contact has the same size.

  When manufacturing the semiconductor device of the present embodiment, a gate electrode, an interlayer insulating film, a wiring, or the like is formed in order from the semiconductor substrate 1S side, so that a first layer wiring L1 connected to the gate electrode G1 is formed. At this time, the first layer wiring L1 is connected only to the gate electrode G1 insulated from the semiconductor substrate 1S by the gate insulating film, and is not connected to the semiconductor substrate 1S or other wiring. That is, in the manufacturing process of the semiconductor device, the first layer wiring L1 connected to the gate electrode G1 is in a floating state insulated from the semiconductor substrate 1S and the like, and the barrier insulating film BI1 and the interlayer insulating film IL2 are formed thereon. Subsequently, an opening made of a wiring trench and a via hole penetrating the barrier insulating film BI1 and the interlayer insulating film IL2 is formed, and the upper surface of the first layer wiring L1 is exposed.

  It is conceivable that the wiring groove and the via hole are formed by an etching method using a photolithography technique. However, an etching residue remains on the semiconductor substrate 1S after the wiring groove and the via hole are formed by this etching method. In order to remove the residue and the like, the main surface of the semiconductor substrate 1S is washed with a chemical solution, and then further washed with water (pure water). In addition, when etching is performed so that the upper surface of the first layer wiring L1 is exposed in this way, there is a high possibility that charges are accumulated in the first layer wiring L1.

  Similarly to the second layer wiring L2, the third layer wiring L3 to the fifth layer wiring L5 are formed on the second layer wiring L2. Each of third layer wiring L3 to fifth layer wiring L5 is formed in contact with each of interlayer insulating films IL3 to IL5.

  Specifically, a barrier insulating film BI2 is formed on the interlayer insulating film IL2, on the dummy wiring D2 and on the second layer wiring L2, in contact with the interlayer insulating film IL2 and the second layer wiring, and on the barrier insulating film BI2. An interlayer insulating film IL3 is formed, and the upper surfaces of the second layer wiring and the interlayer insulating film IL2 are in contact with the barrier insulating film BI2. For example, the barrier insulating film BI2 is formed of any one of a SiCN film and a laminated film of a SiOC film provided on the SiCN film, a SiC film, or a SiN film. For example, it is formed from a SiOC film. In the barrier insulating film BI2 and the interlayer insulating film IL3, third-layer wirings L3 and L3a and a connection via PL3 are formed to be embedded. The third layer wiring L3 is electrically connected to the second layer wiring L2 through the connection via PL3. The third layer wirings L3, L3a and the connection via PL3 are formed from, for example, a copper film, and the third layer wiring L3 and the lower connection via PL3 are formed from an integral copper film formed by a dual damascene method. ing.

  In the same layer as the third layer wiring L3, a third layer wiring L3a having no via in contact with the lower surface is formed. That is, the entire lower surface of the third layer wiring L3a is in contact with the interlayer insulating film IL3, and the third layer wiring L3a is not electrically connected to other conductors through the lower surface.

  When manufacturing the semiconductor device of the present embodiment, an interlayer insulating film or wiring is formed in order from the semiconductor substrate 1S side, so that the third layer wiring L3a to which no connection via is connected is formed on the lower surface. At the time, the third layer wiring L3a is in a floating state insulated from the semiconductor substrate 1S or other wiring. That is, until the connection via formed on the third layer wiring L3a in the manufacturing process of the semiconductor device is connected to the wiring connected to the semiconductor substrate 1S or the like, the third layer wiring L3a is electrically connected to other conductors. It becomes a floating state insulated by. Therefore, when the third layer wiring L3a is formed, it is in a floating state. When the connection via is formed on the third layer wiring L3a, first, a barrier insulating film and an interlayer insulating film are formed on the third layer wiring L3a. Subsequently, an opening made of a wiring groove and a via hole penetrating the barrier insulating film and the interlayer insulating film is formed, and the upper surface of the third layer wiring L3a is exposed.

  It is conceivable that the wiring groove and the via hole are formed by an etching method using a photolithography technique. However, an etching residue remains on the semiconductor substrate 1S after the wiring groove and the via hole are formed by this etching process. In order to remove the residue and the like, the surface of the semiconductor substrate 1S is washed with a chemical solution, and then further washed with water (pure water).

  Next, a barrier insulating film BI3 is formed on the interlayer insulating film IL3, the third layer wiring L3, and the third layer wiring L3a in contact with the interlayer insulating film IL3 and the third layer wirings L3 and L3a. An interlayer insulating film IL4 is formed over the film BI3. The barrier insulating film BI3 is formed of, for example, any one of a laminated film of a SiCN film and a SiOC film provided on the SiCN film, a SiC film, or a SiN film, and the interlayer insulating film IL4 is For example, it is formed from a SiOC film. In the barrier insulating film BI3 and the interlayer insulating film IL4, a fourth layer wiring L4, a dummy wiring D4, a connection via PL4, and a dummy via DP4 are formed to be embedded. The fourth layer wiring L4 is electrically connected to the third layer wiring L3 or the third layer wiring L3a through the connection via PL4. The dummy wiring D4 is electrically connected to the third layer wiring L3a through the dummy via DP4. The fourth layer wiring L4, the dummy wiring D4, the dummy via DP4, and the connection via PL4 are made of, for example, a copper film and are formed by a dual damascene method.

  The connection via PL4 formed in contact with the upper surface of the third layer wiring L3a and the fourth layer wiring L4 integrated with the connection via PL4 are connected to the third layer via the via formed in contact with the upper surface or the lower surface. It is electrically connected to a wiring other than the wiring L3a. For example, one of the connection vias PL4 formed in contact with the upper surface of the third layer wiring L3a is electrically connected to a fifth layer wiring L5 described later via the connection via PL5 in contact with the upper surface. The other connection via PL4 that is connected and formed in contact with the upper surface of the third layer wiring L3a is connected to another wiring in a region not shown. Therefore, the third layer wiring L3 is connected to another wiring via the plurality of connection vias PL4 and the fourth layer wiring L4 formed on the upper surface thereof, and functions as a part of the circuit of the semiconductor device.

  On the upper surface of the third layer wiring L3a, a dummy wiring D4 and a dummy via DP4 formed by the same process as the connection via PL4 and the fourth layer wiring L4 are formed. The dummy wiring D4 is connected to the third layer wiring L3a via the dummy via DP4 below the dummy wiring D4. However, the entire upper surface of the dummy wiring D4 is covered with an insulating film, and other wiring that functions as a circuit of the semiconductor device is used. Is not connected. That is, the dummy wiring D4 is connected to the third layer wiring L3a through the dummy via DP4, but is connected to other wiring through a route other than the dummy via DP4 connecting the dummy wiring D4 and the third layer wiring L3a. No. Therefore, dummy wiring D4 and dummy via DP4 are wiring that does not function as a circuit of the semiconductor device shown in FIG. 1, that is, wiring that does not function electrically, like dummy wiring D2 and dummy via DP2.

  The width of the dummy via DP4 in the direction along the main surface of the semiconductor substrate 1S is the same as that of the connection via PL4 in the same layer in the same direction. That is, the dummy via DP4 and the connection via PL4 are formed according to the same rule (standard), have the same diameter (diameter), and have the same shape.

  Further, a barrier insulating film BI4 is formed on the interlayer insulating film IL4, the fourth layer wiring L4, and the dummy wiring D4 in contact with the interlayer insulating film IL4, the fourth layer wiring L4, and the dummy wiring D4. An interlayer insulating film IL5 is formed on BI4. The barrier insulating film BI4 is formed in contact with the entire upper surface of the dummy wiring D4. The barrier insulating film BI4 is formed of, for example, any one of a laminated film of a SiCN film and a SiOC film provided on the SiCN film, a SiC film, or a SiN film, and the interlayer insulating film IL5 is For example, it is formed from a SiOC film. The barrier insulating film BI4 and the interlayer insulating film IL5 are formed so that the fifth layer wiring L5 and the connection via PL5 are embedded. The fifth layer wiring L5 is electrically connected to the fourth layer wiring L4 through the connection via PL5. The fifth layer wiring L5 and the connection via PL5 are made of, for example, a copper film. Here, the second layer wiring L2 to the fifth layer wiring L5 and the interlayer insulating films IL2 to IL5 formed in the same layer may be collectively referred to as a second fine layer in the present application. A plurality of wirings are respectively formed in the interlayer insulating films IL2 to IL5 that are the second fine layers.

  As shown in FIG. 1, the third-layer wiring L3a is electrically connected to the fifth-layer wiring L5 via the connection vias PL4 and PL5 and the fourth-layer wiring L4 above the fifth-layer wiring L5a. L5 is a main surface of the semiconductor substrate 1S via the fourth layer wiring L4, the third layer wiring L3, the second layer wiring L2, the first layer wiring L1, the connection vias PL2 to PL5 and the plug PL1 formed in the lower part thereof. The p-type diffusion layer PS is electrically connected. That is, the third layer wiring L3a is electrically connected to the semiconductor substrate 1S through the via in contact with the upper portion thereof.

  A barrier insulating film BI5 is formed on the interlayer insulating film IL5 and the fifth layer wiring L5 in contact with the interlayer insulating film IL5 and the fifth layer wiring L5, and an interlayer insulating film IL6 is formed on the barrier insulating film BI5. Yes. The barrier insulating film BI5 is formed of, for example, one of a laminated film of a SiCN film and a SiOC film provided on the SiCN film, a SiC film, or a SiN film, and the interlayer insulating film IL6 is For example, it is formed from a SiOC film. The barrier insulating film BI5 and the interlayer insulating film IL6 are formed so that the sixth layer wiring L6 and the connection via PL6 are embedded. The sixth layer wiring L6 is electrically connected to the fifth layer wiring L5 through the connection via PL6. The sixth layer wiring L6 and the connection via PL6 are formed of, for example, a copper film.

  Next, a barrier insulating film BI6 is formed on the interlayer insulating film IL6, and an interlayer insulating film IL7 is formed on the barrier insulating film BI6. The barrier insulating film BI6 is formed of, for example, one of a laminated film of a SiCN film and a SiOC film provided on the SiCN film, a SiC film, or a SiN film, and the interlayer insulating film IL7 is For example, it is formed from a SiOC film. The barrier insulating film BI6 and the interlayer insulating film IL7 are formed so that the seventh layer wiring L7 and the connection via PL7 are embedded. The seventh layer wiring L7 is electrically connected to the sixth layer wiring L6 through the connection via PL7. The seventh layer wiring L7 and the connection via PL7 are made of, for example, a copper film. Here, the sixth layer wiring L6 and the seventh layer wiring L7 may be collectively referred to as a semi-global layer in the present application.

Further, a barrier insulating film BI7a is formed on the interlayer insulating film IL7, and an interlayer insulating film IL8a is formed on the barrier insulating film BI7a. An etching stop insulating film BI7b is formed on the interlayer insulating film IL8a, and an interlayer insulating film IL8b is formed on the etching stop insulating film BI7b. The barrier insulating film BI7a is formed of, for example, one of a laminated film of a SiCN film and a SiOC film, a SiC film, or a SiN film, and the etching stop insulating film BI7b is, for example, a SiCN film, a SiC film The interlayer insulating film IL8a and the interlayer insulating film IL8b are formed of, for example, a silicon oxide film (SiO ₂ film), a SiOF film, or a TEOS film. Yes. The barrier insulating film BI7a and the interlayer insulating film IL8a are formed so that the connection via PL8 and the connection via PL8 are embedded, and the eighth-layer wiring L8 is embedded in the etching stop insulating film BI7b and the interlayer insulating film IL8b. It is formed as follows. The eighth layer wiring L8 is electrically connected to the seventh layer wiring L7 through the connection via PL8. The eighth layer wiring L8 and the connection via PL8 are made of, for example, a copper film. Here, the eighth layer wiring L8 may be referred to as a global layer in the present application.

A barrier insulating film BI8 is formed on the interlayer insulating film IL8b, and an interlayer insulating film IL9 is formed on the barrier insulating film BI8. The barrier insulating film BI8 is formed of, for example, any one of a laminated film of a SiCN film and a SiOC film, a SiC film, or a SiN film, and the interlayer insulating film IL9 is formed of, for example, a silicon oxide film (SiO 2 ₂ film), a SiOF film, and a TEOS film. A connection via PL9 is embedded in the barrier insulating film BI8 and the interlayer insulating film IL9. A ninth layer wiring L9 is formed on the interlayer insulating film IL9. The ninth layer wiring L9 is electrically connected to the eighth layer wiring L8 through the connection via PL9. The connection via PL9 and the ninth layer wiring L9 are made of, for example, an aluminum film.

  A passivation film PAS serving as a surface protective film is formed on the ninth layer wiring L9, and a part of the ninth layer wiring L9 is exposed from the opening formed in the passivation film PAS. The exposed region of the ninth layer wiring L9 becomes the pad PD. The passivation film PAS has a function of protecting the semiconductor device from intrusion of impurities, and is formed of, for example, a silicon oxide film and a silicon nitride film provided on the silicon oxide film. A polyimide film PI is formed on the passivation film PAS. This polyimide film PI also opens an area where the pad PD is formed. The pad PD is a region that becomes an electrode of a semiconductor chip including the semiconductor device shown in FIG. 1, and is a region that is electrically connected to another conductive member via a metal wire or the like in a package on which the semiconductor chip is mounted. is there.

  The barrier insulating films BI1 to BI8 shown in FIG. 1 have a function of preventing Cu (copper) in a copper film in contact with the lower surface of each barrier insulating film from diffusing into an interlayer insulating film or the like on each barrier insulating film. It is a liner film and also functions as an etching stopper film when a via hole is formed in the interlayer insulating film on each barrier insulating film.

  As described above, the semiconductor device of this embodiment includes wirings formed in each of a plurality of layers, and is part of the wiring, and is electrically connected as part of the circuit in the semiconductor device. The wiring that functions in this manner has a via that is in contact with the upper surface of the wiring and does not function electrically. A dummy wiring is formed above the dummy via. In this way, the wiring directly connected to the lower surface of the dummy via is temporarily in a floating state insulated from other conductors in the manufacturing process, and an insulating film is formed in the floating state in the floating state. After the opening is formed, a part of the upper surface is cleaned at the bottom of the opening by cleaning water.

  When the floating wiring is exposed to cleaning water in this way, the wiring near the bottom of the via hole formed on the wiring partially disappears and a void (gap) is formed. Knowing that the wiring becomes high resistance, or that the wiring is cut off, there is a problem that the circuit does not operate, and a semiconductor device in which the disappearance of the wiring does not occur was studied.

  Here, as a comparative example, FIG. 33 shows a cross-sectional view of the semiconductor device in the case where copper constituting the wiring is melted. 33 is an enlarged cross-sectional view of a main part of a semiconductor device as a comparative example. A first layer wiring L1b shown in FIG. 33 is a wiring corresponding to the first layer wiring L1 shown in FIG. The lower surface of the layer wiring L1b and the upper surface of the gate electrode G1 below the first layer wiring L1b are electrically connected by a plug PL1. A second layer wiring L2 is disposed immediately above the first layer wiring L1b, and the first layer wiring L1b and the second layer wiring L2 are connected between the first layer wiring L1b and the second layer wiring L2. A connection via PL2 for this purpose is formed. A third layer wiring L3 is formed on the second layer wiring L2 through a connection via PL3, and a plurality of layers of wiring are further connected to the upper portion of the third layer wiring L3. Illustration of the structure above the three-layer wiring L3 is omitted.

  A connection via PL2 that functions electrically is formed above the first layer wiring L1, but a dummy via that does not function electrically is not formed. The first layer wiring L1 is a relatively long copper wiring and has a property that charges are likely to be accumulated by a semiconductor process such as dry etching. Further, the number of connection vias PL2 formed on the upper surface of the first layer wiring L1 is extremely small. Even if the length of the first layer wiring L1 is relatively short, when the gate electrode G1 connected to the lower portion of the first layer wiring L1 has a long and wide area, the first layer connected to the gate electrode G1 is used. The wiring L1 has a structure in which charges are easily accumulated.

  As described above, the first layer wiring L1b in the vicinity of the bottom of the via hole in which the connection via PL2 is embedded partially disappears and a void VO is formed, which is originally connected to the upper surface of the first layer wiring L1b. The via PL2 must be in contact, but here, the void VO is formed so that the first layer wiring L1b and the second layer wiring L2 are insulated. Accordingly, when the first layer wiring L1b and the second layer wiring L2 are not electrically connected, or when the area of the interface between the first layer wiring L1b and the second layer wiring L2 is reduced, the semiconductor device Since the resistance value of the wiring increases or the wiring is completely broken, the circuit does not operate normally. The reason why a part of the copper wiring disappears is as follows.

  The disappearance of the wiring is a process before forming the connection via on the wiring that is in a floating state in the manufacturing process of the semiconductor device, and after forming the via hole for embedding the connection via, the surface of the semiconductor substrate on which the wiring is formed is formed. This occurs when the copper constituting the wiring dissolves into the cleaning water (pure water) used for cleaning.

Since the wiring in the floating state in the manufacturing process is insulated from the semiconductor substrate or other conductors, it is easily charged (charged up) by a semiconductor process such as dry etching. As a result, a large charge accumulates in the wiring in the floating state, and then the copper (Cu) constituting the wiring exposed at the bottom of the via hole when the charged charge is moved into the cleaning water by cleaning the wiring. ) Is deprived of electrons (negative charges) and becomes copper ions (Cu ²⁺ ) and dissolves into the cleaning water, resulting in partial disappearance of the wiring. At this time, the electric charge charged in the wiring is released into the cleaning water while causing an electrochemical reaction that dissolves, oxidizes, and ionizes copper constituting the wiring.

  The longer the time for performing the cleaning process with the cleaning water, the greater the amount of lost wiring. Also, if the via hole diameter is small or the number of via holes is small, the area of the upper surface of the wiring exposed at the bottom of the via hole becomes small, so that the electric charge flowing into the cleaning water will flow in a narrow area. The copper constituting the wiring tends to disappear. Further, the electric charge charged to the wiring becomes larger when the length of the wiring is long, that is, when the wiring area or volume is large.

  The inventors of the present invention used TEG (Test Element Group) in which a test pattern for evaluation was formed on a semiconductor substrate, and examined the occurrence of voids for a plurality of wirings having different lengths. Note that the TEG wiring is a one-layer wiring that is not connected to the semiconductor substrate by a contact plug. By using this TEG, it is possible to evaluate the side effects on the floating wiring with higher sensitivity. FIG. 37 is a graph showing the relationship between the length of the void and the length of the wiring. The horizontal axis indicates the length of the wiring, and the vertical axis indicates the length of the void. As the value of the vertical axis of the graph increases, the amount of copper that forms the wiring increases, and the length of the formed void increases. Here, as shown in FIG. 37, when the length of the wiring is about 1 mm or more, it has been found that a part of the copper wiring disappears and a void is formed. That is, no void is generated when the length of the wiring is smaller than 1000 μm. However, including an appearance abnormality by observation using an electron microscope, an abnormality, that is, generation of a void can be confirmed when the wiring length becomes 0.7 mm or more. Therefore, in the case of a single-layer wiring that is not connected to the semiconductor substrate by the contact plug, a void is generated when the wiring length becomes 0.7 mm or more.

  When such a loss of wiring occurs, even if the connection via and its upper layer wiring are formed in the process after the cleaning, it is difficult to bury copper in the region where the wiring has disappeared, There is a high possibility that the wiring resistance will rise and the circuits constituting the semiconductor device will not operate normally. Therefore, in a semiconductor device including a wiring that is in a floating state in the manufacturing process, there is a problem that the reliability of the semiconductor device is lowered because the circuit does not operate normally when the wiring disappears. The phenomenon that part of the wiring melts and disappears as described above is not limited to the first-layer wiring or the third-layer wiring, and the copper wiring that is in a floating state in the manufacturing process even in the wiring of other layers This may occur at a location where a via hole is exposed.

  Even if the copper wiring does not disappear, if the charge moves at a high charge density in a partial region of the upper surface of the copper wiring, the copper in the partial region is oxidized to form a copper oxide film. For example, the resistance at the interface between the copper wiring and the connection via formed thereon may be increased.

  The above problem is caused in the copper wiring that is in a floating state during the manufacturing process, such as the first layer wiring L1 connected to the gate electrode G1 shown in FIG. 1 or the third layer wiring L3a in which the connection via is not formed on the lower surface. It is what happens. Therefore, like the fifth-layer wiring L5, the fourth-layer wiring L4, the third-layer wiring L3, the second-layer wiring L2, the first-layer wiring L1, the connection vias PL2 to PL5, and the plug PL1 are already formed at the time of formation. For example, even if the wiring connected to the main surface of the semiconductor substrate 1S is processed by, for example, a dry etching process, a large charge does not accumulate in the wiring.

  In addition, if the length of the wiring that is in the floating state in the manufacturing process is short, the amount of charge to be charged is small. Therefore, in the case of the wiring having a short length including the connection via, the cleaning is performed after the large charge is accumulated as described above. Due to flowing out into water, there is no problem that the copper constituting the wiring melts and the wiring partially disappears. Specifically, when the wiring is connected to the semiconductor substrate by the contact plug, as described below, when the length of the wiring including the connection via is less than 4 mm, the void or the high resistance layer is formed. Therefore, the resistance of the wiring does not increase.

  FIG. 38 is a graph showing the relationship between the length of each wiring and the defect occurrence rate of a wiring having a contact plug connected to the semiconductor substrate and a wiring having no contact plug connected to the semiconductor substrate. . That is, FIG. 38 is a graph showing the influence on the wiring defect occurrence rate due to the presence or absence of the contact plug connected to the semiconductor substrate. The horizontal axis in FIG. 38 shows the wiring area per connection via formed on the uppermost surface of each of the multilayer wiring and single layer wiring, and the vertical axis in FIG. 38 shows the void in the multilayer wiring or single layer wiring. The probability that the wiring resistance rises due to the occurrence of the high resistance layer or the generation of the high resistance layer, that is, the defect occurrence rate is shown. A graph composed of black rhombus plots shows the defect occurrence rate of wirings having contact plugs connected to the semiconductor substrate, and a graph composed of white square plots shows defect occurrence rates of wirings not having contact plugs. Is shown.

  As shown in FIG. 38, each wiring has a feature that the defect occurrence rate increases as the wiring area increases. This is because as the length of the wiring is longer and the area is larger, larger charges are more likely to accumulate, and the density of charges moving during cleaning increases, so that the incidence of voids or high resistance layers also increases. In addition, when there is a contact plug connected to the semiconductor substrate and when there is no contact plug, that is, between the wiring connected to the contact plug connected to the semiconductor substrate and the wiring that does not, the failure occurs when the contact plug is present The rate is low.

  Here, when the wiring area of the multilayer wiring having the contact plug connected to the semiconductor substrate is 5 to 50 times the wiring area of the multilayer wiring having no contact plug connected to the semiconductor substrate, the defect occurrence rate Are equivalent. In other words, when the occurrence of a defect becomes significant when the single-layer wiring has a specific wiring length, the laminated wiring has a defect when the wiring length is 5 to 50 times the wiring length of the single-layer wiring. The occurrence of is remarkable. In the evaluation using the TEG without the contact plug, the formation of voids was confirmed when the wiring length of the single-layer wiring became 0.7 mm or more, and a defect occurred. Even in the multilayer wiring having the contact plug, When the wiring length is 4 mm or more, which is 5 to 50 times that of the single-layer wiring, the generation of voids becomes significant, and an increase in wiring resistance becomes a problem.

  In response to the above-described problem of wiring loss, the present inventors provide dummy vias that are not used for electrical connection for the operation of the semiconductor device on wirings that are in a floating state in the manufacturing process. It has been found that by increasing the number of locations in contact with the wiring, it is possible to disperse the places where the charges charged in the wiring are released into the wash water and reduce the current density flowing at the bottom of one via hole. . If the density of charges moving in each via hole is reduced in this way, it is possible to prevent the copper wiring from partially disappearing as described above. For the same reason, it is also possible to prevent a copper oxide film from being formed between the copper wiring and the connection via thereover. That is, even if the total wiring length of a specific wiring and all conductors (eg, gate electrodes) electrically connected to the lower surface of the wiring is 4 mm or more, a part of the copper wiring An abnormal increase in wiring resistance due to disappearance or the formation of a high resistance film such as an oxide film on the upper surface of the connection via can be prevented.

  The effects of the semiconductor device of this embodiment will be described below. This embodiment includes a multilayer wiring having a laminated structure of two or more layers, and the multilayer wiring is mainly composed of copper, and when the part of the wiring is in a floating state in the manufacturing process, In a semiconductor device in which a connection via is formed on the upper portion, a dummy via that does not function electrically and is in contact with the upper surface of the wiring is formed.

  That is, in the semiconductor device of the present embodiment, as shown in FIG. 1, the dummy via DP2 is formed so as to be in contact with the upper surface of the first layer wiring L1 connected to the gate electrode G1, and is formed on the upper surface of the third layer wiring L3a. A dummy via DP4 is formed in contact therewith. A dummy wiring D2 integrated with the dummy via DP2 is formed above the dummy via DP2, and a dummy wiring D4 integrated with the dummy via DP4 is formed above the dummy via DP4. The dummy vias DP2 and DP4 are not directly electrically connected except for the dummy wiring integrated in the upper part thereof and the wiring that is in contact with the lower surfaces of the dummy wirings D2 and D4. In addition, the dummy wirings D2 and D4 are not directly electrically connected except for the dummy via integrated at the lower portion thereof, and the upper surface and side surfaces thereof are covered with an insulating film (for example, the barrier insulating films BI2 and BI4). Yes. That is, the dummy wirings D2 and D4 are both covered with the insulating film on the side walls and the upper surface.

  That is, the copper wiring composed of the dummy via DP2 and the dummy wiring D2 is directly connected to the lower first layer wiring L1, but is not connected to other wiring and the like and does not function electrically. That is, the wiring does not contribute to the operation of the circuit constituting the semiconductor device. On the upper surface of the wiring that is in contact with the lower surface of the dummy via, a connection via that functions electrically in addition to the dummy via and forms a part of the circuit is formed. The connection via is directly connected to the other wiring on the wiring. It is in contact and electrically connected.

  As described above, both the first layer wiring L1 connected to the gate electrode G1 insulated from the semiconductor substrate 1S by the gate insulating film and the third layer wiring L3a having no connection via formed on the lower surface are manufactured. This is a copper wiring that is in a floating state during the process. A major feature of the semiconductor device according to the present embodiment is that an electrically functioning connection via is disposed above the copper wiring that is in a floating state during the manufacturing process. A dummy via is not provided. Note that the electrically functioning connection via formed in the same layer and the dummy via not functioning electrically are formed in the same process and have the same configuration.

  If a dummy via that does not function electrically is provided on the wiring in this way, in the manufacturing process of the semiconductor device, for example, the barrier insulating film BI1 formed on the first layer wiring L1 after forming the first layer wiring L1 and The number of via holes penetrating through the interlayer insulating film IL2 and exposing the first layer wiring L1 increases as the number of dummy vias increases. Therefore, even if the charge is accumulated in the first layer wiring L1 by performing dry etching or the like and the charge flows into the pure water used for the rinse cleaning, the portion where the first layer wiring L1 is exposed at the bottom of the via hole is exposed. Since it can increase, it can prevent that the electric charge which flows out in washing water concentrates on a narrow area | region, and flows. The same applies to the third layer wiring L3a that is in a floating state during the manufacturing process.

  In other words, the partial disappearance of the copper wiring occurs when large charges accumulated in the wiring due to the semiconductor process concentrate on the bottom of the via hole and flow into the cleaning water. The number of via holes that are provided to expose the wiring is increased, and the electric charge flowing out from the wiring into the cleaning water is dispersed in the respective via holes on the upper surface of the wiring and discharged into the cleaning water. Therefore, since the amount of electric charge flowing out from each via hole on the upper surface of the wiring can be reduced, it is possible to prevent the copper constituting the wiring from being dissolved into the cleaning water by a large current. In other words, it is possible to disperse charges in the via holes forming the dummy vias, and to reduce the charge transfer density in each via hole when the charge charged up to the wiring moves into the cleaning water. Wiring breakage or high resistance can be prevented. This effect is particularly effective when providing a connection via with a reduced diameter due to miniaturization of the semiconductor device.

  As described above, in the present embodiment, the formation of the dummy via can prevent the concentrated movement of electric charges and prevent the disappearance of a part of the copper wiring, so that the wiring resistance increases due to the elution of the copper wiring. This can be prevented and the reliability of the semiconductor device can be improved.

  The above effect is obtained by increasing the area where the electric charge flows into the cleaning water, that is, the area where the lower layer wiring is exposed by the via hole. From the viewpoint of increasing the area where the electric charge flows out, the number of dummy vias is as shown in FIG. It is preferable not to provide only one on one wiring, but to provide a plurality on one wiring. This effectively prevents loss of copper wiring even when the length of the lower layer wiring is long and large charges tend to accumulate, or when there are few electrically functioning connection vias on the lower layer wiring. it can.

  Note that it is conceivable to increase the width of the dummy via or the connection via for the purpose of increasing the area where the lower layer wiring is exposed by the via hole, for example, to form a large via extending along the shape of the lower layer wiring. It is preferable that the shape of each and the shape of the connection via are formed in the same manner, and formed with the same design rule. In other words, it is preferable that the width of the dummy via is formed with the minimum design rule as in the case of the electrically functioning connection via, and the size of each via is made uniform. This is because if vias with different widths are formed in the same layer, the risk of residue residue due to the formation of via holes increases, and there may be other problems due to the presence of many unevenly sized via holes. It is. As shown in FIG. 1, the connection vias and dummy vias in the same layer are formed with the same width, and each via can be reliably formed by aligning the dimensions.

  Also, in semiconductor devices where wiring and vias are densely packed in a narrow area, it is often difficult to provide dummy vias larger than normal connection vias used for circuit configuration. Formation of the via hinders miniaturization of the semiconductor device.

  Conversely, it is conceivable that the dummy via is formed with a width (diameter) smaller than that of the electrically functioning connection via in the same layer, but it is important to increase the area of the lower layer wiring exposed by the via hole as described above. Therefore, if the width of the dummy via is smaller than the connection via, it is difficult to obtain the effect of the present embodiment. Further, if the width of the dummy via is made smaller than that of the connection via, the dummy via cannot be reliably embedded in the via hole, which causes a part of the copper wiring to be lost.

  Since dummy vias are wiring that does not function electrically, the vias are not completely embedded in the via holes, so the dummy vias are not filled to the bottom of the via holes, and even if there is a space between the dummy vias and the lower layer wiring, the operation of the electric circuit There is no problem. However, even after the connection via and the dummy via are formed on the wiring in the floating state, there is still a risk that a part of the copper wiring is lost in the cleaning process performed after the polishing process for forming the connection via. At this time, if a dummy via securely connected to the lower layer wiring is formed above the lower layer wiring, the wiring on the connection via can be prevented from being partially lost in the cleaning step after the polishing step. it can.

  Therefore, it is important that the diameter of the dummy via is not made smaller than that of the connection via in the same layer, and that the dummy via is formed so as to be surely connected to the lower layer wiring to reduce the risk of non-conduction.

  In addition, in order to obtain the effect of the semiconductor device of this embodiment, it is necessary that the dummy wiring is integrally formed on the dummy via formed by the dual damascene method. As will be described later in the description of the manufacturing process, in the via and wiring forming process by the dual damascene method, a via hole is first formed, and then a wiring groove (trench) is formed by etching at the bottom of the via hole. This is because the wiring is exposed and a part of the wiring is lost by the cleaning process performed thereafter. That is, immediately after the via hole is formed, the lower layer wiring is not yet exposed, and cleaning after forming the wiring groove on the via hole becomes a problem.

  By forming the dummy via and the dummy wiring thereon with the same shape as the other connection via and the upper layer wiring thereon, the dummy via and the dummy wiring can be formed more reliably and stably. Therefore, in this embodiment, like the dummy vias DP2 and DP4 and the dummy wirings D2 and D4 shown in FIG. 1, the dummy vias are formed integrally with the connection vias formed by the dual damascene method and the dummy vias in the same layer as the upper layer wirings. The dummy wiring is formed.

  Of the wirings shown in FIG. 1, the third-layer wiring L3 and the like that are electrically connected to the gate electrode G1 are also wirings that are in a floating state during the manufacturing process, and are not shown in FIG. By providing the dummy via and the dummy wiring also on the upper surface of the third layer wiring L3, the effect of the present embodiment can be obtained.

  Next, FIG. 2 shows a modification of the semiconductor device of this embodiment. FIG. 2 is a cross-sectional view of a semiconductor device having a stacked wiring structure as in FIG. The semiconductor device shown in FIG. 2 has substantially the same structure as the semiconductor device shown in FIG. 1, but the semiconductor element formed on the upper surface of the semiconductor substrate 1S and the structure of the first fine layer in the same layer and The arrangement of the second layer wiring L2, dummy via DP2, and dummy wiring D2 above the first fine layer is different from the semiconductor device shown in FIG.

  First, the semiconductor element formed on the upper surface of the semiconductor substrate 1S is not the MISFET used as a switching element or the like, but the capacitive element C1 and the split gate type memory M1. The capacitive element C1 includes a polysilicon film 1 formed on a semiconductor substrate via an insulating film, and a polysilicon film 2 formed on the polysilicon film 1 via an insulating film. And an element utilizing charges accumulated between the polysilicon film 2 and the polysilicon film 2. Note that a sidewall made of an insulating film is formed on the sidewall of the polysilicon film 1, and is a side surface of the polysilicon film 2 formed with a narrower width than the polysilicon film 1 and also directly above the polysilicon film 1. Side walls are formed.

  The split gate type memory M1 is a nonvolatile memory including a control MISFET and a memory MISFET formed on the p well PW on the upper surface of the semiconductor substrate 1S. The gate electrode (control gate electrode 3) of the control MISFET is made of, for example, an n-type polysilicon film as a conductive film, and is made of, for example, a high dielectric constant film (high-k film) such as a silicon oxide film or hafnium oxide (HfSiON). The gate insulating film is formed on the semiconductor substrate 1S. Further, the gate electrode (memory gate electrode 4) of the memory MIS FET is made of, for example, an n-type polysilicon film as a conductive film, and is arranged on one side wall of the control gate electrode 3 via the gate insulating film 5. Yes.

  The memory gate electrode 4 is electrically isolated from the control gate electrode 3 and the p well PW through a gate insulating film 5 made of a laminated film of a bottom oxide film, a silicon nitride film, and a top oxide film. Note that the silicon nitride acts as a charge retention film. An n-type diffusion layer NS that functions as a drain region and a source region of the memory cell is formed in the p well PW in the vicinity of the control gate electrode 3. The split gate type memory M1 includes a control gate electrode 3, a memory gate electrode 4, a gate insulating film 5, and an n-type diffusion layer NS. The split gate type memory M1 is erased by a write operation using hot electrons called a source side injection method (source side injection method) or a BTBT (Band to Band Tunneling) erase method in which hot holes generated by a band open tunneling phenomenon are injected. This is a non-volatile memory in which charges are taken in and out of the silicon nitride film by performing operations, and information is written and erased.

  As shown in FIG. 2, a plug PL1 is connected to the upper surface of the polysilicon film 1 which is the lower electrode of the capacitive element C1 formed on the semiconductor substrate 1S, and the polysilicon film 1 and the first layer wiring L1 above the polysilicon film 1 are connected. And are electrically connected. A plug PL1 and a dummy via DP1 are connected to the upper surface of the polysilicon film 2 which is the upper electrode of the capacitive element C1, and the plug PL1 electrically connects the polysilicon film 2 and the first layer wiring L1 above it. The dummy via DP1 electrically connects the polysilicon film 2 and the dummy wiring D1 above it. The dummy via DP1 and the plug PL1 are the same layer connection members that are formed in the same structure and have the same diameter. The dummy via DP1 and the plug PL1 are formed by the same manufacturing process and mainly include tungsten (W), and the dummy wiring D1 and the first layer wiring L1 are single damascene wirings formed by the same manufacturing process.

  However, the dummy via DP1 and the dummy wiring D1 are connected only to the polysilicon film 2, and like the dummy wirings D2 and D4 and the dummy vias DP2 and DP4 shown in FIG. This wiring does not contribute to operation. Here, the dummy via DP1 and the dummy wiring D1 connected to the polysilicon film 2 which is the upper electrode of the capacitive element C1 have been described, but the dummy via connected to the polysilicon film 1 which is the lower electrode of the capacitive element C1 and the second A dummy wiring in the same layer as the first layer wiring L1 may be provided.

  Further, a plug PL1 is connected to the upper surface of the memory gate electrode 4 constituting the split gate type memory M1 formed on the semiconductor substrate 1S, and the plug PL1 is connected to the memory gate electrode 4 and the first layer wiring L1 above it. And are electrically connected. The control gate electrode 3 and the memory gate electrode 4 are electrodes in a floating state insulated from the semiconductor substrate 1S by an insulating film, and the first layer wiring L1 which is an upper layer wiring connected to these electrodes is used for manufacturing a semiconductor device. The wiring is in a floating state in the process. An electrically functioning connection via PL2 is connected to the upper surface of the first layer wiring L1 electrically connected to the memory gate electrode 4, and a plurality of dummy vias DP2 are connected. As described above, by forming the plurality of dummy vias connected to the upper surface of the wiring that is in a floating state in the manufacturing process, it is possible to more effectively prevent the copper wiring from partially disappearing as described above.

  Here, the configuration in which the dummy via is connected to the wiring connected to the memory gate electrode 4 has been described. Similarly, the dummy via is formed above the wiring in the same layer as the first layer wiring L1 connected to the control gate electrode 3. It may be provided. Although not shown, a metal made of nickel silicide or the like is formed on the upper surfaces of the control gate electrode 3, the memory gate electrode 4, the polysilicon films 1 and 2, the n-type diffusion layer NS, and the p-type diffusion layer PS, for example. A silicide layer is formed to reduce the contact resistance between the control gate electrode 3, the memory gate electrode 4, the polysilicon films 1 and 2, the n-type diffusion layer NS and the p-type diffusion layer PS and their upper plug PL1. ing.

  Here, a description will be given of an aspect in which a copper wiring formed by a single damascene method is formed on a plug (dummy via DP1) mainly containing tungsten like a dummy wiring D1 connected to the capacitive element C1 shown in FIG. The purpose of forming the dummy wiring D1 is to prevent an increase in wiring resistance caused by movement of charges accumulated in the polysilicon film 2 at a high density in the cleaning water in the manufacturing process. This is the same as the dummy wirings D2 and D4 and the dummy vias DP2 and DP4 shown. However, when the dummy wiring D1 which is a single damascene wiring is not formed, the wiring resistance increases because an insulating film is formed at the interface between the plug PL1 connected on the polysilicon film 2 and the first layer wiring L1 above the plug PL1. This is due to the formation.

  As a comparative example, FIG. 34 shows an enlarged cross-sectional view of a connection portion between the plug PL1 mainly containing tungsten and the first layer wiring L1 above the plug PL1. As shown in FIG. 34, a plug (contact plug) PL1 made of a barrier conductor film 6 made of a titanium / titanium nitride film and a tungsten film 7 whose side walls are covered with the barrier conductor film 6 penetrates the contact interlayer insulating film CIL. Is formed. On the contact interlayer insulating film CIL, an interlayer insulating film IL1 is formed via an etching stopper film ES1 made of, for example, a silicon nitride film, and a wiring groove penetrating the interlayer insulating film IL1 and the etching stopper film ES1 is formed. Has been. A barrier conductor film 8 including tantalum (Ta) and titanium (Ti) is formed on the inner wall and bottom of the wiring groove, and a main conductor film made of copper (Cu) is formed on the barrier conductor film 8 so as to fill the wiring groove. 9 is formed, and the barrier conductor film 8 and the main conductor film 9 constitute the first layer wiring L1. The upper surface of the plug PL1 is connected to the lower surface of the first layer wiring L1.

  However, a tungsten oxide film, which is an insulating film obtained by oxidizing the tungsten film 7 constituting the plug PL1, is interposed between the upper surface of the plug PL1 and the lower surface of the first layer wiring L1 (not shown). It is important that the plug PL1 and the first layer wiring L1 are connected with a low resistance. In this case, since the tungsten oxide film as described above is formed, the wiring resistance is increased, and the semiconductor device is There is a risk of malfunction.

  The phenomenon in which the tungsten oxide film is formed in this manner is connected to the lower part of the plug PL1 in the cleaning process using pure water performed in the manufacturing process of the semiconductor device, similarly to the partial disappearance of the copper wiring described above. For example, this is caused by oxidation of the upper surface of the tungsten film 7 when a charge, which is a conductor, for example, is charged on a wiring, a gate electrode, or an electrode of a capacitive element, moves from the upper surface of the plug PL1 into the cleaning water.

  Specifically, when the plug PL1 and the first layer wiring L1 are formed, first, the plug PL1 is formed in the contact hole provided in the contact interlayer insulating film CIL, and then the plug PL1 and the contact interlayer insulating film CIL. Then, an etching stopper film ES1 and an interlayer insulating film IL1 are sequentially formed. Subsequently, after forming a wiring groove that penetrates the etching stopper film ES1 and the interlayer insulating film IL1 and exposes the upper surface of the plug PL1, etching residues on the upper surface of the semiconductor substrate are removed by cleaning with pure water (rinse cleaning). To do. Thereafter, the barrier conductor film 8 and the main conductor film 9 are embedded in the wiring groove, and then the excess barrier conductor film 8 and the main conductor film 9 on the interlayer insulating film IL1 are polished and removed, thereby forming the wiring groove. A first layer wiring L1 composed of the remaining barrier conductor film 8 and main conductor film 9 is formed.

  In this case, when the charge is accumulated in the plug PL1 and the conductor film in a floating state below the plug PL1, and then the charge of the conductor film moves into the cleaning water at a high density through the upper surface of the plug PL1, the tungsten film 7 Oxidation of the surface occurs.

Here, FIG. 35 and FIG. 36 show, as a comparative example, a graph showing the evaluation results of the contact resistance between the contact plug and the wiring measured by the present inventors through experiments. The horizontal widths of FIGS. 35 and 36 indicate the magnitude of the contact resistance, and the vertical axis indicates the standard deviation. Each figure is similar to the graph in the case where cleaning is performed with CO ₂ (carbon dioxide) introduced into the cleaning water when rinsing and cleaning the upper surface of the contact plug to increase the conductivity of the cleaning water. A graph when cleaning is performed while moving a nozzle (water outlet) for supplying cleaning water to the semiconductor substrate surface in the rinse cleaning step after introducing CO ₂ into the cleaning water, and CO in the rinse cleaning water. ₂ is a graph in which ₂ is not introduced and the nozzle is not moved.

  FIG. 35 is a graph in the case where the area of the underlying wiring contacting with the lower surface of the contact plug is 1.0 (μm) × 1.0 (μm). The length of the underlying wiring is short and the area is small. The amount of electric charge that is charged up is small, and the wiring resistance does not increase due to the oxidation of the upper surface of the plug due to the electric charge flowing into the cleaning water. Originally, as shown in each graph of FIG. 35, it is desirable that the contact resistance has little variation in the resistance value, and that the contact resistance is almost constant in any region of the semiconductor substrate. In addition to the above, the present inventors have a case where the area of the underlying wiring is 10 (μm) × 10 (μm), 10 (μm) × 50 (μm), and 30 (μm) × 100 (μm). An experiment was also conducted to determine whether or not there was variation in contact resistance. As in the graph of FIG. 35, there was no increase in resistance value, and good results were obtained.

However, in the graph of FIG. 36, which is a graph in the case where the area of the base wiring is 60 (μm) × 100 (μm), the CO ₂ is not introduced into the rinse water and the nozzle is not moved. As a result, the contact resistance greatly increases, and the wiring resistance varies. In addition to the above, the present inventors also conducted an experiment to determine whether contact resistance variation occurred even when the area of the underlying wiring was 100 (μm) × 100 (μm). The result is the same as the graph of FIG. As a result, the resistance value significantly increased and the resistance value varied.

Thus, as shown in FIG. 36, when the area of the underlying wiring is increased, the charge accumulated in the underlying wiring is increased, so that the contact resistance between the plug connected on the underlying wiring and the wiring above it has a high resistance. It turns out that the place which becomes becomes easy to generate | occur | produce. In addition, when CO ₂ is introduced to increase the conductivity of the cleaning water, and when the cleaning water from the nozzle is not concentrated on one part of the semiconductor substrate, the contact resistance increases. It can be seen that such a phenomenon does not occur. From this, it can be seen that the variation in contact resistance is caused by a cleaning process using high-resistance cleaning water.

  As described above, when a single damascene wiring is formed on a contact plug containing tungsten connected to a wiring that is in a floating state during the manufacturing process, a gate electrode, or a capacitor element, as shown in FIG. By forming the dummy via DP1 and the dummy wiring D1 connected to the polysilicon film 2, it is possible to reduce the density of electric charge flowing out from the upper surface of the plug PL1 in the manufacturing process. In the modification of the semiconductor device of the present embodiment, the plug PL1 is formed on the polysilicon film 2 in a floating state where charges are accumulated and the dummy via DP1 is formed, so that the semiconductor film 2 is moved into the cleaning water. The electric charge to be distributed can be dispersed in the plug PL1 and the dummy via DP1, and an increase in wiring resistance due to the formation of an insulating film on the upper surface of the plug PL1 can be prevented. Thereby, the reliability of the semiconductor device can be improved.

  Note that in the layer forming the single damascene wiring such as the first layer wiring L1, the dummy wiring D1 is not formed, but only the dummy via DP1 is formed as a wiring that does not function electrically, and the upper surface of the dummy via DP1 is the interlayer insulating film IL1. Alternatively, it is conceivable that the structure is covered with an insulating film such as the etching stopper film ES1 shown in FIG. However, when the dummy wiring D1 is not formed, the wiring groove for forming the dummy wiring D1 is not formed when the wiring groove for forming the first layer wiring L1 is formed and rinsed. The upper surface of the dummy via DP1 is not exposed, and the effect of reducing the charge density that moves from the plug into the cleaning water during the cleaning process cannot be obtained. Therefore, in a semiconductor device in which a single damascene wiring mainly containing copper is formed on an electrically functioning contact plug, when a dummy via that does not function electrically is provided in the same layer of the contact plug, a single damascene is always formed on the dummy via. It is necessary to arrange dummy wiring that is wiring.

  Further, FIG. 2 illustrates the case where the copper wiring is formed on the polysilicon film via the tungsten plug. However, the underlying wiring of the tungsten plug is not limited to the polysilicon film, but a metal film mainly containing copper or aluminum. It may be.

  Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 3 to 30 are sectional views showing a method of manufacturing the semiconductor device of the present embodiment shown in FIG. Since the present invention is an invention related to the laminated wiring formed on the semiconductor substrate, detailed description of the process for forming the MISFET is omitted here.

  First, by using a normal semiconductor manufacturing technique, a MISFET Q1 having a gate electrode G1, a MISFET Q2 having a gate electrode G2, a p-well PW and a p-type diffusion layer PS are formed on a semiconductor substrate 1S as shown in FIG. To do. When the p-type diffusion layer PS and the n-type diffusion layer NS are formed, ions are formed for forming the respective extension layers by using a photolithography technique, and the p-type diffusion layer is formed in a separate process. PS and n-type diffusion layer NS are formed. At this time, since both the gate electrodes G1 and G2 are formed on the semiconductor substrate 1S via the gate insulating film, the gate electrodes G1 and G2 are in a floating state electrically insulated from the semiconductor substrate 1S.

  Next, as shown in FIG. 4, a contact interlayer insulating film CIL is formed on the semiconductor substrate 1S on which the plurality of MISFETs Q1 and Q2 are formed. The contact interlayer insulating film CIL is formed so as to cover the plurality of MISFETs Q1 and Q2. Specifically, the contact interlayer insulating film CIL is, for example, an ozone TEOS film formed by a thermal CVD method using ozone and TEOS as raw materials, and a plasma using TEOS as a raw material disposed on the ozone TEOS film. It is formed from a laminated film with a plasma TEOS film formed by a CVD method. Note that an etching stopper film made of, for example, a silicon nitride film may be formed under the ozone TEOS film.

  Next, as shown in FIG. 5, a contact hole CH is formed in the contact interlayer insulating film CIL by using a photolithography technique and an etching method. The contact hole CH is processed so as to penetrate the contact interlayer insulating film CIL and reach the n-type diffusion layer NS that is the source region or drain region of the MISFET Q2 formed in the semiconductor substrate 1S. In the region not shown, a contact hole reaching the upper surface of the gate electrode G2 of the MISFET Q2 is also formed. The contact holes CH reaching the upper surfaces of the gate electrode G1 and the source / drain regions are also formed in the MISFET Q1, but the contact holes reaching the source / drain regions of the MISFET Q1 are not shown here. Further, some of the contact holes CH are processed so as to penetrate the contact interlayer insulating film CIL and reach the p-type diffusion layer PS formed in the semiconductor substrate 1S.

  Next, as shown in FIG. 6, a plug PL1 is formed by embedding a metal film in the contact hole CH formed in the contact interlayer insulating film CIL. Specifically, a titanium / titanium nitride film to be a barrier conductor film is formed on the contact interlayer insulating film CIL in which the contact holes CH are formed by using, for example, a sputtering method. Then, a tungsten film is formed on the titanium / titanium nitride film. Thereby, a titanium / titanium nitride film is formed on the inner wall (side wall and bottom surface) of the contact hole CH, and a tungsten film is formed so as to bury the contact hole CH on the titanium / titanium nitride film. Thereafter, unnecessary titanium / titanium nitride films and tungsten films formed on the contact interlayer insulating film CIL are removed by a CMP (Chemical Mechanical Polishing) method. Thereby, the plug PL1 in which the titanium / titanium nitride film and the tungsten film are buried only in the contact hole CH can be formed. A plug PL1 is formed immediately above the gate electrode G1 constituting the MISFET Q1, the n-type diffusion layer NS and the p-type diffusion layer PS constituting the MISFET Q2.

  Next, as shown in FIG. 7, an interlayer insulating film IL1 is formed on the contact interlayer insulating film CIL on which the plug PL1 is formed. This interlayer insulating film IL1 is formed of, for example, a SiOC film, and is formed by using, for example, plasma CVD.

  Then, as shown in FIG. 8, a wiring trench WD1 is formed in the interlayer insulating film IL1 by using a photolithography technique and an etching method. The wiring trench WD1 is formed so that the bottom surface reaches the contact interlayer insulating film CIL through the interlayer insulating film IL1 made of the SiOC film. As a result, the surface of the plug PL1 is exposed at the bottom of the wiring groove WD1. Thereafter, the main surface of the semiconductor substrate 1S is exposed to a chemical solution in order to remove residues and dust remaining on the substrate by the etching process in which the wiring groove WD1 is formed, and then cleaning with pure water (ultra pure water) ( By performing (rinse cleaning), the residue remaining inside the wiring trench WD1 is removed.

  Thereafter, as shown in FIG. 9, a barrier conductor film (copper diffusion prevention film) (not shown) is formed on the interlayer insulating film IL1 in which the wiring trench WD1 is formed. Specifically, the barrier conductor film is made of tantalum (Ta), titanium (Ti), ruthenium (Ru), tungsten (W), manganese (Mn), nitrides or silicides thereof, or a laminated film thereof. For example, it is formed by using a sputtering method.

  Subsequently, a seed film made of, for example, a thin copper film is formed by sputtering on the barrier conductor film formed inside the wiring trench WD1 and on the interlayer insulating film IL1. Then, a copper film Cu1 is formed by an electrolytic plating method using this seed film as an electrode. The copper film Cu1 is formed so as to fill the wiring groove WD1. The copper film Cu1 is formed from a film mainly composed of copper, for example. Here, although the copper film Cu1 is formed using the electrolytic plating method, the copper film Cu1 may be formed using the CVD method.

  Next, as shown in FIG. 10, the unnecessary barrier conductor film and copper film Cu1 formed on the interlayer insulating film IL1 are removed by CMP. Thereby, a layer (first fine layer) including the first layer wiring L1 in which the barrier conductor film and the copper film Cu1 are embedded in the wiring groove WD1 can be formed. That is, the first layer wiring L1 including the copper film Cu1 is formed immediately above the plug PL1.

  Thereafter, ammonia plasma treatment is performed on the surface of the interlayer insulating film IL1 on which the first layer wiring L1 is formed to clean the surface of the first layer wiring L1 and the surface of the interlayer insulating film IL1. Subsequently, as shown in FIG. 11, a barrier insulating film BI1 is formed on the interlayer insulating film IL1 on which the first layer wiring L1 is formed. The barrier insulating film BI1 is composed of, for example, a laminated film of a SiCN film and a SiOC film. For example, the laminated film can be formed by a CVD method. Then, an interlayer insulating film IL2 is formed over the barrier insulating film BI1. Further, a CMP protective film CMP1 is formed on the interlayer insulating film IL2.

  Subsequently, as shown in FIG. 12, a photoresist film PR1 is formed on the CMP protective film CMP1. Then, the photoresist film PR1 is patterned by performing exposure / development processing on the photoresist film PR1. Patterning is performed so as to open a region for forming a via hole. Thereafter, the CMP protective film CMP1 and the interlayer insulating film IL2 are etched using the patterned photoresist film PR1 as a mask. Thus, via holes V1 and V1d that penetrate the CMP protective film CMP1 and the interlayer insulating film IL2 and expose the barrier insulating film BI1 can be formed. As described above, the barrier insulating film BI1 functions as an etching stopper during etching.

  Here, at least two or more via holes are formed immediately above the first layer wiring L1 electrically connected to the gate electrode G1. That is, a via hole V1 for embedding an electrically functioning connection via and a via hole V1d for embedding an electrically nonfunctional dummy via immediately above the first layer wiring L1 electrically connected to the gate electrode G1. Form. Note that there is only one via hole opened immediately above each of the first layer wirings L1 electrically connected to the n-type diffusion layer NS or the p-type diffusion layer PS formed on the main surface of the semiconductor substrate 1S. Also good. A via hole V1 is formed above the first layer wiring L1 electrically connected to the n-type diffusion layer NS or p-type diffusion layer PS formed on the main surface of the semiconductor substrate 1S, but a dummy via is buried. The via hole V1d is not formed.

  Next, as shown in FIG. 13, the patterned photoresist film PR1 is removed by plasma ashing, and then the main surface of the semiconductor substrate 1S is cleaned. This cleaning step is performed using a chemical solution and cleaning water in order to remove residues generated by processing when forming the via holes V1 and V1d. In the cleaning step, after the semiconductor wafer is exposed to a chemical solution, the semiconductor wafer is cleaned with cleaning water (such as pure water) in order to remove the chemical solution remaining on the semiconductor wafer. The semiconductor substrate 1S is a disk-shaped semiconductor wafer provided with a notch or an orientation flat. In cleaning using cleaning water, for example, from the center of a circular semiconductor wafer in a direction perpendicular to the semiconductor substrate 1S. The entire semiconductor wafer is cleaned by rotating the semiconductor wafer around the extending line and supplying cleaning water from the axial direction of the rotating semiconductor wafer to the center of the semiconductor wafer. That is, cleaning is performed by dropping water from the nozzle to the center of the rotating semiconductor wafer. Also in the subsequent steps, for example, after the etching, the semiconductor wafer is cleaned, and in this case, the same method as the above cleaning step is used. Note that the amount of electric charge that is charged in the wiring tends to increase toward the center of the semiconductor wafer where water is dropped from the nozzle. Therefore, the central portion of the semiconductor wafer is more likely to increase the wiring resistance due to the disappearance of a part of the wiring than the end portion of the semiconductor wafer.

  Thereafter, a photoresist film PR2 is formed on the CMP protective film CMP1, and this photoresist film PR2 is subjected to exposure / development treatment, thereby patterning the photoresist film PR2. The patterning of the photoresist film PR2 is performed so as to open a region for forming a wiring groove.

  Thereafter, as shown in FIG. 14, the CMP protective film CMP1 is etched by anisotropic etching using the patterned photoresist film PR2 as a mask. Then, after removing the patterned photoresist film PR2 by plasma ashing, the main surface of the semiconductor substrate 1S is cleaned.

  Subsequently, as shown in FIG. 15, the barrier insulating film BI1 exposed at the bottoms of the via holes V1 and V1d is removed by an etch back method. As a result, the surface of the first layer wiring L1 is exposed at the bottom of the via holes V1 and V1d. By this etch back process, a part of the interlayer insulating film IL2 exposed from the patterned CMP protective film CMP1 is also etched to form the wiring trench WD2. Thus, after opening the via holes V1 and V1d and the wiring groove WD2 to expose the upper surface of the first layer wiring L1, rinsing cleaning using pure water is performed to clean the main surface of the semiconductor substrate 1S. Etching residues and the like remaining on the surface of the substrate 1S are removed. At the time of performing this cleaning process, the first layer wiring L1 connected to the gate electrode G1 is insulated from the semiconductor substrate 1S and is in a floating state.

  Next, as shown in FIG. 16, a barrier conductor film (not shown) is formed on the interlayer insulating film IL2 in which the wiring trench WD2 and the via holes V1 and V1d are formed and on the CMP protective film CMP1.

  Subsequently, a seed film (not shown) made of, for example, a thin copper film is formed by a sputtering method on the inside of the wiring trench WD2 and on the barrier conductor film formed on the CMP protective film CMP1. Then, a copper film Cu2 is formed by an electrolytic plating method using this seed film as an electrode. The copper film Cu2 is formed so as to fill the wiring groove WD2. The copper film Cu2 is formed of a film mainly composed of copper, for example.

  Subsequently, as shown in FIG. 17, the unnecessary barrier conductor film and copper film Cu2 formed on the CMP protective film CMP1 are removed by the CMP method. Thereby, the interlayer insulating film IL2 is exposed, and the second layer wiring L2 and the dummy wiring D2 in which the barrier conductor film and the copper film Cu2 are buried in the wiring trench WD2 are formed. In addition, by the same process, the connection via PL2 in which the barrier conductor film and the copper film Cu2 are embedded in the via hole V1, and the dummy via DP2 in which the barrier conductor film and the copper film Cu2 are embedded in the via hole V1d can be formed.

  The connection via PL2 is formed in contact with the upper surface of the first layer wiring L1, and the second layer wiring L2 is formed in the wiring groove WD2 integrally with the connection via PL2 on the connection via PL2. The dummy via DP2 is formed in contact with the upper surface of the first layer wiring L1 connected to the gate electrode G1, and the dummy wiring D2 is formed on the dummy via DP2 in the wiring groove WD2 integrally with the dummy via DP2. The CMP protective film CMP1 is provided to protect the semiconductor device during the manufacturing process from the polishing pressure and scratch damage by the CMP method at this time.

  In this embodiment, as described with reference to FIGS. 12 to 17, in the step of forming the second layer wiring L2, the connection via PL2, the dummy wiring D2, and the dummy via DP2, via holes V1, Vla are formed in the interlayer insulating film IL2. A via first manufacturing method is used in which the wiring trench WD2 is formed after forming the wiring trench. However, a trench first manufacturing method in which the via holes V1 and VIa are formed after the wiring trench WD2 is formed in the interlayer insulating film IL2 may be used. Absent.

  Thereafter, as shown in FIG. 18, ammonia plasma treatment is performed on the surface of the interlayer insulating film IL2 on which the second layer wiring L2 and the dummy wiring D2 are formed, and the surface of the second layer wiring L2 and the interlayer insulating film IL2 Clean the surface. Subsequently, a barrier insulating film BI2 is formed on the interlayer insulating film IL2 on which the second layer wiring L2 and the dummy wiring D2 are formed. The barrier insulating film BI2 is composed of, for example, a laminated film of a SiCN film and a SiOC film. For example, the laminated film can be formed by a CVD method. By repeating such a manufacturing process, connection vias PL2 to PL5, PL2 to PL5, third layer wiring L3 to fifth layer wiring L5 are formed. Thereby, the second fine layer including the second layer wiring L2 to the fifth layer wiring L5 can be formed.

  Here, the third layer wiring L3 is formed above the second layer wiring L2, and the third layer wiring L3 and the second layer wiring L2 immediately below the third layer wiring L3 are connected by the same method as the connection via PL2. Connected by via PL3. That is, the second layer wiring L2 is a wiring that is connected to another wiring and electrically functions as a circuit of the semiconductor device after the semiconductor device is completed. On the other hand, the dummy wiring D2 is not connected to the upper wiring, and only the first layer wiring L1 is connected to the dummy wiring D2 via a via. Accordingly, a via hole that exposes the upper surface of the dummy via DP2 is not formed in the interlayer insulating film IL3 immediately above the dummy via DP2. Therefore, an electrically functioning wiring can be connected to the upper portion of the dummy wiring D2 via the connection via. Absent. That is, the dummy wiring D2 and the dummy via DP2 are wirings that do not function electrically.

  As shown in FIG. 18, in the layer including the third-layer wiring L3, a third-layer wiring L3a having the same structure as the third-layer wiring L3 is provided in the step of forming the third-layer wiring L3. Since the third layer wiring L3a is a wiring formed in a region where the connection via PL3 that connects the second layer wiring L2 and the upper layer wiring is not formed, the lower surface of the third layer wiring L3a is in contact with the connection via. Absent. Therefore, until the fourth layer wiring L4 and the third layer wiring L3 connected to the semiconductor substrate 1S are connected via the connection via PL4 on the third layer wiring L3, the third layer wiring L3a It becomes a floating state insulated from the wiring or the semiconductor substrate 1S.

  Further, as shown in FIG. 18, in addition to the connection via PL4, a dummy via DP4 is formed on the upper surface of the third layer wiring L3a, and a dummy wiring D4 is formed above the dummy via DP4. The dummy via DP4 and the dummy wiring D4 are wirings formed in the same process as the dummy via DP2 and the dummy wiring D2, and are provided as wirings that do not function electrically like the dummy via DP2 and the dummy wiring D2. Therefore, the dummy wiring D4 is not connected to the electrically functioning wiring above the dummy wiring D4.

  Subsequently, a process of forming a semi-global layer on the second fine layer will be described. As shown in FIG. 19, the surface of the interlayer insulating film IL5 on which the fifth layer wiring L5 is formed is subjected to ammonia plasma treatment to clean the surface of the fifth layer wiring L5 and the surface of the interlayer insulating film IL5. . Subsequently, a barrier insulating film BI5 is formed on the interlayer insulating film IL5 on which the fifth layer wiring L5 is formed. The barrier insulating film BI5 is composed of, for example, a laminated film of a SiCN film and a SiOC film. For example, the laminated film can be formed by a CVD method. Thereafter, an interlayer insulating film IL6 is formed over the barrier insulating film BI5. The interlayer insulating film IL6 is formed from, for example, a SiOC film, and is formed by using, for example, a plasma CVD method.

  Next, as shown in FIG. 20, by using a photolithography technique and an etching method, a wiring groove WD4 and a via hole V3 are formed in the interlayer insulating film IL6. The via hole V3 is formed so as to penetrate the interlayer insulating film IL6 made of the SiOC film and have a bottom surface reaching the fifth layer wiring L5. As a result, the surface of the fifth layer wiring L5 is exposed at the bottom of the via hole V3.

  Next, as shown in FIG. 21, a barrier conductor film (not shown) which is a copper diffusion preventing film is formed on the interlayer insulating film IL6 in which the wiring trench WD4 and the via hole V3 are formed. Specifically, the barrier conductor film is made of tantalum (Ta), titanium (Ti), ruthenium (Ru), tungsten (W), manganese (Mn), nitrides or silicides thereof, or a laminated film thereof. For example, it is formed by using a sputtering method.

  Subsequently, a seed film made of, for example, a thin copper film is formed by sputtering on the barrier conductor film formed inside the wiring trench WD4 and the via hole V3 and on the interlayer insulating film IL6. Then, a copper film Cu3 is formed by an electrolytic plating method using this seed film as an electrode. The copper film Cu3 is formed so as to fill the wiring groove WD4 and the via hole V3. The copper film Cu3 is formed from a film mainly composed of copper, for example.

  Next, as shown in FIG. 22, the unnecessary barrier conductor film and copper film Cu3 formed on the interlayer insulating film IL6 are removed by CMP. Thus, the sixth layer wiring L6 in which the barrier conductor film and the copper film Cu3 are embedded in the wiring groove WD4, and the connection via PL6 in which the barrier conductor film and the copper film Cu3 are embedded in the via hole V3 can be formed. The connection via PL6 is formed in contact with the upper surface of the fifth layer wiring L5, and the sixth layer wiring L6 is formed integrally with the connection via PL6 on the connection via PL6.

  As described above, the sixth-layer wiring L6 can be formed. By repeating such a manufacturing process, a seventh layer wiring L7 as shown in FIG. 23 is also formed. Thereby, a semi-global layer including the connection vias PL6 and PL7, the sixth layer wiring L6, and the seventh layer wiring L7 can be formed.

  Next, a process for forming a global layer on the semi-global layer will be described. As shown in FIG. 24, the surface of the interlayer insulating film IL7 on which the seventh layer wiring L7 is formed is subjected to ammonia plasma treatment to clean the surface of the seventh layer wiring L7 and the surface of the interlayer insulating film IL7. Subsequently, a barrier insulating film BI7a is formed on the interlayer insulating film IL7 on which the seventh layer wiring L7 is formed. The barrier insulating film BI7a is composed of, for example, a laminated film of a SiCN film and a SiOC film. For example, the laminated film can be formed by a CVD method.

  Next, an interlayer insulating film IL8a is formed over the barrier insulating film BI7a. The interlayer insulating film IL8a is formed of, for example, a TEOS film or a silicon oxide film, and is formed by using, for example, a plasma CVD method. Further, an etching stop insulating film BI7b is formed on the interlayer insulating film IL8a, and an interlayer insulating film IL8b is formed on the etching stop insulating film BI7b. The etching stop insulating film BI7b is formed of, for example, a SiCN film. For example, the stacked film can be formed by a CVD method. The interlayer insulating film IL8b is formed of, for example, a TEOS film or a silicon oxide film, and is formed by using, for example, a plasma CVD method.

  Next, as shown in FIG. 25, by using a photolithography technique and an etching method, a wiring trench WD5 is formed in the interlayer insulating film IL8b and the etching stop insulating film BI7b, and the interlayer insulating film IL8a and the barrier insulating film are formed. A via hole V4 is formed in the BI 7a. The via hole V4 is formed so as to penetrate the interlayer insulating film IL8a made of a TEOS film, a silicon oxide film, or the like so that the bottom surface reaches the seventh layer wiring L7. As a result, the surface of the seventh layer wiring L7 is exposed at the bottom of the via hole V4.

  Thereafter, as shown in FIG. 26, a barrier conductor film (not shown) as a copper diffusion preventing film is formed on the interlayer insulating film IL8b in which the wiring trench WD5 is formed and on the interlayer insulating film IL8a in which the via hole V4 is formed. Specifically, the barrier conductor film is made of tantalum (Ta), titanium (Ti), ruthenium (Ru), tungsten (W), manganese (Mn), nitrides or silicides thereof, or a laminated film thereof. For example, it is formed by using a sputtering method.

  Subsequently, a seed film made of, for example, a thin copper film is formed by sputtering on the barrier conductor film formed in the wiring trench WD5 and the via hole V4 and on the interlayer insulating film IL8b. Then, a copper film Cu4 is formed by an electrolytic plating method using this seed film as an electrode. The copper film Cu4 is formed so as to fill the wiring groove WD5 and the via hole V4. The copper film Cu4 is formed from a film mainly composed of copper, for example.

  Next, as shown in FIG. 27, the unnecessary barrier conductor film and copper film Cu4 formed on the interlayer insulating film IL8b are removed by CMP. Thereby, the eighth layer wiring L8 in which the barrier conductor film and the copper film Cu4 are embedded in the wiring groove WD5, and the connection via PL8 in which the barrier conductor film and the copper film Cu4 are embedded in the via hole V4 can be formed. The connection via PL8 is formed in contact with the upper surface of the seventh layer wiring L7, and the eighth layer wiring L8 is formed integrally with the connection via PL8 on the connection via PL8. As described above, the eighth-layer wiring L8 can be formed. Thereby, a global layer including the eighth layer wiring L8 can be formed.

  Next, as shown in FIG. 28, a barrier insulating film BI8 is formed on the interlayer insulating film IL8b on which the eighth layer wiring L8 is formed, and an interlayer insulating film IL9 is formed on the barrier insulating film BI8. The barrier insulating film BI8 is composed of, for example, a laminated film of a SiCN film and a SiOC film. For example, the laminated film can be formed by a CVD method. The interlayer insulating film IL9 is formed of, for example, a TEOS film or a silicon oxide film, and is formed by using, for example, a plasma CVD method. Then, a via hole penetrating through the interlayer insulating film IL9 and the barrier insulating film BI8 is formed.

  Next, a laminated film in which a titanium / titanium nitride film, an aluminum film, and a titanium / titanium nitride film are sequentially laminated is formed on the sidewall and bottom surface of the via hole and the interlayer insulating film IL9, and the laminated film is patterned to be connected. A via PL9 and a ninth layer wiring L9 which is the uppermost layer wiring are formed. The connection via PL9 is formed in contact with the upper surface of the eighth layer wiring L8, and the ninth layer wiring L9 is formed in contact with the upper surface of the connection via PL9.

  Next, as shown in FIG. 29, a passivation film PAS serving as a surface protective film is formed on the interlayer insulating film IL9 on which the ninth layer wiring L9 is formed. The passivation film PAS is formed of, for example, a silicon oxide film and a silicon nitride film disposed on the silicon oxide film, and can be formed by, for example, a CVD method. Thereafter, by using a photolithography technique and an etching method, an opening is formed in the passivation film PAS, and a part of the ninth-layer wiring L9 is exposed to form a pad PD. In the region not shown, the upper surface of the ninth layer wiring L9 is also exposed and a pad is formed.

  Next, as shown in FIG. 30, a polyimide film PI is formed on the passivation film PAS where the pad PD is exposed. Then, the pad PD is exposed by patterning the polyimide film PI. As described above, by forming the multilayer wiring connected to the diffusion layer formed on the semiconductor substrate 1S, the semiconductor device of the present embodiment shown in FIGS. 1 and 2 is completed.

  The semiconductor device of the present embodiment may be a wiring that is connected to the semiconductor substrate 1S or the like and is not in a floating state when the semiconductor device is completed, such as the first layer wiring L1 or the third layer wiring L3. In the manufacturing process, if the wiring is insulated from the semiconductor substrate 1S or the like, the wiring may have a high resistance. For this purpose, dummy vias and dummy wiring that do not function electrically are provided on the wiring. is there.

  As described with reference to FIG. 15, when the via hole V1 and the wiring groove WD2 exposing the upper surface of the first layer wiring L1 are opened and subsequently rinsed with pure water, the gate electrode G1 is connected. The first layer wiring L1 is in a floating state. When the dummy via DP2 and the dummy wiring D2 are not provided, when the charge charged in the first layer wiring L1 moves into the cleaning water, the charge concentrates on the bottom of the via hole V1 for forming the connection via PL2 (see FIG. 17). The copper in the first layer wiring L1 exposed from the interlayer insulating film IL2 may melt into the cleaning water. In this case, a high resistance region such as a void is formed between the first layer wiring L1 from which copper has melted and the connection via PL2, and as a result, the semiconductor device does not operate normally, or Since problems such as variations in the performance of the semiconductor device occur, the reliability of the semiconductor device decreases.

  Similarly, the third layer wiring L3a shown in FIG. 30 is insulated from the semiconductor substrate 1S or other wiring until the middle of the manufacturing process. Therefore, after the semiconductor device is completed, the connection via is not in contact with the lower surface of the third layer wiring L3a, and other wiring or the semiconductor substrate 1S and the third layer wiring L3a are connected to the side surface of the third layer wiring L3a. No electrically conductive film is formed, and the electrically functioning conductor (connection via) is connected only to the upper surface of the third layer wiring L3a. That is, in the completed semiconductor device shown in FIG. 30, the side surface and the lower surface of the third layer wiring L3a are covered with the insulating film.

  In the rinsing cleaning step after forming the via hole and the wiring groove exposing the upper surface of the third layer wiring L3a during the manufacturing process, the charge accumulated in the third layer wiring L3a by dry etching or the like is the third layer at the bottom of the via hole. There is a possibility that part of the third layer wiring L3a exposed at the bottom of the via hole disappears due to the concentrated flow in the wiring L3a. However, in the present embodiment, similar to the dummy via DP2 and the dummy wiring D2 on the first layer wiring L1, the dummy via DP4 and the dummy wiring D4 are provided on the third layer wiring L3a. Accordingly, the number of via holes opened on the third layer wiring L3a is increased to avoid concentration of electric charges, thereby preventing a part of the third layer wiring L3a from being lost, and the dummy via DP2 and the dummy wiring D2 on the first layer wiring L1. The same effect as that obtained by forming can be obtained.

  In the present embodiment, dummy vias and dummy wirings that do not function electrically are formed, and the number of via holes opened above the copper wiring that is in a floating state during the manufacturing process is increased, thereby forming the via holes and wiring grooves. It is possible to reduce the charge density of each via hole when the electric charge withstanding the copper wiring flows into the cleaning water in the rinse cleaning process to be performed later, and to prevent a part of the copper wiring from melting and increasing the resistance of the wiring. It is said. As a result, the resistance of the circuit of the semiconductor device can be prevented from increasing, and the reliability of the semiconductor device can be improved.

  In this embodiment, an example in which a plug and a wiring that are connected to the upper surface of the dummy wiring are not provided has been described. However, an upper dummy via and an upper layer that do not function electrically are provided above the dummy wiring D2 illustrated in FIG. A dummy wiring may be further formed and connected to the dummy wiring D2. Thus, when a via hole for embedding the connection via PL3 is formed on the second layer wiring L2 immediately above the first layer wiring L1 to which the dummy wiring D2 is connected, the upper layer dummy via is also formed on the dummy wiring D2. Therefore, in the subsequent cleaning process, it is possible to prevent the copper constituting the second-layer wiring L2 still in a floating state from being melted and increasing the resistance.

  Further, as in the dummy via DP1 and the dummy wiring D1 shown in FIG. 2, the dummy via and the dummy wiring are directly formed in the floating polysilicon film or the like formed on the main surface of the semiconductor substrate 1S via the insulating film. Also good. The semiconductor device shown in FIG. 2 is formed by substantially the same process as the manufacturing process described with reference to FIGS. 3 to 30 except that the capacitor element C1 and the split gate type memory M1 are formed on the main surface of the semiconductor substrate 1S. Therefore, description of the manufacturing process is omitted.

  However, the dummy via DP1 and the dummy wiring D1 do not prevent an increase in wiring resistance due to the disappearance of a part of the copper wiring, but the wiring for forming the first layer wiring L1 as described with reference to FIG. Rinse cleaning after the formation of the groove is performed for the purpose of preventing a large charge from concentrating on the plug PL1 containing tungsten and thereby preventing an oxide film from being formed on the upper surface of the plug PL1. By forming the dummy via DP1 and the dummy wiring D1 in this way, when the copper wiring is formed on the polysilicon film in the floating state via the plug containing tungsten, the charge charged in the polysilicon film becomes the plug. Therefore, it is possible to prevent a tungsten oxide film from being formed on the upper surface of the plug and increase the wiring resistance of the circuit in the semiconductor device. Thereby, the dispersion | variation in the performance of a semiconductor substrate can be suppressed and the reliability of a semiconductor device can be improved.

(Embodiment 2)
In the first embodiment, when the copper wiring is formed on the polysilicon film or the like via the plug containing tungsten like the first fine layer, the semi-global layer, and the global layer, or the copper is formed on the copper wiring. Next, the case where the copper wiring is formed through the connection via mainly included has been described. That is, the dummy via and the dummy wiring described in the first embodiment are formed in contact with the polysilicon film formed on the main surface of the semiconductor substrate via the insulating film, or the upper surface of the upper copper wiring. It is provided in order to prevent the intermediate layer or lower layer wiring of the stacked semiconductor device from increasing in resistance.

  In contrast, in the present embodiment, when an aluminum wiring mainly containing aluminum (A1) is formed on a wiring made of a conductor such as copper via a connection via made of copper, the lower part of the aluminum wiring is formed. A dummy via is provided on the wiring formed through the connection via to prevent the wiring such as the connection via from increasing in resistance.

  FIG. 31 is a cross-sectional view of the semiconductor device of this embodiment. 31 is a cross-sectional view of the semiconductor device at a location corresponding to FIG. 1, and the semiconductor device shown in FIG. 31 has a structure substantially similar to that of the semiconductor device shown in FIG. However, in addition to the connection via PL9 for electrically connecting the ninth layer wiring L9 and the eighth layer wiring above the eighth layer wiring L8, the vias are not connected to the ninth layer wiring L9. The semiconductor device of the present embodiment is different from the semiconductor device described in the first embodiment in that a dummy via DP9 that does not function electrically is formed in the semiconductor layer device. Note that no dummy wiring is formed on the upper surface of the dummy via DP9, and no electrically functioning wiring is formed. An opening exposing the upper surface of the ninth layer wiring L9 is formed on the ninth layer wiring L9, and the ninth layer wiring L9 in the exposed region is used as a pad. It is assumed that the part is provided in another region not shown.

  In the manufacturing process of the semiconductor device, even an upper layer wiring such as the eighth layer wiring L8 shown in FIG. 31 may be in a floating state insulated from the semiconductor substrate or the like when formed. In this case, as described with reference to FIG. 33, charges accumulate in the copper wiring and the wiring connected to the wiring by dry etching or the like that opens a via hole for forming a connection via on the copper wiring, and the charge However, since the copper wire concentrates in the via hole and moves into the cleaning water at a high density, there is a problem that a part of the copper wiring disappears and the resistance value of the wiring becomes high.

  On the other hand, in the semiconductor device of the present embodiment, by forming the dummy via DP9, the number of via holes opened above the eighth layer wiring L8 is increased during the manufacturing process of the semiconductor device, and the cleaning after the opening of the via holes is performed. In the process, the density of charges moving from the eighth layer wiring L8 into the cleaning water can be dispersed in the via hole for embedding the dummy via DP9. Thereby, it is possible to prevent electric charges from concentrating on the upper surface of the eighth layer wiring L8 exposed from a part of the via holes, and it is possible to prevent the copper constituting the eighth layer wiring L8 from melting into the cleaning water. As in the first embodiment, partial loss of wiring can be prevented. For the same reason, an oxide film is formed at the interface between the wiring and the connection via, so that the wiring can be prevented from having a high resistance. Therefore, the reliability of the semiconductor device can be improved. In addition, it is possible to suppress the occurrence of variations in the wiring resistance of the semiconductor device.

  Note that it is not necessary to form dummy wirings above the dummy vias, like the dummy vias DP2 and DP4 shown in FIG. 1 and the dummy via DP1 shown in FIG. 2 above the dummy via DP9 shown in FIG. This is because the wiring formed above the connection via PL9 in the same layer of the dummy via DP9 is not a copper wiring formed by the damascene method but an aluminum wiring.

  As described with reference to FIG. 2 in the first embodiment, for example, the first layer wiring L1 and the dummy wiring D1 containing copper formed by the single damascene method are provided on the plug PL1 and the dummy via DP1, respectively. However, the wiring formed on the dummy via DP9 shown in FIG. 31 is a wiring formed by forming an aluminum film on the entire surface of the semiconductor substrate 1S by sputtering or the like and then patterning the aluminum film. For this reason, a part of the insulating film on the dummy via DP9 is partially removed to expose the upper surface of the dummy via DP9, and a process for forming a wiring groove is not performed. Therefore, the rinse cleaning can be performed with only the upper surface of the via exposed. Absent. Therefore, it is not necessary to provide a dummy wiring above the dummy via DP9.

  However, as shown in FIG. 32, if the dummy wiring D9 is formed on the dummy via DP9, the aluminum wiring can be processed more stably. FIG. 32 is a cross-sectional view showing a modification of the semiconductor device of the present embodiment, which is different in structure from the semiconductor device shown in FIG. 31 in that a dummy wiring D9 is formed on the dummy via DP9.

  That is, when the dummy wiring D9 is formed on the dummy via DP9, the structure including the dummy via DP9 and the dummy wiring D9 can be the same as the structure including the electrically functioning connection via PL9 and the ninth layer wiring L9. Therefore, dummy vias can be reliably formed by aligning the via and wiring structures. For example, when the dummy wiring D9 is not formed, a part of the upper surface of the dummy via DP9 may be removed by the etching process in the step of forming the ninth layer wiring L9 by patterning using an etching method. In this case, the flatness of the surface of the semiconductor device during the manufacturing process or after completion may be impaired, and the upper portion of the dummy via DP9 is unintentionally cut, and an unexpected etching residue may be generated.

  As described above, forming a via having a structure different from that of other electrically functioning connection vias and wiring causes an unexpected problem such as generation of a residue, so that the dummy wiring D9 is formed on the dummy via DP9. The wiring structure may be aligned by forming.

  Further, if a plurality of dummy vias DP9 are formed, more portions through which charges pass can be provided, so that an increase in wiring resistance can be effectively prevented. However, as described in the first embodiment, the diameter of the dummy via DP9 is the same as that of the connection via PL9 in the same layer as the dummy via DP9, so that the via is formed in accordance with the wiring standard of the same layer. This is very important.

  As mentioned above, the invention made by the present inventors has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is effective when applied to a manufacturing technique of a semiconductor device provided with a wiring that is in a floating state during the manufacturing process and a via thereover.

DESCRIPTION OF SYMBOLS 1 Polysilicon film 1S Semiconductor substrate 2 Polysilicon film 3 Control gate electrode 4 Memory gate electrode 5 Gate insulation film 6 Barrier conductor film 7 Tungsten film 8 Barrier conductor film 9 Main conductor films BI1 to BI8 Barrier insulation film BI7a Barrier insulation film BI7b Etching Stop insulating film C1 Capacitor element CH Contact hole CIL Contact interlayer insulating film CMP1 CMP protective film Cu1-Cu4 Copper film D1, D2, D4, D9 Dummy wiring ES1 Etching stopper film G1, G2 Gate electrodes IL1-IL7 Interlayer insulating film IL8a Interlayer Insulating film IL8b Interlayer insulating film IL9 Interlayer insulating films L1, L1b First layer wiring L2 Third layer wiring L3 Third layer wiring L3a Third layer wiring L4 Fourth layer wiring L5 Fifth layer wiring L6 Sixth layer wiring L7 Seventh layer Wiring L8 8th layer wiring L9 9th layer wiring M1 Togeto memory NS n-type diffusion layer PAS passivation film PD pad PI polyimide film PL1 plug PL2~PL9 connection via PR1, PR2 photoresist film PS p-type diffusion layer PW p-well Q1, Q2 MISFET
V1, V1d, V3, V4 Via hole VO Void WD1, WD2, WD4, WD5 Wiring groove

Claims (20)

A gate insulating film formed on the main surface of the semiconductor substrate;
A conductive film functioning as a gate formed on the gate insulating film;
A first interlayer insulating film formed on the conductive film;
A first wiring buried in a groove formed in the first interlayer insulating film and electrically connected to the conductive film;
A second interlayer insulating film formed on the first wiring;
A connection via that penetrates through the second interlayer insulating film and is electrically connected to the first wiring, constitutes a circuit and functions electrically, and does not function electrically in the same layer as the connection via Dummy vias,
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein the connection via and the dummy via are films containing copper formed by a damascene method.   2. The second wiring connected to the connection via is formed on the connection via, and the dummy wiring connected to the dummy via is formed on the dummy via. The semiconductor device described.   4. The semiconductor device according to claim 3, wherein the second wiring and the dummy wiring are single damascene wirings including copper.   The semiconductor device according to claim 1, wherein the connection via and the dummy via include tungsten.   2. The semiconductor device according to claim 1, wherein a third wiring containing aluminum connected to the connection via is formed on the connection via, and the upper surface of the dummy via is covered with an insulating film. . Both the connection via and the second wiring contain copper, and are formed by a dual damascene method and integrated.
4. The semiconductor device according to claim 3, wherein each of the dummy via and the dummy wiring contains copper and is formed by a dual damascene method and integrated.   4. The semiconductor device according to claim 3, wherein a side wall and an upper surface of the dummy wiring are covered with an insulating film.   The semiconductor device according to claim 1, wherein the conductive film contains polysilicon.   2. The semiconductor device according to claim 1, wherein a total length of the first wiring and all conductors electrically connected to a lower surface of the first wiring is 4 mm or more.   The semiconductor device according to claim 1, wherein the connection via and the dummy via have the same width in a direction along a main surface of the semiconductor substrate. A first wiring formed on a semiconductor substrate and having a side surface and a lower surface covered with an insulating film;
A first interlayer insulating film formed on the first wiring;
A connection via that penetrates through the first interlayer insulating film and is electrically connected to the first wiring and constitutes a circuit and functions electrically. The connection via formed in the same layer as the connection via does not function. Dummy vias,
A semiconductor device comprising:   13. The semiconductor device according to claim 12, wherein the connection via and the dummy via are films containing copper formed by a damascene method.   13. The second wiring connected to the connection via is formed on the connection via, and the dummy wiring connected to the dummy via is formed on the dummy via. The semiconductor device described.   15. The semiconductor device according to claim 14, wherein the second wiring and the dummy wiring are single damascene wiring containing copper.   13. The semiconductor device according to claim 12, wherein a third wiring containing aluminum connected to the connection via is formed on the connection via, and an upper surface of the dummy via is covered with an insulating film. . Both the connection via and the second wiring contain copper, and are formed by a dual damascene method and integrated.
15. The semiconductor device according to claim 14, wherein each of the dummy via and the dummy wiring contains copper and is formed by a dual damascene method and integrated.   15. The semiconductor device according to claim 14, wherein a side wall and an upper surface of the dummy wiring are covered with an insulating film.   13. The semiconductor device according to claim 12, wherein the connection via and the dummy via have the same width in a direction along the main surface of the semiconductor substrate.   The semiconductor device according to claim 12, wherein a length of the first wiring is 0.7 mm or more.

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