JP2006165191A - Structure with semiconductor layer of iii-v compound and its manufacturing method - Google Patents

Structure with semiconductor layer of iii-v compound and its manufacturing method Download PDF

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JP2006165191A
JP2006165191A JP2004353108A JP2004353108A JP2006165191A JP 2006165191 A JP2006165191 A JP 2006165191A JP 2004353108 A JP2004353108 A JP 2004353108A JP 2004353108 A JP2004353108 A JP 2004353108A JP 2006165191 A JP2006165191 A JP 2006165191A
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substrate
semiconductor
surface
groove
semiconductor layer
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JP4452167B2 (en
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Shen Fon Chin
Toru Kachi
Masahiro Sugimoto
Tsutomu Uesugi
チンシェンフォン
勉 上杉
徹 加地
雅裕 杉本
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Toyota Central Res & Dev Lab Inc
Toyota Motor Corp
トヨタ自動車株式会社
株式会社豊田中央研究所
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure where heat generated from a semiconductor device formed in a semiconductor layer of a III-V compound can efficiently be discharged outside the semiconductor layer. <P>SOLUTION: The structure is provided with the semiconductor layer 40 of gallium nitride (GaN), and a lower layer 60 which is brought into contact with the semiconductor layer 40. The lower layer 60 is provided with a metal region 50 extending from the surface of the lower layer 60 to a backside. In a face orthogonal with a direction connecting the surface and the backside of the lower layer 60, the metal regions 50 are repetitively formed by leaving an interval. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a structure including a semiconductor layer of a III-V group compound having a low density of crystal defects and a method for manufacturing the structure. More specifically, the present invention relates to a structure capable of efficiently transferring heat generated from a semiconductor device to the outside of the semiconductor layer when a semiconductor device is formed on a semiconductor layer of a III-V group compound, and a method for manufacturing the structure.

The present applicant discloses, in Patent Document 1 and Patent Document 2, a technique capable of obtaining a semiconductor layer of a III-V group compound such as gallium nitride in a low density state of crystal defects. These technologies prepare a substrate (for example, silicon) on which a groove extending from the front surface toward the back surface is formed, epitaxially grow gallium nitride from the surface of the substrate, and bridge the upper portion of the groove. This is a technology for creating a gallium semiconductor layer. The produced gallium nitride semiconductor layer is obtained with a low density of crystal defects. By forming the groove, the contact area between the silicon substrate and the gallium nitride semiconductor layer is reduced, and the generation of stress due to lattice mismatch, difference in thermal expansion coefficient, etc. is alleviated. A gallium nitride semiconductor layer can be obtained.
In Patent Document 1 and Patent Document 2, it is assumed that a plurality of projection groups are formed on the surface of the substrate. However, if the surface of the projection group is evaluated as the surface of the substrate, the remaining portion of the projection group extends from the surface of the substrate to the back side. It can be evaluated as a groove extending toward the surface. The projection group and the groove are different expressions, and are interpreted as similar techniques.
JP 2002-241192 A JP 2002-293698 A

Using a gallium nitride semiconductor layer created by the techniques of Patent Literature 1 and Patent Literature 2, semiconductors such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), and diodes are formed in the semiconductor layers. A device is created. It is sufficient that the thickness of the semiconductor layer necessary for manufacturing the semiconductor device is several tens of μm. However, a semiconductor layer having a thickness of several tens of μm has low physical strength. Therefore, in order to ensure the physical strength of the semiconductor layer, the substrate and the semiconductor layer may be used as a unit. That is, after the semiconductor layer is epitaxially grown, the substrate and the semiconductor layer may be used as they are without removing the substrate. If the semiconductor layer is formed with a thickness of several hundred μm, the physical strength can be ensured. However, in this case, there is a problem that the time required for epitaxial growth of the semiconductor layer becomes extremely long and the manufacturing cost increases. Therefore, there is a demand for forming a gallium nitride semiconductor layer with a thickness of several tens of μm necessary for manufacturing a semiconductor device.
However, when the semiconductor device formed on the semiconductor layer is operated, there is a problem that heat generated from the semiconductor device cannot be efficiently transferred outside the semiconductor layer by the hollow space defined by the groove. For this reason, there is a problem that it is difficult to stably operate the semiconductor device.
One object of the present invention is to provide a method for easily producing a structure capable of efficiently transferring heat generated from a semiconductor device formed in a semiconductor layer of a III-V compound compound to the outside of the semiconductor layer. It is aimed. It is another object of the present invention to provide a structure that can efficiently exhaust heat generated from a semiconductor device formed in a semiconductor layer of a III-V compound compound to the outside of the semiconductor layer.

In the method for producing a structure of the present invention, it is preferable to carry out at least the following steps. First, the process of forming the groove | channel extended toward the back surface side from the surface of a board | substrate is implemented. Next, a step of forming a semiconductor layer that crystallizes a III-V group compound semiconductor from the surface of the substrate and bridges above the groove is performed. Next, the process of removing a board | substrate is implemented until the said groove | channel is exposed from the back surface of a board | substrate. Then, a step of filling the exposed groove with a material having a heat conduction coefficient larger than that of air is performed. A structure can be obtained through these steps.
Prior to crystal growth of the III-V compound semiconductor from the surface of the substrate, a material having a melting point higher than that of the III-V compound semiconductor (for example, silicon carbide (SiC), aluminum nitride (AlN), or spinel (MaAl 2 O 4 ) can be preferably used) on the surface of the substrate, and a III-V compound semiconductor crystal may be grown from the formed layer. By the presence of this layer, it is possible to suppress the reaction between the substrate and the III-V group compound semiconductor to form a polycrystalline III-V group compound semiconductor crystal.
In the step of forming a groove extending from the front surface of the substrate toward the back surface, the groove may penetrate the substrate and be exposed from the back surface. In this case, since the formed groove is exposed from the back surface of the substrate, it can be evaluated that the process of removing the back surface of the substrate is performed at the same time until the groove is exposed. Moreover, there is no restriction | limiting in particular regarding the shape etc. of the groove | channel to form, For example, a groove | channel may be formed in stripe form or a grid | lattice form on the surface of a board | substrate, and even if the groove | channel distributed on the surface of a board | substrate is formed in a dot form Alternatively, the projections may be distributed on the surface of the substrate, and the remainder may be formed as a groove, or may be formed by combining them.
For the step of removing the substrate from the back surface of the substrate until the groove is exposed, a method of polishing and removing the back surface of the substrate, a method of removing the back surface of the substrate by etching, or the like can be suitably used.

  In the above manufacturing method, by forming the groove on the surface side of the substrate, the contact area between the substrate and the semiconductor layer of the III-V compound semiconductor is reduced, so that it is based on a lattice mismatch or a difference in thermal expansion coefficient. The generation of stress is relaxed, and a semiconductor layer with low density of crystal defects can be obtained. A semiconductor device can be formed in the semiconductor layer by using the structure including the semiconductor layer. When a semiconductor device formed in the semiconductor layer is operated, heat is generated, but the heat can be efficiently transferred to the substrate side. Since the groove is filled with a material having a heat conduction coefficient larger than that of air, the heat generated from the semiconductor device is efficiently transferred to the substrate side as compared with the case where the groove is a hollow space. It is. By simply removing the backside of the substrate until the groove is exposed and filling the exposed groove with a material having a thermal conductivity coefficient greater than that of air, the stability of the operation of the semiconductor device is significantly improved. Thus, it is possible to obtain a structure that can be improved.

  Preferably, the metal is selected as a material having a thermal conductivity coefficient greater than that of air. Metal is a material having a large thermal conductivity coefficient and a small resistance value. For example, using both the semiconductor layer and substrate of a III-V compound semiconductor, one main electrode (drain electrode and source electrode, anode electrode and cathode electrode, collector electrode and emitter electrode, etc.) is used. When a vertical semiconductor device in which an electrode is formed on the surface of a semiconductor layer and the other main electrode is formed on the back surface of the substrate is produced, the resistance of current flowing in the vertical direction can be reduced due to the presence of metal. By using the structure manufactured by this manufacturing method, a vertical semiconductor device with low on-resistance can be obtained.

The substrate is preferably a semiconductor.
When a substrate made of a semiconductor material is used, a semiconductor layer of a III-V group compound semiconductor can be grown from the surface of the substrate to obtain a semiconductor layer with a low density of crystal defects.

The substrate is preferably silicon (Si).
According to the manufacturing method of the present invention, a semiconductor layer of a III-V group compound semiconductor having low density of crystal defects can be obtained even when an inexpensive silicon substrate is used. A structure can be obtained at a very low cost without using an expensive III-V compound substrate.

It is preferable that (111) is selected for the surface orientation of the surface of the substrate.
When a group III-V compound semiconductor crystal is grown from the (111) plane, a semiconductor layer of a group III-V compound semiconductor with low density of crystal defects can be obtained.

In the step of forming the groove, a plurality of groove groups extending from the front surface of the substrate toward the back surface are preferably formed in a stripe shape. Furthermore, it is preferable that the longitudinal direction of the groove group is selected in the <11-2> direction of the (111) plane of the substrate or an equivalent direction.
When the longitudinal direction of the groove group is formed in the <11-2> direction, when a group III-V compound semiconductor is grown from the surface of the substrate, the group III-V compound semiconductor is bridged above the groove. In addition, it can grow beautifully laterally from the surface of the substrate. A semiconductor layer of a III-V group compound semiconductor with low density of crystal defects can be obtained. In the (111) plane of the substrate, the direction in which the formed angle is inclined at 60 ° with respect to an arbitrary direction can be evaluated as a direction equivalent to the arbitrary direction. Therefore, even if the longitudinal direction of the groove group is selected in a direction equivalent to the <11-2> direction, the same effect as described above can be obtained.

  The structure of the present invention includes an upper layer of a III-V compound semiconductor and a lower layer in contact with the upper layer. The lower layer comprises a partial region of material that extends from the lower surface to the back surface and that has a thermal conductivity coefficient greater than that of air. In the plane orthogonal to the direction connecting the front surface and the back surface of the lower layer, the partial regions are repeatedly formed at intervals. The term “repetition” as used herein refers to, for example, a case where partial areas are formed in a stripe shape or a lattice shape, a case where partial areas or lower layers are formed in a dispersed manner in a dot shape, or a combination thereof. It is interpreted including the case where it is done.

Since a III-V compound semiconductor has a large breakdown electric field, a saturated electron density, etc., a semiconductor device that can control a large current with a high breakdown voltage can be obtained by creating a semiconductor device on the upper layer of the III-V compound semiconductor of the above structure. Obtainable. The semiconductor device to be created may be a horizontal type in which a pair of main electrodes are formed on the upper surface side, or a vertical type formed separately on the upper surface side and the lower surface back side. There may be.
The heat generated when the semiconductor device formed in the upper layer is operated is efficiently transferred to the lower layer side due to the presence of a partial region of the material having a heat conduction coefficient larger than that of air. Therefore, when a semiconductor device is formed using the structure of the present invention, the operation stability of the semiconductor device can be significantly improved.

  According to the present invention, it is possible to easily manufacture a structure that can efficiently transfer heat generated from a semiconductor device formed in a semiconductor layer of a III-V group compound to the outside of the semiconductor layer. Further, it is possible to provide a structure that can efficiently transfer heat generated from a semiconductor device formed in a semiconductor layer of a III-V group compound to the outside of the semiconductor layer.

The main features of the examples are listed.
(First Form) The width of the groove extending from the front surface to the back surface of the substrate is preferably 5 μm or less.
(2nd form) It is preferable that the depth of the groove | channel extended toward the back surface side from the surface of a board | substrate is half or more of the width | variety of a groove | channel.
(Third Embodiment) the width of the groove extending toward the surface of the substrate to the back side (32W 1 in FIG. 2), the ratio of the width of the protrusions formed as a remainder (32W 2 in FIG. 2) (32W 1 / 32W 2 ) Is preferably 1 or more.
(4th form) It is preferable to form the semiconductor layer which bridge | crosslinks above the said groove | channel by crystal-growing a III-V group compound semiconductor from the surface of a board | substrate using the lateral selective growth method (ELO: Epitaxial Lateral Overgrowth). .

In this embodiment, a method for manufacturing a structure including a semiconductor layer of gallium nitride (GaN) having low density of crystal defects will be described with reference to FIGS. It should be noted that the structures shown in FIGS. 1 to 5 show only the repetitive structure of the main part, and actually the repetitive structure is further continuous.
First, as shown in FIG. 1, for example, a silicon single crystal semiconductor substrate 30 is prepared. The (111) plane is selected as the surface orientation of the surface of the semiconductor substrate 30. Next, a plurality of trenches 32 extending from the front surface to the back surface of the semiconductor substrate 30 are formed in a stripe shape by dry etching using, for example, RIE (Reactive Ion Etching). The longitudinal direction of the group of trenches 32 is selected in the <11-2> direction of the (111) plane of the semiconductor substrate 30. In the (111) plane of the semiconductor substrate 30 made of silicon, the direction inclined at 60 ° with respect to the <11-2> direction can be evaluated as a direction equivalent to the <11-2> direction. Therefore, the longitudinal direction of the group of trenches 32 may be selected in such an equivalent direction.
FIG. 2 is a cross-sectional view of the main part corresponding to the II-II line of the main part perspective view of FIG.
The depth of the trench 32 30H is preferably formed with more than half of the depth of the width 32W 1 of the trench 32. When the depth 30H of the trench 32 is formed to be shallower than this value, as will be described in a later step, the upper layer is to be bridged above the trench 32 by a lateral selective growth method (ELO: Epitaxial Lateral Overgrowth). Sometimes, the inside of the trench 32 is filled, and the lateral selective growth method cannot be performed. It becomes difficult to obtain an upper layer having a low density of crystal defects.
Width 32W 1 of the trench 32 is preferably at 5μm or less. If the width 32W 1 of the trench 32 is 5μm or more, it becomes difficult to crosslink upper layer above the trench 32 by the lateral selective growth. Thus, preferably the width 32W 1 of the trench 32 is 5μm or less.
The ratio (32W 1 / 32W 2 ) between the width 32W 1 of the trench 32 and the width 32W 2 of the protrusion formed as the remainder is preferably 1 or more. When the ratio between the two is smaller than 1, the region where crystal defects exist in a high density in the upper layer formed by the lateral selective growth method is increased. Therefore, the ratio (32W 1 / 32W 2 ) is preferably 1 or more.

Next, as shown in FIG. 3, for example, epitaxial growth is performed from the surface of the semiconductor substrate 30 by a lateral selective growth method (ELO: Epitaxial Lateral Overgrowth) using metal organic chemical vapor deposition (MOCVD). Then, the gallium nitride semiconductor layer 40 (an example of the upper layer) is formed so that the layer thickness 40H is several tens of μm. The semiconductor layer 40 is epitaxially grown in the lateral direction from the surface of the semiconductor substrate 30 to above the trench 32. Since the (111) plane is selected as the surface orientation of the surface of the semiconductor substrate 30, the semiconductor layer 40 can be epitaxially grown cleanly from the surface of the semiconductor substrate 30. Further, since the longitudinal direction of the group of trenches 32 is selected as <11-2> of the crystal orientation of the semiconductor substrate 30, the semiconductor layer 40 is beautiful in the lateral direction from the surface of the semiconductor substrate 30 to above the trench 32. Can be epitaxially grown. As a result, as shown in FIG. 3, the semiconductor layer 40 is formed by bridging above the trench 32. At this time, trimethylgallium (TMGa) can be preferably used as the gallium source, and ammonia gas (NH 3 ) can be preferably used as the nitrogen source.
If necessary, the semiconductor layer 40 may be made n-type using monosilane (SiH 4 ), monomethylsilane (SiH 3 (CH 3 )) or the like as a dopant material, and cyclopentadienyl as a dopant material. The p-type may be formed using magnesium (CP2-Mg) or the like. The surface of the semiconductor layer 40 can be planarized by adjusting the concentration of the source gas, the reaction temperature, and the like. Through this step, the gallium nitride semiconductor layer 40 with low density of crystal defects can be obtained.
Instead of metal organic vapor phase epitaxy, for example, molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or liquid phase epitaxy (LPE) Phase Epitaxy) or a combination of these may be used.

Next, polishing is performed from the back surface of the semiconductor substrate 30 until the trench 32 is exposed. As a result, as shown in FIG. 4, the plate-like semiconductor regions 30a (the portions remaining after the polishing of the semiconductor substrate 30) exist in a state of being arranged in parallel.
Next, as shown in FIG. 5, a metal region 50 (an example of a partial region) is formed by embedding and growing aluminum in the exposed trench 32 by, for example, CVD (Chemical Vapor Deposition). Thereby, the lower layer 60 is constituted by the semiconductor region 30 a and the metal region 50. The semiconductor region 30a and the metal region 50 are both plate-shaped. Therefore, the semiconductor region 30 a is repeatedly formed in one direction at intervals corresponding to the width of the metal region 50 in a plane orthogonal to the direction connecting the front surface and the back surface of the lower layer 60.
Moreover, the physical strength of the semiconductor layer 40 can be ensured by forming the lower layer 60 with a sufficiently large thickness 30H. The thickness 30H of the lower layer 60 substantially corresponds to the depth 30H of the trench 32 (actually depends on the amount of polishing of the semiconductor substrate 30. However, if the polishing is finished when the trench 32 is exposed, The thickness 30H of the lower layer 60 substantially corresponds to the depth 30H of the trench 32). In other words, it is preferable to set the depth of the trench 32 in advance so that the physical strength of the semiconductor layer 40 can be ensured.
Note that, instead of the CVD method, the trench can be filled with a metal such as aluminum by, for example, a sputtering method, a vapor deposition method, or a plating method.
Through these steps, a structure including the semiconductor layer 40 of gallium nitride (GaN) having low density of crystal defects can be obtained.

Next, for example, a semiconductor device such as a MOSFET, IGBT, or diode can be formed in the semiconductor layer 40. The produced semiconductor device may be a horizontal type in which a pair of main electrodes are formed on the surface of the semiconductor layer 40. Alternatively, a vertical type in which one of the pair of main electrodes is formed on the surface of the semiconductor layer 40 and the other main electrode is formed on the back surface of the lower layer 60 may be used. When a vertical semiconductor device is formed, a semiconductor device with low on-resistance can be obtained due to the presence of the low-resistance metal region 50. In this case, the semiconductor region 30a of the lower layer 60 preferably contains an impurity. The semiconductor region 30a can also be used as a current path, and a semiconductor device with low on-resistance can be obtained. In addition, the semiconductor region 30a containing an impurity can be easily obtained by using the semiconductor substrate 30 containing an impurity in advance.
When the semiconductor device created in the semiconductor layer 40 is operated, heat is generated from the semiconductor device. Since the generated heat is transferred to the lower layer 60 side through the aluminum metal region 50a having a large thermal conductivity coefficient, the situation where the semiconductor layer 40 is brought into an excessively high temperature state is suppressed. Therefore, the semiconductor device can operate stably.

This embodiment may be the following modification.
Instead of the silicon semiconductor substrate 30 of this embodiment, for example, a semiconductor substrate such as gallium nitride (GaN) can be used. Further, a substrate such as sapphire can be used instead of the semiconductor substrate. In particular, when a horizontal semiconductor device is formed in a semiconductor layer, an insulating material may be used because the substrate or the lower layer does not serve as a current path.
As a material for filling the trench 32, for example, a metal such as copper or nickel can be used instead of aluminum. These metals can be easily filled in the trenches using existing manufacturing techniques. Further, instead of metal, a semiconductor material such as silicon may be used. In short, any material having a heat conduction coefficient larger than that of air may be used.
In this embodiment, the semiconductor layer 40 of gallium nitride is directly grown from the surface of the semiconductor substrate 30 by a lateral selective growth method using a metal organic chemical vapor deposition method. Instead of this method, prior to crystal growth of a III-V compound semiconductor such as gallium nitride from the surface of the semiconductor substrate, a material having a melting point higher than that of the III-V compound semiconductor (for example, silicon carbide (SiC), Aluminum nitride (AlN) or spinel (MaAl 2 O 4 ) can be suitably used) is formed on the surface of the substrate, and a III-V compound semiconductor is crystal-grown from the formed layer. Also good. By the presence of this layer, it is possible to suppress the reaction of the semiconductor (typically silicon) and the group III-V compound semiconductor to form a polycrystalline group III-V compound semiconductor crystal.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

It is a perspective view which shows the state which formed the trench group in the surface of the semiconductor substrate. The principal part sectional drawing of FIG. 1 is shown. It is principal part sectional drawing which shows the state in which the semiconductor layer was formed. It is principal part sectional drawing which shows the state which grind | polished the semiconductor substrate from the back surface. It is principal part sectional drawing which shows the state with which the metal was filled in the trench.

Explanation of symbols

30: Semiconductor substrate 30a: Semiconductor region 32: Trench 40: Semiconductor layer 50: Metal region 60: Lower layer

Claims (7)

  1. Forming a groove extending from the front surface of the substrate toward the back surface;
    Forming a semiconductor layer in which a III-V group compound semiconductor is crystal-grown from the surface of the substrate and crosslinked above the groove;
    Removing the substrate from the back surface of the substrate until the groove is exposed;
    The manufacturing method of the structure characterized by providing the process which fills the material which has a heat conductivity coefficient larger than the heat conductivity coefficient of air in the exposed groove | channel.
  2.   2. The method of manufacturing a structure according to claim 1, wherein a metal is selected as a material having a thermal conductivity coefficient larger than that of air.
  3.   3. The method of manufacturing a structure according to claim 1, wherein the substrate is a semiconductor.
  4.   4. The method of manufacturing a structure according to claim 3, wherein the substrate is silicon (Si).
  5.   5. The method of manufacturing a structure according to claim 3, wherein (111) is selected as a surface orientation of the surface of the substrate.
  6.   In the step of forming the groove, a plurality of groove groups extending from the front surface to the back surface side of the substrate are formed in a stripe shape, and the longitudinal direction of the groove group is the <11-2> direction of the (111) plane of the substrate. Alternatively, the structure is selected in the direction equivalent to this.
  7. An upper layer of a III-V compound semiconductor;
    It has a lower layer that touches the upper layer,
    The lower layer comprises a partial region of material that extends from the lower surface to the back surface and has a thermal conductivity coefficient greater than that of air,
    A structure in which the partial regions are repeatedly formed at intervals in a plane orthogonal to the direction connecting the front surface and the back surface of the lower layer.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011155164A (en) * 2010-01-28 2011-08-11 Toyota Central R&D Labs Inc Nitride semiconductor device, and method of manufacturing the same
US8557681B2 (en) * 2006-10-30 2013-10-15 International Rectifier Corporation III-nitride wafer fabrication

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8557681B2 (en) * 2006-10-30 2013-10-15 International Rectifier Corporation III-nitride wafer fabrication
JP2011155164A (en) * 2010-01-28 2011-08-11 Toyota Central R&D Labs Inc Nitride semiconductor device, and method of manufacturing the same

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