JP2006164998A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for reducing fluctuation in the threshold voltage using a high dielectric constant insulating film and also provide a manufacturing method of the same. <P>SOLUTION: A gate insulating film 9 formed on a semiconductor substrate 5 includes a high dielectric constant insulating film. The MOSFET including the same gate length and gate insulating film among a plurality of MOSFETs has a structure that a single channel having the channel width W is provided or a plurality of channels having the channel width W are provided in parallel. Moreover, a radius of curvature at the end part of an element isolating region 6 of MOSFETs having different channel widths is also different. In this case, it is preferable that the surface of the element isolating region 6 is substantially same and depth up to the bottom surface from the font surface of the element isolating region 6 is different. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a high dielectric constant insulating film and a manufacturing method thereof.

  In recent years, high integration in semiconductor integrated circuit devices has greatly advanced. In MOS (Metal Oxide Semiconductor) type semiconductor devices, miniaturization of elements such as transistors and high performance have been achieved. In particular, with regard to the gate insulating film which is one of the elements constituting the MOS structure, the thinning is rapidly progressing to cope with the miniaturization, high speed operation and low voltage of the transistor.

Conventionally, a silicon oxide film (SiO ₂ film), a silicon oxynitride film (SiON film), or the like has been used as a material constituting the gate insulating film. However, when these materials are used, there is a problem in that power consumption increases due to an increase in leakage current accompanying thinning.

  On the other hand, a sub 0.1 μm generation CMOS (Complementary Metal Oxide Semiconductor) requires a performance of 1.5 nm or less in terms of a silicon oxide film with respect to a gate insulating film. However, in the conventional structure using a silicon oxide film or a silicon oxynitride film as a gate insulating film, when the film thickness is 1.5 nm or less, the leakage current flowing through the capacitor increases. For this reason, although high-speed operation can be realized, there is a problem that it is difficult to achieve low power consumption.

  To solve these problems, it is proposed to use a material having a high relative dielectric constant, such as a metal oxide such as hafnium (Hf), aluminum (Al), or zinc (Zn), nitride, or silicide, as the gate insulating film. Has been. In general, the amount of charge accumulation increases as the relative dielectric constant increases. Therefore, when the gate capacitance is the same, the physical film thickness can be made thicker than the silicon oxide film by using the high dielectric constant insulating film. That is, by using the high dielectric constant insulating film as the gate insulating film, an increase in the leakage current of the capacitor can be suppressed.

  On the other hand, conventionally, when MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) have various channel widths, in an integrated circuit constituted by these MOSFETs, the signal generated in each signal circuit is different from the threshold voltage. There was a problem that the timing was not matched and the circuit operation was hindered.

  To solve this problem, a method has been proposed in which all the MOSFETs are formed with substantially the same channel width so that the threshold voltages are the same (for example, see Patent Document 1).

JP 2001-185721 A

  However, when a high dielectric constant insulating film is used as the gate insulating film, the threshold voltage further varies due to the influence of fixed charges and interface states generated at the interface between the substrate and the insulating film or between the insulating film and the gate electrode. There was a problem.

  For example, when a high dielectric constant insulating film containing hafnium is used, the threshold voltage of a PMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor) increases. On the other hand, when a high dielectric constant insulating film containing aluminum is used, the threshold voltage of an NMOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor) increases.

  When the increase of the threshold voltage exceeds the range that can be controlled by the impurity concentration, the driving capability of the MOSFET is lowered. Therefore, compared with the conventional silicon oxide film or silicon oxynitride film, the gate leakage current can be reduced, but the on-current is reduced and the high speed and low power consumption cannot be achieved. Occurs. It is difficult to sufficiently solve these problems even by the conventional method.

  The present invention has been made in view of such problems. That is, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can reduce fluctuations in threshold voltage using a high dielectric constant insulating film.

  Other objects and advantages of the present invention will become apparent from the following description.

  A first invention of the present application is a semiconductor device including a plurality of MOSFETs arranged on a semiconductor substrate, wherein the MOSFET gate insulating film is an insulating film including a high dielectric constant insulating film, and among the MOSFETs, the gate length and Those having the same gate insulating film have a structure in which a single channel having a channel width W or a plurality of channels having a channel width W are arranged in parallel, and the curvature at the end of the element isolation region of MOSFETs having different channel widths The present invention relates to a semiconductor device characterized by having different values.

  According to a second aspect of the present invention, in a semiconductor device including a plurality of MOSFETs disposed on a semiconductor substrate, the gate insulating film of the MOSFET is an insulating film including a high dielectric constant insulating film. Those having the same length and gate insulating film have a structure in which a single channel having a channel width of W or a plurality of channels having a channel width of W are arranged in parallel. The present invention relates to a semiconductor device characterized in that the bottom surface is substantially the same surface and the depth from the surface of the element isolation region to the bottom surface is different.

  According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a high dielectric constant insulating film as a gate insulating film, the step of forming a groove portion in a predetermined region of a semiconductor substrate to be an element isolation region, A step of forming a first oxide film on the inner surface of the groove portion by an oxidation reaction, a step of selectively removing the first oxide film from the groove portions in regions having different channel widths, and a step of forming the groove portion by a second oxidation reaction. The present invention relates to a method for manufacturing a semiconductor device, comprising: a step of forming a second oxide film on an inner surface; and a step of forming an insulating film so as to fill a groove.

  Further, the fourth invention of the present application is a method of manufacturing a semiconductor device having a high dielectric constant insulating film as a gate insulating film, the step of forming a groove in a predetermined region of a semiconductor substrate to be an element isolation region, and an oxidation reaction. A semiconductor comprising: a step of forming an oxide film on an inner surface of a groove portion; a step of embedding an insulating film in the groove portion; and a step of selectively etching an insulating film in a region having a different channel width to a predetermined thickness The present invention relates to a device manufacturing method.

  According to the first invention of this application, since the threshold voltage becomes an appropriate value, a decrease in on-current can be suppressed even when a high dielectric constant insulating film is used. Further, the threshold voltage can be controlled in a wide range by optimizing the combination of the channel width and the curvature.

  In addition, according to the second invention of the present application, since the threshold voltage becomes an appropriate value, it is possible to suppress a decrease in on-state current even when a high dielectric constant insulating film is used. Further, the threshold voltage can be controlled in a wide range by optimizing the channel width and the depth from the surface to the bottom surface of the element isolation region in combination.

  Further, according to the third invention of the present application, it is possible to manufacture a semiconductor device capable of reducing the fluctuation of the threshold voltage by using the high dielectric constant insulating film.

  Furthermore, according to the fourth invention of the present application, it is possible to manufacture a semiconductor device capable of reducing fluctuations in threshold voltage by using a high dielectric constant insulating film.

Embodiment 1 FIG.
FIG. 1 is a plan view of the semiconductor device according to the present embodiment. As shown in the figure, a gate electrode 3 is provided on the active region 1 of the PMOSFET and the active region 2 of the NMOSFET. Each MOSFET is connected to a wiring layer (not shown) via a contact 4.

FIG. 2A is a diagram showing the relationship between the channel width of NMOSFET and the threshold voltage. FIG. 2B is a diagram showing the relationship between the channel width of the PMOSFET and the threshold voltage. In the present embodiment has a first feature in that to determine the desired seek channel width corresponding to the threshold voltage, respectively NMOSFET and PMOSFET from this value the channel width _{W n} and _{W p.}

In the present embodiment, NMOSFET is characterized by having a structure in which channel width parallel a plurality of single channel or the channel is W _n. Similarly, the PMOSFET, characterized by having a structure in which channel width parallel a plurality of single channel or the channel is W _p. FIG. 1 shows an example in which there is one such NMOSFET and one PMOSFET. Further, FIG. 3, there one 2 NMOSFET is in parallel with the channel width _{W n,} is an example one 3 PMOSFET is in parallel with a channel width _{W p.} Furthermore, in the present embodiment, any one of such NMOSFETs and PMOSFETs is sufficient. For example, the present invention can be applied only to the NMOSFET and PMOSFET that are more difficult to control the threshold voltage.

However, a single channel having a channel width W _n or NMOSFETs having a structure in which a plurality of such channels are arranged in parallel have the same gate length and gate insulating film. Similarly, the structure in which the channel width is parallel a plurality of single channel or the channel is W _p also, the same gate length and a gate insulating film.

How to arrange the transistors having the channel width W _n or W _p can be determined as follows. In general, in a semiconductor device, a transistor group having different threshold voltages is manufactured by changing the film thickness, gate length, and substrate concentration of a gate insulating film in accordance with an operating voltage and operating performance. Therefore, the same channel width is determined for transistors having the same threshold voltage, and the number of transistors in parallel with the same channel width is determined so that the drain current of the transistor is optimized.

  By doing so, the threshold voltage becomes an appropriate value, so that a decrease in on-current can be suppressed even when a high dielectric constant insulating film is used. Therefore, if the circuit speed is the same, it is possible to suppress the power consumption corresponding to the reduced gate leakage current as compared with the case where the silicon oxide film is used as the gate insulating film (FIG. 4). .

  FIG. 5 is a cross-sectional view of the semiconductor device in this embodiment.

  In FIG. 5, the semiconductor substrate 5 is provided with an element isolation region 6 for electrically insulating and isolating the active region. The active region into which the P-type impurity is introduced constitutes the P well 7, and the active region into which the N-type impurity is introduced constitutes the N well 8. A gate electrode 10 is provided on the semiconductor substrate 5 via a gate insulating film 9. In FIG. 5, 11 is an interlayer insulating film, 12 is a contact, and 13 is a wiring layer.

  In the present embodiment, it is assumed that the gate insulating film 9 is an insulating film including a high dielectric constant insulating film. For example, the gate insulating film may be a single layer film made of an oxide, nitride, silicide, or the like of a metal such as hafnium (Hf), aluminum (Al), or zinc (Zn), or a high dielectric constant thereof. It may be a laminated film of an insulating film and a silicon oxide film.

  The gate electrode 10 can be made of, for example, a polysilicon film. In this case, a metal silicide film such as a nickel silicide film or a cobalt silicide film may be formed on the polysilicon film. Further, the gate electrode 10 may be formed using a metal film instead of the polysilicon film.

  The second feature of the present embodiment is that MOSFETs having different channel widths have different curvatures at the end of the element isolation region. This can also be said to be characterized by the fact that MOSFETs having different threshold voltages have different curvatures in the element isolation region. This is because, as described above, the first feature of the present embodiment is that the channel width is determined from the predetermined threshold voltage.

  In the example of FIG. 5, the curvature of the end of the element isolation region 6 in the N well 8 is smaller than the curvature of the end of the element isolation region 6 in the P well 7.

  FIG. 6 is an enlarged cross-sectional view of the element isolation region 6 at the boundary between the NMOSFET and the PMOSFET in FIG. As can be seen from FIG. 6, the curvature of the end on the PMOSFET side is smaller than the curvature of the end on the NMOSFET side.

  FIG. 7 is a diagram showing the relationship between the channel width and the threshold voltage when the curvature is changed. As can be seen from the figure, the degree of change of the threshold voltage with respect to the channel width changes as the curvature changes. Therefore, the threshold voltage can be controlled in a wide range by optimizing the channel width and the curvature in combination.

  For example, when a high dielectric constant insulating film containing hafnium is used, it is known that the threshold voltage of the PMOSFET increases. Therefore, the curvature of the end portion of the element isolation region in the PMOSFET may be increased. On the other hand, when a high dielectric constant insulating film containing aluminum is used, it is known that the threshold voltage of the NMOSFET increases. Therefore, the curvature of the end portion of the element isolation region in the NMOSFET may be increased.

  Next, an example of a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. In these drawings, the parts denoted by the same reference numerals are the same.

  First, after a silicon oxide film 22 and a silicon nitride film 23 are stacked in this order on the silicon substrate 21, the silicon oxide film 22 and the silicon nitride film 23 in a portion other than the predetermined region are removed by using a photolithography method. (FIG. 8). A semiconductor substrate other than a silicon substrate may be used, and not only a bulk silicon substrate but also an SOI (Silicon on Insulator) substrate or the like may be used.

  Next, the groove 24 is formed by etching the silicon substrate 21 using the laminated film composed of the silicon oxide film 22 and the silicon nitride film 23 as a mask (FIG. 9).

  Next, a first oxide film is formed on the inner surface of the groove 24 by a first oxidation reaction. Specifically, a silicon oxide film 25 is formed on the inner wall of the groove 24 by thermal oxidation or plasma oxidation at a high temperature (FIG. 10). In consideration of plasma damage, the first oxidation reaction is preferably thermal oxidation at a high temperature.

  Next, the silicon oxide film 25 in the region where the curvature at the end of the element isolation region is desired to be reduced is removed. For example, as shown in FIG. 11, the region to be the NMOSFET is covered with a resist film 26, and the silicon oxide film 25 in the exposed region to be the PMOSFET is removed by etching. At this time, a part of the underlying silicon substrate 21 is also etched together with the silicon oxide film 25. Thereby, since the element isolation region of the PMOSFET becomes deep, the breakdown voltage of the semiconductor device can be improved. In this case, it is preferable to etch the silicon substrate 21 at a depth d of 20 nm to 30 nm (FIG. 11).

  Next, after removing the resist film 26 that is no longer needed, a second oxide film is formed on the inner surface of the groove 24 by a second oxidation reaction. Specifically, thermal oxidation or plasma oxidation is again performed at a high temperature to form a silicon oxide film 27 on the inner wall of the groove 24 (FIG. 12). In FIG. 12, the silicon oxide film 25 (FIG. 11) in the region of the NMOSFET cannot be distinguished from the silicon oxide film formed by the second oxidation. In consideration of plasma damage, the second oxidation reaction is preferably thermal oxidation at a high temperature as in the first oxidation reaction.

  As shown in FIG. 12, the silicon oxide film 27 formed in the region of the PMOSFET has a reduced curvature at the upper end portion of the side wall of the groove portion 24 due to the penetration of the bird's beak. On the other hand, in the silicon oxide film 27 formed in the region of the NMOSFET, since the second oxidation reaction hardly proceeds, there is no change in the curvature at the upper end portion of the side wall portion of the groove portion 24.

  Next, a silicon oxide film 28 as an insulating film is formed on the entire surface so as to fill the groove 24 (FIG. 13). Next, the silicon oxide film 28, the silicon nitride film 23, and the silicon oxide film 22 over the region to be an active region are removed by performing a CMP (Chemical Mechanical Polishing) method or dry or wet etching. By the above steps, as shown in FIG. 14, the element isolation regions 29 having different curvatures at the end portions can be formed by the NMOSFET and the PMOSFET. The region isolated by the element isolation region 29 becomes the active region 30.

  After the element isolation region is formed, a well, a gate insulating film, a gate electrode, and source / drain regions are formed, and then a contact and wiring formation process is performed to complete a semiconductor integrated circuit.

  In FIG. 14, in MOSFETs having different channel widths, the surface of the element isolation region is substantially the same surface, and the depth from the surface to the bottom surface of the element isolation region is different. In the present embodiment, the difference in depth is preferably in the range of 20 nm to 30 nm. In FIG. 11, the structure of FIG. 5 is obtained when the surface of the silicon substrate 21 is not intentionally etched. That is, in FIG. 5, even in the case of MOSFETs having different channel widths, the surface and the bottom surface of the element isolation region are substantially the same surface. Although this embodiment may have any structure, as described above, the structure of FIG. 14 is preferable from the viewpoint of improving the pressure resistance.

  The present embodiment can also be applied to a semiconductor device having a FinFET (Fin Field Effect Transistor) structure as shown in FIG. In FIG. 15, 31 is a silicon substrate, 32 is an element isolation region, 33 is a gate insulating film, and 34 is a gate electrode.

  As shown in FIG. 15, the gate insulating film 33 and the gate electrode 34 have a structure sandwiching the active region 35. The end portion of the element isolation region 32 corresponds to the end portion of the active region 35. Therefore, the effects of the present invention can be obtained by changing the curvature at the end of the active region for MOSFETs having different threshold voltages. For example, in the example of FIG. 15, the curvature at the end of the active region 35 is smaller in the PMOSFET than in the NMOSFET.

Embodiment 2. FIG.
FIG. 16 is a cross-sectional view of the semiconductor device according to the present embodiment. In this embodiment, too, it obtains a channel width corresponding to the desired threshold voltage, and the first determining means determines the NMOSFET and PMOSFET respective channel width _{W n} and _{W p} from this value.

  In FIG. 16, the semiconductor substrate 41 is provided with an element isolation region 42 that electrically isolates and isolates the active region. The active region into which the P-type impurity is introduced constitutes the P well 43, and the active region into which the N-type impurity is introduced constitutes the N well 44. A gate electrode 46 is provided on the semiconductor substrate 41 with a gate insulating film 45 interposed therebetween. In FIG. 16, 47 is an interlayer insulating film, 48 is a contact, and 49 is a wiring layer.

  The gate insulating film 45 is assumed to be an insulating film including a high dielectric constant insulating film. For example, the gate insulating film may be a single layer film made of an oxide, nitride, silicide, or the like of a metal such as hafnium (Hf), aluminum (Al), or zinc (Zn), or a high dielectric constant thereof. It may be a laminated film of an insulating film and a silicon oxide film.

  The gate electrode 46 can be made of, for example, a polysilicon film. A metal silicide film such as a nickel silicide film or a cobalt silicide film may be formed on the polysilicon film.

  The second feature of the present embodiment is that MOSFETs having different channel widths have substantially the same bottom surface in the element isolation region and the depths from the surface to the bottom surface of the element isolation region are different. It is said. This can be said that MOSFETs having different threshold voltages are characterized in that the bottom surfaces of the element isolation regions are substantially the same and the depths from the surface to the bottom surface of the element isolation regions are different. . This is because, as described above, the first feature of the present embodiment is that the channel width is determined from the predetermined threshold voltage.

In the example of FIG. 16, the depth h ₁ from the surface to the bottom surface of the element isolation region 42 in the P well 43 is smaller than the depth h ₂ from the surface to the bottom surface of the element isolation region 42 in the N well 44. In other words, the depth h ₁ from the surface to the bottom surface of the element isolation region on the NMOSFET side is smaller than the depth h ₂ from the surface to the bottom surface of the element isolation region on the PMOSFET side.

  FIG. 17 is a diagram showing the relationship between the channel width and the threshold voltage when the depth from the surface to the bottom surface of the element isolation region is changed. As can be seen from the figure, as the depth from the surface to the bottom surface of the element isolation region changes, the degree of change of the threshold voltage with respect to the channel width changes. Therefore, the threshold voltage can be controlled in a wide range by optimizing the channel width and the depth from the surface to the bottom surface of the element isolation region in combination.

  Next, an example of a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. In these drawings, the parts denoted by the same reference numerals are the same.

  First, after a silicon oxide film 52 and a silicon nitride film 53 are stacked in this order on the silicon substrate 51, the silicon oxide film 52 and the silicon nitride film 53 in a portion other than a predetermined region are removed by using a photolithography method. (FIG. 18). A semiconductor substrate other than a silicon substrate may be used, and not only a bulk silicon substrate but also an SOI (Silicon on Insulator) substrate or the like may be used.

  Next, a groove portion 54 is formed by etching the silicon substrate 51 using a laminated film composed of the silicon oxide film 52 and the silicon nitride film 53 as a mask (FIG. 19).

  Next, a silicon oxide film 55 is formed on the inner wall of the groove 54 by thermal oxidation or plasma oxidation at a high temperature (FIG. 20).

  Next, a silicon oxide film 56 as an insulating film is formed on the entire surface so as to fill the groove 54 (FIG. 21). Next, the silicon oxide film 56, the silicon nitride film 53, and the silicon oxide film 52 over the region to be the active region are removed by performing a CMP (Chemical Mechanical Polishing) method or dry or wet etching (FIG. 22). . In FIG. 22, since the silicon oxide film 55 cannot be distinguished from the silicon oxide film 56, both are combined into a silicon oxide film 56.

  Next, a part of the silicon oxide film 56 in a region where the depth from the surface to the bottom surface of the element isolation region is desired to be reduced is removed. For example, as shown in FIG. 23, the PMOSFET region is covered with a resist film 57, and the silicon oxide film 56 in the exposed NMOSFET region is etched to a predetermined thickness.

  Thereafter, by removing the resist film 57, as shown in FIG. 24, element isolation regions 58 having different depths from the front surface to the bottom surface can be formed between the MNOSFET and the PMOSFET. The region isolated by the element isolation region 58 becomes the active region 59.

  After the element isolation region is formed, a well, a gate insulating film, a gate electrode, and source / drain regions are formed, and then a contact and wiring formation process is performed to complete a semiconductor integrated circuit.

  The present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

2 is an example of a plan view of the semiconductor device in Embodiment 1. FIG. (A) is a figure which shows the relationship between the channel width and threshold voltage of NMOSFET, (b) is a figure which shows the relationship between the channel width and threshold voltage of PMOSFET. FIG. 10 is another example of a plan view of the semiconductor device in the first embodiment. It is a figure which shows the relationship between a gate leak current and the ON current of a transistor. 3 is an example of a cross-sectional view of the semiconductor device in Embodiment 1. FIG. FIG. 6 is a partially enlarged cross-sectional view of an element isolation region in FIG. 5. It is a figure which shows the relationship between the channel width when changing a curvature, and a threshold voltage. 8 is a diagram for describing the method for manufacturing the semiconductor device in Embodiment 1. FIG. 8 is a diagram for describing the method for manufacturing the semiconductor device in Embodiment 1. FIG. 8 is a diagram for describing the method for manufacturing the semiconductor device in Embodiment 1. FIG. 8 is a diagram for describing the method for manufacturing the semiconductor device in Embodiment 1. FIG. 8 is a diagram for describing the method for manufacturing the semiconductor device in Embodiment 1. FIG. 8 is a diagram for describing the method for manufacturing the semiconductor device in Embodiment 1. FIG. 8 is a diagram for describing the method for manufacturing the semiconductor device in Embodiment 1. FIG. FIG. 10 is another example of a cross-sectional view of the semiconductor device in the first embodiment. FIG. 3 is an example of a cross-sectional view of a semiconductor device in a second embodiment. It is a figure which shows the relationship between the channel width and threshold voltage by the depth of an element isolation region. FIG. 10 illustrates a method for manufacturing a semiconductor device in a second embodiment. FIG. 10 illustrates a method for manufacturing a semiconductor device in a second embodiment. FIG. 10 illustrates a method for manufacturing a semiconductor device in a second embodiment. FIG. 10 illustrates a method for manufacturing a semiconductor device in a second embodiment. FIG. 10 illustrates a method for manufacturing a semiconductor device in a second embodiment. FIG. 10 illustrates a method for manufacturing a semiconductor device in a second embodiment. FIG. 10 illustrates a method for manufacturing a semiconductor device in a second embodiment.

Explanation of symbols

1, 2, 30, 35, 59 Active region 3 Gate electrode 4 Contact 5, 41 Semiconductor substrate 6, 29, 32, 42, 58 Element isolation region 7, 43 P well 8, 44 N well 9, 33, 45 Gate insulation Film 10, 34, 46 Gate electrode 11, 47 Interlayer insulating film 12, 48 Contact 13, 49 Wiring layer 21, 31, 51 Silicon substrate 22, 25, 27, 52, 55, 56 Silicon oxide film 23, 53 Silicon nitride film 24, 54 Groove 26, 57 Resist film

Claims (9)

In a semiconductor device comprising a plurality of MOSFETs arranged on a semiconductor substrate,
The gate insulating film of the MOSFET is an insulating film including a high dielectric constant insulating film,
Among the MOSFETs, those having the same gate length and gate insulating film have a structure in which a single channel having a channel width of W or a plurality of channels having a channel width of W are arranged in parallel,
A semiconductor device characterized in that curvatures at the end portions of the element isolation regions of the MOSFETs having different channel widths are different.   2. The semiconductor device according to claim 1, wherein in the MOSFETs having different channel widths, the surface of the element isolation region is substantially coplanar, and the depth from the surface to the bottom surface of the element isolation region is different.   The semiconductor device according to claim 2, wherein the difference in depth is within a range of 20 nm to 30 nm. In a semiconductor device comprising a plurality of MOSFETs arranged on a semiconductor substrate,
The gate insulating film of the MOSFET is an insulating film including a high dielectric constant insulating film,
Among the MOSFETs, those having the same gate length and gate insulating film have a structure in which a single channel having a channel width of W or a plurality of channels having a channel width of W are arranged in parallel,
The semiconductor device according to claim 1, wherein the bottom surfaces of the element isolation regions are substantially coplanar and the depths from the surface to the bottom surface of the element isolation regions are different for the MOSFETs having different channel widths.   The semiconductor device according to claim 1, wherein the MOSFET is at least one of NMOSFET and PMOSFET. A method for manufacturing a semiconductor device having a high dielectric constant insulating film as a gate insulating film,
Forming a groove in a predetermined region of the semiconductor substrate to be an element isolation region;
Forming a first oxide film on the inner surface of the groove by a first oxidation reaction;
Selectively removing the first oxide film for the trenches in regions having different channel widths;
Forming a second oxide film on the inner surface of the groove by a second oxidation reaction;
And a step of forming an insulating film so as to fill the groove.   The method for manufacturing a semiconductor device according to claim 6, wherein, following the step of selectively removing the first oxide film, the semiconductor substrate is etched to a predetermined depth.   The method of manufacturing a semiconductor device according to claim 7, wherein the predetermined depth is in a range of 20 nm to 30 nm. A method for manufacturing a semiconductor device having a high dielectric constant insulating film as a gate insulating film,
Forming a groove in a predetermined region of the semiconductor substrate to be an element isolation region;
Forming an oxide film on the inner surface of the groove by an oxidation reaction;
Embedding an insulating film in the groove;
And a step of selectively etching the insulating film in regions having different channel widths to a predetermined thickness.

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