JP2006164396A - Data reproducing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data reproducing apparatus in which jitter can be reduced without attenuating a signal component. <P>SOLUTION: The data reproducing apparatus includes a state detecting circuit 101 for discriminating a signal in a plurality of states; a high frequency band attenuation circuit 102 for attenuating a high frequency band of the signal; and a gain setting circuit 105 for setting weight to a first weighting circuit 103 and a second weighting circuit 104 in accordance with a state of the state detecting circuit 101, and in a state in which the apparatus is affected by jitter largely, weighting of the second weighting circuit 104 is made large, otherwise, weighting of the first weighting circuit 103 is made large, thereby, jitter in the high frequency band is reduced without attenuating a signal component. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data reproduction apparatus, and more particularly to a technique for suppressing jitter of a reproduction signal in the data reproduction apparatus.

  In recent years, with the increase in the amount of information handled, the storage capacity of magnetic recording and reproducing devices has been rapidly increasing, and in order to cope with this, the recording density of recording media has been increased. Since an increase in recording density causes a deterioration in data quality and data reliability is impaired, a perpendicular magnetic recording method for recording data perpendicularly to a magnetic recording surface has recently attracted attention.

  The perpendicular magnetic recording method has the effect of reducing the recording area compared to the conventional horizontal recording method, while the magnetic particles on the surface of the magnetic medium are not uniform in size and magnetized in the same direction. The problem is the noise of the medium caused by magnetic clusters, which are a group of particles. As a countermeasure against such noise, there is known a method of suppressing jitter of a signal read from a medium by using adaptive equalization (see, for example, Patent Document 1).

  FIG. 12 is a diagram for explaining jitter suppression using adaptive equalization. In FIG. 12, a signal read from a recording medium is sampled at an appropriate timing by an AD converter (not shown) through an amplifier (not shown). The sampled digital data is equalized by an equalization circuit 1201 so as to be easily binarized by a binarization circuit 1204 provided at a subsequent stage. This equalization is performed with particular emphasis on jitter reduction. The equalization error detection circuit 1202 obtains an equalization error near the zero cross where the influence of jitter is strong. The equalization control circuit 1203 controls the coefficient of the equalization circuit 1201 so that the error output from the equalization error detection circuit 1202 is minimized.

Thus, the conventional jitter suppression method performs jitter suppression using feedback control such as detecting the amount of jitter and learning the coefficient.
Japanese Patent Laid-Open No. 9-73726 (page 3-8, FIG. 1)

  However, in the above-described conventional jitter suppression method, in the feedback loop, calculation delays by the equalization circuit 1201, the equalization error detection circuit 1202, and the equalization control circuit 1203 occur, and the loop gain of this control system can be increased. I could not do it. For this reason, the controllable frequency band cannot be widened, and there is a problem that jitter in a high frequency band cannot be removed.

  The present invention has been made to solve the above-described conventional problems, and an object of the present invention is to provide a data reproducing apparatus capable of suppressing jitter spreading to a high frequency band.

In order to solve the conventional problem, the data reproducing apparatus according to claim 1 of the present invention removes a high frequency component of a digital sampling signal obtained by sampling a signal read from a recording medium. An attenuation circuit, a state detection circuit for detecting the state of the digital sampling signal, a first weighting circuit for weighting the digital sampling signal, and a weight for a signal output from the high-frequency attenuation circuit A second weighting circuit to perform, a gain setting circuit for setting the weighting of the first weighting circuit and the second weighting circuit, a signal output from the first weighting circuit, and the second weighting An addition circuit for adding a signal output from the circuit, wherein the gain setting circuit is configured to output the first signal according to a state output from the state detection circuit. Weighting circuits, and is for setting the weighting for each of the second weighting circuit.
As a result, the signal whose jitter is suppressed by the high-frequency cutoff and the original reproduced signal are weighted differently according to the signal state, and by adding both, jitter is maintained while leaving the high-frequency signal. It can be reduced.

According to a second aspect of the present invention, there is provided a data reproduction apparatus comprising: a high frequency attenuation circuit for removing a high frequency component of a digital sampling signal obtained by sampling a signal read from a recording medium; and the digital sampling signal A state detection circuit for detecting the state of the digital sampling signal, a first weighting circuit for weighting the digital sampling signal, a second weighting circuit for weighting the signal output from the high-frequency attenuation circuit, A gain setting circuit for setting weights of the first weighting circuit and the second weighting circuit; a signal output from the first weighting circuit; and a signal output from the second weighting circuit. From the addition circuit for adding, the equalization circuit for equalizing the signal output from the addition circuit, the signal output from the addition circuit, and the equalization circuit An equalization coefficient learning circuit for calculating an equalization coefficient of the equalization circuit by a received signal, and jitter for detecting a jitter amount in the digital sampling signal by an equalization error output from the equalization coefficient learning circuit The gain setting circuit according to a state output from the state detection circuit and a jitter amount output from the jitter detection circuit, according to the first weighting circuit and the second weighting circuit. A weight is set for each of the above.
As a result, the signal whose jitter is suppressed by the high-frequency cutoff and the original reproduced signal are weighted differently according to the signal state, and by adding both, jitter is maintained while leaving the high-frequency signal. It can be reduced. Further, by performing equalization after jitter reduction, a signal with less distortion can be obtained.

According to a third aspect of the present invention, in the data reproduction device according to the first or second aspect, the state detected by the state detection circuit is that the digital sampling signal is near zero cross. It is either a state or a state not near the zero cross.
As a result, different weights can be applied to a signal in the vicinity of the zero cross where the influence of jitter is large and a signal in a state where the influence of the jitter is not near the zero cross.

According to a fourth aspect of the present invention, there is provided the data reproduction device according to the first or second aspect, wherein the state detection circuit includes a plurality of consecutive samples of the digital sampling signal and a prediction. The minimum error for detecting the pattern with the smallest error by comparing the magnitudes of the plurality of error signals output from the plurality of pattern error detection circuits and the plurality of pattern error detection circuits for calculating the error with the pattern to be detected A pattern detection circuit for detecting the pattern having the smallest error as the state of the digital sampling signal.
This makes it possible to perform more detailed and reliable state determination than when detecting a state using only one sample.

According to a fifth aspect of the present invention, there is provided the data reproduction device according to the first or second aspect, wherein the high frequency attenuation is the data reproduction device according to the first or second aspect. The circuit is characterized in that the transfer function is (1 + 2 · D + D · D) · A, where • represents multiplication, D is a delay operator, and A is an arbitrary value. is there.
As a result, it is possible to generate a signal in which jitter is suppressed by high-frequency cutoff.

According to a sixth aspect of the present invention, there is provided the data reproduction device according to the second aspect, wherein the jitter detection circuit has an equalization error in a state near the zero cross, an error in the state not near the zero cross, and the like. , And the gain setting circuit detects the magnitude of jitter in the vicinity of the zero cross and the jitter in the state not near the zero cross. And the weights for the first weighting circuit and the second weighting circuit are determined based on the comparison results and the magnitudes of the respective jitters.
As a result, more appropriate weighting can be set, so that jitter can be reduced more effectively.

  According to the data reproducing device of the present invention, a signal whose jitter is suppressed by high-frequency cutoff and an original reproduced signal are weighted differently according to the state of the signal, and both are added, It is possible to reduce the jitter while leaving the signal in the area.

  In addition, since equalization is performed after jitter reduction, it is possible to obtain a signal with less distortion.

  Embodiments of a data reproducing apparatus according to the present invention will be described below in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a diagram showing a configuration of a data reproducing apparatus according to Embodiment 1 of the present invention.
As shown in FIG. 1, the data reproducing apparatus 100 according to the first embodiment of the present invention includes a state detection circuit 101, a high-frequency attenuation circuit 102, a first weighting circuit 103, a second weighting circuit 104, The gain setting circuit 105, the addition circuit 106, the equalization circuit 107, and the binarization circuit 108 are provided.

  The state detection circuit 101 detects the current state of the sampled digital signal S1. The high frequency attenuating circuit 102 attenuates the high frequency part of the sampled digital signal S1. Each of the first weighting circuit 103 and the second weighting circuit 104 weights the input signal. The gain setting circuit 105 sets a predetermined weight for the first weighting circuit 103 and the second weighting circuit 104 based on the state of the digital signal S1. The adder circuit 106 adds the output signals of the two weighting circuits. The equalization circuit 107 filters the output signal of the addition circuit 106. The binarization circuit 108 binarizes the output signal of the equalization circuit 107.

Next, the operation will be described.
In FIG. 1, after the amplitude of a signal read from a recording medium is adjusted by an amplifier (not shown), a partial response class 1 (PR (1, 1)) type is obtained by a pre-stage equalizer (not shown). Alternatively, it is equalized to a type close to that and sampled at an appropriate timing by an AD converter circuit (not shown). The sampled digital signal S <b> 1 is input to the state detection circuit 101, the high frequency attenuation circuit 102, and the first weighting circuit 103.

  The state detection circuit 101 detects the state of the digital signal S 1 and outputs it to the gain setting circuit 105. Further, the high frequency attenuating circuit 102 attenuates the high frequency part of the digital signal S 1 and inputs it to the second weighting circuit 104.

  The gain setting circuit 105 sets weights to the first weighting circuit 103 and the second weighting circuit 104 based on the state of the digital signal S1 input from the state detection circuit 101, respectively. For example, when the state of the digital signal S1 is near zero cross, the weight of the first weighting means 103 is set to 0.2, and the weight of the second weighting means 104 is set to 0.8.

  The first weighting circuit 103 and the second weighting circuit 104 respectively weight and add the sampled digital signal S1 and the signal S2 whose high frequency part has been attenuated by the high frequency attenuation circuit 102. Output to the circuit 106. The adder circuit 106 adds the two input signals and outputs the result to the equalization circuit 107.

  The equalization circuit 107 filters the output signal S3 of the addition circuit 106 so as to be easily binarized by the subsequent binarization circuit 108, and equalizes again to the PR (1, 1) type. The output signal S4 of the equalization circuit 107 is input to the binarization circuit 108, and the binarization circuit 108 binarizes the filtered signal by the maximum likelihood decoding method.

The signal processing in the above operation will be described with reference to FIG.
FIG. 6A shows the digital signal S1 without jitter. As described above, since the digital signal S1 is equalized to the PR (1, 1) type, it can be seen that it has three values. FIG. 6B shows the digital signal S1 when there is jitter. It can be seen that the deviation in the amplitude direction is caused by jitter, and in particular, the zero cross (intermediate value) error is larger than the upper and lower errors among the three values. This is because the signal slope is larger in the vicinity of the zero cross and is greatly affected by jitter.

  FIG. 6C is a diagram illustrating a signal obtained by applying high-frequency attenuation to the output signal S2 of the high-frequency attenuation circuit 102, that is, the digital signal S1 having jitter. When high-frequency attenuation is applied, the amount of amplitude deviation due to jitter is reduced, but the high-frequency component of the signal is also attenuated, so the S / N is not improved.

  FIG. 6D shows the output signal S3 of the adder circuit 106, that is, the signal near the zero cross where the influence of jitter is large increases the ratio of the signal attenuated by the high band, and the signal not near the zero cross is the signal of the original digital signal S1. It is a figure showing the signal which increased the ratio and synthesize | combined both signals. As is apparent from FIG. 6, the output signal S3 of the adder circuit 106 is one in which signal attenuation is suppressed and the influence of jitter is reduced. Also, in this signal processing, no delay due to feedback occurs, so that jitter existing in a high band can be suppressed.

Next, a detailed configuration and operation of the data reproducing apparatus 100 according to the first embodiment will be described.
First, the state detection circuit 101 will be described.

  The state detection circuit 101 is a circuit that determines what state the digital signal S1 is currently in. As described above, the digital signal S1 is equalized to PR (1, 1) or a type close thereto by a pre-equalizer (not shown), and sampling by the AD converter circuit is appropriately performed. In this case, the signal becomes ternary as shown in FIG. The state determination of the digital signal S1 by the state detection circuit 101 can detect, for example, these three values as the state A, the state B, and the state C, respectively, and determine whether the digital signal S1 is near the zero cross. Such a determination can be made, for example, by determining the state A and the state B with a predetermined threshold and similarly determining the state B and the state C with a predetermined threshold.

  In addition, the state determination of the digital signal S1 by the state detection circuit 101 calculates the error between the consecutive sample values of the digital signal S1 and a plurality of predicted signal patterns in addition to the state determination using the above three values. Of the calculation results, the pattern with the smallest error may be output as the state of the digital signal S1. Hereinafter, the state detection circuit 101 that determines the state of the digital signal S1 by calculating an error with a plurality of predicted signal patterns will be described.

  FIG. 3 is a diagram illustrating the configuration of the state detection circuit 101. In FIG. 3, the state detection circuit 101 includes a pattern error detection circuit 301 and a minimum error pattern detection circuit 302.

  The pattern error detection circuit 301 calculates an error between a plurality of predicted signal patterns and the input digital signal S1 for each of a plurality of predicted signal patterns, and according to the number of predicted signal patterns, n pattern Pn error detection circuits 301 (n) are provided. Here, in the first embodiment, state determination is performed using three consecutive samples. In this case, the number of predicted signal patterns is 3 to the third power = 27. That is, the pattern error detection circuit 301 includes 27 pattern Pn error detection circuits 301 (n).

FIG. 4A shows the configuration of the pattern Pn error detection circuit 301 (n).
The pattern Pn error detection circuit 301 (n) includes delay units 401 and 402, subtracters 403, 404, and 405, absolute value calculators 406, 407, and 408, and an adder 409. The digital signal S1 input to the error detection circuit 301 (n) can be evaluated with respect to three consecutive sample values using the delay units 401 and 402.

Next, the operation of the state detection circuit 101 will be described.
The digital signal S1 input to the state detection circuit 101 is input to the pattern Pn error detection circuits 301 (1) to (27), respectively.

  In each pattern Pn error detection circuit 301 (1) to (27), the digital signal S 1 is sequentially input to the delay devices 401 and 402. The input digital signal S1, the output of the delay unit 401, and the output of the delay unit 402 are input to the subtracter 403, the subtracter 404, and the subtracter 405, respectively. Another input terminal of the subtracter 403, the subtracter 404, and the subtracter 405 receives the estimated value X, estimated value Y, and estimated value Z of three consecutive samples.

Here, the estimated value X, the estimated value Y, and the estimated value Z differ depending on the pattern. For example, in the case of the pattern P22 in FIG. 4B, the inputs to the estimated value X, the estimated value Y, and the estimated value Z are the target value C, the target value B, and the target value A in FIG. In the case of the pattern P18 in FIG. 4B, the estimated values X, Y, and Z are the target value B, the target value C, and the target value C, respectively. As described above, when three consecutive samples are used, there are a total of 3 to the power of 3 = 27 types of patterns. Table 1 shows examples of estimated values corresponding to all patterns.

  The errors between the estimated values calculated by the subtractors 403, 404, and 405 and the sample values are input to the absolute value calculators 406, 407, and 408, respectively, and the absolute values thereof are calculated. The outputs of the absolute value calculators 406, 407, and 408 are added by the adder 409, and the magnitude of the error between the three consecutive sample values and the three consecutive estimated values (patterns) is calculated. The pattern Pn error detection circuits 301 (1) to (27) output the calculated error amount to the minimum error pattern detection circuit 302.

  The minimum error pattern detection circuit 302 compares the respective error amounts output from the pattern Pn error detection circuits 301 (1) to (27), and outputs the pattern having the minimum error as the state of the digital signal S1. For example, when the error of the pattern P1 is 56, the error of the pattern P2 is 78, the error of the pattern P3 is 9, the error of the pattern P4 is 67, and the errors of the other patterns are all larger than 50, a value representing the pattern P3 is output. With such a configuration, the Euclidean distance can be made longer than in the case where the state is detected using only one sample, so that more detailed and reliable state determination can be performed.

Next, the high-frequency attenuation circuit 102 will be described with reference to FIG.
FIG. 5 is a diagram illustrating the configuration of the high-frequency attenuation circuit 102. The high-frequency attenuation circuit 102 is configured by an FIR (Finite Impulse Response) filter as shown in FIG. The digital signal S1 input to the high-frequency attenuation circuit 102 is a tap input of three consecutive samples using the delay units 501 and 502. Each tap input is input to multipliers 503, 504, and 505, and coefficient A, coefficient B, and coefficient C are input to the other input terminals of the multipliers 503, 504, and 505, respectively. The outputs of the multipliers 503, 504, and 505 are input to the adder 506 and become the output S2 of the high-frequency attenuation circuit 102. The coefficient A, the coefficient B, and the coefficient C are set to values that provide high-frequency attenuation characteristics. In this embodiment, [1, 2, 1] / 4 is set. That is, the coefficient A is set to 1/4, the coefficient B is set to 2/4, and the coefficient C is set to 1/4. The high frequency component of the digital signal S1 that has passed through the high frequency attenuation circuit 102 in which this coefficient is set is attenuated.

Next, the gain setting circuit 105 will be described with reference to FIGS.
In FIG. 1, the gain setting circuit 105 sets weights to the first weighting circuit 103 and the second weighting circuit 104 in accordance with the state of the digital signal S1 input from the state detection circuit 101.

  Here, when the state detection circuit 101 determines the states A, B, and C using threshold values as shown in FIG. 2, the gain setting circuit 105 determines the first setting according to each state A, B, and C. A weight is set to the weighting circuit 103 and the second weighting circuit 104. For example, when the state of the digital signal S1 is the state A or the state C, the weight of the first weighting circuit 103 is 0.7, the weight of the second weighting circuit 104 is 0.3, and the ratio of the input digital signal S1 Set a larger value. When the state of the digital signal S1 is the state B, the output signal of the high-frequency attenuation circuit 102 is set such that the weight of the first weighting circuit 103 is 0.2 and the weight of the second weighting circuit 104 is 0.8. The ratio of S2 is set large.

  On the other hand, when the state detection circuit 101 determines the state of the digital signal S1 by pattern detection as shown in FIGS. 3 and 4, when the digital signal S1 crosses zero, that is, as the estimated values X, Y, and Z, One of the values A, B, C, target values A, B, B, target values A, B, A, target values C, B, A, target values C, B, B, and target values C, B, C In the case of a pattern taking the following, the ratio of the output signal S2 of the high-frequency attenuation circuit 102 is set to be large, such that the weight of the first weighting circuit 103 is 0.2 and the weight of the second weighting circuit 104 is 0.8. To do. In other cases, the ratio of the input digital signal S1 is set to a large value such that the weight of the first weighting circuit 103 is 0.7 and the weight of the second weighting circuit 104 is 0.3. The weights of the first weighting circuit 103 and the second weighting circuit 104 are set so that an equalization error of an output of an equalization circuit 107 described later becomes small. For example, iterative calculation may be performed by the least square method.

  Next, the first weighting circuit 103 and the second weighting circuit 104 will be described.

  The first weighting circuit 103 adds the weight set in the first weighting circuit 103 to the digital signal S1 and outputs it. That is, “weighting circuit output = weighting circuit input × weight”. The second weighting circuit 104 adds the weight set in the second weighting circuit 104 to the output signal S2 of the high-frequency attenuation circuit 102 and outputs the signal.

Next, the equalization circuit 107 will be described with reference to FIG.
The equalizing circuit 107 returns the characteristic of the output signal S3 of the adding circuit 106 to the PR (1, 1) type. In other words, the output signal S3 of the adder circuit 106 has been reduced in the influence of jitter while suppressing the attenuation of the signal component by the above signal processing, but attenuated the high frequency with the original digital signal S1. Since it is a combination of the digital signal S2, it deviates from the PR (1, 1) type characteristics. The equalizing circuit 107 returns this shifted characteristic to the PR (1, 1) type.

FIG. 7 is a block diagram showing a configuration of the equalization circuit 107.
As shown in FIG. 7, the equalizing circuit 107 is configured by an FIR filter. In the first embodiment, a 5-tap FIR filter is used. Specifically, the delay units 701, 702, 703, and 704, multipliers 705, 706, 707, 708, and 709, and an adder 710 are included. The filter coefficient is set so that the output of the equalization circuit 107 returns to the PR (1, 1) type.

Next, the operation of the equalization circuit 107 will be described.
The output signal S3 of the adder circuit 106 is sequentially input to the delay units 701, 702, 703, and 704, and five tap inputs are generated. Each tap input is input to one terminal of each of the multipliers 705, 706, 707, 708, and 709. Coefficients I, J, K, L, and M are set to the other input terminals of the multipliers 705, 706, 707, 708, and 709 from a register (not shown). These coefficients I, J, K, L, and M are for making the characteristic of the digital signal S3 a PR (1, 1) type. For example, a Wiener filter (Wiener) is obtained from an actual signal and its target value. Filter) coefficient can be obtained and set.

  Each multiplier 705, 706, 707, 708, 709 multiplies each tap input by a coefficient, and these operation values are added by an adder 710 to become an output S4 of the equalization circuit 107.

Next, the binarization circuit 108 will be described.
The binarization circuit 108 outputs the most probable data series by maximum likelihood decoding. Maximum likelihood decoding is a decoding circuit that can obtain an improved error rate when there is a correlation between signal sequences, and decodes data with the highest probability. In this embodiment, since there is a signal sequence correlation of PR (1, 1), an error rate can be improved.

  As described above, the data reproducing apparatus according to the first embodiment weights the digital signal S1 and the digital signal S1 attenuated in the high frequency component according to the state of the digital signal S1, and the weighting is performed. Since the performed signals are added, the influence of jitter can be reduced while suppressing attenuation of the signal. In addition, since the predetermined equalization characteristic is given after the influence of jitter is reduced, a signal with less distortion can be obtained.

  In particular, as in the first embodiment, if the influence of a signal attenuated in the high band near the zero cross is largely taken, a perpendicular recording system used for recording and reproduction on a HDD (Hard Disk Drive), or a CD (Compact Disk) is used. Or a DVD (Digital Versatile Disk) recording / reproducing optical recording / reproducing method, or a DDS (Digital Data Storage) recording / reproducing combination of a longitudinal recording method and an integral reproducing method, etc. A favorable effect can be obtained in the integral reproduction system.

  Further, if the influence of a signal attenuated by a high frequency other than the vicinity of the zero cross is largely taken, a favorable effect can be obtained in a differential reproduction system such as a longitudinal recording system used for recording and reproduction on an HDD (Hard Disk Drive).

  In the first embodiment, the characteristic of the output signal S3 of the adder circuit 106 is returned to the PR (1, 1) type by the equalization circuit 107, but it may be equalized to another type. The binarization circuit 108 needs to be a decoding circuit suitable for the equalized type. For example, when using NPML (Nise Predictive Maximum-Likelihood), it is possible to improve the error rate by performing equalization so that noise is whitened.

(Embodiment 2)
FIG. 8 is a diagram showing a configuration of a data reproducing apparatus according to the second embodiment of the present invention.
The data reproduction device 800 according to the second embodiment of the present invention replaces the equalization circuit 107 and the gain setting circuit 105 of the data reproduction device 100 according to the first embodiment with an equalization circuit 801 and a gain setting circuit 804, respectively. Further, an equalization coefficient learning circuit 802 and a jitter detection circuit 803 are added. The other components are the same as those of the data reproducing apparatus of the first embodiment. Therefore, the same components as those of the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  The equalization circuit 801 equalizes the output S5 of the adder circuit 106, and equalizes the output S5 of the adder circuit 106 with the coefficient calculated by the equalization coefficient learning circuit 802. The equalization circuit 801 has the same configuration as the equalization circuit 107 of the first embodiment shown in FIG. However, the coefficients set in the equalization coefficient learning circuit 802 are used as the coefficients I, J, K, L, and M in FIG. The equalization coefficient learning circuit 802 calculates a coefficient used in the equalization circuit 801. The jitter detection circuit 803 detects the jitter amount of the digital signal S1. The gain setting circuit 804 sets weights to the first weighting circuit 103 and the second weighting circuit 104, and the state of the digital signal S 1 detected by the state detection circuit 101 and the jitter detection circuit 803. The weight is set based on the output jitter amount.

Next, the operation will be described.
The state detection circuit 101 determines the state of the input digital signal S1 as one of the states A, B, and C as shown in FIG. 2 and outputs it to the gain setting circuit 804. The gain setting circuit 804 sets weights to the first weighting circuit 103 and the second weighting circuit 104 in accordance with the state of the digital signal S1, and the weight values at this time are the values of the digital signal S1 being A, In either case of B or C, 1.0 is set in the first weighting circuit 103 and 0.0 is set in the second weighting circuit 104. That is, the output signal S2 of the high frequency attenuation circuit 102 is not used.

  The outputs of the first weighting circuit 103 and the second weighting circuit 104 are added by the adder circuit 106, then input to the equalization circuit 801, and equalized using the coefficients output from the equalization coefficient learning circuit 802. Is done.

  The equalization coefficient learning circuit 802 calculates an optimum equalization coefficient based on the input signal S5 to the equalization circuit and the output signal S6 of the equalization circuit 801, and outputs it to the equalization circuit 801. Various parameter values necessary for jitter amount detection are output to the jitter detection circuit 803.

  The jitter detection circuit 803 detects an error amount (jitter amount) in the amplitude direction due to jitter corresponding to each state of the digital signal S 1, and outputs it to the gain setting circuit 804. The gain setting circuit 804 analyzes the jitter amount of each state detected by the jitter detection circuit 803 and sets weights to the first weighting circuit 103 and the second weighting circuit 104. Then, the first weighting circuit 103 and the second weighting circuit 104 weight the digital signal S1 and the output signal S2 of the high-frequency attenuation circuit 102, respectively. Thereafter, the above-described operation is performed, and the most likely data is decoded by the maximum likelihood decoding by the binarization circuit 108.

  In the above operation, when the equalization coefficient learning circuit 802 calculates the optimum coefficient, the control circuit (not shown) stops updating the equalization coefficient of the equalization coefficient learning circuit 802 and the gain setting circuit 804 sets an appropriate weight. When the combination is set, control for restarting the update of the equalization coefficient of the equalization coefficient learning circuit 802 is performed.

  Next, a detailed configuration and operation of the data reproduction device 800 according to the second embodiment will be described.

First, the equalization coefficient learning circuit 802 will be described.
The equalization coefficient learning circuit 802 calculates an optimal equalization coefficient using the LMS algorithm. Here, the LMS algorithm is a method of calculating a coefficient so that the square error between the input signal value and the equalization target value d (n) is minimized, and the calculation formula is as follows: It is represented by the formula and the formula (2).
h (n + 1) = h (n) + (1/2) μe (n) u (n) (1)
e (n) = d (n) -uT (n) h (n) (2)

  In the above equations (1) and (2), h (n) is a filter coefficient vector before update, h (n + 1) is a filter coefficient vector after update, μ is a step size parameter, and e (n) is The error signal at the n-th iteration, u (n) is the tap input vector at the n-th iteration, d (n) is the desired response, and uT (n) is the transposition of the tap input vector.

  When the LMS algorithm is operated, the coefficient vector h (n) approaches the optimum value h0 so that the error signal e (n) is minimized, that is, the equalization error is minimized. In order to use this algorithm, an input / output signal of an equalizer and an equalization target value d (n) (desired response) are required. The equalization coefficient learning circuit 802 of the second embodiment uses the input / output signal S5 and the output signal S6 of the equalization circuit 801 as the input / output signals of the equalizer, and also uses the output signal S6 of the equalization circuit 801. Then, an equalization target value d (n) is generated, and an optimum equalization coefficient is calculated using these values.

  FIG. 9 is a diagram illustrating the configuration of the equalization coefficient learning circuit 802. The equalization coefficient learning circuit 802 includes an equalization target generation circuit 901 that generates an equalization target value d (n), an equalization error calculation circuit 902 that calculates an error signal e (n), and an updated filter coefficient vector. and an equalization coefficient calculation circuit 903 for calculating h (n + 1).

Next, the operation of the equalization coefficient learning circuit 802 will be described.
First, the equalization target generation circuit 901 receives the output signal S6 of the equalization circuit 801 and generates an equalization target value d (n). The equalization target value d (n) can be generated by many methods. For example, the output signal S6 of the equalization circuit 801 is discriminated into states A, B, and C with a predetermined threshold as shown in FIG. By defining the equalization target value d (n) for each state as the target values A, B, and C, the equalization target value d (n) corresponding to each state can be generated. The generated equalization target value d (n) is output to the equalization error calculation circuit 902.

  The equalization error calculation circuit 902 calculates the error signal e (n) according to the above equation (2). Here, the error signal e (n) is equal to the equalization target value d (n) generated by the equalization target generation circuit 901 and the output signal uT ( n) Difference from h (n). The equalization error calculation circuit 902 performs such subtraction processing and outputs the calculation result to the equalization coefficient calculation circuit 903.

  The equalization coefficient calculation circuit 903 calculates the updated filter coefficient vector h (n + 1) based on the input signal S5 to the equalization circuit 801 and the error signal e (n). Specifically, the calculation of the above equation (1) is performed using the tap input u (n) of the equalization circuit 801 generated from the input signal S5 of the equalization circuit 801 and the error that is the output of the equalization error calculation circuit 902. The signal e (n), the pre-update filter coefficient vector h (n), which is the equalization coefficient output in the past (present) by the equalization coefficient calculation circuit 903, and the control of adaptive equalization are not diverged. This is performed using an arbitrarily set step size parameter μ. Then, the equalization coefficient that is the calculation result is output to the equalization circuit 801. The equalization coefficient learning circuit 802 outputs the equalization target value d (n) and the error signal e (n) calculated in the equalization coefficient calculation process to the jitter detection circuit 803.

  Next, the jitter detection circuit 803 will be described with reference to FIG.

FIG. 10 is a diagram illustrating the configuration of the jitter detection circuit 803.
As shown in FIG. 10, the jitter detection circuit 803 includes a jitter determination circuit 1001, an upper jitter amount calculation circuit 1002, a zero cross jitter amount calculation circuit 1003, and a lower jitter amount calculation circuit 1004.

  The jitter discriminating circuit 1001 distributes the equalization error e (n) to the upper jitter amount calculating circuit 1002, the zero cross jitter amount calculating circuit 1003, and the lower jitter amount calculating circuit 1004 according to the equalization target value d (n). It is. The upper jitter amount calculation circuit 1002, the zero cross jitter amount calculation circuit 1003, and the lower jitter amount calculation circuit 1004 perform quantitative analysis of jitter.

Next, the operation of the jitter detection circuit 803 will be described.
The equalization error e (n) and the equalization target value d (n) input to the jitter detection circuit 803 are input to the jitter determination circuit 1001. The jitter determination circuit 1001 distributes the equalization error e (n) to the upper jitter amount calculation circuit 1002, the zero cross jitter amount calculation circuit 1003, and the lower jitter amount calculation circuit 1004 according to the equalization target value d (n). . For example, the equalization target values d (n) of the states A, B, and C in FIG. 2 are set as the target values A, B, and C. Then, the equalization target value d (n) is input in the order of C, B, A, A, and the equalization error is in the order of e (1), e (2), e (3), e (4). If it is input, it can be seen that the error e (1) when the target value C is input is the state C, that is, the lower error among the three values. Similarly, it can be seen that the error e (2) when the target value B is input is an error in the state B, that is, the center of the ternary value (zero cross). Thus, the error is discriminated and distributed to the upper jitter amount calculation circuit 1002, the zero cross jitter amount calculation circuit 1003, or the lower jitter amount calculation circuit 1004.

  The upper jitter amount calculation circuit 1002, the zero-cross jitter amount calculation circuit 1003, and the lower jitter amount calculation circuit 1004 calculate and output an average of the distributed error magnitude (absolute value) for a certain period, for example, 100. Thus, an error amount for each state in the amplitude direction due to jitter is obtained and output to the gain setting circuit 804.

Next, the gain setting circuit 804 will be described.
The gain setting circuit 804 analyzes the jitter amount in each state detected by the jitter detection circuit 803 and sets an appropriate weight. Hereinafter, a jitter amount analysis and a weight setting method in the gain setting circuit 804 will be described with reference to FIG.

  FIG. 11 is a diagram showing an eye pattern when jitter exists. In FIG. 11, it can be observed that the sampling points are divided into three values. These three values correspond to states A, B, and C. As is clear from FIG. 11, when there is jitter, the noise near the zero cross (state C) is larger than the upper noise (state A) and the lower noise (state B). I understand that.

  The gain setting circuit 804 performs a first analysis and a second analysis as an analysis of the jitter amount. In the first analysis, it is determined whether the upper jitter amount, the jitter amount near the zero cross, and the lower jitter amount are all smaller than a first set value set in a register (not shown). In addition, the second analysis is based on whether the upper jitter amount is smaller than the jitter amount near the zero cross and the difference value is larger than a second set value set in a register (not shown), It is determined whether the jitter amount is smaller than the jitter amount near the zero cross and the difference value is larger than the second set value.

  As a result of the first analysis, the gain setting circuit 804 determines that all of the jitter amount on the upper side (state A), the jitter amount near the zero cross (state B), and the jitter amount on the lower side (state C) are When it is smaller than the set value, the current weight, that is, the setting of 1.0 of the first weighting circuit 103 and 0.0 of the second weighting circuit 104 is maintained. This is a case where the amount of jitter is small and there is no need to change the weight any more. In this example, 1.0 is set in the first weighting circuit 103 and 0.0 is set in the second weighting circuit 104 in all states A, B, and C.

  On the other hand, as a result of the first analysis, when all of the upper jitter amount, the jitter amount near the zero cross, and the lower jitter amount are larger than the first set value, the second analysis result is obtained. Refer to If the result of the second analysis is greater than the second set value, the weight is changed. This is because there is a high possibility that the cause of the large amount of jitter in each state is due to jitter, and the influence of jitter is reduced by changing the weight. For example, in states A and C, 0.9 is set in the first weighting circuit 103, and 0.1 is set in the second weighting circuit 104. In state B, the first weighting circuit 103 is set in 0.5, The weighting circuit 104 is set to 0.5. On the other hand, if the result of the second analysis is smaller than the second set value, the current setting is maintained. This is a case where there is a high possibility that the cause of the large amount of jitter in each of the states A, B, and C is due to something other than jitter, so there is no need to change the weight any more. In this example, 1.0 is set in the first weighting circuit 103 and 0.0 is set in the second weighting circuit 104 in all states A, B, and C.

  As described above, in the gain setting circuit 804, when noise is large due to jitter, the influence of jitter can be reduced by changing the weight. The combinations of weights for the states A, B, and C may be stored in advance in several types of tables, and the combination of weights that can most reduce the influence of jitter may be selected. By doing so, an appropriate weight can be set and the influence of jitter can be reduced.

  As described above, since the equalization coefficient learning circuit 802 and the jitter detection circuit 803 are provided in the data reproduction apparatus 800 according to the second embodiment, the equalization circuit 801 uses the optimum coefficient for equalization. Further, the gain setting circuit 804 can set an appropriate weight based on the state of the input digital signal S1 and the jitter amount detected by the jitter detection circuit 803. Thereby, the jitter can be accurately reduced to a high band without attenuating the input digital sampling signal, and a signal with less distortion can be obtained by equalization again after the jitter reduction.

  In particular, as in the first embodiment, if the influence of a signal attenuated in the high band near the zero cross is largely taken, a perpendicular recording system used for recording and reproduction on a HDD (Hard Disk Drive), or a CD (Compact Disk) is used. Or a DVD (Digital Versatile Disk) recording / reproducing optical recording / reproducing method, or a DDS (Digital Data Storage) recording / reproducing combination of a longitudinal recording method and an integral reproducing method, etc. A favorable effect can be obtained in the integral reproduction system.

  Further, if the influence of a signal attenuated by a high frequency other than the vicinity of the zero cross is largely taken, a favorable effect can be obtained in a differential reproduction system such as a longitudinal recording system used for recording and reproduction on an HDD (Hard Disk Drive).

  The data reproducing apparatus according to the present invention has an effect of reducing jitter to a high band without attenuating signal components, and is useful as a reproducing apparatus of a perpendicular magnetic recording system. Further, the present invention can also be applied to applications such as an optical disc apparatus that requires a reduction in jitter.

It is a figure which shows the structure of the data reproduction apparatus by Embodiment 1 of this invention. The figure for demonstrating the state detection circuit by Embodiment 1 of this invention. It is a figure which shows the structural example of the state detection circuit by Embodiment 1 of this invention. (A) is a figure which shows the detailed structure of a state detection circuit. (B) is a figure for demonstrating the state detection circuit by Embodiment 1 of this invention. It is a figure which shows the structure of the high region attenuation circuit by Embodiment 1 of this invention. It is a figure for demonstrating the reduction of the jitter by Embodiment 1 of this invention. It is a figure which shows the structure of the equalization circuit by Embodiment 1 and Embodiment 2 of this invention. It is a figure which shows the structure of the data reproduction apparatus by Embodiment 2 of this invention. It is a figure which shows the structure of the equalization coefficient learning circuit by Embodiment 2 of this invention. It is a figure which shows the structure of the jitter detection circuit by Embodiment 2 of this invention. It is a figure for demonstrating the jitter by Embodiment 2 of this invention. It is a figure which shows the structure of the conventional data reproducing | regenerating apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 State detection circuit 102 High frequency attenuation circuit 103 1st weighting circuit 104 2nd weighting circuit 105 Gain setting circuit 106 Adder circuit 107 Equalization circuit 108 Binarization circuit 301 Pattern error detection circuit 301 (1) -301 (n) ) Pattern Pn error detection circuit 302 Minimum error pattern detection circuit 401, 402, 501, 502, 701 to 704 Delay devices 403, 404, 405 Subtractors 406, 407, 408 Absolute value calculators 409, 506, 710 Adders 503 505, 705 to 709 Multiplier 801 Equalization circuit 802 Equalization coefficient learning circuit 803 Jitter detection circuit 804 Gain setting circuit 901 Equalization target generation circuit 902 Equalization error detection circuit 903 Equalization coefficient calculation circuit 1001 Jitter discrimination circuit 1002 Upper jitter Quantity calculation circuit 1003 Rokurosujitta amount calculating circuit 1004 lower jitter amount calculating circuit

Claims (6)

A high-frequency attenuation circuit for removing high-frequency components of a digital sampling signal obtained by sampling a signal read from a recording medium;
A state detection circuit for detecting a state of the digital sampling signal;
A first weighting circuit for weighting the digital sampling signal;
A second weighting circuit for weighting a signal output from the high-frequency attenuation circuit;
A gain setting circuit for setting weights of the first weighting circuit and the second weighting circuit;
An addition circuit for adding the signal output from the first weighting circuit and the signal output from the second weighting circuit;
The gain setting circuit sets a weight to each of the first weighting circuit and the second weighting circuit according to the state output by the state detection circuit.
A data reproducing apparatus characterized by that. A high-frequency attenuation circuit for removing high-frequency components of a digital sampling signal obtained by sampling a signal read from a recording medium;
A state detection circuit for detecting a state of the digital sampling signal;
A first weighting circuit for weighting the digital sampling signal;
A second weighting circuit for weighting a signal output from the high-frequency attenuation circuit;
A gain setting circuit for setting weights of the first weighting circuit and the second weighting circuit;
An adder circuit for adding a signal output from the first weighting circuit and a signal output from the second weighting circuit;
An equalization circuit for equalizing the signal output from the addition circuit;
An equalization coefficient learning circuit that calculates an equalization coefficient of the equalization circuit based on a signal output from the addition circuit and a signal output from the equalization circuit;
A jitter detection circuit for detecting a jitter amount in the digital sampling signal based on an equalization error output from the equalization coefficient learning circuit;
The gain setting circuit sets a weight to each of the first weighting circuit and the second weighting circuit according to a state output from the state detection circuit and a jitter amount output from the jitter detection circuit. To
A data reproducing apparatus characterized by that. In the data reproducing device according to claim 1 or 2,
The state detected by the state detection circuit is either a state where the digital sampling signal is near zero-cross or a state where it is not near zero-cross.
A data reproducing apparatus characterized by that. In the data reproducing device according to claim 1 or 2,
The state detection circuit includes:
A plurality of pattern error detection circuits for calculating an error between a plurality of consecutive samples of the digital sampling signal and a predicted pattern;
A minimum error pattern detection circuit for comparing a plurality of error signals output from the plurality of pattern error detection circuits and detecting a pattern having a minimum error; Detect as sampling signal status,
A data reproducing apparatus characterized by that. In the data reproducing device according to claim 1 or 2,
The high-frequency attenuation circuit has a transfer function of (1 + 2 · D + D · D) · A.
Here, · represents multiplication, D is a delay operator, A is an arbitrary value,
A data reproducing apparatus characterized by that. The data reproducing apparatus according to claim 2, wherein
The jitter detection circuit detects an equalization error near the zero cross and an equalization error not near the zero cross as a jitter amount near the zero cross and a jitter amount not near the zero cross,
The gain setting circuit compares the magnitude of jitter in the vicinity of the zero cross with the magnitude of jitter not in the vicinity of the zero cross, and based on the comparison result and the magnitude of each jitter, A weighting circuit and a weighting to the second weighting circuit are determined.
A data reproducing apparatus characterized by that.

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