JP2006159780A - Substrate for ink jet recording head and drive control method, ink jet recording head, ink jet recording head cartridge and ink jet recorder - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain a high density select circuit by decreasing the number of high breakdown voltage elements being arranged in each segment. <P>SOLUTION: The substrate for ink jet recording head mounts a heater array 310 generating thermal energy being utilized for ejecting ink, a drive select circuit array 308 and a drive circuit array 309 for driving the heater array 310. An element drive signal circuit 304, a block select circuit 305 and level conversion circuits 312, 313 output a signal for selecting an electrothermal conversion element to be driven based on an input signal of first voltage amplification level with a second voltage amplification level higher than the first voltage amplification level. The drive select circuit array 308 and the drive circuit array 309 receive the select signal outputted with the second voltage amplification level and performs drive control of the heater. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an ink jet recording head substrate, an ink jet recording head, and a recording apparatus using the recording head, and more particularly to an electrothermal conversion element that generates thermal energy necessary for ejecting ink and a driving circuit for driving the electrothermal conversion element. The present invention relates to an ink jet recording head formed on the same substrate and a recording apparatus using the recording head.

  In general, an electrothermal conversion element (heater) of a recording head and a driving circuit thereof mounted on a recording apparatus according to an ink jet method are formed on the same substrate using a semiconductor process technique as shown in, for example, Patent Document 1 and Patent Document 2. Formed on top. In addition to this drive circuit, the state of the semiconductor substrate, for example, a digital circuit for detecting the substrate temperature is formed on the same substrate, and the ink supply port is located near the center of the substrate and sandwiched between them. A configuration of a recording head in which a heater faces is proposed.

  FIG. 1 is a diagram schematically showing the circuit block of this type of ink jet recording head semiconductor substrate (hereinafter referred to as a head substrate) and the flow of electrical signals. As shown in FIG. 1, circuit blocks are symmetrically arranged around the ink supply port 111. These circuit blocks include a heater array 110 composed of a plurality of heaters across an ink supply port, a drive circuit array 109 having a switching element for flowing current to each heater of the heater array 110, and a drive circuit for controlling the drive circuit. A drive selection circuit array 108, an element drive circuit 104 and a block selection circuit 105 that generate signals to be transmitted to the drive selection circuit array, and an input circuit 103 for processing a signal input from the pad 102 are included.

  Hereinafter, only the function of each circuit block and the signal flow will be described for one circuit block group that is symmetrical about the ink supply port 111.

  The head substrate 101 is formed by forming each circuit block and a heater for heating ink using an LSI process on a silicon substrate. A signal input from the pad 102 for inputting and outputting the power supply voltage and image data is transmitted to the element drive signal circuit 104 and the block selection circuit 105 via the input circuit 103. Signals appropriately processed by the element drive signal circuit 104 and the block selection circuit 105 are routed in the heater arrangement direction by bus lines 106 and 107 formed of a plurality of wirings.

  Signals from the bus lines 106 and 107 are respectively connected to a drive selection circuit that is a component of the drive selection circuit array 108, and on / off of the drive selection circuit is determined by signals from the bus lines 106 and 107. When an ink ejection operation is performed, a signal that turns on a desired drive selection circuit is applied to the bus lines 106 and 107, and the corresponding drive circuit in the drive circuit array 109 is turned on from the drive selection circuit. The signal is output as follows. When the drive circuit is turned on, a current flows through the corresponding heater in the heater array 110. The heater is heated by this current, and ink foaming and ejection operations are performed.

  FIG. 2 is a circuit diagram in which a drive selection circuit and a drive circuit corresponding to any one heater in the heater array 110 are extracted from the drive selection circuit array 108 and the drive circuit array 109 described above.

  Signals are taken into the drive selection circuit from the bus lines 106 and 107 that route the output signals from the element drive signal circuit 104 and the block selection circuit 105 shown in FIG. 208a to 208l are circuit elements constituting the drive selection circuit. An input terminal of the NAND gate 208a is connected to the bus lines 106 and 107, and a corresponding signal is input from each bus line. The inverter 208b inverts the output signal from the NAND gate 208a and outputs an inverted signal, and the inverter 208c further inverts the inverted signal. The MOS transistors 208d to 208i constitute a level conversion circuit for converting the voltage amplitude of the signal. MOS transistors 208j and 208k constitute an inverter for buffering the output signal of the level conversion circuit. A resistor 208l is provided to increase the output impedance when the output of the inverter formed by the MOS transistors 208j and 208k changes from a low level (hereinafter referred to as Lo) to a high level (hereinafter referred to as Hi). It has been.

  The MOS transistor 209 forms a drive circuit that performs on / off control of the heater current. Heating for ink foaming by the heater 210 is controlled by turning on and off the heater current by the MOS transistor 209.

  The operation of the circuit shown in FIG. 2 will be described. Output signals from the element drive signal circuit 104 and the block selection circuit 105 in FIG. 1 are input to the NAND gate 208 a through the bus lines 106 and 107. Here, only when both inputs to the NAND gate 208a become Hi, the output of the NAND gate 208a becomes Lo. The operation when the Lo signal is output from the NAND gate 208a will be described below. The Lo signal output from the NAND gate 208a is inverted by the inverter 208b and becomes Hi. Further, the Hi signal that is the output of the inverter 208b is input to the inverter 208c, inverted again, and output as a Lo signal. The voltage amplitude of the bus lines 106 and 107, the NAND gate 208a, the inverters 208b and 208c, etc. is VDD, and the potential of the VDD has the same amplitude as a signal input from the outside.

  Output signals from inverters 208b and 208c are input to level converters including MOS transistors 208d to 208i, respectively. Here, the same Lo potential (0V) as the output signal of the NAND gate 208a is applied to the gates of the MOS transistors 208d and 208e, and the Hi potential (VDD) which is an inverted signal of the NAND gate output is applied to the gates of 208g and 208h. ) Is applied.

  Since the MOS transistor 208g to which VDD is applied to the gate is an NMOS transistor, it is turned on. Therefore, the drain terminal of the NMOS transistor 208g is connected to the GND potential with a low impedance. The drain terminal of the NMOS transistor 208g is connected to the gate of the PMOS transistor 208f. Therefore, the gate of the PMOS transistor 208f is connected to the GND potential with a low impedance, and the PMOS transistor 208f is turned on. The PMOS transistor 208e connected in series to the PMOS transistor 208f is turned on because 0V is applied to the gate, and the NMOS transistor 208d connected in series is turned off because 0V is applied to the gate. . Since the PMOS transistors 208f and 208e are on and the NMOS transistor 208d is off, the potential of the node connected to the drain of the PMOS transistor 208e and the NMOS transistor 208d and connected to the gate of the PMOS transistor 208i is the power supply potential of the level conversion circuit. It becomes a certain VDDM. Therefore, the PMOS transistor 208i is turned off. Since the PMOS transistor 208i is off and the NMOS transistor 208g is on, the drain terminals of the PMOS transistor 208h and the NMOS transistor 208i are connected, and the potential of the node connected to the gate of the PMOS transistor 208f is determined to be 0V. The potential of this node becomes the output signal of the level converter and is input to the gate of the inverter composed of the NMOS transistor 208j and the PMOS transistor 208k.

  Thus, when 0 V is applied to the gate of each transistor of the inverter composed of the NMOS transistor 208j and the PMOS transistor 208k, the PMOS transistor 208k is turned on and the NMOS transistor 208j is turned off. As a result, the inverter outputs the VDDM potential and is connected to the gate of the NMOS transistor 209 which is a drive circuit for performing heater on / off control. The NMOS transistor 209 to which VDDM is applied is turned on, and a heater current flows from the heater power supply potential VH through the heater 210, and the heater through which the current flows generates heat necessary for ink bubbling and ejection.

  Thus, the heater current flows when the signals connected from the bus lines 106 and 107 to the NAND gate 208a both become Hi.

Here, the resistor 208l is arranged to suppress a steep rise in the heater current. That is, when the gate potential of the NMOS transistor 209 that controls on / off of the heater current instantaneously changes from 0 V to VDDM potential to turn on the heater current, the heater current also flows instantaneously. This change in current may cause noise in the power supply and cause malfunction. The resistor 208l is inserted between the PMOS transistor 208k and the NMOS transistor 209 in order to prevent this malfunction. The steep rise of the gate potential of the NMOS transistor 209 is suppressed by the delay effect of the on-resistance of the PMOS transistor 208k and the series resistance of the resistor 280l and the gate capacitance of the NMOS transistor 209, so that the instantaneous flow of the heater current is suppressed. Thus, malfunction is prevented.
JP-A-5-185594 US Pat. No. 6,290,334

  In general, with respect to an ink jet recording head, a large number of nozzles and a high density have been promoted in order to increase the recording speed and / or improve the recording quality. However, in the case of a thermal ink jet printer that discharges ink by the heat generated by the heater, it is necessary to use a high power supply voltage in order to cause the heater to generate energy necessary for the foaming of ink and the accompanying discharge. Therefore, in the heater drive control circuit, it is necessary to ensure the breakdown voltage for the high power supply voltage in the constituent elements. In general, the size of each element increases in order to ensure the breakdown voltage of the constituent elements, making it difficult to place a high-density circuit (with a small arrangement pitch) on the substrate.

  For example, in the conventional circuit form as shown in FIG. 2, a signal based on image data transmitted from the element drive signal circuit 104 via the bus line 106 and a signal transmitted from the block selection circuit 105 via the bus line 107 are transmitted. The voltage amplitude is increased after taking the logical product with the block selection signal to be processed. In such a configuration, it is necessary to provide a level conversion circuit for each heater, and it is necessary to arrange a large number of high-breakdown-voltage elements. For this reason, it is difficult to arrange high-density elements (with a small circuit arrangement pitch) on the substrate. That is, the arrangement pitch cannot be made sufficiently small due to the presence of a large number of high breakdown voltage elements, leading to an increase in chip size and the like.

  2 are a level converter and an inverter connected to VDDM, which is an intermediate potential, and a transistor (209) for driving a heater connected to VH.

  The present invention has been made in view of the above problems, and an object of the present invention is to reduce the number of high withstand voltage elements arranged in each segment and achieve a higher density of selection circuits.

In order to achieve the above object, an ink jet recording head according to an aspect of the present invention comprises the following arrangement. That is,
A substrate on which an electrothermal conversion element for generating thermal energy used for ejecting ink and a drive circuit for driving the electrothermal conversion element are mounted;
Each of a block selection signal for selecting a block to be driven based on an input signal of the first voltage amplitude level and an element drive signal for driving an electrothermal transducer to be driven according to image data A first circuit unit for outputting at a second voltage amplitude level higher than the first voltage amplitude level;
A NOR circuit that inputs a signal output from the first circuit unit and outputs a control signal having the second voltage amplitude level for controlling a drive circuit corresponding to the electrothermal transducer to be driven A second circuit unit.

  According to another aspect of the present invention, there are provided an inkjet recording head drive control method, an inkjet recording head, an inkjet recording head cartridge, and an inkjet recording apparatus using the inkjet recording head substrate.

  According to the present invention, the number of high voltage elements placed in each segment can be reduced, and the density of the selection circuit can be increased.

  Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

  In this specification, “recording” (sometimes referred to as “printing”) is not only for forming significant information such as characters and figures, but also for human beings visually perceived regardless of significance. Regardless of whether or not it has been manifested, it also represents a case where an image, a pattern, a pattern, or the like is widely formed on a recording medium or the medium is processed.

  “Recording medium” refers not only to paper used in general recording apparatuses but also widely to cloth, plastic film, metal plate, glass, ceramics, wood, leather, and the like that can accept ink. Shall.

  Furthermore, “ink” (sometimes referred to as “liquid”) is to be interpreted broadly in the same way as the definition of “recording (printing)” above. It represents a liquid that can be used for forming a pattern or the like, processing a recording medium, or processing an ink (for example, solidification or insolubilization of a colorant in ink applied to the recording medium).

  Furthermore, unless otherwise specified, the “nozzle” collectively refers to an ejection port or a liquid channel communicating with the ejection port and an element that generates energy used for ink ejection.

  The expression “on the element substrate” used in the description not only indicates the element substrate, but also indicates the surface of the element substrate and the inside of the element substrate near the surface. In addition, the term “built-in” as used in the present invention is not a term indicating that individual elements are simply arranged on a substrate, but each element is a manufacturing process of a semiconductor circuit. It shows that it is integrally formed and manufactured on the element substrate by the above.

<First Embodiment>
First, an example of an ink jet recording apparatus to which the present invention can be applied will be described. FIG. 9 is an external perspective view showing an outline of the configuration of the ink jet recording apparatus 1 which is a typical embodiment of the present invention.

  As shown in FIG. 8, an ink jet recording apparatus (hereinafter referred to as a recording apparatus) transmits a driving force generated by a carriage motor M1 to a carriage 2 on which a recording head 3 that performs recording by discharging ink according to an ink jet system is mounted. 4, the carriage 2 is reciprocated in the direction of arrow A, and for example, a recording medium P such as recording paper is fed through a paper feeding mechanism 5 and conveyed to a recording position. Recording is performed by ejecting ink onto the recording medium P.

  Further, in order to maintain the state of the recording head 3 satisfactorily, the carriage 2 is moved to the position of the recovery device 10 and the ejection recovery process of the recording head 3 is performed intermittently.

  In addition to mounting the recording head 3 on the carriage 2 of the recording apparatus 1, an ink cartridge 6 for storing ink to be supplied to the recording head 3 is mounted. The ink cartridge 6 is detachable from the carriage 2.

  The recording apparatus 1 shown in FIG. 8 is capable of color recording. For this reason, the carriage 2 contains four inks containing magenta (M), cyan (C), yellow (Y), and black (K) inks, respectively. An ink cartridge is installed. These four ink cartridges are detachable independently.

  Now, the carriage 2 and the recording head 3 can achieve and maintain a required electrical connection by properly contacting the joint surfaces of both members. The recording head 3 applies energy according to a recording signal to selectively eject ink from a plurality of ejection ports for recording. In particular, the recording head 3 of this embodiment employs an ink jet system that ejects ink using thermal energy, and responds by applying a pulse voltage to a corresponding electrothermal transducer in accordance with a recording signal. Ink is ejected from the ejection port.

  Further, in FIG. 8, reference numeral 14 denotes a transport roller that is driven by a transport motor M2 to transport the recording medium P.

  In the above-described example, the recording head and the ink cartridge for storing ink are separable. However, as described below, the head cartridge in which these recording head and ink cartridge are integrated is used as the carriage 2. May be installed.

  FIG. 9 is an external perspective view showing an example of the configuration of the head cartridge. In FIG. 8, the ink cartridge 6 and the recording head 3 are separated, but the ink jet recording head substrate of the present invention can also be applied to a head cartridge in which the ink cartridge and the storage head are integrated.

  As shown in FIG. 9, the inkjet cartridge IJC is composed of a cartridge IJCK that discharges black ink and a cartridge IJCC that discharges three color inks of cyan (C), magenta (M), and yellow (Y). These two cartridges are separable from each other and can be detached from the carriage 2 independently.

  The cartridge IJCK includes an ink tank ITK that stores black ink and a recording head IJHK that discharges and records black ink. These cartridges have an integrated configuration. Similarly, the cartridge IJCC includes an ink tank ITC that stores three color inks of cyan (C), magenta (M), and yellow (Y), and a recording head IJHC that discharges and records these color inks. However, these are integrated. In this embodiment, the ink tank is filled with ink.

  Further, as is apparent from FIG. 9, the nozzle row for ejecting black ink, the nozzle row for ejecting cyan ink, the nozzle row for ejecting magenta ink, and the nozzle row for ejecting yellow ink are arranged side by side in the carriage movement direction. The nozzle arrangement direction intersects the carriage movement direction.

  Next, a head substrate used in the recording head 3 of the recording apparatus having the above configuration will be described. FIG. 10 is a perspective view showing a three-dimensional structure of a recording head IJHC that discharges three color inks.

  FIG. 10 reveals the flow of ink supplied from the ink tank ITC. The recording head IJHC includes an ink channel 2C that supplies cyan (C) ink, an ink channel 2M that supplies magenta (M) ink, and an ink channel 2Y that supplies yellow (Y) ink. The ink channels are provided with supply paths (not shown) for supplying respective inks from the back side of the substrate.

  Through these ink channels, the C ink, M ink, and Y ink are respectively guided to an electrothermal transducer (heater) 210 provided on the substrate by ink flow paths 1301C, 1301M, and 1301Y. When the electrothermal converter (heater) 210 is energized through a circuit to be described later, heat is applied to the ink on the electrothermal converter (heater) 210 and the ink is boiled. Ink droplets 1900C, 1900M, and 1900Y are ejected from the ejection ports 1302C, 1302M, and 1302Y by bubbles.

  In FIG. 10, reference numeral 301 denotes an electrothermal transducer which will be described in detail later, various circuits for driving the same, memory, various pads serving as electrical contacts with the carriage HC, and a head formed with various signal lines. It is a substrate.

  One electrothermal transducer (heater), a MOS-FET for driving the electrothermal transducer, and the electrothermal transducer (heater) are collectively referred to as a recording element, and a plurality of recording elements are collectively referred to as a recording element section.

  Although FIG. 10 shows the three-dimensional structure of the recording head IJHC that discharges color ink, the recording head IJHK that discharges black ink also has the same structure. However, the structure is one third of the configuration shown in FIG. That is, there is one ink channel, and the size of the head substrate is about one third.

  Next, the control configuration of the ink jet recording apparatus will be described. FIG. 11 is a block diagram showing a control configuration of the recording apparatus shown in FIG.

  As shown in FIG. 11, the controller 60 includes an MPU 60a, a ROM 60b storing a program corresponding to a control sequence to be described later, a required table, and other fixed data, control of the carriage motor M1, control of the transport motor M2, and recording. A special-purpose integrated circuit (ASIC) 60c that generates a control signal for controlling the head 3, and a RAM 60d, an MPU 60a, an ASIC 60c, and a RAM 60d provided with an image data development area, a program execution area, and the like are connected to each other. A system bus 60e for transferring data, and an A / D converter 60f for inputting analog signals from the sensor group described below, A / D converting them, and supplying digital signals to the MPU 60a, and the like.

  In FIG. 11, reference numeral 61a denotes a computer (or an image reading reader, a digital camera, or the like) serving as a supply source of image data, and is collectively referred to as a host device. Image data, commands, status signals, and the like are transmitted and received between the host apparatus 61a and the recording apparatus 1 via an interface (I / F) 61b.

  Further, reference numeral 62 denotes a switch group, which instructs activation of a power switch 62a, a print switch 62b for instructing printing start, and a process (recovery process) for maintaining the ink ejection performance of the recording head 3 in a good state. For example, a recovery switch 62c for receiving the command input from the operator. Reference numeral 63 denotes a position sensor 63a such as a photocoupler for detecting the home position h, a temperature sensor 63b provided at an appropriate location of the recording apparatus for detecting the environmental temperature, and the like. It is a sensor group.

  Further, 64a is a carriage motor driver for driving the carriage motor M1 for reciprocating scanning of the carriage 2 in the direction of arrow A, and 64b is a transport motor driver for driving the transport motor M2 for transporting the recording medium P.

  The ASIC 60c transfers drive data (DATA) of the printing element (heater) to the print head while directly accessing the storage area of the RAM 60d during print scan by the print head 3.

  Next, the head substrate (element substrate) used in the recording head of the recording apparatus having the above configuration will be described in detail. In particular, the configuration of the drive circuit built on the head substrate (on the heater board) will be mainly described. As described above, the members (not shown) that form the ink discharge ports 30C, M, Y corresponding to the respective recording elements and the flow paths 31C, M, Y communicating with the ink discharge ports on the head substrate. ) Is provided, thereby forming a recording head. The ink supplied onto the recording element is heated by driving the recording element to generate bubbles due to film boiling, and the ink is ejected from the ejection port.

  FIG. 3 is a circuit block diagram schematically showing the circuit configuration of the head substrate 301 and the flow of electric signals according to the first embodiment. In FIG. 3, a head substrate 301 is a substrate in which a heater and a drive circuit are integrally formed by a semiconductor process technology, and corresponds to the above-described head substrate 1705. As shown in FIG. 3, in the substrate 301, circuit blocks are symmetrically arranged around the ink supply port 311. As elements constituting this circuit block, a heater array 310 composed of a plurality of heaters across an ink supply port 311, a drive circuit array 309 for flowing current to the heaters, a drive selection circuit array 308 for controlling the drive circuits, and a drive An element drive circuit 304 and a block selection circuit 305 that generate signals to be transmitted to the selection circuit array, and an input circuit 303 for processing signals input from the pads 302 are included. Since these circuit blocks are symmetrically arranged with respect to the ink supply port 311, common numbers are assigned to the symmetrically arranged blocks. Hereinafter, the function of each block and the signal flow will be described.

  The head substrate 301 is formed by forming each circuit block and a heater for heating ink using an LSI process on a silicon substrate. A signal input from the pad 302 for inputting / outputting the power supply voltage and image data is transmitted to the element drive signal circuit 304 and the block selection circuit 305 via the input circuit 303. The block selection circuit 305 generates a block selection signal for selecting a block to be driven based on the input signal. The element drive signal circuit 304 generates an element drive signal for driving each heater in the selected block according to the image data based on the input signal. These element drive signals and block selection signals are supplied to level conversion circuits 312 and 313, respectively. Level conversion circuits 312 and 313 level-shift the input signal to a signal having a power supply voltage amplitude larger than the input signal amplitude. The element drive signal and the block selection signal output from the level conversion circuits 312 and 313 are routed in the heater arrangement direction by bus lines 306 and 307 including a plurality of wirings.

  The element drive signal and the block selection signal from the bus lines 306 and 307 are respectively connected to a drive selection circuit that is a component of the drive selection circuit array 308, and the signal from the bus lines 306 and 307 turns on / off the drive selection circuit. Off is determined. When an ink ejection operation is performed, a bus line signal that turns on a desired drive selection circuit is applied, and a signal is output from the drive selection circuit to turn on the corresponding drive circuit. When the drive circuit is turned on, a current is supplied to the corresponding heater, and the heater is heated by the flowing current to perform ink foaming and ejection operations.

  FIG. 4 is a circuit diagram in which a drive selection circuit and a drive circuit corresponding to any one heater in the heater array 310 are extracted from the drive selection circuit array 308 and the drive circuit array 309 described above.

  As described above, the output signals from the element drive signal circuit 304 and the block selection circuit 305 are level-shifted by the level conversion circuits 312 and 313, and have a signal amplitude of the voltage VDDM higher than the input signal amplitude VDD. The bus lines 306 and 307 route signals having such a signal amplitude of the voltage VDDM.

  The circuit elements 408a to 408d are high breakdown voltage elements that operate at the VDDM potential, and constitute a drive selection circuit (NOR gate) corresponding to one heater in the drive selection circuit array 308. The output of the NOR gate is connected to the gate of an NMOS transistor 409 which is a drive circuit that performs heater on / off control. The operation of turning on this segment is as follows.

  First, the output signals from the element drive signal circuit 304 and the block selection circuit 305 are level-converted to VDDM in the level conversion circuits 312 and 313. Here, the output signals from the element drive signal circuit 304 and the block selection circuit 305 output the VDDM potential that is Hi level when the corresponding element and block are not selected, and 0 V that is Lo level when the selection is made. It is configured to output to the bus line.

  Therefore, in the unselected segment, at least one of the signals input from the bus lines 306 and 307 to the NOR gate has the VDDM potential. Since the VDDM potential is input to at least one of the inputs of the NOR gate, the output potential is 0 V, and the transistor 409 is not turned on and the heater current does not flow. On the other hand, when both of the input signals from the bus lines 306 and 307 become 0V, the output of the NOR gate becomes the VDDM potential. As a result, the transistor 409 is turned on, and a heater current flows from the heater power supply potential VH through the heater 410. The heater through which current flows generates heat necessary for ink foaming and ejection.

  In the NOR gate, the output becomes Hi only when all the input signals become 0V. Therefore, if it is a NOR gate, the heater current drive NMOS transistor 409 can be controlled by itself. On the other hand, when the NAND gate is used, the output becomes Lo only when all the input signals to the NAND gate are Hi (VDDM). For this reason, in order to control the heater current drive NMOS transistor by the calculation result by the NAND gate, it becomes necessary to insert an inverter for performing the NOT calculation further, increasing the number of elements per segment, and increasing the density. This may be an obstacle to the arrangement of the selection circuit.

  The reason why the NMOS transistor 409 is used for driving the heater current is that, since the NMOS transistor generally uses electrons having higher mobility than holes as carriers, the on-resistance per area is made lower than that of the PMOS transistor. Because it can. That is, the on-resistance is reduced by using a field effect transistor having a channel with electrons as carriers in the heater drive circuit.

  In recent thermal ink jet heads, a DMOS (Diffusion MOS) structure may be employed in order to increase the breakdown voltage of the NMOS transistor 409 and lower the on-resistance. In this DMOS structure, a channel layer of a transistor is formed by impurity diffusion.

  The gate length of a normal MOS transistor is defined by the line width of a gate metal (such as POLY-Si), while the channel length of a DMOS transistor is defined by the diffusion length of impurities. Specifically, after a region for forming a source / drain of the DMOS is formed by a field oxide film and a gate electrode, a channel forming impurity is ion-implanted into the source region. After that, activation is performed while thermally diffusing impurities for channel formation so as to go under the gate electrode by heat treatment. Thereafter, an impurity having a polarity opposite to that for the channel is implanted into the source / drain region at a high concentration to form the source / drain. Here, the impurity in the source / drain region is activated by a heat treatment that does not diffuse more than the channel impurity. Then, a DMOS transistor is manufactured in which the difference in diffusion length between the channel impurity and the source / drain impurity becomes the channel length. That is, the DMOS transistor is a field effect transistor that defines the channel length by the diffusion length of impurities.

  In such a DMOS transistor, the source-substrate breakdown voltage may be lowered due to its structure. In such a case, in order to use the DMOS transistor, it is necessary to make the source potential and the substrate potential the same. On the other hand, since the source potential of the DMOS transistor can always be set to the substrate potential (0 V) by using the NOR circuit as in this embodiment, the DMOS transistor can be used also in the drive selection circuit. A withstand voltage drive selection circuit can be realized with a small number of elements. (For example, if a NAND circuit is used in place of the NOR circuit and the NAND circuit is configured with the same number of elements as the NOR circuit, NMOS (here, DMOS) must be connected in series. (In this case, the source potential of the DMOS may not be the substrate potential.) The above-described NOR circuit may include a MOS transistor having the same structure as the heater driving MOS transistor. You may make it use in a NOR circuit.

  Furthermore, as shown in FIG. 4, a NOR gate by CMOS (complementary MOS transistor) is used and PMOS transistors are connected in series. That is, as shown in FIG. 4, a NOR gate is formed by a CMOS structure including a PMOS transistor 408b and an NMOS transistor 408a, and a CMOS structure including a PMOS transistor 408d and an NMOS transistor 408c, and the PMOS transistor 408b and the PMOS transistor 408d are connected in series. Has been. With this configuration, it is possible to obtain the function of the resistor 208l described in FIG. 2, that is, the effect of making the steep rise of the heater current gentle. That is, since the PMOS transistor constituting the NOR gate is connected from the power supply potential to the output node in series, the PMOS transistor and the NMOS transistor have the same gate width and gate length when the output is changed from Lo to Hi. Compared with the case of using an inverter (an inverter formed by the PMOS transistor 208K and the NMOS transistor 208j in FIG. 2), it can be made higher. The steep rise of the heater current is alleviated by the ON resistance due to the PMOS transistors 408b and 408d being connected in series and the time constant due to the gate capacitance of the heater drive transistor 409, and malfunction due to noise can be suppressed. That is, the resistor 208l arranged for the purpose of alleviating steep current rise in FIG. 2 can be replaced with a low resistance element having a smaller element area, and the drive control circuit can be arranged at high density. It becomes possible.

  As described above, according to the first embodiment, the number of high withstand voltage elements arranged in each segment is reduced, and the circuits necessary for the head substrate 301 are arranged at a high density without increasing the chip size. Is possible. Further, by arranging the heaters corresponding to the heater selection circuits arranged at a high density, it is possible to achieve a high-density heater arrangement. That is, it is possible to provide a circuit configuration capable of selectively driving heaters arranged at high density without increasing the chip size.

Second Embodiment
In the first embodiment, the level conversion circuits 312 and 313 are connected to the outputs of the element drive signal circuit 304 and the block selection circuit 305, respectively. In the second embodiment, a configuration in which the level conversion circuit is connected to the input side of the element drive signal circuit and the block selection circuit will be described.

  FIG. 5 is a circuit block diagram schematically showing a circuit configuration example of the head substrate 301 ′ according to the second embodiment and the flow of electric signals. The circuit block in FIG. 5 shows a symmetrical arrangement with the ink supply port 311 as the center, as in the first embodiment. Elements constituting this circuit block are a heater array 310 composed of a plurality of heaters across the ink supply port 311, a drive circuit array 309 for flowing current to the heaters, a drive selection circuit array 308 for controlling the drive circuits, and a drive An element drive circuit 504 and a block selection circuit 505 that generate signals to be transmitted to the selection circuit array, and an input circuit 303 for processing signals input from the pads 302.

  The second embodiment is different from the first embodiment in that level conversion is performed to perform conversion from a first power supply voltage amplitude having the same voltage amplitude as the input signal to a second power supply voltage amplitude having a higher power supply voltage amplitude. This is the insertion position of the circuit. In the second embodiment, level conversion circuits 512 and 513 are connected to the output side of the input circuit 303, and an element drive signal circuit 504 and a block selection circuit 505 are connected to the public corporation of the level conversion circuits 512 and 513. In the first embodiment, the element drive signal circuit 304 and the block selection circuit 305 are operated by the first power supply voltage (VDD), and the output signal from these circuits is supplied to the second power supply voltage (VDDM). Level conversion circuits 312 and 313 for performing signal amplitude conversion have been inserted. In the second embodiment, level conversion circuits 512 and 513 are inserted to perform signal amplitude conversion of the output signal from the input circuit 303 to the second power supply voltage (VDDM), and the element drive signal circuit 504 and the block selection are inserted. The circuit 505 is operated with the second power supply voltage (VDDM).

  By adopting the configuration of the second embodiment as described above, for example, when the block selection circuit is a decoder that develops an input signal, it is possible to suppress the scale of the level conversion circuit that increases the layout area. . For example, consider a case where the selection circuit has a decoder that selects one of 16 signal lines from a 4-bit input signal and outputs a signal. FIG. 6 shows a circuit configuration of the level conversion circuit 513 and the block selection circuit 505 in the second embodiment. FIG. 7 shows circuit configurations of the level conversion circuit 313 and the block selection circuit 305 in the first embodiment.

  Here, in order to select any one line from the 16 bus lines by the 4-bit input signal, the Hi / Lo logics of the four input signals are changed to the 16 4-input AND gates so as to be different from each other. Need to connect with. In the decoder of the second embodiment, a 4-bit input signal is connected from the output of the input circuit 601 to the four level conversion circuits 513a to 513d, and the output and 16 signals obtained by inverting the logic by the inverters 603a to 603d The AND gates 604a to 604p are connected differently. Here, the output voltage of the level conversion circuits 513a to 513d is a second power supply voltage that is higher than the first power supply voltage that is the power supply voltage of the input signal. Therefore, the inverters 603a to 603d and the AND gates 604a to 604p operate with the second power supply voltage. With this configuration, four level conversion circuits are arranged.

  On the other hand, in the circuit configuration of the first embodiment shown in FIG. 7, since up to the block selection circuit 305 is operated with the first power supply voltage, one of the 16 bus lines as the output of the block selection circuit 305 is used. It is necessary to arrange the level conversion circuits 313a to 313p one by one, that is, to the outputs of the 16 AND gates 704a to 704p. As described above, according to the second embodiment, the number of level conversion circuits can be reduced to ¼ compared to the first embodiment shown in FIG. 7, and the number of elements can be reduced. .

  Since the level conversion circuits 512 and 513 are arranged in front of the element drive signal circuit 504 and the block selection circuit 505, the elements that constitute the level drive circuits 512 and 513 have a high breakdown voltage. Is required, and the element area increases. Therefore, whether the level conversion circuits 512 and 513 are arranged before or after each of the circuits 504 and 505 depends on the reduction of the circuit area due to the reduction in the number of elements required for the level conversion circuit and the high voltage resistance of the circuits 504 and 505. What is necessary is just to determine by balance with the increase in the circuit area at the time of becoming.

  For example, if there is no change in the number of input / output signal lines of the element drive signal circuit 504, it is advantageous to arrange the level conversion circuit 512 at the subsequent stage of the element drive signal circuit 504. This is because the element drive signal circuit 504 can be configured with low breakdown voltage elements, which is advantageous in terms of high density. Therefore, in such a case, a level conversion circuit may be provided in the preceding stage for the block selection circuit 505, and a level conversion circuit may be provided in the subsequent stage for the element drive signal circuit 504.

  As described above, according to the second embodiment, in addition to the effects of the first embodiment, the circuit area related to the block selection circuit and the element drive signal circuit can be further reduced.

It is the circuit block diagram of the conventional semiconductor substrate for inkjet recording heads, and the schematic diagram which shows the flow of an electrical signal. It is a figure which shows the drive circuit per segment of the conventional semiconductor substrate for inkjet recording heads. FIG. 2 is a circuit block diagram of the semiconductor substrate for an ink jet recording head according to the first embodiment of the present invention and a schematic diagram showing a flow of electric signals. It is a figure which shows the drive circuit per segment of the semiconductor substrate for inkjet recording heads of 1st Embodiment of this invention. It is the schematic diagram which shows the circuit block diagram of the semiconductor substrate for inkjet recording heads of 2nd Embodiment of this invention, and the flow of an electrical signal. It is a figure which shows the block selection circuit of the semiconductor substrate for inkjet recording heads of 2nd Embodiment of this invention. It is a figure which shows the block selection circuit of the semiconductor substrate for inkjet recording heads of 1st Embodiment of this invention. 1 is an overview of an ink jet recording apparatus to which the present invention can be applied. It is an external appearance perspective view which shows the detailed structure of the inkjet cartridge IJC. 3 is a perspective view illustrating a three-dimensional structure of a recording head IJHC that discharges three color inks. FIG. It is a figure which shows the control structure for performing recording control of the inkjet recording device shown in FIG.

Claims (12)

A substrate on which an electrothermal conversion element for generating thermal energy used for ejecting ink and a drive circuit for driving the electrothermal conversion element are mounted;
Each of a block selection signal for selecting a block to be driven based on an input signal of the first voltage amplitude level and an element drive signal for driving an electrothermal transducer to be driven according to image data A first circuit unit for outputting at a second voltage amplitude level higher than the first voltage amplitude level;
A NOR circuit that inputs a signal output from the first circuit unit and outputs a control signal having the second voltage amplitude level for controlling a drive circuit corresponding to the electrothermal transducer to be driven An inkjet recording head substrate.   2. The ink jet recording head substrate according to claim 1, wherein the NOR gate is realized by a complementary MOS transistor.   2. The ink jet recording head substrate according to claim 1, wherein the driving circuit is composed of one or more field effect transistors.   4. The substrate for an ink jet recording head according to claim 3, wherein the NOR gate includes an element having an element structure common to a field effect transistor constituting the driving circuit.   2. The substrate for an ink jet recording head according to claim 1, wherein the driving circuit includes a field effect transistor having a channel using electrons as carriers.   2. The substrate for an ink jet recording head according to claim 1, wherein the driving circuit includes a field effect transistor that defines a channel length by an impurity diffusion length.   The first circuit unit includes a conversion unit that converts a signal having the first voltage amplitude level into a signal having the second voltage amplitude level, in a stage preceding the circuit that generates the block selection signal. The ink jet recording head substrate according to claim 2.   The first circuit unit includes a conversion unit that converts a signal having the first voltage amplitude level into a signal having the second voltage amplitude level, in a stage preceding the circuit that generates the element driving signal. 2. The ink jet recording head substrate according to claim 1. A drive control method for an electrothermal conversion element on a substrate on which an electrothermal conversion element for generating thermal energy used for discharging ink and a drive circuit for driving the electrothermal conversion element are mounted There,
Input an input signal of the first voltage amplitude level,
A block selection signal for selecting a block to be driven based on the input signal and an element drive signal for driving an electrothermal transducer to be driven in accordance with image data are respectively set to the first. Output at a second voltage amplitude level higher than the voltage amplitude level of
A control signal having the second voltage amplitude level for controlling the drive circuit corresponding to the electrothermal transducer to be driven by inputting the signal output at the second voltage amplitude level to the NOR circuit. Output
A drive control method for an ink jet recording head, wherein the electrothermal conversion element is driven based on the control signal. An ejection port for ejecting ink;
An electrothermal conversion element provided corresponding to the discharge port;
Comprising a substrate mounted with a drive circuit for driving the electrothermal transducer,
The substrate is
Each of a block selection signal for selecting a block to be driven based on an input signal of the first voltage amplitude level and an element drive signal for driving an electrothermal transducer to be driven according to image data A first circuit unit for outputting at a second voltage amplitude level higher than the first voltage amplitude level;
A NOR circuit that inputs a signal output from the first circuit unit and outputs a control signal having the second voltage amplitude level for controlling a drive circuit corresponding to the electrothermal transducer to be driven An ink jet recording head comprising: the second circuit portion. An ink jet recording head comprising a substrate on which an ejection port for ejecting ink, an electrothermal conversion element provided corresponding to the ejection port, and a drive circuit for driving the electrothermal conversion element are mounted;
An ink tank filled with ink to be supplied to the inkjet recording head,
The substrate is
Each of a block selection signal for selecting a block to be driven based on an input signal of the first voltage amplitude level and an element drive signal for driving an electrothermal transducer to be driven according to image data A first circuit unit for outputting at a second voltage amplitude level higher than the first voltage amplitude level;
A NOR circuit that inputs a signal output from the first circuit unit and outputs a control signal having the second voltage amplitude level for controlling a drive circuit corresponding to the electrothermal transducer to be driven An ink jet recording head cartridge. An ink jet recording head having a substrate on which an ejection port for ejecting ink, an electrothermal conversion element provided corresponding to the ejection port, and a drive circuit for driving the electrothermal conversion element are mounted;
A circuit for transmitting a control signal to the inkjet recording head,
The substrate is
Each of a block selection signal for selecting a block to be driven based on an input signal of the first voltage amplitude level and an element drive signal for driving an electrothermal transducer to be driven according to image data A first circuit unit for outputting at a second voltage amplitude level higher than the first voltage amplitude level;
A NOR circuit that inputs a signal output from the first circuit unit and outputs a control signal having the second voltage amplitude level for controlling a drive circuit corresponding to the electrothermal transducer to be driven An ink jet recording apparatus comprising: the second circuit portion.

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