JP2006157783A - Drive method of solid-state imaging element, and solid-state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a drive method of a solid-state imaging element capable of suppressing degradation of the horizontal resolution of detected colors existing in respective pixels whose number is relatively smaller than that of the other color pixels in the case of capturing an image through summation of the pixels and extracting image signals at a high speed by decreasing the difference between the numbers of horizontally transferred images even in the case of executing full pixel reading. <P>SOLUTION: A solid-state imaging element disclosed herein includes: many pixels each including a photoelectric conversion section and arranged in a matrix form over a plurality of rows and a plurality of columns, each photoelectric conversion section being sensitive to light of any color in a plurality of the detected colors; a plurality of vertical transfer sections located along the columnar direction adjacently to each pixel; and a horizontal transfer section arranged at downstream ends of the vertical transfer sections in the columnar direction, the arrangement of many of the pixels is configured such that the detected colors by the photoelectric conversion sections are regularly and repetitively arranged and a plurality of the different detected colors are distributed, and in the case of reading electric charge signals from each pixel, only the pixels of the G color whose number is relatively larger than the other color pixels among a plurality of the different detected colors and the homochromatic pixels arranged in the same row of the pixels above are summated. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for driving a solid-state imaging device and a solid-state imaging device.

  Imaging devices such as digital still cameras and digital video cameras that use a CCD solid-state imaging device as an area image sensor are rapidly spreading. In a CCD type solid-state imaging device, a vertical charge transfer device (comprising a CCD (charge coupled device)) in which a large number of photoelectric conversion devices are arranged in a matrix over a plurality of rows and columns on one surface of a semiconductor substrate. VCCD) is disposed along one photoelectric conversion element array, for example, one for each photoelectric conversion element array. Further, a horizontal charge transfer element (HCCD) constituted by a CCD is disposed at the output end of each vertical charge transfer element.

  In a single-plate CCD solid-state imaging device used for color photography, a color filter array is arranged above a large number of photoelectric conversion elements arranged in a matrix. The color filter array is composed of color filters arranged one above the individual photoelectric conversion elements, and there are three primary color system color filter arrays and complementary color system color filter arrays. As complementary color filter arrays, there are known a color filter array composed of only complementary color filters and a color filter array composed of complementary color filters and green color filters. The color of the color filter becomes the color of the pixel.

  Each pixel in the single-plate CCD type solid-state imaging device has a photoelectric conversion element constituted by a photodiode, and one color filter disposed above the photoelectric conversion element. A microlens is disposed on the color filter as necessary.

  In the configuration of the CCD solid-state imaging device having the above configuration, when light enters a pixel on the device, an amount of charge corresponding to the amount of light is accumulated in the photoelectric conversion device of the pixel. The charge accumulated in each pixel (photoelectric conversion element) is read out to the vertical charge transfer element corresponding to this pixel, and further transferred to the horizontal charge transfer element by this vertical charge transfer element. The charges accumulated in each pixel belonging to one pixel row are read to the corresponding vertical charge transfer element at the same timing and transferred to the horizontal charge transfer element at the same timing. The horizontal charge transfer element sequentially transfers the charges received from each of the vertical charge transfer elements in a predetermined direction and outputs them.

The charges output from the horizontal charge transfer element are detected by the output circuit unit formed on the semiconductor substrate. The output circuit unit generates a signal voltage corresponding to the detected charge, amplifies the signal voltage, and outputs the amplified signal voltage. The charge detected by the output circuit unit is absorbed by the power supply voltage after being swept out to the drain region, for example.
An imaging apparatus using such a CCD solid-state imaging device generates an image signal using a signal voltage (pixel signal; unit signal) output from an output circuit unit.

  As a solid-state imaging device used as an area image sensor, a device in which a large number of pixels are arranged in a square lattice pattern (including those having different numbers of rows and columns) is known. As an array of color filters widely used in such a solid-state imaging device, there is a Bayer array. The Bayer array is formed by alternately repeating pixel rows in which R pixels and G pixels are alternately arranged and pixel rows in which G pixels and B pixels are alternately arranged. Also known is a pixel array in which pixels in odd-numbered rows and odd-numbered columns and pixels in even-numbered rows and even-numbered columns are shifted by ½ pitch. In a solid-state imaging device having such a pixel array, as shown in FIG. In addition, a so-called G stripe R / B color checkered color filter in which the row direction and the column direction of the Bayer array are inclined by about 45 ° is used.

  As a driving method of a CCD type solid-state imaging device composed of pixels of the above arrangement, signal charges from all photoelectric conversion elements are usually used as pixel signals, but a monitor mode in an electronic still camera using a solid-state imaging device In (a mode in which a captured image is displayed on the display unit of the camera) and a moving image shooting mode (the number of recording pixels is generally small), it is sufficient to obtain signals that are thinned out in the vertical and horizontal directions.

In this case, thinning out in the vertical direction is realized by thinning out reading from the photoelectric conversion element to the vertical transfer unit or adding (mixing) charges of a plurality of photoelectric conversion elements in the vertical direction through the vertical transfer path. . In the horizontal thinning, a line memory for temporarily accumulating signal charges is provided between the vertical transfer unit and the horizontal transfer unit, and a transfer column from the vertical transfer unit to the horizontal transfer unit is thinned out. This is realized by adding (mixing) charges from a plurality of vertical transfer units. When signal charges are added, the signal amount (charge amount) handled as one pixel in signal processing is increased, so that there is an advantage that imaging sensitivity is improved.
As described above, for example, Patent Document 1 discloses a solid-state imaging device that adds signal charges in a horizontal transfer unit.

FIG. 17 is a diagram illustrating a schematic configuration as an example of a solid-state imaging device that is configured by the pixel array illustrated in FIG. 16 and performs addition of signal charges in a horizontal transfer unit.
The solid-state imaging element 1 is provided adjacent to the photoelectric conversion elements 2 and the plurality of photoelectric conversion elements 2 arranged in a matrix over a plurality of rows and columns on the surface of the semiconductor substrate. A plurality of vertical transfer units 3 that transfer the generated signal charges in the column direction Y, a charge reading unit 4 that reads the signal charges of the photoelectric conversion element 1 to the vertical transfer unit 3, and an end of the vertical transfer unit 3, A line memory 5 that temporarily accumulates signal charges from the vertical transfer unit 3, a horizontal transfer unit 6 that transfers signal charges from the line memory 5 in the row direction X, and a signal charge that is transferred by the horizontal transfer unit 6 And an output unit 7 for outputting a signal. In addition, the code | symbol of FIG. 17 attaches the number on behalf of only the part.

  The photoelectric conversion element 2 is realized by an embedded photodiode, and generates and accumulates signal charges corresponding to the amount of incident light. A color filter (not shown) is provided above each photoelectric conversion element 2, and each photoelectric conversion element 2 generates and accumulates signal charges having spectral sensitivity corresponding to the color of the filter. The color filter may be, for example, red (hereinafter may be simply described as “R”), green (hereinafter may be simply described as “G”), blue (hereinafter simply described as “B”). There are three primary colors.

  The vertical transfer unit 3 stores a charge read out from the photoelectric conversion element 2 and transfers the vertical charge transfer channel and a vertical transfer electrode provided thereabove (corresponding to a vertical charge transfer channel region in FIG. 17). The region to be formed is schematically represented as a vertical transfer unit 3). The signal charge of the photoelectric conversion element 2 is read to the vertical transfer unit 3 through the charge reading unit 4. Since various things are known for the shape and arrangement of the photoelectric conversion element 2, the vertical transfer unit 3, and the charge readout unit 4, and the shape and arrangement of the vertical transfer electrode (not shown), detailed description thereof will be omitted.

The line memory 5 is configured as one charge transfer stage following the vertical transfer unit 3. The charge transfer stage constituting the line memory 5 has the same configuration as the charge transfer stage of the second type charge transfer element, an n ⁻ -type impurity addition region on the upstream vertical transfer unit 3 side, and a downstream horizontal transfer An n-type impurity doped region is formed on the part 3 side. Therefore, after accumulating signal charges in the charge transfer stage of the vertical transfer unit 3 adjacent to the upstream side, a relatively low level voltage is applied to the charge transfer stage, and a relatively high level voltage is applied to the line memory 5. Is applied, the signal charge from the vertical transfer unit 3 can be transferred to the line memory 5 and stored.

  The horizontal transfer unit 6 includes a second type charge transfer element, and has one charge transfer stage corresponding to one vertical transfer unit 3. Then, the signal charges accumulated in the line memory 5 provided at the downstream end of the vertical transfer unit 3 are transferred to the corresponding charge transfer stage, accumulated, and transferred to the output unit 7.

JP 2002-112119 A

  In the case of the arrangement of R, G, and B pixels shown in FIG. 12, as shown in FIG. 14, pixel addition in the horizontal direction adds G pixels, R pixels, and G pixels. Although the adjacent pixels having the horizontal distance L are added to the G pixel having a large number, the pixel addition is performed by skipping one horizontal pixel having the horizontal distance 2L to the R pixel and the B pixel having a small relative number. ing. Therefore, the horizontal resolution for the R pixel and the B pixel of the image signal after pixel addition is lowered.

  The present invention has been made in view of the above situation, and provides a solid-state imaging device driving method and a solid-state imaging device capable of suppressing a decrease in horizontal resolution of detection colors with a small relative number when an image is captured by adding pixels. It is intended to provide.

The above object of the present invention is achieved by the following configuration.
(1) A large number of pixels in which photoelectric conversion units that generate charges in response to light of any one of a plurality of detection colors are arranged in rows and columns, and each of these pixels A plurality of vertical transfer units that are provided adjacent to each other and transfer the charges generated by the respective pixels to the downstream side in the column direction, and are arranged on the downstream side in the column direction of the respective vertical transfer units and transferred from the vertical transfer unit A solid-state imaging device driving method including a horizontal transfer unit that transfers charges to the downstream side in the row direction, wherein the plurality of detection colors are one or a plurality of first detection colors having a relatively small number of corresponding pixels. And the pixels having one or a plurality of second detection colors having a relatively large number of corresponding pixels and sensitive to the light of the detection colors are regularly distributed, and the charge of the pixels For the charge of the pixel of the first detection color when transferring The solid-state imaging element driving method of adding the charges of pixels of the same color arranged in the same row and adjacent to each other for the charges of the pixels of the second detection color without adding the charges of the pixels of the second detection color.

  According to this solid-state imaging device driving method, when reading out charges from the photoelectric conversion unit of each pixel, even if charge addition transfer is performed to add an image by adding charges from a plurality of pixels, For the charge of the pixel of the first detection color (for example, R, B) having a relatively small number, the charge of the other pixel is not added, and the second detection color (the number of corresponding pixels is relatively large). For example, for the charge of the pixel G), the charges of pixels of the same color arranged in the same row and adjacent to each other are added. Therefore, pixels with a relatively small number of detected colors arranged at relatively distant positions do not perform pixel addition, and pixels with a relatively large number of detected colors arranged at relatively close positions are adjacent pixels in the same row. By performing the addition, an image signal obtained by pixel addition can be obtained without reducing the horizontal resolution.

(2) In the driving method of the solid-state imaging device according to (1), a plurality of charge transfers from the vertical transfer unit to the horizontal transfer unit are provided at the column direction downstream end of the vertical transfer unit. Transferring the charges of the pixels of the first detection color accumulated in the charge accumulation unit to the horizontal transfer unit, which is performed after the charge is once accumulated in the charge accumulation unit; Transferring the charge transferred to the horizontal transfer unit downstream in the horizontal transfer unit; transferring the charge from the vertical transfer unit to the charge storage unit; and the first charge stored in the charge storage unit. Transferring the charge of a pixel of one detection color to the horizontal transfer unit without adding to the charge of the first detection color transferred downstream in the horizontal transfer unit; and storing in the charge storage unit Of the detected pixels of the second detection color Transferring a part of the load to the horizontal transfer unit, transferring the charge transferred to the horizontal transfer unit downstream in the horizontal transfer unit, and the first charge stored in the charge storage unit. Transferring the remaining charge of the pixels of the two detection colors to the horizontal transfer unit, and adding the charge to the second detection color transferred to the downstream side in the horizontal transfer unit. Driving method.

  According to this driving method of the solid-state imaging device, for the detection colors having a large relative number, the positions of the charges are aligned between adjacent pixels by driving the horizontal transfer unit, and the charges are added in the horizontal transfer unit.

(3) The method for driving a solid-state imaging device according to (1) or (2), wherein the charge-adding transfer for selectively adding and transferring charges between adjacent pixels of the same color is selectively performed. .

  According to this solid-state image sensor driving method, by performing charge addition transfer particularly when pixel addition is required, post-processing after image signal extraction eliminates the need for data calculation for pixel addition. Processing speed is improved.

(4) The solid-state imaging device driving method according to (3), wherein the charge addition transfer is performed when a moving image is captured and recorded by the solid-state imaging device.

  According to this solid-state imaging device driving method, post-processing of an image signal generated at the time of shooting is reduced by performing charge addition transfer when shooting and recording a moving image.

(5) The method for driving a solid-state imaging device according to (3) or (4), wherein the charge addition transfer is performed when the captured image is displayed on the monitor by the solid-state imaging device.

  According to this method for driving a solid-state imaging element, processing of an image signal output at the time of display is reduced by performing charge addition transfer when performing monitor display.

(6) A large number of pixels in which photoelectric conversion units that generate charges in response to light of any one of a plurality of detection colors are arranged in a matrix over a plurality of rows and columns, and each of these pixels A plurality of vertical transfer units that are provided adjacent to each other and transfer charges generated by the respective pixels to the downstream side in the column direction, and are arranged at the column direction downstream end of each of the vertical transfer units and transferred from the vertical transfer unit A solid-state imaging device having a horizontal transfer unit that transfers charges to the downstream side in the row direction, and a control for outputting a drive signal for performing drive based on the drive method according to any one of (1) to (5) A solid-state imaging device.

  According to this solid-state imaging device driving method, when reading out charges from the photoelectric conversion unit of each pixel, even if charge addition transfer is performed to add an image by adding charges from a plurality of pixels, For the charge of the pixel of the first detection color (for example, R, B) having a relatively small number, the charge of the other pixel is not added, and the second detection color (the number of corresponding pixels is relatively large). For example, for the charge of the pixel G), the charges of pixels of the same color arranged in the same row and adjacent to each other are added. As a result, charge addition transfer can be performed while suppressing a decrease in horizontal resolution of detected colors with a small relative number.

  According to the solid-state imaging device driving method and the solid-state imaging device of the present invention, it is possible to suppress a decrease in the horizontal resolution of detected colors with a small relative number when an image is captured by adding pixels.

Preferred embodiments of a solid-state imaging device driving method and a solid-state imaging device according to the present invention will be described below in detail with reference to the drawings.
First, the configuration of the solid-state imaging device will be described.
FIG. 1 is a block diagram illustrating an outline of the solid-state imaging device according to the present embodiment. As shown in the figure, the solid-state imaging device 100 according to the present embodiment includes an imaging optical system 11, a solid-state imaging device 13, a drive circuit 15, an image signal processing circuit 17, an image data output unit 19, a display unit 21, and a recording unit 23. A control unit 25, an operation unit 27, and a pulse signal generation unit 29.

  The imaging optical system 11 forms an optical image on the solid-state imaging device 13. The imaging optical system 11 includes, for example, an optical lens, a diaphragm, an optical low-pass filter, and the like. The arrow L in the figure indicates light.

  The solid-state image sensor 13 is composed of, for example, a CCD image sensor, and converts an optical image formed by the imaging optical system 11 into an electrical signal. The solid-state imaging device 13 includes a photoelectric conversion device, a vertical charge transfer device (VCCD), a horizontal charge transfer device (HCCD), an output unit, and a color filter array. Details of the solid-state imaging device 13 will be described later.

  The drive circuit 15 supplies drive signals and control signals necessary for the operation of the solid-state image sensor 13 to the solid-state image sensor 13. The drive circuit 15 includes, for example, a vertical driver, a horizontal driver, a DC power source, and the like. Further, a circuit for controlling the optical lens and the diaphragm of the imaging optical system 11 is included as necessary.

  The image signal processing circuit 17 receives the image signal generated by the solid-state imaging device 13 and performs various processes on the image signal to generate image data. The image signal processing circuit 17 includes, for example, an analog / digital converter, a CDS circuit (correlated double sampling circuit), a color separation circuit, a delay line, and the like.

  The image data output unit 19 receives the image data output from the image signal processing circuit 17 and stores the image data in a storage medium such as a frame memory.

  The display unit 21 displays a still image or a moving image based on the image data supplied from the image data output unit 19. The display unit 21 includes a display device such as a liquid crystal display.

  The recording unit 23 records the image data supplied from the image data output unit 19 on a recording medium such as a memory card.

  The control unit 25 outputs a drive signal that controls operations of the drive circuit 15, the image signal processing circuit 17, the image data output unit 19, and the like. The control unit 25 is constituted by, for example, a central processing unit (CPU). A mode selection unit 26 is included in the control unit 25.

  The mode selection unit 26 is a selection switch for selecting an imaging mode of the solid-state imaging device 100. The solid-state imaging device 100 includes, for example, at least two imaging modes, that is, a still image recording mode that captures and records a still image, and a monitor mode that displays an image on the display unit 21 when capturing a moving image or a still image. Have The mode selection unit 26 is operated by the user of the solid-state imaging device 100 via the operation unit 27, or any mode is automatically selected according to other settings.

  The pulse signal generator 29 generates a pulse signal for unifying the operation timing in the apparatus, and supplies the pulse signal to the drive circuit 15, the image signal processing circuit 17, the controller 25, and the like. The pulse signal generator 29 includes, for example, an original oscillation that generates pulses at a constant period, a timing generator, and the like.

  The solid-state imaging device 13 which is one component of the solid-state imaging device 100 is a CCD image sensor that can vertically and horizontally add charges accumulated in a plurality of photoelectric conversion elements in the solid-state imaging device 13. Hereinafter, the configuration of the CCD image sensor will be described with a detailed example.

  FIG. 2 is a partial plan view schematically showing a planar arrangement of the photoelectric conversion element, the vertical charge transfer element, the CCD line memory unit, the horizontal charge transfer element, and the output unit in the solid-state imaging device 13 according to the present embodiment.

  As shown in FIG. 2, in the solid-state imaging device 13 of the present embodiment, a large number of photoelectric conversion elements 31 are arranged with a pixel shift. In the figure, for convenience, a red filter is indicated by a symbol R, a green filter is indicated by a symbol G1 or G2, and a blue filter is indicated by a symbol B.

  The color filter array shown in FIG. 2 includes a first color filter row FC1 composed only of a green filter G1, a second color filter row FC2 in which blue filters B and red filters R are alternately arranged, and a green filter. A third color filter row FC3 constituted only by G2 and a fourth color filter row FC4 in which red filters R and blue filters B are alternately arranged are repeatedly arranged in this order from the left to the right of the drawing. Has been. In addition, the arrangement of the red filter R and the blue filter B in the second color filter array FC2 is opposite to the arrangement of the red filter R and the blue filter B in the fourth color filter array FC4. The color filters G1, R, G2, and B are arranged so as to be shifted in pixels, and are shifted in the color filter column direction and the color filter row direction.

  The green color filter G1 constituting the first color filter row FC1 and the green color filter G2 constituting the third color filter row FC3 are merely made by changing reference numerals for convenience, and both are formed of the same material. ing.

  Here, the “pixel shifting arrangement” means the following arrangement in this specification. That is, for each photoelectric conversion element in the odd-numbered photoelectric conversion element array, each photoelectric conversion element in the even-numbered photoelectric conversion element array is approximately 1/2 the pitch of the photoelectric conversion elements in the photoelectric conversion element array, For each photoelectric conversion element in the photoelectric conversion element row corresponding to the odd-numbered photoelectric conversion element row, the photoelectric conversion elements in the even-numbered photoelectric conversion element row are approximately 1 / th of the pitch of the photoelectric conversion elements in the photoelectric conversion element row. 2. It means an arrangement of a large number of photoelectric conversion elements that are shifted in the row direction and each of the photoelectric conversion element columns includes only odd-numbered or even-numbered photoelectric conversion elements. “Pixel shifting arrangement” is one form of a large number of photoelectric conversion elements formed in a matrix over a plurality of rows and columns.

  As shown in FIG. 2, one vertical transfer unit 33 meandering along one pixel column (photoelectric conversion element column) is arranged in each pixel column. Each vertical transfer unit 33 includes a vertical charge transfer channel 37 formed in the semiconductor substrate 35 and a plurality of first vertical transfer electrodes disposed on the semiconductor substrate 35 via an electrical insulating film (not shown). 41, a second vertical transfer electrode 43, first to third auxiliary transfer electrodes 45 to 47, first and second transfer control electrodes LM1 and LM2, and first and second horizontal transfer electrodes Ha and Hb. .

  In this specification, the movement of the charges transferred by the charge transfer element is regarded as one flow, and the relative positions of the individual members and the like are set to “what upstream”, “ It is specified as “downstream” or the like.

  The first and second vertical transfer electrodes 41 and 43 are arranged one by one on the downstream side of one pixel row (photoelectric conversion element row). Each of the first vertical transfer electrodes 41 also constitutes a read gate that controls charge transfer from the photoelectric conversion element 31 to the vertical transfer unit 33.

  FIG. 3 is a cross-sectional view schematically showing one pixel and its periphery in the solid-state imaging device 13 shown in FIG. In FIG. 1, a light shielding film and a passivation film not shown in FIG. 1 and members disposed above the semiconductor substrate are shown. Among the constituent elements shown in FIG. 3, the constituent elements already shown in FIG. 2 are assigned the same reference numerals as those used in FIG.

As shown in FIG. 3, in the photoelectric conversion element 31, an n-type impurity addition region 31a is provided at a predetermined position of the p-type impurity addition region 35b on the semiconductor substrate 35, and a p ⁺ -type impurity is provided on the n-type impurity addition region 31a. It is constituted by a buried photodiode formed by providing the addition region 31b. The n-type impurity added region 31a functions as a charge storage region.

  One p-type impurity addition region 35b is exposed along the right edge in FIG. 3 of each photoelectric conversion element 31 (n-type impurity addition region 31a). This region in the p-type impurity doped region 35b is used as a channel region 52a for the read gate 52. The vertical charge transfer channel 37 and the photoelectric conversion element 31 corresponding thereto are adjacent to each other through the channel region 52a.

  The electrical insulating film 53 is formed of, for example, a single layer silicon oxide film, a laminated film of a silicon oxide film and a silicon nitride film, or the like.

  On the surface of the first vertical transfer electrode 41, an electrical insulating film IF composed of a thermal oxide film or the like is formed. The same applies to the second vertical transfer electrode 43 and the auxiliary transfer electrodes 45 to 47 that are not visible in FIG.

Except for the location where the channel region 52a is formed, the channel stop region CS includes the periphery of each photoelectric conversion element 31 in plan view, the periphery of each vertical charge transfer channel 37 in plan view, and the horizontal charge transfer channel 55 (FIG. 2). (See Fig. 2) in the plan view. The channel stop region CS is formed, for example, by providing a p ⁺ -type impurity added region at a predetermined position of the p-type impurity added region 35b. The concentration of the p-type impurity in the p ⁺ -type impurity added region is higher than the concentration of the p-type impurity in the p-type impurity added region.

  Each impurity added region can be formed by, for example, ion implantation and subsequent annealing. The p-type impurity added region 35b can also be formed by, for example, an epitaxial growth method.

  A light shielding film 61 is formed so as to cover the vertical charge transfer element (hereinafter referred to as a vertical transfer part) 33, the horizontal charge transfer element (hereinafter referred to as a horizontal transfer part) 57, and the output circuit part 59 (see FIG. 2). Is formed. This light shielding film 61 has one opening 61 a above each photoelectric conversion element 31. A region located in a plan view in the opening 61 a on the surface of each photoelectric conversion element 31 is a light incident surface in the photoelectric conversion element 31.

  The light shielding film 61 is formed using, for example, a metal material such as aluminum, chromium, tungsten, titanium, molybdenum, or an alloy material composed of two or more of these metals.

  The passivation film 63 covers the light shielding film 61 and the electrical insulating film 53 exposed from the opening 61a, and protects the underlying members. The passivation film 63 is made of, for example, silicon nitride, silicon oxide, or the like.

  Further, the first planarization film 65 covers the passivation film 63. The first planarization film 65 is also used as a focus adjustment layer for the microlens 72 described later. An inner lens is formed in the first planarization film 65 as necessary. The first planarizing film 65 is formed by applying a transparent resin such as a photoresist to a desired thickness by, for example, a spin coating method.

  One color filter is arranged on each photoelectric conversion element 31 to form a photoelectric conversion unit for a specific detection color. The color filter sets the detection color of the photoelectric conversion element 31 and is formed on the first planarization film 65. In FIG. 3, three green filters 67 are shown.

  The color filter can be produced, for example, by forming a resin (color resin) layer containing a pigment or dye of a desired color at a predetermined location by a method such as a photolithography method.

  A second planarization film 69 is formed on each color filter on the color filter to form a flat surface for forming the microlens 72. The second planarizing film 69 is formed by applying a transparent resin such as a photoresist to a desired thickness by, for example, a spin coating method.

  A microlens 72 is formed on the second planarization film 69. One microlens 72 is arranged above each photoelectric conversion element 31. For example, the microlens 72 is formed by partitioning a layer made of a transparent resin (including a photoresist) having a refractive index of approximately 1.3 to 2.0 into a predetermined shape by a photolithography method or the like, and then heat-treating the transparent resin in each partition. For example, the layer is melted, the corners are rounded by surface tension, and then cooled. One section becomes one microlens 72.

  4 is a partially enlarged plan view schematically showing a horizontal transfer unit in the solid-state imaging device shown in FIG. As shown in the figure, the horizontal transfer unit 57 includes one horizontal charge transfer channel 55 extending in a strip shape in the row direction of the photoelectric conversion elements, and a large number of second charge transfer channels 55 formed on the horizontal charge transfer channel 55. 1 and second horizontal transfer electrodes Ha and Hb. Each first horizontal transfer electrode Ha has a rectangular shape in plan view. Each of the second horizontal transfer electrodes Hb has an inverted L shape in plan view.

  The first and second horizontal transfer electrodes Ha and Hb are formed on the semiconductor substrate 35 via the electrical insulating film 53, and are made of, for example, a polysilicon layer.

  FIG. 5 is an explanatory diagram showing an AA cross section of the solid-state imaging device shown in FIG. FIG. 5 shows the positional relationship between the electrodes and impurity regions of the vertical transfer unit, line memory, and horizontal transfer unit, and the dimensions of each element (for example, n-type impurities below the first horizontal transfer electrode Ha). The dimensions of the area etc.) are not accurate.

On the vertical charge transfer channel 37 (partially numbered) partitioned in the channel stop region CS (see FIG. 3), as shown in FIG. 2, corresponds to the most downstream photoelectric conversion element. Vertical transfer electrodes V2, V3, and V4 are provided in order from the vertical transfer electrode V1 downward in the figure, and subsequently, transfer control electrodes LM (in this example, the first transfer control electrode LM1 and the second transfer control electrode LM2). However, since the same voltage is applied, it is simply described as “LM”). As shown in the cross-sectional view of FIG. The vertical charge transfer channel 37 is formed of an n-type impurity region. Following the vertical charge transfer channel 37, an n ⁻ -type impurity region 71 and an n-type impurity region 73 of the transfer control electrode LM are provided.

As described above, the horizontal transfer unit 57 includes one horizontal charge transfer channel 55 extending in a strip shape in the row direction, and a number of first horizontal transfer electrodes Ha formed above the horizontal charge transfer channel 55. And a second horizontal transfer electrode Hb. The first horizontal transfer electrode Ha is provided above the n-type impurity region 75 of the horizontal charge transfer channel, and the second horizontal transfer electrode Hb is provided above the n ⁻ -type impurity region 77 of the horizontal charge transfer channel. The second horizontal transfer electrode Hb wraps around a region between the second transfer control electrode LM2 and the first horizontal transfer electrode Ha, and the n ^- type impurity region is also below the wrap-around portion.

  The vertical transfer electrodes V1, V2, V3 and V4 are driven by four-phase drive pulses φV1 to φV4, and the horizontal transfer electrodes Ha and Hb are driven by four-phase drive pulses φH1 to φH4. Since the same drive pulse is applied to the vertical transfer electrodes Ha and Hb having the same charge transfer function, the vertical transfer electrodes Ha and Hb are adjusted to the corresponding applied drive pulses φH1 to φH4 as necessary. , H1-H4.

Here, a basic charge transfer method will be described.
6 shows changes in the level of the drive pulse applied to the vertical transfer electrodes V1 to V4, the transfer control electrode LM, and the horizontal transfer electrodes H1, H4, and H3. It is explanatory drawing shown corresponding to a)-(e). “H” in FIG. 6 is described as a state where a relatively high level voltage (hereinafter simply referred to as “high level”) is applied to the corresponding electrode (hereinafter simply referred to as “high level”). “L” indicates a state in which a relatively low level voltage is applied to the corresponding electrode (hereinafter, simply referred to as “low level”).

  In FIG. 6A, the electrodes V1, V4, H1, and H7 are at the low level, and the electrodes V2, V3, LM, and H4 are at the high level, and the signal charge of the vertical transfer unit 33 is below the electrodes V2 and V3. Indicates the accumulated state. In this state, as shown in FIG. 6B, when the electrode V4 is set to the high level, the barrier region below the electrode V4 disappears, so that the signal charge is stored in the line memory below the transfer control electrode LM (hereinafter simply referred to as line memory). (Also described as LM).

Next, as shown in FIG. 6C, the electrode V4 is set to the low level to form a barrier region to inhibit the charge transfer to the vertical transfer unit 33, and then the electrode H1 is set to the high level. However, since the n ⁻ impurity region exists between the transfer control electrode LM and the horizontal transfer unit 57, the signal charge of the line memory does not move. As shown in FIG. 6D, when the transfer control electrode LM is set to the low level, the signal charge moves below the electrode H1. This state is a state in which the signal charge has moved from the vertical transfer unit 33 to the horizontal transfer unit 57.

  The charge transfer in the horizontal transfer unit 57 is performed by changing the level of the adjacent electrode and setting the upstream side to the low level. As shown in FIG. 6E, when both the electrodes H1 and H4 are at the low level, the signal charge does not move as in FIG. 6D. The electrode H1 is set to the low level from the state of FIG. 6D, or the electrode H4 is set to the high level from the state of FIG. 6E, so that the upstream electrode is at the low level and the downstream electrode is at the high level. Then, the signal charge accumulated on the upstream side moves to the downstream side.

  The charge transfer in the horizontal transfer unit 57 and the horizontal transfer unit 57 from the line memory described above is performed by controlling the level of the voltage applied to the transfer control electrode LM and the horizontal transfer electrodes H1 to H4 (Ha, Hb). Can move freely.

Next, an operation when thinning out by adding signal charges in the horizontal direction using the solid-state imaging device 100 having the above configuration will be described.
The pixel addition method according to the present invention does not perform pixel addition on a first color pixel (R pixel and B pixel) with a small relative number among a plurality of different detection colors, and has a large relative number. For a pixel of two colors (G pixel), the pixel is added to the pixel of the same color that is arranged in the same row as the pixel and is adjacent thereto.

  FIG. 7 is an explanatory diagram schematically showing a planar arrangement of pixels of the solid-state imaging device. In the figure, the vertical direction corresponds to the vertical charge transfer direction, and the horizontal direction corresponds to the horizontal charge transfer direction. This solid-state imaging device has a so-called G stripe RB checkered pixel arrangement in which a large number of green pixels G, blue pixels B, and red pixels R are arranged in a shifted manner. Each pixel has a photoelectric conversion element and a color filter arranged above the photoelectric conversion element. The shape of the pixel shown in FIG. 7 schematically shows the outline of the color filter that the pixel has. Here, in order to simplify the description, the descriptions of “G1” and “G2” shown in FIG. 2 are simply rewritten as “G”.

  When two pixels are added in the horizontal direction to the pixel array shown in FIG. 7 using the above-described solid-state imaging device 100, the pixels surrounded by a solid line are added to the G pixel, and the R pixel and Pixel addition is not performed for the B pixel. That is, pixel addition with adjacent pixels in the same row is performed only for the G pixel.

  By applying the above pixel addition, for the R pixel and the B pixel, the same color pixels that are adjacent in the same row are added to each other, and the addition is performed for each distance L of skipping one pixel. By performing pixel addition only for G pixels that are large in number and short in distance to adjacent pixels, it is possible to suppress the decrease in the horizontal resolution of the entire image and reduce the number of horizontal transfer pixels to ½ of all pixels. .

Next, a driving method of the solid-state imaging device for performing the above pixel addition will be described with reference to FIGS.
8 to 11 show driving pulses applied to the vertical transfer electrode V4 (not shown in FIGS. 9 and 11) of the vertical transfer unit, the transfer control electrode LM of the line memory, and the horizontal transfer electrodes H1 to H4 of the horizontal transfer unit. FIG. 4 is a timing chart of φV4, φLM, φH1 to φH4, and an explanatory diagram showing the state of a line memory and a horizontal transfer unit corresponding to the state of drive pulses.

  In this example, for convenience of explanation, only the vertical transfer electrode V4, the line memory LM, and the horizontal transfer unit 57 corresponding to the vertical transfer units for 12 horizontal transfer electrodes are shown. In addition, the code | symbol and number are attached | subjected only to one part.

  First, at time t1 shown in FIG. 8, the vertical transfer electrode V4 is changed from the high level to the low level, and the signal charge for one row from the vertical transfer unit is accumulated in the line memory LM. At this timing, the drive pulse φLM is held at a high level, and the drive pulses φH1 to φH4 are held at a low level.

  Next, the signal charges stored in the line memory LM are transferred to the horizontal transfer unit 57 and transferred in the horizontal transfer unit 57. First, the signal charges in the column corresponding to the horizontal transfer electrode H1 (corresponding to the red filter). The signal charge corresponding to the detection light having the spectral sensitivity is described as “R charge.” Similarly, the signal charge corresponding to the green filter is “G charge”, and the signal charge corresponding to the blue filter is “B charge. ").) Is transferred.

  The transfer of the R charges in the column corresponding to the horizontal transfer electrode H1 to the horizontal transfer unit 57 is performed by setting the drive pulse φH1 to the high level and the drive pulse φLM to the low level (see time t2). Next, the drive pulse φLM is set to a high level to make it impossible to move other signal charges accumulated in the line memory LM, and then the R charge of the horizontal transfer unit 57 is transferred to the lower side of the horizontal transfer electrode H4 (time). t3).

  Next, in order to transfer the G charge in the column corresponding to the horizontal transfer electrode H2, the drive pulse φH2 is set to the high level, the drive pulse φLM is set to the low level, and the charge is transferred to the horizontal transfer unit 57 (see time t4). ).

  Next, the drive pulse φLM is returned to the high level, the drive pulses φH1 and φH3 are set to the high level, the drive pulses φH2 and φH4 are set to the low level, and the R charges and G charges below the horizontal transfer electrodes H2 and H4 are simultaneously transferred (time t5). reference). Further, the polarities of the drive pulses φH1 to φH4 are inverted, and both the R charge and the G charge of the horizontal transfer unit 57 are transferred until the G charge transferred by the horizontal transfer unit 57 reaches a position below the horizontal transfer electrode H4. (See time t6).

  Here, since the signal charge in the column corresponding to the horizontal transfer electrode H4 stored in the line memory LM is G charge, the drive pulse φH4 is set to high level and the drive pulse φLM is set to low level to transfer the charge horizontally. When transferred to the unit 57, the G charges can be added (described as “2G”) (see time t7). It should be noted that here, the drive pulse φH2 is also set to the high level in order to share with the subsequent sequences. This addition of G charges is a pixel addition corresponding to the G pixel pair 81 shown in FIG.

  Next, the polarity of the drive pulses φH1 to φH4 is repeatedly inverted with respect to the horizontal transfer electrodes H1 to H4, and the R charges and 2G charges of the horizontal transfer unit 57 are transferred to the output circuit unit 59 (see FIG. 2) (time). t8 to t9). At this time, B charges remain in the column corresponding to the horizontal transfer electrode H3 in the line memory LM.

  The remaining B charges are transferred to the horizontal transfer unit 57 with the drive pulse φH3 at the high level and the drive pulse φLM at the low level (see time t10). Then, the B charges of the horizontal transfer unit 57 are transferred to the lower side of the horizontal transfer electrode H2 (see time t11).

In this state, the vertical transfer electrode V4 is changed from the high level to the low level, and the signal charge for the next row is accumulated in the line memory LM from the vertical transfer unit (see time t12).
Then, the drive pulse φH4 is set to the high level, the drive pulse φLM is set to the low level, and the G charge, which is the signal charge in the column corresponding to the horizontal transfer electrode H4, is transferred to the horizontal transfer unit 57 (see time t13).

  Further, the polarity of the drive pulses φH1 to φH4 is repeatedly inverted with respect to the horizontal transfer electrodes H1 to H4, and the B charge and G charge of the horizontal transfer unit 57 are transferred until the G charge reaches below the waterside transfer electrode H2. (See times t14 to t15).

  Since the signal charge in the column corresponding to the horizontal transfer electrode H2 stored in the line memory LM is G charge, the drive pulse φH2 is set to high level, the drive pulse φLM is set to low level, and the charge is transferred to the horizontal transfer unit. When transferred to 57, G charges can be added (see time t16). This addition of G charges is a pixel addition corresponding to the G pixel pair 83 shown in FIG.

As a result, the 2G charge and the B charge are repeatedly arranged in the horizontal transfer unit 57 so as to skip one horizontal transfer electrode.
Then, the polarity of the drive pulses φH1 to φH4 is repeatedly inverted with respect to the horizontal transfer electrodes H1 to H4, and 2G charges and B charges of the horizontal transfer unit 57 are transferred to the output circuit unit 59 (see FIG. 2) (time). t17 to t18). At this time, in the line memory LM, R charges remain in the column corresponding to the horizontal transfer electrode H1, and B charges remain in the column corresponding to the horizontal transfer electrode H3.

The remaining R charge and B charge are transferred to the horizontal transfer unit 57 with the drive pulses φH1 and φH3 set to high level and the drive pulse φLM set to low level (see time t19). As a result, R charges and G charges are repeatedly arranged in the horizontal transfer portion 57 so as to skip one horizontal transfer electrode.
Then, the polarity of the drive pulses φH1 to φH4 is repeatedly inverted with respect to the horizontal transfer electrodes H1 to H4, and the R charge and B charge of the horizontal transfer unit 57 are transferred to the output circuit unit 59 (see FIG. 2) (time). t20).

  At this time, there is no charge left in the line memory LM, and the above-described processing from time t1 is repeated.

  That is, the first charge reading of the horizontal transfer unit 57 is repetition of R charge and 2G charge, the second charge reading is repetition of 2G charge and B charge, and the third charge reading is repetition of R charge and B charge. It becomes. The fourth charge readout is the same as the first, the fifth charge readout is the same as the second, and this is repeated.

By controlling the line memory LM and the horizontal transfer unit 57 in this way, desired charges can be added (horizontal addition) within the horizontal transfer unit 57.
The output circuit unit 59 sequentially outputs image signals (signal voltages) based on the charges received from the horizontal transfer unit 57. The image signal processing circuit 17 shown in FIG. 1 generates image data using these image signals (signal voltages). The image data generated by the image signal processing circuit 17 is sent to the image data output unit 19 and temporarily stored in a storage medium such as a frame memory. Thereafter, image data is supplied from the image data output unit 19 to the display unit 21, and the display unit 21 displays an image.

  In addition, pixel addition is not performed in the case of still image recording or the like in which all pixels are read to obtain high-resolution image data. In that case, the solid-state imaging device 100 has a function of selectively setting execution / non-execution of pixel addition, so that it can appropriately cope with various usage states of the imaging device. That is, the adjacent G color pixels are added together to generate a unit signal at each pixel position for image signal generation, and the charge accumulated in each color pixel is individually And a mode selection unit 26 (see FIG. 1) for selectively performing the individual readout mode for generating the unit signal.

  Accordingly, the mode selection unit 26 of the solid-state imaging device 100 selects a mode according to the use condition of the solid-state imaging device, and selectively switches between charge addition transfer and normal charge transfer. The image can be read out. In particular, when pixel addition is required, by performing charge addition transfer on the solid-state imaging device side, it is not necessary to calculate data for pixel addition in post-processing after image signal extraction, improving processing speed can do.

  According to the driving method of the solid-state imaging device described above, the G pixels are subjected to horizontal pixel addition in the same row, and the R and B pixels are output without pixel addition. Therefore, the reduction in the horizontal resolution can be improved as compared with the conventional method in which pixel addition is performed by skipping R and B pixels in the horizontal direction by one pixel. In addition, since the number of horizontal transfer pixels is the same as that in the conventional method, charge readout can be performed at a high frame rate. Furthermore, since the charges of a plurality of G pixels are added, an effect of increasing sensitivity can be obtained. In addition, the number of horizontal transfer pixels can be halved for all pixel readout, and high-speed driving can be performed while suppressing a decrease in horizontal resolution. Further, the horizontal transfer unit can be driven by four-phase drive, and simple horizontal transfer drive control is sufficient.

Although the pixel arrangement in the above-described pixel addition method is a pixel-shifted arrangement, the present invention is not limited to this, and a so-called square lattice arrangement can also be applied. In addition, application to any arrangement is possible without departing from the gist of the present invention.
Further, in the present embodiment, a solid-state imaging device having R pixels, G pixels, and B pixels as basic colors is illustrated, but the present invention is not limited to this, and magenta, cyan, yellow, and even emerald colors are used. The present invention can also be applied to those configured using other colors, and the same effects can be obtained.

It is a block diagram which shows the outline of the solid-state imaging device concerning this invention. 2 is a partial plan view schematically showing a planar arrangement of a photoelectric conversion element, a vertical transfer unit, a CCD line memory unit, a horizontal transfer unit, and an output unit of a solid-state imaging device. FIG. FIG. 3 is a cross-sectional view schematically showing one pixel and its periphery in the solid-state imaging device shown in FIG. 2. FIG. 3 is a partially enlarged plan view schematically showing a water horizontal transfer unit in the solid-state imaging device shown in FIG. 2. It is explanatory drawing which shows the AA cross section of the solid-state image sensor shown in FIG. The potential levels of the impurity regions in the portion shown in FIG. 5 are shown in correspondence with changes in the levels of drive pulses applied to the vertical transfer electrodes V1 to V4, the transfer control electrode LM, and the horizontal transfer electrodes H1, H4, and H3. FIG. It is explanatory drawing which shows roughly the planar arrangement | positioning of the pixel of a solid-state image sensor. Timing chart of drive pulses φV4, φLM, φH1 to φH4 applied to the vertical transfer electrode V4 of the vertical transfer unit, the transfer control electrode LM of the line memory, and the horizontal transfer electrodes H1 to H4 of the horizontal transfer unit, and the state of the drive pulse FIG. 3 is an explanatory diagram (part 1) illustrating a state of a line memory and a horizontal transfer unit corresponding to FIG. Timing chart of drive pulses φV4, φLM, φH1 to φH4 applied to the transfer control electrode LM of the line memory and the horizontal transfer electrodes H1 to H4 of the horizontal transfer unit, and the line memory and the horizontal transfer unit corresponding to the state of the drive pulse It is explanatory drawing (the 2) which shows the state of. Timing chart of drive pulses φV4, φLM, φH1 to φH4 applied to the vertical transfer electrode V4 of the vertical transfer unit, the transfer control electrode LM of the line memory, and the horizontal transfer electrodes H1 to H4 of the horizontal transfer unit, and the state of the drive pulse FIG. 6 is an explanatory diagram (part 3) illustrating a state of a line memory and a horizontal transfer unit corresponding to FIG. Timing chart of drive pulses φV4, φLM, φH1 to φH4 applied to the transfer control electrode LM of the line memory and the horizontal transfer electrodes H1 to H4 of the horizontal transfer unit, and the line memory and the horizontal transfer unit corresponding to the state of the drive pulse It is explanatory drawing (the 4) which shows the state of. It is explanatory drawing which shows the pixel arrangement from the past made into the G stripe R / B complete checkered arrangement by inclining the row direction and column direction of a Bayer arrangement | sequence about 45 degrees. FIG. 13 is a plan view showing a schematic configuration as an example of a conventional solid-state imaging device configured by the pixel array shown in FIG. 12 and adding signal charges in a horizontal transfer unit. It is explanatory drawing showing the pixel addition with respect to the conventional horizontal direction.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Imaging optical system 13 Solid-state image sensor 15 Drive circuit 17 Image signal processing circuit 19 Image data output part 21 Display part 23 Recording part 25 Control part 26 Mode selection part 27 Operation part 29 Pulse signal generation part 31 Photoelectric conversion element 33 Vertical charge transfer Element (vertical transfer unit)
57 Horizontal charge transfer device (horizontal transfer unit)
59 Output circuit unit 81 G pixel pair 83 G pixel pair 100 Solid-state imaging device FC1 First color filter array FC2 Second color filter array FC3 Third color filter array FC4 Fourth color filter array LM1 First transfer control electrode LM2 2 transfer control electrode LM transfer control electrode Ha first horizontal transfer electrode Hb second horizontal transfer electrode V1 vertical transfer electrode V2 vertical transfer electrode V3 vertical transfer electrode V4 vertical transfer electrode

Claims (6)

A plurality of pixels in which a photoelectric conversion unit that generates a charge in response to light of any one of a plurality of detection colors is arranged in rows and columns and adjacent to each of these pixels. A plurality of vertical transfer units that transfer the charges generated by the pixels to the downstream side in the column direction, and the charges transferred from the vertical transfer units arranged on the downstream side in the column direction of the vertical transfer units. A solid-state imaging device driving method having a horizontal transfer unit for transferring to the downstream side in the direction,
The plurality of detection colors include one or a plurality of first detection colors with a relatively small number of corresponding pixels and one or a plurality of second detection colors with a relatively large number of corresponding pixels,
The pixels sensitive to the light of the detection color are regularly distributed and arranged,
When transferring the charge of the pixel, the charge of the pixel of the first detection color is not added to the charge of the other pixel, and the charge of the pixel of the second detection color is in the same row. A method for driving a solid-state imaging device, in which the charges of pixels of the same color arranged in close proximity are added. A method for driving a solid-state imaging device according to claim 1,
Charge transfer from the vertical transfer unit to the horizontal transfer unit is performed after the charge is temporarily stored in a plurality of charge storage units provided at the column direction downstream end of the vertical transfer unit. ,
Transferring the charges of the pixels of the first detection color accumulated in the charge accumulation unit to the horizontal transfer unit;
Transferring the charges transferred to the horizontal transfer unit downstream in the horizontal transfer unit;
Transferring charges from the vertical transfer unit to the charge storage unit;
The charge of the pixel of the first detection color accumulated in the charge accumulation unit is transferred to the horizontal transfer unit without being added to the charge of the first detection color transferred downstream in the horizontal transfer unit. And steps to
Transferring a part of the charges of the pixels of the second detection color accumulated in the charge accumulation unit to the horizontal transfer unit;
Transferring the charges transferred to the horizontal transfer unit downstream in the horizontal transfer unit;
The remaining charge of the pixel of the second detection color accumulated in the charge accumulation unit is transferred to the horizontal transfer unit and added to the charge of the second detection color transferred downstream in the horizontal transfer unit. And steps to
A method for driving a solid-state imaging device including: A method for driving a solid-state imaging device according to claim 1 or 2,
A driving method of a solid-state imaging device that selectively performs charge addition transfer in which charges of adjacent pixels of the same color are added and transferred. A method for driving a solid-state imaging device according to claim 3,
A method for driving a solid-state imaging device, wherein the charge addition transfer is performed when a moving image is captured and recorded by the solid-state imaging device. A method for driving a solid-state imaging device according to claim 3 or 4,
A method for driving a solid-state imaging device, wherein the charge addition transfer is performed when a captured image is displayed on the monitor by the solid-state imaging device. A plurality of pixels in which a plurality of rows and a plurality of photoelectric conversion units that generate charges in response to light of any one of a plurality of detection colors are arranged in rows and columns;
A plurality of vertical transfer units that are provided adjacent to each of the pixels and transfer charges generated by the pixels to the downstream side in the column direction;
A solid-state imaging device having a horizontal transfer unit disposed at the column direction downstream end of each vertical transfer unit and transferring the charge transferred from the vertical transfer unit to the downstream side in the row direction;
A solid-state imaging device comprising: a control unit that outputs a driving signal for performing driving based on the driving method according to claim 1.

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