JP4478651B2 - IMAGING DEVICE, CCD TYPE SOLID-STATE IMAGING ELEMENT MOUNTED ON THE IMAGING DEVICE, AND ITS DRIVING METHOD - Google Patents

Description

  The present invention relates to an image pickup apparatus, a CCD (Charge Coupled Device) type solid-state image pickup element mounted on the image pickup apparatus, and a driving method thereof. In particular, pixel addition in a horizontal transfer path (HCCD) can be easily performed. The present invention relates to a possible imaging device, a CCD solid-state imaging device, and a driving method thereof.

  Patent Document 1 below describes a CCD solid-state imaging device that performs pixel addition in a horizontal transfer path (HCCD). This CCD type solid-state imaging device is a memory unit that temporarily accumulates signal charges at the connection point between the end portion of each vertical transfer path provided in a plurality of rows and the horizontal transfer path (because it is provided along the horizontal transfer path, (Referred to as (LM)). Then, the timing at which the line memory moves the signal charge received from each vertical transfer path to the horizontal transfer path is adjusted in accordance with the signal charge transfer drive in the horizontal transfer path to perform horizontal pixel addition.

JP 2002-112119 A

  In the conventional CCD type solid-state imaging device, the entire line memory is driven in one phase. Therefore, if the horizontal transfer drive is complicated and not matched with the one-phase drive of the line memory, the pixel addition in the horizontal direction is performed accurately. In other words, it is difficult to create the drive timing of the image sensor and the manufacturing cost increases.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an image pickup apparatus that can easily perform transfer driving of a horizontal transfer path and accurately perform pixel addition in the horizontal direction, a CCD solid-state image pickup device mounted on the image pickup apparatus, and a driving method thereof. It is to provide.

The CCD type solid-state imaging device of the present invention includes a plurality of vertical transfer paths that transfer signal charges read from a plurality of photodiodes arrayed on the surface of a semiconductor substrate in the vertical direction, and each vertical transfer path. A horizontal transfer path that receives the signal charges transferred by the horizontal transfer path and transfers them in the horizontal direction, and a signal charge temporary storage section provided for each of the vertical transfer paths is continuous in the horizontal direction with a barrier interposed therebetween. A line memory provided between a transfer path and each end of the plurality of vertical transfer paths, wherein each of the signal charge temporary storage units corresponds to the vertical transfer path when a high level of a pulse signal is applied C and a line memory to transfer the signal charges to the horizontal transfer path when the low level of the pulse signal is applied by the temporary storage to the required timing the signal charge received from In the D-type solid-state imaging device, the line memory is constituted by dividing the line memory divided into a horizontal direction for each two of the signal charge temporary storage portion continuing to drive the divided line memory in the pulse signal of a plurality of phases In addition, an electrode wiring for applying the same pulse signal to the two signal charge temporary storage portions of each divided line memory is provided.

  The CCD type solid-state imaging device of the present invention is characterized in that the odd-numbered photodiodes arrayed on the surface of the semiconductor substrate are formed so as to be shifted by 1/2 pitch with respect to the even-numbered photodiodes. And

The driving method of the CCD solid-state imaging device of the present invention is a driving method of the CCD solid-state imaging device as described above, the driven front Symbol dividing line memories a pulse signal of a plurality of phases signal charge horizontal transfer path Is added.

  In the method for driving a CCD solid-state imaging device according to the present invention, the addition of the signal charges is performed between signal charges of the same color adjacent in the horizontal direction.

  An image pickup apparatus according to the present invention includes the CCD solid-state image pickup device described above and a drive unit that generates a pulse signal at a timing for realizing the drive method described above.

  According to the present invention, the line memory is divided into a plurality of lines in the horizontal direction, and each divided line memory is driven with a plurality of phase pulses. Therefore, the transfer pulse for driving the horizontal transfer path can be set as a fixed period pulse. Pixel addition on the transfer path is facilitated.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a functional configuration diagram of a digital camera according to an embodiment of the present invention. The digital camera includes an imaging unit 1, an analog signal processing unit 2 that performs analog processing such as automatic gain adjustment (AGC) and correlated double sampling processing on analog image data output from the imaging unit 1, and an analog signal processing unit. 2, analog / digital conversion unit (A / D) 3 for converting analog image data output to digital image data, and A / D 3, analog signal processing unit 2, in response to an instruction from a system control unit (CPU) 9 described later. A drive unit (including a timing pulse TG that generates read pulses, vertical transfer pulses, horizontal transfer pulses φH1 and φH2, line memory drive pulses φLM1 to φLM4, etc., which will be described later) that controls the drive of the imaging unit 1, and a CPU 9 And a flash 5 that emits light according to instructions.

  The imaging unit 1 includes an optical lens system 1a that condenses light from the object scene, a diaphragm or a mechanical shutter 1b that condenses the light that has passed through the optical lens system 1a, and a diaphragm that is condensed by the optical lens system 1a. A CCD type solid-state imaging device 100 that receives the received light and outputs captured image data (analog image data).

  The digital camera according to the present embodiment further includes a digital signal processing unit 6 that takes in digital image data output from the A / D 3 and performs interpolation processing, white balance correction, RGB / YC conversion processing, and the like. A compression / expansion processing unit 7 that compresses or decompresses the image data, a display unit 8 that displays a menu or the like, displays a through image or a captured image, and a system control unit that performs overall control of the entire digital camera ( CPU) 9, an internal memory 10 such as a frame memory, and a media interface (I / F) unit 11 that performs an interface process between a recording medium 12 that stores JPEG image data and the like, and a bus that interconnects them. The system control unit 9 is connected to an operation unit 13 for inputting instructions from the user.

  FIG. 2 is a schematic view of the surface of the CCD solid-state imaging device 100 shown in FIG. A large number of photodiodes 101 are arranged in a two-dimensional array on the semiconductor substrate of the CCD type solid-state imaging device in the example shown in the figure, and even-numbered photodiodes 101 are ½ of odd-numbered photodiodes 101. They are arranged at different pitches to form a so-called honeycomb pixel array.

  “R”, “G”, and “B” illustrated on each photodiode 101 represent the color of the color filter (red = R, green = G, blue = B) stacked on each photodiode. The diode 101 accumulates signal charges corresponding to the amount of received light of one of the three primary colors.

  In the horizontal direction of the semiconductor substrate surface, vertical transfer electrodes are laid to meander so as to avoid the photodiodes 101. In the semiconductor substrate, a buried channel (not shown) is formed to meander in the vertical direction so as to avoid the photodiode 101 at the side of the photodiode row arranged in the vertical direction. A vertical transfer path (VCCD) 102 is formed by the buried channel and a vertical transfer electrode provided on the buried channel and arranged in a meandering manner in the vertical direction.

  A horizontal transfer path (HCCD) 103 is provided on the lower side of the semiconductor substrate. This horizontal transfer path 103 is also composed of a buried channel and a horizontal transfer electrode provided thereon, and this horizontal transfer path 103 is driven in two phases by transfer pulses φH1 and φH2.

  An amplifier 104 is provided on the output side of the horizontal transfer path 103, and a voltage value signal corresponding to the amount of signal charge transferred to the output end of the horizontal transfer path 103 is output by the amplifier 104.

  The terms “vertical” and “horizontal” are used, which means “one direction” along the surface of the semiconductor substrate and “a direction substantially perpendicular to the one direction”.

  A line memory 105 is provided between the end of each vertical transfer path 102 and the horizontal transfer path 103. The line memory 105 is configured to receive the signal charge transferred to the end of the vertical transfer path 102, temporarily store it, and output it to the horizontal transfer path 103 at a predetermined timing.

  The line memory 105 of the present embodiment has substantially the same configuration as the line memory described in Patent Document 1, but the line memory described in Patent Document 1 is configured to be driven in one phase, whereas this embodiment The line memory 105 is configured to be driven in four phases.

  That is, in the line memory 105, one signal charge temporary storage unit is provided for one vertical transfer path, and this signal charge temporary storage unit is continuously provided in the horizontal direction across the barrier. In the line memory 105 of the embodiment, the first divided line memory (LM1), the second divided line memory (LM2), the third divided line memory (LM3), the fourth divided, every time two signal charge temporary storage units continue. The divided line memory (LM4), the first divided line memory (LM1),... Are divided, the first divided line memory is driven by the drive pulse φLM1, the second divided line memory is φLM2, and the third divided line memory is φLM3. The fourth divided line memory has an electrode wiring structure for driving with φLM4.

  The drive pulses φLM1 to φLM4, the horizontal transfer pulses φH1 and φH2, and the vertical transfer pulse are generated by the drive unit 4 of FIG.

  In the CCD solid-state imaging device 100 having such a configuration, signal charges corresponding to the amount of light received for each color are accumulated in each photodiode 101, and when a readout pulse is applied to the vertical transfer electrode serving as the readout electrode, the photodiode 101 The signal charge is read out from the vertical transfer path 102.

  The signal charge read to the vertical transfer path 102 is transferred in the vertical direction every time a vertical transfer pulse is applied to the vertical transfer path 102, and the signal charge transferred to the end of the vertical transfer path 102 is transferred to the line memory 105. Into the corresponding signal charge temporary storage section.

  Then, when a drive pulse is applied to the corresponding divided line memory (LM1, LM2, LM3, LM4) of the line memory 105, the signal charge of the signal charge temporary storage unit is transferred to the horizontal transfer path 103 as will be described in detail later. The pixel addition in the horizontal direction is performed. The signal charge obtained by pixel addition is transferred in the horizontal direction, and a voltage value signal corresponding to the signal charge amount is output from the amplifier 104 to the analog signal processing unit 2 in FIG.

  FIG. 3 is an enlarged schematic view of the main part of the horizontal transfer path and the line memory. The horizontal transfer path 103 includes buried channels 103a and first-layer horizontal transfer electrodes 103b and second-layer horizontal transfer electrodes 103c that are alternately provided on the buried channels.

  The first phase transfer pulse φH1 is applied to the continuous first layer and second layer horizontal transfer electrodes 103b and 103c, and the second phase transfer is performed to the next successive first layer and second layer horizontal transfer electrodes 103b and 103c. The pulse φH2 is applied, and further, the first phase transfer pulse φH1 is applied to the succeeding first layer and second layer horizontal transfer electrodes 103b and 103c, and the horizontal transfer path 103 is driven in two phases. .

  The upper two stages of FIG. 4 show the pulse waveforms of the horizontal transfer pulses φH1 and φH2 used in this embodiment. The transfer pulse φH1 is a periodic pulse that becomes high level at an even time and low level at an odd time among the times t1, t2, t3,. The transfer pulse φH2 is a pulse having a phase opposite to that of the transfer pulse φH1. Thus, in this embodiment, the horizontal transfer path is driven in two phases by a simple transfer pulse.

  Returning to FIG. 3, each of the divided line memories LM1, 2, 3 and 4 is provided corresponding to a portion in which two sets of adjacent first layer and second layer transfer electrodes 103b and 103c are continuous. Each of the divided line memories LM1, LM2, LM3, and LM4 includes two signal charge temporary storage units 105a and 105b, two barrier units 105c and 105d that separate the signal charge temporary storage units, and the divided line memory. Each is configured to include an electrode film to which drive pulses φLM1, φLM2, φLM3, and φLM4 are applied and a wiring 105e.

  With such a configuration, the B signal charge and the R signal charge are alternately input to the signal charge temporary storage unit 105a on the output terminal side of the divided line memories LM1 and LM3. The G signal charge is input to the other signal charge temporary storage unit 105b. R signal charges and B signal charges are alternately input to the signal charge temporary storage unit 105a on each output end side of the divided line memories LM2 and LM4, and a G signal charge is input to the other signal charge temporary storage unit 105b. The

  The lower four stages of FIG. 4 show the pulse waveforms of the drive pulses φLM1 to φLM4 for driving the divided line memories LM1 to LM4 in four phases. φLM1 is at low level at times t2 and t3, and is at high level at other times, φLM2 is at low level at times t1 and t4, and is at high level at other times, and φLM3 is at low level at times t3 and t6, and others The waveform of LM4 becomes a low level at times t1 and t8 and becomes a high level at other times.

  FIG. 5 is a diagram for explaining horizontal pixel addition using the horizontal transfer pulses φH1 and φH2 and the line memory drive pulses φLM1 to φLM4 shown in FIG. 4, and the R, G, and B signal charges on the horizontal transfer path and The state of the transfer is shown in order.

  According to the vertical transfer of the vertical transfer path 102 shown in FIG. 2, the R signal charges, the G signal charges, and the B signal charges are sequentially transferred to the signal charge temporary storage units 105a and 105b of the divided line memories LM1 to LM4. Has been.

  While a high level signal is applied to the divided line memories LM1 to LM4, a potential well is formed in the divided line memory portion, and signal charges (electrons in this example) are held in the potential well. When a low level signal is applied to the divided line memory, the bottom of the potential well is lifted and the potential well disappears, and the adjacent electrode on the horizontal transfer path becomes high level at the same timing, and a potential well is formed thereunder. Then, the signal charges of the divided line memory move into the potential well.

  At time t1 in FIG. 5, the R signal charge or the B signal charge has not yet moved to the signal charge temporary storage unit 105a of the divided line memories LM2 and LM4, and is empty. However, the G signal charge is stored in the other signal charge temporary storage unit 105b.

  At time t1, when the divided line memories LM2 and LM4 become low level and the horizontal transfer pulse φH2 becomes high level, the G signal charge in the divided line memories LM2 and LM4 moves to the horizontal transfer path.

  At the next time t2, the transfer on the horizontal transfer path advances to the output side by one step (adjacent first layer and second layer transfer electrodes 103b and 103c), and at the same time, the divided line memory LM1 becomes low level. As a result, the R signal charge in the divided line memory LM1 moves into the potential well after the G signal charge on the horizontal transfer path.

  At the next time t3, the transfer on the horizontal transfer path advances one step to the output side, and at the same time, the divided line memories LM1 and LM3 become low level. As a result, the G signal charge in the divided line memory LM1 moves into the potential well holding the previous G signal charge on the horizontal transfer path, and the two G signal charges are added. That is, the signal charges of the G pixels 201 and 202 adjacent in the horizontal direction in FIG. 2 are added, and the signal charges of the G pixels 203 and 204 are also added.

  At the next time t4, the transfer on the horizontal transfer path advances one step to the output side, and at the same time, the divided line memory LM2 becomes low level. As a result, the B signal charge in the division line memo LM2 moves into an empty potential well on the horizontal transfer path.

  At the next time t5, the transfer in the horizontal transfer path advances one step to the output side, but since all the divided line memories are maintained at the high level, there is no movement of signal charges from the line memory to the horizontal transfer path.

  At the next time t6, the transfer on the horizontal transfer path advances one step to the output side, and the divided line memory L3 becomes low level. As a result, the R signal charge in the divided line memory LM3 is added to the R signal charge previously transferred onto the horizontal transfer path. That is, the horizontal line of the R pixel shown in FIG. 2 is arranged in the order of —R—B—R—B—R—B—, but the signal charges of the two R pixels on both sides of the B pixel are added. Become.

  At the next time t7, the transfer in the horizontal transfer path advances one step to the output side, but since all the divided line memories are maintained at the high level, there is no movement of signal charges from the line memory to the horizontal transfer path.

  At the next time t8, the transfer on the horizontal transfer path advances one step to the output side, and the divided line memory LM4 becomes low level. As a result, the B signal charge in the divided line memory LM4 is added to the B signal charge previously transferred onto the horizontal transfer path. That is, in the horizontal line of the R pixel shown in FIG. 2, the signal charges of the two B pixels on both sides of the R pixel are added out of —R—B—R—B—R—B—. .

  As described above, the signal charge obtained by adding two pixels in the horizontal direction is stored in each potential well on the horizontal transfer path, and thereafter transferred to the output amplifier 104 side according to the horizontal transfer pulses φH1 and φH2.

  As described above, according to the present embodiment, the horizontal transfer path can be transferred and driven by simple fixed-period pulses φH1 and φH2, so that the design of the drive timing of the CCD solid-state imaging device having no existing line memory can be used as it is. Thus, it is only necessary to newly create the division line memory according to the pixel arrangement of the CCD solid-state image pickup device and the like, and only the pixel addition.

  In the above-described embodiment, the divided line memory is driven in four phases by taking a CCD solid-state image pickup device having a honeycomb pixel arrangement as an example. However, the CCD solid-state image pickup device is not limited to the honeycomb pixel arrangement, and the divided line memory is also used. Needless to say, the pixel addition may be performed not by four-phase driving but by other plural-phase driving.

  Since the image pickup apparatus according to the present invention and its CCD solid-state image pickup device can easily perform pixel addition in the horizontal direction, for example, when picking up and outputting a still image, the line memory is driven in one phase as in the prior art. This is useful for a digital camera or the like that performs pixel addition when a moving image is captured and output without pixel addition.

It is a functional block diagram of the digital camera which concerns on one Embodiment of this invention. It is a surface schematic diagram of the CCD type solid-state imaging device shown in FIG. FIG. 3 is a partially enlarged schematic diagram of a horizontal transfer path and a line memory shown in FIG. 2. It is a figure which shows the horizontal transfer pulse and division line memory drive pulse which are used by this embodiment. It is explanatory drawing of the pixel addition of the horizontal direction by this embodiment.

Explanation of symbols

4 Drive unit (including timing generator)
100 CCD type solid-state image sensor 101 Photodiode (pixel)
102 Vertical transfer path (VCCD)
103 Horizontal transfer path (HCCD)
104 Output amplifier 105 Line memory LM1, LM2, LM3, LM4 Divided line memory φLM1, φLM2, φLM3, φLM4 Divided line memory drive pulse φH1, φH2 Horizontal transfer pulse

Claims (5)

A plurality of vertical transfer paths for vertically transferring signal charges read from a plurality of photodiodes arranged in an array on the surface of the semiconductor substrate, and the signal charges transferred by the respective vertical transfer paths are received. A horizontal transfer path for transferring in the horizontal direction and a signal charge temporary storage section provided for each vertical transfer path are arranged in a horizontal direction across a barrier, and are formed by the horizontal transfer path and the plurality of vertical transfer paths. Each of the signal charge temporary storage units is a line memory provided between each end and temporarily stores the signal charge received from the corresponding vertical transfer path when a high level of a pulse signal is applied. in a CCD type solid-state imaging device and a line memory to transfer the signal charges to the horizontal transfer path when the low level of the pulse signal is applied at a required timing, the The in-memory, together constitute a split line memory divided horizontally every time two of the signal charge one continuous accumulation unit, and drives each of the divided line memory by the pulse signal of a plurality of phases, said respective divided line memory A CCD type solid-state imaging device, wherein electrode wiring for applying the same pulse signal is provided in two signal charge temporary storage portions .   2. The CCD type according to claim 1, wherein the odd-numbered photodiodes arranged on the surface of the semiconductor substrate are formed so as to be shifted by ½ pitch with respect to the even-numbered photodiodes. 3. Solid-state image sensor. A driving method of the CCD solid-state imaging device according to claim 1 or claim 2, drives the front Symbol dividing line memories a pulse signal of a plurality of phases in the horizontal transfer path to make the addition of the signal charges A driving method of a CCD type solid-state image pickup device characterized.   4. The method of driving a CCD type solid-state imaging device according to claim 3, wherein the addition of the signal charges is performed between signal charges of the same color adjacent in the horizontal direction.   An imaging device comprising: the CCD solid-state imaging device according to claim 1 or 2; and a driving unit that generates a pulse signal at a timing for realizing the driving method according to claim 3 or 4. apparatus.

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