JP2006156631A - Wiring board with resistive element, and its manufacturing method - Google Patents

Wiring board with resistive element, and its manufacturing method Download PDF

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JP2006156631A
JP2006156631A JP2004343638A JP2004343638A JP2006156631A JP 2006156631 A JP2006156631 A JP 2006156631A JP 2004343638 A JP2004343638 A JP 2004343638A JP 2004343638 A JP2004343638 A JP 2004343638A JP 2006156631 A JP2006156631 A JP 2006156631A
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electrode
wiring board
resistor
resistance
substrate
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Rika Sato
里佳 佐藤
Kenji Kawamoto
憲治 河本
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Toppan Inc
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Toppan Printing Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To enable application to the inner layer of a multilayer substrate and reduction in the variation of resistance values as well as improvement in accuracy of a shape at the time of resistance body formation by improving the shape of a resistance body in a wiring board with a resistive element. <P>SOLUTION: On the substrate of a base, the wiring board with a resistive element is connected with a resistance body 7 and a pair of element electrodes via a second electrode 4 provided for mitigating contact resistance. It is provided with an element electrode 3 provided on the substrate, a second electrode provided on this element electrode, an insulating layer 5 embedded where the upper surface of the second electrode is exposed on the whole surface from the substrate between the element electrode and the second electrode, and a resistance body provided between the second electrodes. The insulating layer and the upper surface of the second electrode exposed on the insulating layer upper surface are flat. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、電子装置の小型化及び電子部品の高密度化実装に最適な抵抗素子付き配線基板や部品内蔵の抵抗素子付き配線基板とその製造方法に関する。   The present invention relates to a wiring board with a resistance element optimal for miniaturization of electronic devices and high-density mounting of electronic components, a wiring board with a resistance element built in a component, and a manufacturing method thereof.

近年、電子部品小型化、薄型化の要求に伴い、電子部品およびこの電子部品を搭載するプリント配線基板等(以下配線基板と記す)に関しても、パターンの微細化・高密度化による小型化、厚みの薄い材料を用いることによる薄型化が要求されている。これに伴い、従来表面実装していた抵抗チップ部品を印刷抵抗体として形成した抵抗素子を内層した部品内蔵の抵抗素子付き配線基板が開発されつつある。これより、抵抗体の実装面積が減り、抵抗体の厚みもチップ部品に比べて薄くできるため、配線基板の小型化および薄型化を可能にする。   In recent years, with the demand for smaller and thinner electronic components, electronic components and printed wiring boards (hereinafter referred to as wiring boards) on which these electronic components are mounted are also reduced in size and thickness due to finer and higher density patterns. Thinning is required by using a thin material. Along with this, a wiring board with a resistive element having a built-in component in which a resistive element formed by using a resistor chip component that has been conventionally surface-mounted as a printed resistor has been developed. As a result, the mounting area of the resistor is reduced, and the thickness of the resistor can be made thinner than that of the chip component. Therefore, the wiring board can be reduced in size and thickness.

抵抗素子付き配線基板における従来の抵抗体形成方法に関し、スクリーン印刷法により基板上の一対の素子電極に抵抗体を印刷形成する方法や銅電極上(以下素子電極と記す)に第2電極として銀電極を印刷形成した後、抵抗体を印刷形成する方法がある。また、銅素地上にニッケル金めっき処理を施して第2電極を形成した後に、抵抗体を印刷形成する方法もある。   Regarding a conventional resistor forming method in a wiring board with a resistor element, a method of printing a resistor on a pair of element electrodes on a substrate by a screen printing method or silver as a second electrode on a copper electrode (hereinafter referred to as an element electrode) There is a method in which a resistor is printed after an electrode is printed. There is also a method in which a resistor is printed after forming a second electrode by performing nickel gold plating on a copper substrate.

しかしながら、抵抗体形成にスクリーン印刷法を用いる場合、印刷面の段差による印刷にじみや印刷ダレおよび膜厚バラつき等といった印刷性の課題を避けられないため、特に微細パターン形成は困難である。さらに、従来の素子電極上に形成した抵抗体の場合、抵抗体の形成後に空気中の水分や酸素の影響を受けて素子電極材料の銅と抵抗体との界面における接触抵抗が増加し、抵抗値が変動するという課題があった。その解決手段として、素子電極と抵抗体との間に接触抵抗が小さい材料による第2電極を形成する方法がある。   However, when the screen printing method is used for forming the resistor, it is difficult to form a fine pattern, because printability problems such as printing bleeding due to a step on the printing surface, printing sagging, and film thickness variation cannot be avoided. Furthermore, in the case of a resistor formed on a conventional element electrode, the contact resistance at the interface between the copper of the element electrode material and the resistor increases due to the influence of moisture and oxygen in the air after the resistor is formed. There was a problem that the value fluctuated. As a solution, there is a method of forming a second electrode made of a material having a small contact resistance between the element electrode and the resistor.

この第2電極に銀ペーストを印刷・形成した銀電極が用いられる場合、抵抗値の変動は低減化できるが、上述したように、印刷面の段差による印刷ダレや膜厚バラつき等が生じ、微細な電極間抵抗の形成がより困難になるという課題があった。さらに、微細な抵抗の形成がより困難であるため、多層基板の内層に適用することに課題があった。   When a silver electrode printed and formed with a silver paste is used for the second electrode, fluctuations in resistance can be reduced. However, as described above, printing sagging due to a step on the printing surface, film thickness variation, etc. occur, resulting in fine There is a problem that it is more difficult to form a proper interelectrode resistance. Furthermore, since it is more difficult to form a fine resistor, there is a problem in applying it to the inner layer of the multilayer substrate.

また、銅素地上にニッケル金メッキを施し第2電極を形成する方法もあるが、その後の表面処理が困難で、銅パターン上に黒化処理と呼ばれる酸化膜処理を行えないため、導体パターンと樹脂との密着性を確保することができず、多層基板の内層に適用することは困難であるという課題があった(特許文献1、特許文献2参照)。   There is also a method of forming a second electrode by performing nickel gold plating on the copper substrate, but the subsequent surface treatment is difficult, and the oxide film treatment called blackening treatment cannot be performed on the copper pattern, so the conductor pattern and resin There is a problem that it is difficult to secure the adhesiveness to the inner layer of the multilayer substrate and it is difficult to apply to the inner layer of the multilayer substrate (see Patent Document 1 and Patent Document 2).

以下に公知文献を記す。
特開平1−173778号公報 特開昭64−42895号公報
The known literature is described below.
JP-A-1-173778 Japanese Unexamined Patent Publication No. 64-42895

そこで、本発明はこれらの課題を解決するためになされたもので、抵抗体形状の向上により、抵抗体形成時の形状精度向上と共に抵抗値変動の低減化と、多層基板の内層への適用を可能にすることを目的とする。   Therefore, the present invention has been made to solve these problems, and by improving the shape of the resistor, it is possible to improve the shape accuracy at the time of forming the resistor, reduce the fluctuation of the resistance value, and apply it to the inner layer of the multilayer substrate. The purpose is to make it possible.

本発明の請求項1に係る発明は、ベースの基板上に、抵抗体と一対の素子電極が接触抵抗軽減のための第2電極を介して接続された抵抗素子を有する配線基板であって、
基板上に設けられた素子電極と、該素子電極上に設けられた第2電極と、
前記基板の全面に積層され、前記素子電極及び第2電極が、該第2電極の上面を露出した状態で埋め込まれている絶縁層と、
前記第2電極間に設けられた抵抗体と、
を具備し、前記絶縁層及び絶縁層上面に露出した第2電極上面は平坦であることを特徴とする抵抗素子付き配線基板である。
The invention according to claim 1 of the present invention is a wiring board having a resistance element in which a resistor and a pair of element electrodes are connected via a second electrode for reducing contact resistance on a base substrate,
An element electrode provided on the substrate; a second electrode provided on the element electrode;
An insulating layer laminated on the entire surface of the substrate, wherein the element electrode and the second electrode are embedded with the upper surface of the second electrode exposed;
A resistor provided between the second electrodes;
And the upper surface of the insulating layer and the second electrode exposed on the upper surface of the insulating layer are flat.

本発明の請求項2に係る発明は、前記第2電極の厚みは、10μmから20μmの範囲であることを特徴とする請求項1記載の抵抗素子付き配線基板である。   The invention according to claim 2 of the present invention is the wiring board with a resistance element according to claim 1, wherein the thickness of the second electrode is in the range of 10 μm to 20 μm.

本発明の請求項3に係る発明は、前記絶縁層上に、さらに配線パターンが設けられていることを特徴とする請求項1、又は2記載の抵抗素子付き配線基板である。   The invention according to claim 3 of the present invention is the wiring board with a resistance element according to claim 1 or 2, wherein a wiring pattern is further provided on the insulating layer.

本発明の請求項4に係る発明は、抵抗体と素子電極が接触抵抗軽減のための第2電極を介して接続された抵抗素子を有する請求項1乃至3のいずれか1項記載の抵抗素子付き配線基板の製造方法において、(a)基板上に配線パターン及び素子電極を形成する工程と、
(b)前記素子電極上に第2電極を形成する工程と、(c)前記基板上の配線パターン、素子電極及び第2電極を絶縁樹脂で覆い、絶縁層を形成する工程と、(d)前記絶縁層表面を前記第2電極表面が露出するまで研磨する工程と、(e)前記絶縁層上に露出した第2電極間に抵抗体を形成する工程とを少なくとも含むことを特徴とした抵抗素子付き配線基板の製造方法である。
The invention according to claim 4 of the present invention is the resistance element according to any one of claims 1 to 3, further comprising a resistance element in which the resistor and the element electrode are connected via a second electrode for reducing contact resistance. In the method for manufacturing a wiring board with a substrate, (a) a step of forming a wiring pattern and an element electrode on the substrate;
(B) forming a second electrode on the element electrode; (c) covering the wiring pattern, the element electrode and the second electrode on the substrate with an insulating resin to form an insulating layer; and (d). A resistance comprising at least a step of polishing the surface of the insulating layer until the surface of the second electrode is exposed, and (e) a step of forming a resistor between the second electrodes exposed on the insulating layer. It is a manufacturing method of a wiring board with an element.

本発明の請求項5に係る発明は、さらに前記絶縁層上に、第2の配線パターンを設ける工程を含むことを特徴とする請求項4記載の抵抗素子付き配線基板の製造方法である。   The invention according to claim 5 of the present invention is the method of manufacturing a wiring board with a resistance element according to claim 4, further comprising a step of providing a second wiring pattern on the insulating layer.

本発明の請求項6に係る発明は、前記第2電極は、導電性ペーストをスクリーン印刷することによって形成することを特徴とする請求項4、又は5記載の抵抗素子付き配線基板の製造方法である。   The invention according to claim 6 of the present invention is the method for manufacturing a wiring board with a resistance element according to claim 4 or 5, wherein the second electrode is formed by screen printing a conductive paste. is there.

本発明の請求項7に係る発明は、前記抵抗体は、樹脂バインダー中に導電性フィラーを分散させた抵抗ペーストをスクリーン印刷することによって形成することを特徴とする請求項4乃至6のいずれか1項記載の抵抗素子付き配線基板の製造方法である。   The invention according to claim 7 of the present invention is characterized in that the resistor is formed by screen printing a resistor paste in which a conductive filler is dispersed in a resin binder. It is a manufacturing method of the wiring board with a resistance element of 1 item | term.

本発明によれば、ポリマーのペースト材料による第2電極および印刷抵抗体を形成する際、抵抗体形成部位が平坦であるため、電極との段差による印刷ダレを防止し良好な形状で形成することができる。さらに抵抗体は銀電極を介して素子電極と接続されるため、抵抗値の変動を抑えたより信頼性の高いポリマー抵抗素子を形成することが可能となり、抵抗素子付き配線基板を内層に適用できる。   According to the present invention, when the second electrode and the printed resistor are formed of the polymer paste material, the resistor forming portion is flat, so that the printing sagging due to a step with the electrode is prevented and the printed resistor is formed in a good shape. Can do. Furthermore, since the resistor is connected to the element electrode via the silver electrode, it is possible to form a more reliable polymer resistor element with suppressed fluctuations in resistance value, and the wiring board with the resistor element can be applied to the inner layer.

上記の製造方法により、微細な抵抗体形状を良好に形成することができ、素子形成時における精度を向上させることができる。また、抵抗素子が第2電極の銀電極を介して素子電極と接続される構造をとることにより、接触抵抗を小さくし抵抗値変動の低減化が可能となる。さらに上記の製造方法で製造した配線基板は、その後の表面処理、例えば黒化処理等を行うことができるため、多層基板の内層に適用することができる。   By the above manufacturing method, a fine resistor shape can be formed satisfactorily, and the accuracy at the time of element formation can be improved. Further, by adopting a structure in which the resistance element is connected to the element electrode via the silver electrode of the second electrode, it is possible to reduce the contact resistance and reduce the resistance value fluctuation. Furthermore, since the wiring board manufactured by the above manufacturing method can be subjected to subsequent surface treatment, such as blackening treatment, it can be applied to the inner layer of the multilayer substrate.

本発明の抵抗素子付き配線基板及びその製造方法を一実施形態に基づいて以下説明する。   A wiring board with a resistance element and a method for manufacturing the same according to the present invention will be described below based on an embodiment.

図1は、ベースの基板1上に一対の素子電極3と、第1の配線パターン2が形成され、一対の素子電極3上に導電性樹脂で形成した第2電極4を介して設けられた抵抗体7を形成する構造であって、前記ベースの基板1から素子電極3及び第2電極4までの全面に、第2電極4の上面を露出した状態まで絶縁樹脂5を形成し、露出した第2電極4の上面に抵抗体7が形成された抵抗素子付き配線基板である。第1の配線パターン2は、配線回路部及び外部との入出力する端子部の機能を備えている(図示せず)。   In FIG. 1, a pair of element electrodes 3 and a first wiring pattern 2 are formed on a base substrate 1 and are provided on a pair of element electrodes 3 via a second electrode 4 formed of a conductive resin. In the structure for forming the resistor 7, the insulating resin 5 is formed on the entire surface from the base substrate 1 to the device electrode 3 and the second electrode 4 until the upper surface of the second electrode 4 is exposed and exposed. This is a wiring board with a resistance element in which a resistor 7 is formed on the upper surface of the second electrode 4. The first wiring pattern 2 has a function of a wiring circuit portion and a terminal portion that inputs and outputs to the outside (not shown).

図1に示す本発明の抵抗素子付き配線基板の製造方法を説明する。ベースの基板上に設けられた任意の素子電極3上に、導電性ペースト等の導電性樹脂により第2電極4を印刷形成する工程と、ベースの基板及び素子電極及び第2電極の上面、すなわち、配線板表面を絶縁樹脂5にて覆う工程と、絶縁樹脂5の表面を、物理的研磨あるいは化学的処理により第2電極4が露出するまで削り、平坦化させる工程と、抵抗体形成部分に抵抗ペースト等の抵抗体樹脂7を印刷する工程と、により製造する抵抗素子付き配線基板の製造方法である。なお、本発明の製造方法は、抵抗体形成前に、絶縁樹脂上面と第2電極の上面とが同一面で平坦化され、その平坦面に抵抗体を形成することが特徴である。   The manufacturing method of the wiring board with a resistance element of the present invention shown in FIG. 1 will be described. A step of printing and forming the second electrode 4 on an arbitrary element electrode 3 provided on the base substrate with a conductive resin such as a conductive paste; and the upper surfaces of the base substrate, the element electrode, and the second electrode, A step of covering the surface of the wiring board with the insulating resin 5, a step of scraping and planarizing the surface of the insulating resin 5 by physical polishing or chemical treatment until the second electrode 4 is exposed, and a resistor forming portion. And a step of printing a resistor resin 7 such as a resistance paste, and a method of manufacturing a wiring board with a resistance element manufactured by the method. The manufacturing method of the present invention is characterized in that before the resistor is formed, the upper surface of the insulating resin and the upper surface of the second electrode are flattened on the same surface, and the resistor is formed on the flat surface.

図2は、ベースの基板1上に一対の素子電極3と、第1の配線パターン2が形成され、一対の素子電極3上に導電性樹脂で形成した第2電極4を介して設けられた抵抗体7を形成する構造であって、前記ベースの基板1から素子電極3及び第1の配線パターン2及び第2電極4までの全面に、第2電極4の上面を露出した状態まで絶縁樹脂5を形成し、露出した第2電極4の上面に抵抗体7が形成され、絶縁樹脂5の上面に第2配線パターン6とを形成した抵抗素子付き配線基板である。第1及び第2の配線パターン2、6は、配線回路部の機能を備え、第1の配線パターンと第2の配線パターン6とは絶縁樹脂に形成した導通孔(ビアホール内をビアめっきした)を介して配線回路を形成している(図示せず)。   In FIG. 2, a pair of element electrodes 3 and a first wiring pattern 2 are formed on a base substrate 1 and are provided on a pair of element electrodes 3 via a second electrode 4 formed of a conductive resin. In the structure for forming the resistor 7, the insulating resin is used until the upper surface of the second electrode 4 is exposed on the entire surface from the base substrate 1 to the device electrode 3, the first wiring pattern 2, and the second electrode 4. 5, a resistor 7 is formed on the exposed upper surface of the second electrode 4, and a second wiring pattern 6 is formed on the upper surface of the insulating resin 5. The first and second wiring patterns 2 and 6 have a function of a wiring circuit unit, and the first wiring pattern and the second wiring pattern 6 are conductive holes formed in an insulating resin (via holes are plated in via holes). A wiring circuit is formed via (not shown).

図2に示す抵抗素子付き配線基板の製造方法を説明する。ベースの基板上に設けられた任意の素子電極3上に、導電性ペースト等の導電性樹脂により第2電極4を印刷形成する工程と、ベースの基板及び素子電極及び第2電極の上面、すなわち、配線板表面を絶縁樹脂5にて覆う工程と、絶縁樹脂5の表面を、物理的研磨あるいは化学的処理により第2電極4の上面が露出するまで削り、平坦化させる工程と、抵抗体形成部分に抵抗ペースト等の抵抗体樹脂を印刷する抵抗体7の形成工程と、により製造する抵抗素子付き配線基板の製造方法である。図2の抵抗素子付き配線基板では、絶縁樹脂5の上面に第2配線パターン6を形成し、第1の配線パターンと第2の配線パターン6とは絶縁樹脂に形成したビアめっきの導通孔を介して配線回路が形成され、該形成では公知の製造方法を用いているため説明は省略する。従って、図2に示す抵抗素子付き配線基板の製造方法は、多層基板の内層に適用することができる。なお、本発明の製造方法は、抵抗体形成前に、絶縁樹脂上面と第2電極の上面とが同一面で平坦化され、その平坦面に抵抗体を形成することが特徴である。   A method for manufacturing the wiring board with a resistance element shown in FIG. 2 will be described. A step of printing and forming the second electrode 4 on an arbitrary element electrode 3 provided on the base substrate with a conductive resin such as a conductive paste; and the upper surfaces of the base substrate, the element electrode, and the second electrode, A step of covering the surface of the wiring board with the insulating resin 5, a step of scraping and flattening the surface of the insulating resin 5 by physical polishing or chemical treatment until the upper surface of the second electrode 4 is exposed, and resistor formation A method for manufacturing a wiring board with a resistance element manufactured by forming a resistor 7 by printing a resistor resin such as a resistance paste on a portion thereof. 2, the second wiring pattern 6 is formed on the upper surface of the insulating resin 5, and the first wiring pattern and the second wiring pattern 6 have via plating conduction holes formed in the insulating resin. A wiring circuit is formed through this, and since a known manufacturing method is used in the formation, description thereof is omitted. Therefore, the manufacturing method of the wiring board with a resistance element shown in FIG. 2 can be applied to the inner layer of the multilayer board. The manufacturing method of the present invention is characterized in that before the resistor is formed, the upper surface of the insulating resin and the upper surface of the second electrode are flattened on the same surface, and the resistor is formed on the flat surface.

本発明で述べる導電性樹脂とは、樹脂をベースに導電フィラーを配合したペースト状の導電性樹脂である。用いられる樹脂は、フェノール、エポキシ、ウレタン、アクリルなどで、導電フィラーには、金、銀、ニッケル、カーボンなどが用いられる。その作業性から、熱硬化型導電性樹脂で硬化剤が添加された一液型のものが使用しやすい。ここで用いる導電性樹脂としては、抵抗体と銅箔電極間に介在させることで接触抵抗を小さくし抵抗値
安定性を得ることを目的としたペースト材料で、例えばフィラーに銀粒子を用いて樹脂バインダー中に分散させた銀ペーストで10-5Ω・cm程度の電気特性を有する材料である。具体的には、アサヒ化学研究所製のポリマー型銀ペースト LS−504J等が挙げられる。
The conductive resin described in the present invention is a paste-like conductive resin in which a conductive filler is blended based on a resin. The resin used is phenol, epoxy, urethane, acrylic or the like, and gold, silver, nickel, carbon or the like is used for the conductive filler. Due to its workability, a one-pack type thermosetting conductive resin to which a curing agent is added is easy to use. The conductive resin used here is a paste material intended to reduce contact resistance and obtain resistance value stability by interposing between a resistor and a copper foil electrode. For example, a resin using silver particles as a filler A silver paste dispersed in a binder is a material having electrical properties of about 10 −5 Ω · cm. Specific examples include polymer type silver paste LS-504J manufactured by Asahi Chemical Research Laboratory.

本発明で述べる抵抗体材料とは、カーボン粒子を主な導電性フィラーとし、フェノール樹脂、エポキシ樹脂、キシレン樹脂、ポリイミド樹脂、ジアリルフタレート樹脂などのバインダー中に分散させた材料である。具体的には、アサヒ化学研究所製のカーボン抵抗ペースト TU−500−8などが挙げられる。   The resistor material described in the present invention is a material in which carbon particles are used as a main conductive filler and dispersed in a binder such as a phenol resin, an epoxy resin, a xylene resin, a polyimide resin, or a diallyl phthalate resin. Specific examples include carbon resistance paste TU-500-8 manufactured by Asahi Chemical Research Laboratory.

より具体的には、前記記載の抵抗素子付き配線基板の製造方法を図3(a)〜(e)及び図4(g)〜(k)を用いて説明する。図3(a)〜(f)及び図4(g)〜(k)は、抵抗素子付き配線基板の製造工程を示す製造工程図である。   More specifically, the manufacturing method of the wiring board with a resistance element described above will be described with reference to FIGS. 3 (a) to 3 (e) and FIGS. 4 (g) to 4 (k). 3 (a) to 3 (f) and FIGS. 4 (g) to (k) are manufacturing process diagrams showing a manufacturing process of a wiring board with a resistance element.

まず、図3(a)に示すように、ベースの基板1上の銅箔をフォトプロセス法のパターニングをし、第1の配線パターン2及び一対の素子電極3を有した配線基板を作製する。次に、図3(b)に示すように、任意の素子電極3上に導電性樹脂をスクリーン印刷し、第2電極4を形成する。導電性樹脂として、例えばフィラーに銀粒子を用いて樹脂バインダー中に分散させた銀ペーストがある。次に図3(c)に示すように、第2電極4が形成された基板1の全面を絶縁樹脂5で覆う。次に、図3(d)に示すように、物理的研磨や化学的処理により絶縁樹脂5を削り、第2電極4上面を露出させた平坦化面を作製する。研磨の具体的な手法としては、ジャブロ工業製のセラミックバフ研磨(SPC#600)の後に不織布バフ研磨(JPバフサーフェスUF#800、ULF#1200)を組み合わせて用いることができる。次に、図3(e)に示すように、抵抗体形成部位を除く前記平坦化絶縁樹脂5上に、通常のビルドアッププロセスに用いられるアディティブ法により第2の配線パターン6を形成する。次に、図3(f)に示すように、抵抗体形成部位に抵抗ペーストをスクリーン印刷し抵抗体7を形成し、抵抗素子付き配線基板8を作製する。なお、前記第2の配線パターン6を形成しない場合もある。   First, as shown in FIG. 3A, the copper foil on the base substrate 1 is patterned by a photo process method, and a wiring substrate having the first wiring pattern 2 and the pair of element electrodes 3 is manufactured. Next, as shown in FIG. 3B, a conductive resin is screen-printed on an arbitrary element electrode 3 to form the second electrode 4. As the conductive resin, for example, there is a silver paste dispersed in a resin binder using silver particles as a filler. Next, as shown in FIG. 3C, the entire surface of the substrate 1 on which the second electrode 4 is formed is covered with an insulating resin 5. Next, as shown in FIG. 3D, the insulating resin 5 is shaved by physical polishing or chemical treatment to produce a planarized surface with the upper surface of the second electrode 4 exposed. As a specific method of polishing, ceramic buffing (SPC # 600) manufactured by Jaburo Industry, followed by non-woven fabric buffing (JP buffing surface UF # 800, ULF # 1200) can be used. Next, as shown in FIG. 3E, the second wiring pattern 6 is formed on the planarizing insulating resin 5 excluding the resistor forming portion by an additive method used in a normal build-up process. Next, as shown in FIG. 3F, a resistor paste is screen-printed on the resistor forming portion to form the resistor 7, and the wiring substrate 8 with a resistor element is manufactured. In some cases, the second wiring pattern 6 is not formed.

また、抵抗素子付き配線基板8を基板の内層に挿入した部品内蔵基板に適用するには、更に以下の図4(g)〜(k)の工程を実施する。図4(g)に示すように、抵抗素子付き配線基板8に表面粗化工程を施す。このような表面粗化処理を施すのは、銅からなる第2配線パターン6と積層する絶縁樹脂との密着力を強くするためである。ここで用いる表面処理工程として、抵抗素子がこの表面処理工程に対して耐性があればどのような工程でも良く、例えばメック社のCZ処理等が挙げられる。この表面粗化処理工程の後に、図4(h)に示すように樹脂付き銅箔10を真空プレスにより積層する。ここで用いる樹脂付き銅箔10として具体的には、三井金属鉱業株式会社製 MR−700や松下電工株式会社製 R−0880などが挙げられる。続いて図4(i)に示すようにUV−YAGレーザーにより所定のビアホール12を形成した後、アルカリ性過マンガン酸塩によるデスミア処理を行う。この後、図4(j)に示すように無電解銅めっきプロセスおよび電解銅めっきプロセスによりビアめっき13を行い、層間の導通をとる。この後、図4(k)に示すようにサブトラクティブ法により第3の配線パターン14を作製する。このようにして抵抗素子付き配線基板上に1層の導体層が完成する。更に樹脂付き銅箔の積層以降のプロセスを繰り返すことで所望のビルドアップ層を形成する。これにより基板内に抵抗素子付き配線基板を内層させ、部品内蔵基板を作製する。   Further, in order to apply to the component built-in board in which the wiring board 8 with the resistance element is inserted in the inner layer of the board, the following steps shown in FIGS. 4G to 4K are further performed. As shown in FIG. 4G, a surface roughening step is performed on the wiring board 8 with a resistance element. The surface roughening treatment is performed in order to strengthen the adhesion between the second wiring pattern 6 made of copper and the insulating resin to be laminated. The surface treatment step used here may be any step as long as the resistance element is resistant to the surface treatment step, and examples thereof include CZ treatment of MEC. After this surface roughening treatment step, the resin-coated copper foil 10 is laminated by vacuum pressing as shown in FIG. Specific examples of the copper foil 10 with resin used here include MR-700 manufactured by Mitsui Mining & Smelting Co., Ltd. and R-0880 manufactured by Matsushita Electric Works, Ltd. Subsequently, as shown in FIG. 4 (i), after a predetermined via hole 12 is formed by a UV-YAG laser, desmear treatment with an alkaline permanganate is performed. Thereafter, via plating 13 is performed by an electroless copper plating process and an electrolytic copper plating process as shown in FIG. Thereafter, as shown in FIG. 4 (k), a third wiring pattern 14 is produced by a subtractive method. In this way, one conductor layer is completed on the wiring board with a resistance element. Furthermore, a desired buildup layer is formed by repeating the processes after the lamination of the copper foil with resin. As a result, a wiring board with a resistance element is formed in the board to produce a component built-in board.

以下、この発明の具体的な実施例について、図3(a)〜(e)及び図4(g)〜(k)を参照して説明する。   Specific embodiments of the present invention will be described below with reference to FIGS. 3 (a) to 3 (e) and FIGS. 4 (g) to 4 (k).

ベース基板1の材料として三菱ガス化学株式会社製のBT銅張積層板CCL−HL−830を用い、まず図3(a)に示すように、銅箔をサブトラクティブ法によりパターンニングした。   As a material for the base substrate 1, BT copper-clad laminate CCL-HL-830 manufactured by Mitsubishi Gas Chemical Co., Ltd. was used. First, as shown in FIG. 3A, the copper foil was patterned by a subtractive method.

次に、図3(b)に示すように、任意の素子電極3上に導電性樹脂をスクリーン印刷し150℃で熱硬化させ、第2電極4を形成した。第2電極用材料としてアサヒ化学研究所製のポリマー型銀ペースト LS−504Jを用いた。   Next, as shown in FIG. 3 (b), a conductive resin was screen printed on an arbitrary element electrode 3 and thermally cured at 150 ° C. to form a second electrode 4. As the second electrode material, polymer type silver paste LS-504J manufactured by Asahi Chemical Laboratory was used.

次に図3(c)に示すように第2電極4の銀電極を形成した基板1上全面を絶縁樹脂5で覆った。ここで使用した絶縁材料は、味の素社製ABF‐GXや住友化学社製エスフレックスである。   Next, as shown in FIG. 3C, the entire surface of the substrate 1 on which the silver electrode of the second electrode 4 was formed was covered with an insulating resin 5. The insulating material used here is ABF-GX manufactured by Ajinomoto Co. or S-flex manufactured by Sumitomo Chemical.

次に図3(d)に示すように、バフ研磨により前工程で設けた絶縁樹脂を研磨し、第2電極を露出させた平坦化面を作製した。ここで、まず第1軸にジャブロ工業製セラミックバフSPC#600を使用し、銀電極上の絶縁樹脂厚分を研磨すると共に表面段差を均一にした。第2軸にはジャブロ工業製不織布バフであるJPバフサーフェスUF#800、および第3軸にULF#1200を使用し仕上げ研磨を行った。   Next, as shown in FIG. 3D, the insulating resin provided in the previous step was polished by buffing to produce a planarized surface exposing the second electrode. Here, first, a ceramic buff SPC # 600 manufactured by Jablo Industries was used for the first axis, and the thickness of the insulating resin on the silver electrode was polished and the surface step was made uniform. Finish polishing was performed using JP buff surface UF # 800, which is a non-woven buff made by Jablo Industry, on the second axis, and ULF # 1200 on the third axis.

次に図3(e)に示すように、抵抗体形成部位を除く絶縁樹脂5の平坦化面上に、通常のビルドアッププロセスに用いられるアディティブ法により第2の配線パターン6の銅箔を形成した。   Next, as shown in FIG. 3E, the copper foil of the second wiring pattern 6 is formed on the planarized surface of the insulating resin 5 excluding the resistor forming portion by an additive method used in a normal build-up process. did.

次に図3(f)に示すように、抵抗体形成部位に抵抗ペーストをスクリーン印刷し抵抗体7を形成し、抵抗素子付き配線基板を作製した。抵抗ペーストとして、アサヒ化学研究所製のカーボン抵抗ペースト TU−500−8を用い200℃で熱硬化させ、抵抗体7を作製した。この結果、抵抗体7が形成時の印刷ダレを抑制でき、素子形成時の精度を向上させることができた。   Next, as shown in FIG. 3 (f), a resistor paste was screen-printed on the resistor forming portion to form the resistor 7, and a wiring board with a resistor element was manufactured. As a resistance paste, a carbon resistance paste TU-500-8 manufactured by Asahi Chemical Research Laboratories was used for thermosetting at 200 ° C. to prepare a resistor 7. As a result, it was possible to suppress the printing sagging when the resistor 7 was formed, and to improve the accuracy when the element was formed.

また、抵抗素子付き配線基板を基板の内層に挿入した部品内蔵基板に適用するため、更に以下の図4(g)〜(k)の工程を実施した。図4(g)に示すように抵抗体7の形成後に表面粗化工程としてメック株式会社のCZ処理を施し、この表面粗化処理9の工程の後に、図4(h)に示すように三井金属鉱業株式会社製の樹脂付き銅箔10のMR−700(Cu:12、Resin:50)を真空プレスにて圧力40kg/cm2、温度170℃で2時間加熱・加圧して積層した。 Further, in order to apply the wiring board with a resistance element to a component-embedded board inserted in the inner layer of the board, the following steps of FIGS. As shown in FIG. 4G, after the resistor 7 is formed, CZ treatment of MEC Co., Ltd. is applied as a surface roughening step, and after this surface roughening treatment 9 step, Mitsui as shown in FIG. MR-700 (Cu: 12, Resin: 50) of copper foil with resin 10 manufactured by Metal Mining Co., Ltd. was laminated by heating and pressurizing at a pressure of 40 kg / cm 2 and a temperature of 170 ° C. for 2 hours using a vacuum press.

続いて図4(i)に示すようにUV−YAGレーザーにより所定のビアホール12を形成した後、アルカリ性過マンガン酸塩によるデスミア処理を行った。   Subsequently, as shown in FIG. 4 (i), a predetermined via hole 12 was formed by a UV-YAG laser, and then desmear treatment with an alkaline permanganate was performed.

この後、図4(j)に示すようにローム・アンド・ハース電子材料株式会社の無電解銅めっきプロセスで0.3μmめっきした後、電解銅めっきで10μm厚のビアめっき13を行い層間の導通をとった。   After that, as shown in FIG. 4 (j), 0.3 μm plating is performed by the electroless copper plating process of Rohm and Haas Electronic Materials Co., Ltd., and then via plating 13 having a thickness of 10 μm is performed by electrolytic copper plating, and conduction between layers is performed. I took.

この後、図4(k)に示すようにサブトラクティブ法により第3配線パターン14を作製した。このように基板内に抵抗体素子を内層させ、部品内蔵基板を作製した。   Thereafter, as shown in FIG. 4 (k), a third wiring pattern 14 was produced by a subtractive method. In this way, the resistor element was placed in the substrate to produce a component built-in substrate.

本発明の抵抗素子付き配線基板の一事例の部分拡大側断面図である。It is a partial expanded side sectional view of an example of a wiring board with a resistance element of the present invention. 本発明の抵抗素子付き配線基板の一事例の部分拡大側断面図である。It is a partial expanded side sectional view of an example of a wiring board with a resistance element of the present invention. (a)〜(e)は、本発明に係る抵抗素子付き配線板の製造工程を示す側断面図である。(A)-(e) is a sectional side view which shows the manufacturing process of the wiring board with a resistive element which concerns on this invention. (g)〜(k)は、本発明に係る抵抗素子付き配線板の製造工程を示す側断面図である。(G)-(k) is a sectional side view which shows the manufacturing process of the wiring board with a resistive element which concerns on this invention.

符号の説明Explanation of symbols

1…(ベースの)基板
2…第1の配線パターン
3…素子電極
4…第2電極(銀電極)
5…絶縁樹脂
6…第2の配線パターン
7…抵抗体
8…抵抗素子付き配線基板
9…表面粗化処理
10…樹脂付き銅箔
11…UV−YAGレーザー
12…ビアホール
13…ビアめっき
14…第3の配線パターン
DESCRIPTION OF SYMBOLS 1 ... (Base) board | substrate 2 ... 1st wiring pattern 3 ... Element electrode 4 ... 2nd electrode (silver electrode)
DESCRIPTION OF SYMBOLS 5 ... Insulating resin 6 ... 2nd wiring pattern 7 ... Resistance body 8 ... Wiring board 9 with a resistance element ... Surface roughening process 10 ... Copper foil 11 with resin 11 ... UV-YAG laser 12 ... Via hole 13 ... Via plating 14 ... First 3 wiring pattern

Claims (7)

ベースの基板上に、抵抗体と一対の素子電極が接触抵抗軽減のための第2電極を介して接続された抵抗素子を有する配線基板であって、
基板上に設けられた素子電極と、該素子電極上に設けられた第2電極と、
前記基板の全面に積層され、前記素子電極及び第2電極が、該第2電極の上面を露出した状態で埋め込まれている絶縁層と、
前記第2電極間に設けられた抵抗体と、
を具備し、前記絶縁層及び絶縁層上面に露出した第2電極上面は平坦であることを特徴とする抵抗素子付き配線基板。
A wiring board having a resistance element in which a resistor and a pair of element electrodes are connected via a second electrode for reducing contact resistance on a base substrate,
An element electrode provided on the substrate; a second electrode provided on the element electrode;
An insulating layer laminated on the entire surface of the substrate, wherein the element electrode and the second electrode are embedded with the upper surface of the second electrode exposed;
A resistor provided between the second electrodes;
And the upper surface of the insulating layer and the second electrode exposed on the upper surface of the insulating layer are flat.
前記第2電極の厚みは、10μmから20μmの範囲であることを特徴とする請求項1記載の抵抗素子付き配線基板。   The wiring board with a resistance element according to claim 1, wherein the thickness of the second electrode is in the range of 10 μm to 20 μm. 前記絶縁層上に、さらに配線パターンが設けられていることを特徴とする請求項1、又は2記載の抵抗素子付き配線基板。   The wiring board with a resistance element according to claim 1, wherein a wiring pattern is further provided on the insulating layer. 抵抗体と素子電極が接触抵抗軽減のための第2電極を介して接続された抵抗素子を有する請求項1乃至3のいずれか1項記載の抵抗素子付き配線基板の製造方法において、
(a)基板上に配線パターン及び素子電極を形成する工程と、
(b)前記素子電極上に第2電極を形成する工程と、
(c)前記基板上の配線パターン、素子電極及び第2電極を絶縁樹脂で覆い、絶縁層を形成する工程と、
(d)前記絶縁層表面を前記第2電極表面が露出するまで研磨する工程と、
(e)前記絶縁層上に露出した第2電極間に抵抗体を形成する工程と、
を少なくとも含むことを特徴とした抵抗素子付き配線基板の製造方法。
4. The method of manufacturing a wiring board with a resistance element according to claim 1, further comprising a resistance element in which the resistor and the element electrode are connected via a second electrode for reducing contact resistance. 5.
(A) forming a wiring pattern and device electrodes on the substrate;
(B) forming a second electrode on the device electrode;
(C) covering the wiring pattern, the element electrode and the second electrode on the substrate with an insulating resin to form an insulating layer;
(D) polishing the surface of the insulating layer until the surface of the second electrode is exposed;
(E) forming a resistor between the second electrodes exposed on the insulating layer;
A method of manufacturing a wiring board with a resistance element, comprising:
さらに前記絶縁層上に、第2の配線パターンを設ける工程を含むことを特徴とする請求項4記載の抵抗素子付き配線基板の製造方法。   5. The method of manufacturing a wiring board with a resistance element according to claim 4, further comprising a step of providing a second wiring pattern on the insulating layer. 前記第2電極は、導電性ペーストをスクリーン印刷することによって形成することを特徴とする請求項4、又は5記載の抵抗素子付き配線基板の製造方法。   6. The method of manufacturing a wiring board with a resistance element according to claim 4, wherein the second electrode is formed by screen printing a conductive paste. 前記抵抗体は、樹脂バインダー中に導電性フィラーを分散させた抵抗ペーストをスクリーン印刷することによって形成することを特徴とする請求項4乃至6のいずれか1項記載の抵抗素子付き配線基板の製造方法。   The said resistor is formed by screen-printing the resistance paste which disperse | distributed the conductive filler in the resin binder, The manufacturing of the wiring board with a resistive element of any one of Claim 4 thru | or 6 characterized by the above-mentioned. Method.
JP2004343638A 2004-11-29 2004-11-29 Wiring board with resistive element, and its manufacturing method Pending JP2006156631A (en)

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