JP2006148031A - High-frequency plastic package and its manufacturing method - Google Patents
High-frequency plastic package and its manufacturing method Download PDFInfo
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- JP2006148031A JP2006148031A JP2004339751A JP2004339751A JP2006148031A JP 2006148031 A JP2006148031 A JP 2006148031A JP 2004339751 A JP2004339751 A JP 2004339751A JP 2004339751 A JP2004339751 A JP 2004339751A JP 2006148031 A JP2006148031 A JP 2006148031A
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- copper foil
- core substrate
- conductor wiring
- insulating layer
- plastic package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Abstract
Description
本発明は、半導体素子を搭載するためのパッケージに係り、特に非貫通孔を介して層間の導通を取りながら絶縁層及び導体配線パターンを順次積層した多層プリント配線板を備えた高周波用プラスチックパッケージとその製造方法に関する。 The present invention relates to a package for mounting a semiconductor element, and more particularly, to a high-frequency plastic package including a multilayer printed wiring board in which an insulating layer and a conductive wiring pattern are sequentially stacked while maintaining conduction between layers through a non-through hole. It relates to the manufacturing method.
マイクロ波回路などを構成する半導体素子を搭載するための高周波用パッケージの分野では、高周波領域での損失が少なく、耐熱性や機械的強度などに優れるセラミック材料が従来用いられてきた。しかし、パッケージの小型化に伴い、収縮率が大きく、寸法精度の確保が困難なセラミック製のパッケージに代わって、近年、プラスチックパッケージが注目され始めている。 In the field of high-frequency packages for mounting semiconductor elements constituting microwave circuits and the like, ceramic materials that have little loss in the high-frequency region and are excellent in heat resistance, mechanical strength, and the like have been used. However, with the downsizing of packages, plastic packages have begun to attract attention in recent years in place of ceramic packages that have a large shrinkage rate and it is difficult to ensure dimensional accuracy.
高周波用パッケージには、高密度・微細配線を可能とするため、メッキ又はプリントなどによって順次絶縁層と導体配線パターンを積み上げていく製法(以下、ビルドアップ法という。)により形成される多層プリント配線板が用いられることが多い。このような多層プリント配線板では、層間の導通を取るために内壁面に導電被膜が形成された貫通孔が設けられるが、すべての導体配線パターンの同一箇所に開口部が形成されるため、配線設計上の制約を受けるという課題があった。また、貫通孔の内部に充填される樹脂成分が半導体素子実装面の開口部周辺に残存した場合には、伝送特性が低下するという課題があった。 In order to enable high-density and fine wiring in high-frequency packages, multilayer printed wiring formed by a manufacturing method (hereinafter referred to as build-up method) in which an insulating layer and a conductive wiring pattern are sequentially stacked by plating or printing. A board is often used. In such a multilayer printed wiring board, a through-hole with a conductive film formed on the inner wall surface is provided in order to establish conduction between the layers, but an opening is formed at the same location in all the conductor wiring patterns. There was a problem of receiving design constraints. Further, when the resin component filled in the through hole remains in the vicinity of the opening on the semiconductor element mounting surface, there is a problem that transmission characteristics are deteriorated.
このような課題に対処するため、いくつかの発明及び考案が開示されている。例えば特許文献1には、「多層配線基板およびその製造方法」という名称で、高周波特性等の電気特性に優れ、微細化、狭ピッチ化されたビルドアップ多層配線層を形成した多層配線基板およびその製造方法に関する発明が開示されている。 In order to cope with such a problem, several inventions and devices have been disclosed. For example, Patent Document 1 discloses a multilayer wiring board having a build-up multilayer wiring layer having excellent electrical characteristics such as high-frequency characteristics and the like, and having a finer and narrower pitch, and the name “multilayer wiring board and manufacturing method thereof” An invention relating to a manufacturing method is disclosed.
以下、図3を参照しながら、特許文献1に開示された発明について説明する。図3は従来技術に係る多層配線基板の部分縦断面図である。図3に示すように、従来技術に係る発明は、配線層(55a,55b,55c)を有し、3層よりなるコア基板52(52a,52b,52c)と、このコア基板52の片面に絶縁層(59a,59b)及び配線層(58a,58b)からなるビルドアップ配線層53(53a,53b)を形成した多層配線基板51において、コア基板52は導電材料により表裏の導通がなされた複数の導通部54(54a,54b,54c)を備え、ビルドアップ配線層53を構成する配線層(58a,58b)はビア(57a,57b)によりコア基板52の表面上に形成された表層パターン56と電気的に接続されるとともに、コア基板52のXY方向の熱膨張係数が2〜20ppmであり、コア基板52用のコア材52’がシリコン、セラミックス、ガラス、ガラス・エポキシ複合材料から選ばれ、ビルドアップ配線層53の絶縁層59a,59bが250℃以下の温度で熱硬化可能な感光性樹脂であることを特徴とするものである。
このような構造によれば、多層配線のビアをスタック構造とすることができるため、高密度配線が可能となる。
Hereinafter, the invention disclosed in Patent Document 1 will be described with reference to FIG. FIG. 3 is a partial longitudinal sectional view of a multilayer wiring board according to the prior art. As shown in FIG. 3, the prior art invention has a wiring layer (55a, 55b, 55c), a three-layer core substrate 52 (52a, 52b, 52c), and one surface of the core substrate 52. In the multilayer wiring substrate 51 in which the build-up wiring layer 53 (53a, 53b) including the insulating layers (59a, 59b) and the wiring layers (58a, 58b) is formed, the core substrate 52 has a plurality of conductive surfaces that are electrically connected to each other. The conductive layer 54 (54a, 54b, 54c) of the wiring layer (58a, 58b) constituting the build-up wiring layer 53 is formed on the surface of the core substrate 52 by vias (57a, 57b). And the thermal expansion coefficient in the XY direction of the core substrate 52 is 2 to 20 ppm, and the core material 52 ′ for the core substrate 52 is made of silicon, ceramics, The insulating layers 59a and 59b of the build-up wiring layer 53 are selected from glass and glass / epoxy composite materials, and are characterized by being a photosensitive resin that can be thermoset at a temperature of 250 ° C. or lower.
According to such a structure, the vias of the multilayer wiring can be made into a stack structure, so that high-density wiring is possible.
また、特許文献2には「多層配線基板の製造方法」という名称で、複数の配線層を基材上に絶縁層を介して順次積層するビルドアップ方式により内部回路が高密度に構成されるとともに高周波特性や耐圧性に優れる多層配線基板の製造方法に関する発明が開示されている。
特許文献2に開示された発明は、基材に穿設された貫通孔や絶縁層に形成された開口部等を介して異なる配線層を導電接続した構造を形成した後に、開口部の内部に絶縁材を充填し、研磨により基材表面を平坦化することを特徴とするものである。
このような方法によれば、導体量を増加させずに確実な導電接続を行うことができるとともに、配線層間の静電容量を低減し、絶縁抵抗を高めることができるので、基板の高周波特性及び絶縁耐圧の向上を図ることができる。また、上層の絶縁層及び配線層を平坦面状に形成できるため、基板の断面構造を整合させ、配線欠陥等を防止することができる。
Further, Patent Document 2 has a name “manufacturing method of multilayer wiring board”, and the internal circuit is configured with high density by a build-up method in which a plurality of wiring layers are sequentially laminated on a base material via an insulating layer. An invention relating to a method for manufacturing a multilayer wiring board having excellent high-frequency characteristics and pressure resistance is disclosed.
In the invention disclosed in Patent Document 2, after forming a structure in which different wiring layers are conductively connected through a through-hole formed in a base material or an opening formed in an insulating layer, the inside of the opening is formed. The substrate is filled with an insulating material, and the surface of the substrate is flattened by polishing.
According to such a method, it is possible to perform a reliable conductive connection without increasing the amount of conductors, reduce the capacitance between the wiring layers, and increase the insulation resistance. The withstand voltage can be improved. In addition, since the upper insulating layer and the wiring layer can be formed in a flat surface shape, the cross-sectional structure of the substrate can be matched and wiring defects and the like can be prevented.
さらに、特許文献3には「プラスチックパッケージの製造方法」という名称で、コア基板の一面側に穴を有するブラインドビアの内部に気泡が残らないようにソルダーレジストを充填するプラスチックパッケージの製造方法に関する発明が開示されている。
特許文献3に開示された発明は、絶縁性基材の両面に導体回路となる銅箔を貼ったコア基板の一方側の面から穿設されたビアホールの他方側の面を銅箔で閉塞して形成するブラインドビアの開口側に感光性の第1のソルダーレジストを印刷する第1の工程と、第1のソルダーレジストで封じ込められたブラインドビア内の気泡を真空脱泡する第2の工程と、コア基板の両面に感光性の第2のソルダーレジストを印刷し、フォトリソグラフィ法で両面に開口部を備えるソルダーレジスト膜を形成する第3の工程とを有するものである。
このような方法によれば、ブラインドビア内に気泡が残り、水分が溜まって半田ボール接続やボードへの装着時の加熱によって急激に気泡が膨張しプラスチックパッケージを水蒸気爆発で破壊する、いわゆるポップコーン現象を回避することができる。
In the invention disclosed in Patent Document 3, the surface of the other side of the via hole drilled from the surface of one side of the core substrate in which the copper foil serving as the conductor circuit is pasted on both surfaces of the insulating base material is closed with the copper foil. A first step of printing a photosensitive first solder resist on the opening side of the blind via to be formed; and a second step of vacuum degassing bubbles in the blind via sealed with the first solder resist; And a third step of printing a photosensitive second solder resist on both surfaces of the core substrate and forming a solder resist film having openings on both surfaces by a photolithography method.
According to such a method, bubbles remain in the blind vias, and moisture accumulates, causing the bubbles to rapidly expand due to heating at the time of solder ball connection or board mounting, so-called popcorn phenomenon that destroys the plastic package by steam explosion. Can be avoided.
しかしながら、上述の従来技術である特許文献1に開示された発明においては、ソルダーレジストが半導体素子実装面の開口部周辺にも塗布されるため、高周波数信号の伝送特性が低下するという課題があった。 However, in the invention disclosed in Patent Document 1 which is the above-described prior art, since the solder resist is also applied to the periphery of the opening of the semiconductor element mounting surface, there is a problem that transmission characteristics of high frequency signals are deteriorated. It was.
また、特許文献2に開示された発明においては、開口部の内部に絶縁材を充填した後に基材表面を研磨して平坦化する必要があるため、工程数が増加し、製造コストがアップするという課題があった。さらに、平坦研磨した絶縁材上にメッキにより銅配線パターンをつけるため、層間接続信頼性が劣るという課題があった。また、平坦研磨時に生ずる大きな応力により、基板の伸びが発生し、基板寸法が変化するという課題もあった。 Moreover, in the invention disclosed in Patent Document 2, it is necessary to polish and flatten the surface of the base material after filling the opening with an insulating material, which increases the number of processes and increases the manufacturing cost. There was a problem. Furthermore, since a copper wiring pattern is formed by plating on a flat-polished insulating material, there is a problem that the interlayer connection reliability is inferior. Further, there is a problem that the substrate is stretched due to a large stress generated during the flat polishing, and the substrate dimensions are changed.
さらに、特許文献3に開示された発明においては、コア基板上に残存する樹脂成分により高周波信号の伝送特性が阻害されるという現象に対しては何ら有効な対策がとられていないという課題があった。 Furthermore, the invention disclosed in Patent Document 3 has a problem that no effective countermeasure is taken against the phenomenon that the high frequency signal transmission characteristic is hindered by the resin component remaining on the core substrate. It was.
本発明はかかる従来の事情に対処してなされたものであり、非貫通孔を有するビルドアップ多層プリント配線板を備え、高周波信号の伝送特性及び層間接続信頼性に優れる高周波用プラスチックパッケージとその製造方法を提供することを目的とする。 The present invention has been made in response to such a conventional situation, and includes a build-up multilayer printed wiring board having non-through holes, and has a high frequency signal transmission characteristic and interlayer connection reliability, and its manufacture. It aims to provide a method.
上記目的を達成するため、請求項1記載の発明である高周波用プラスチックパッケージは、絶縁性基材の両面に銅箔が貼り付けられたコア基板と、このコア基板の上面及び下面にそれぞれ形成された第1及び第2の導体配線パターンと、コア基板の下面に第2の導体配線パターンを介して積層されるとともに下面に銅箔が貼り付けられた絶縁層と、この絶縁層の下面の銅箔に形成された第3の導体配線パターンと、第3の導体配線パターンを被覆するソルダーレジストとを備え、コア基板は上部が銅箔により閉塞された複数の第1の非貫通孔を有するとともに上面に銅箔及び第1の導体配線パターンを介して半導体素子が実装され、絶縁層は上部が閉塞された複数の第2の非貫通孔を有し、第1及び第2の非貫通孔の内壁面に形成された導電被膜により第1乃至第3の導体配線パターンが電気的に接続されることを特徴とするものである。
上記構成の高周波用プラスチックパッケージにおいては、半導体素子実装面に非貫通孔の開口部が形成されないという作用を有する。また、内層の導体配線パターンに不要な貫通孔が形成されないという作用を有する。
In order to achieve the above object, a high-frequency plastic package according to the first aspect of the present invention is formed on a core substrate in which copper foil is attached to both surfaces of an insulating base, and on the upper surface and the lower surface of the core substrate, respectively. The first and second conductor wiring patterns, the insulating layer laminated on the lower surface of the core substrate via the second conductor wiring pattern and having the copper foil attached to the lower surface, and the copper on the lower surface of the insulating layer The core substrate includes a third conductor wiring pattern formed on the foil and a solder resist covering the third conductor wiring pattern, and the core substrate has a plurality of first non-through holes whose upper portions are closed by copper foil. A semiconductor element is mounted on the upper surface via a copper foil and a first conductor wiring pattern, and the insulating layer has a plurality of second non-through holes closed at the top, and the first and second non-through holes Conductivity formed on the inner wall The first to third conductive wiring pattern by film is characterized in that the electrically connected.
The high-frequency plastic package having the above-described structure has an effect that the opening of the non-through hole is not formed on the semiconductor element mounting surface. Moreover, it has the effect | action that an unnecessary through-hole is not formed in the conductor wiring pattern of an inner layer.
また、請求項2記載の発明は、請求項1記載の高周波用プラスチックパッケージにおいて、コア基板の下面に複数の絶縁層及び第3の導体配線パターンが順次積層され、複数の絶縁層は上部が閉塞された複数の第2の非貫通孔を有し、第1及び第2の非貫通孔の内壁面に形成された導電被膜により第1乃至第3の導体配線パターンが電気的に接続されることを特徴とするものである。
上記構成の高周波用プラスチックパッケージにおいては、請求項1記載の発明と同様の作用を有するとともに、より多層化されたプリント配線板が形成されるという作用を有する。
According to a second aspect of the present invention, in the high-frequency plastic package according to the first aspect, a plurality of insulating layers and a third conductor wiring pattern are sequentially laminated on the lower surface of the core substrate, and the plurality of insulating layers are closed at the top. The first to third conductor wiring patterns are electrically connected by the conductive film formed on the inner wall surfaces of the first and second non-through holes. It is characterized by.
The high-frequency plastic package having the above-described structure has the same effect as that of the first aspect of the invention, and has the effect that a multilayered printed wiring board is formed.
請求項3記載の発明は、請求項1又は請求項2に記載の高周波用プラスチックパッケージの製造方法において、絶縁性基材の両面に銅箔を貼り付けてコア基板を形成する工程と、このコア基板に上部が銅箔により閉塞された複数の第1の非貫通孔を穿設する工程と、コア基板の両面及び第1の非貫通孔の内壁面に導電被膜を形成する工程と、コア基板の上面及び下面の導電被膜上にそれぞれ第1及び第2の導体配線パターンを形成する工程と、コア基板の下面に第2の導体配線パターンを介して絶縁層と銅箔を積層する工程と、この絶縁層に銅箔を貫通するとともに上部が閉塞された複数の第2の非貫通孔を穿設する工程と、絶縁層下面の銅箔及び第2の非貫通孔の内壁面に導電被膜を形成する工程と、絶縁層下面の銅箔の導電被膜上に第3の導体配線パターンを形成する工程と、最下層の第3の導体配線パターンをソルダーレジストにより被覆する工程とを備えたことを特徴とするものである。
上記製造方法によれば、請求項1又は請求項2に記載の高周波用プラスチックパッケージが実現される。
According to a third aspect of the present invention, in the method for manufacturing a plastic package for high frequency according to the first or second aspect, a step of forming a core substrate by attaching a copper foil to both surfaces of an insulating base material, and the core Forming a plurality of first non-through holes whose upper portions are closed with copper foil on the substrate, forming a conductive film on both surfaces of the core substrate and the inner wall surface of the first non-through hole, and the core substrate Forming a first and second conductor wiring pattern on the upper and lower conductive films, respectively, and laminating an insulating layer and a copper foil on the lower surface of the core substrate via the second conductor wiring pattern; A step of drilling a plurality of second non-through holes that penetrate through the copper foil and whose upper portion is blocked in this insulating layer, and a conductive film on the inner wall surface of the copper foil and the second non-through hole on the lower surface of the insulating layer Forming a third step on the conductive film of the copper foil on the lower surface of the insulating layer; Forming a conductive wiring pattern, it is characterized in that a step of coating the solder resist third conductive wiring pattern of the bottom layer.
According to the manufacturing method, the high-frequency plastic package according to claim 1 or 2 is realized.
以上説明したように、本発明の請求項1に記載の高周波用プラスチックパッケージにおいては、銅箔により閉塞された第1の非貫通孔の上部にも半導体素子を実装することができるため、パッケージの小型化が可能となる。また、樹脂成分がコア基板の半導体素子実装面に残存しないため、高周波信号の伝送特性が阻害されることがない。さらに、層間接続の対象となっていない他の導体配線パターンに不要な貫通孔が形成されないため、配線設計上の制約が少なくなるという効果を奏する。 As described above, in the high-frequency plastic package according to claim 1 of the present invention, the semiconductor element can be mounted also on the first non-through hole closed by the copper foil. Miniaturization is possible. In addition, since the resin component does not remain on the semiconductor element mounting surface of the core substrate, the high-frequency signal transmission characteristics are not hindered. Furthermore, since unnecessary through holes are not formed in other conductor wiring patterns that are not targeted for interlayer connection, there is an effect that restrictions on wiring design are reduced.
本発明の請求項2に記載の高周波用プラスチックパッケージにおいては、請求項1記載の発明と同様の効果を奏するとともに、第1及び第2の非貫通孔をスタック構造にすることにより、配線の高密度化とパッケージの小型化が可能となる。 The high-frequency plastic package according to claim 2 of the present invention has the same effect as that of the invention according to claim 1, and the first and second non-through holes have a stacked structure, thereby increasing the wiring height. Density and package size can be reduced.
本発明の請求項3に記載の高周波用プラスチックパッケージの製造方法によれば、請求項1又は請求項2に記載の高周波用プラスチックパッケージを容易に製造することができる。 According to the method for manufacturing a high-frequency plastic package according to claim 3 of the present invention, the high-frequency plastic package according to claim 1 or 2 can be easily manufactured.
以下に、本発明の最良の実施の形態に係る高周波用プラスチックパッケージとその製造方法の実施例について説明する(請求項1乃至請求項3に対応)。 Examples of the high-frequency plastic package and its manufacturing method according to the best mode of the present invention will be described below (corresponding to claims 1 to 3).
本発明の高周波用プラスチックパッケージについてボールグリッドアレイパッケージを例にとって説明する。図1は本発明の実施の形態に係る高周波用プラスチックパッケージの構造を模式的に示す縦断面図である。図1に示すように、高周波用プラスチックパッケージ15を構成する多層プリント配線板16は、BT樹脂(ビスマイレイミドトリアジンを主成分にした樹脂)、エポキシ樹脂やポリイミド樹脂等からなる絶縁性基材1の両面に銅箔3a,3bが貼り付けられ、上部が銅箔3aにより閉塞された複数の非貫通孔5aが形成されたコア基板4と、コア基板4の両面及び非貫通孔5aの内壁面に施された銅メッキなどの導電被膜2a,2bと、コア基板4の下面に導電被膜2bを介して積層され、上部が閉塞された複数の非貫通孔5bが形成されるとともに非貫通孔5aの内部を充填するプリプレグからなる絶縁層6と、絶縁層6の下面に積層される銅箔3cと、銅箔3cに施された導電被膜2cと、導電被膜2a〜2c上にそれぞれ形成された導体配線パターン7a〜7cと、非貫通孔5bの内部を充填するとともに導体配線パターン7cを被覆するソルダーレジスト8とからなる。 The high frequency plastic package of the present invention will be described by taking a ball grid array package as an example. FIG. 1 is a longitudinal sectional view schematically showing the structure of a high-frequency plastic package according to an embodiment of the present invention. As shown in FIG. 1, the multilayer printed wiring board 16 constituting the high-frequency plastic package 15 is an insulating substrate 1 made of BT resin (resin mainly composed of bis-maleimide triazine), epoxy resin, polyimide resin, or the like. The core substrate 4 is formed with a plurality of non-through holes 5a having copper foils 3a and 3b attached to both sides thereof and closed at the top by the copper foil 3a, and both inner surfaces of the core substrate 4 and the inner wall surfaces of the non-through holes 5a. The conductive coatings 2a, 2b, such as copper plating, applied on the bottom of the core substrate 4 are laminated via the conductive coating 2b, and a plurality of non-through holes 5b whose upper portions are blocked are formed and the non-through holes 5a are formed. Insulating layer 6 made of a prepreg filling the inside of copper, copper foil 3c laminated on the lower surface of insulating layer 6, conductive film 2c applied to copper foil 3c, and conductive films 2a to 2c, respectively. And body wiring pattern 7 a to 7 c, consisting of a solder resist 8 which covers the conductive wiring pattern 7c to fill the interior of the non-through hole 5b.
多層プリント配線板16の上部の導電被膜2aにはニッケルメッキ10及び金メッキ11が形成され、多層プリント配線板16上面の略中央部に設けられたキャビティ9の内部には半導体素子12が実装されている。また、半導体素子12はボンディングワイヤ13により導体配線パターン7aと接合されている。さらに、多層プリント配線板16の下部にはニッケルメッキ10及び金メッキ11が形成された導体配線パターン7cがソルダーレジスト8の開口部から露出しており、複数の半田ボール14がニッケルメッキ10及び金メッキ11を介してこれらの導体配線パターン7cと電気的に接合されている。 A nickel plating 10 and a gold plating 11 are formed on the conductive film 2 a on the upper side of the multilayer printed wiring board 16, and a semiconductor element 12 is mounted inside a cavity 9 provided at a substantially central portion on the upper surface of the multilayer printed wiring board 16. Yes. Further, the semiconductor element 12 is bonded to the conductor wiring pattern 7 a by a bonding wire 13. Further, a conductor wiring pattern 7c formed with nickel plating 10 and gold plating 11 is exposed from the opening of the solder resist 8 below the multilayer printed wiring board 16, and a plurality of solder balls 14 are formed on the nickel plating 10 and gold plating 11. Are electrically connected to these conductor wiring patterns 7c.
上記構成の高周波用プラスチックパッケージ15においては、コア基板4の半導体素子12の実装面に非貫通孔5aの開口部が形成されることがないという作用を有する。また、貫通孔を形成した場合には、通常、その経路を必要としない層ではデッドスペースとなるが、本実施例の場合には、例えば導体配線パターン7a,7cが非貫通孔5a,5bの内壁面にそれぞれ形成された導電被膜2a,2bにより電気的に接続されるため、コア基板4と絶縁層6の間に形成された導体配線パターン7bに対して不要な箇所に貫通孔が形成されることがなく、デッドスペースが発生しないという作用を有する。 The high-frequency plastic package 15 configured as described above has an effect that the opening of the non-through hole 5a is not formed on the mounting surface of the semiconductor element 12 of the core substrate 4. In addition, when the through hole is formed, the layer that does not require the path usually becomes a dead space. However, in the case of the present embodiment, for example, the conductor wiring patterns 7a and 7c are formed in the non-through holes 5a and 5b. Since the conductive coatings 2a and 2b respectively formed on the inner wall surfaces are electrically connected, through holes are formed in unnecessary portions with respect to the conductor wiring pattern 7b formed between the core substrate 4 and the insulating layer 6. And no dead space occurs.
次に、本発明の高周波用プラスチックパッケージの製造方法について説明する。図2は本発明の実施の形態に係る高周波用プラスチックパッケージの製造方法を示す工程図である。なお、図1に示した構成要素については図1と同一の符号を付すものとする。
図2に示すように、ステップS1においてBT樹脂やエポキシ樹脂やポリイミド樹脂等からなる絶縁性基材1の両面に銅箔3a,3bを重ねて加圧加熱してコア基板4を形成する。次に、ステップS2で外周にドリリングを行い、コア基板4を所定の大きさに打ち抜く。さらに、レーザ加工時におけるレーザの吸収を良好にするために、ステップS3でコア基板4の下面の銅箔3bの表面を約5μm程度に薄くエッチングするなどの粗化処理を行う。次いで、ステップS4で銅箔3bに炭酸ガスレーザを照射して他方の銅箔3aに達するまで非貫通孔5aを穿設した後、ステップS5でレーザ加工面のバフ研磨を行う。ステップS6では、非貫通孔5aの底に残余した樹脂の染み出し成分をデスミア処理により除去する。デスミアは過マンガン酸カリウムなどの薬品を用いて行うが、レーザ装置などで蒸散させる方法を用いることもできる。ステップS7では、コア基板4にパラジウム等の触媒を付与した後、ホルマリンを還元剤とする強アルカリ浴中で無電解銅メッキを施す。さらに、無電解銅メッキが施された面に電解銅メッキの被膜を形成する。これにより、銅箔3a,3bの表面及び非貫通孔5aの内壁面に銅メッキによる導電被膜2a,2bが形成される。ステップS8では、銅箔3a,3bの表面に形成された導電被膜2a,2b上にフォトリソグラフィ法を用いて所定のマスクを形成し、エッチング処理をするサブトラクティブ法によって導体配線パターン7a,7bを形成する。なお、サブトラクティブ法の代わりに選択メッキによるアディティブ法を用いても良い。ステップS9では、コア基板4の下面の粗化処理を行い、ステップS10でコア基板4の下面に導体配線パターン7bを介して絶縁層6及び銅箔3cを積層する。ステップS11で所定の箇所にドリリングを行い、ステップS12では、絶縁層6の下面の銅箔3cに対してレーザ加工時におけるレーザの吸収を良好にするための粗化処理を施す。
Next, the manufacturing method of the high frequency plastic package of this invention is demonstrated. FIG. 2 is a process diagram showing a method for manufacturing a high-frequency plastic package according to an embodiment of the present invention. The components shown in FIG. 1 are denoted by the same reference numerals as those in FIG.
As shown in FIG. 2, in step S <b> 1, copper cores 3 a and 3 b are overlapped on both surfaces of an insulating base material 1 made of BT resin, epoxy resin, polyimide resin or the like, and heated under pressure to form a core substrate 4. Next, in step S2, drilling is performed on the outer periphery, and the core substrate 4 is punched into a predetermined size. Further, in order to improve the laser absorption at the time of laser processing, a roughening process such as etching the surface of the copper foil 3b on the lower surface of the core substrate 4 to about 5 μm is performed in step S3. Next, in step S4, the carbon foil 3b is irradiated with a carbon dioxide laser to form the non-through hole 5a until it reaches the other copper foil 3a. Then, in step S5, the laser processed surface is buffed. In step S6, the resin exudation component remaining on the bottom of the non-through hole 5a is removed by desmear treatment. Desmear is performed using a chemical such as potassium permanganate, but a method of evaporating with a laser device or the like can also be used. In step S7, after applying a catalyst such as palladium to the core substrate 4, electroless copper plating is performed in a strong alkaline bath using formalin as a reducing agent. Further, an electrolytic copper plating film is formed on the surface on which the electroless copper plating has been applied. Thereby, the conductive films 2a and 2b by copper plating are formed on the surfaces of the copper foils 3a and 3b and the inner wall surface of the non-through hole 5a. In step S8, a predetermined mask is formed on the conductive films 2a and 2b formed on the surfaces of the copper foils 3a and 3b by using a photolithography method, and the conductor wiring patterns 7a and 7b are formed by a subtractive method in which an etching process is performed. Form. Note that an additive method using selective plating may be used instead of the subtractive method. In step S9, the lower surface of the core substrate 4 is roughened, and in step S10, the insulating layer 6 and the copper foil 3c are laminated on the lower surface of the core substrate 4 via the conductor wiring pattern 7b. In step S11, drilling is performed at a predetermined location. In step S12, a roughening process is performed on the copper foil 3c on the lower surface of the insulating layer 6 to improve laser absorption during laser processing.
次いで、ステップS13で銅箔3cに炭酸ガスレーザを照射して導電被膜2bに達するまで非貫通孔5bを穿設した後、ステップS14でレーザ加工面のバフ研磨を行い、ステップS15で非貫通孔5bの底に残余した樹脂の染み出し成分をデスミア処理により除去する。ステップS16では、絶縁層6の下面の銅箔3c及び非貫通孔5bの内壁面に無電解銅メッキ及び電解銅メッキを施し、銅メッキによる導電被膜2cを形成する。ステップS17では、絶縁層6の下面の銅箔3cに形成された導電被膜2c上にステップS8と同様の方法により導体配線パターン7cを形成する。ステップS18において、導体配線パターン7cをソルダーレジスト8により被覆する。なお、ソルダーレジスト8には開口部が設けられており、コア基板4の上面においてはボンディングワイヤ13を用いて半導体素子12と接続するために必要な導体配線パターン7aの一部が開口部から露出し、コア基板4の下面においては半田ボール14と接続するために必要なニッケルメッキ10及び金メッキ11が施された導体配線パターン7cの一部が開口部から露出している。 Next, in step S13, the carbon foil 3c is irradiated with a carbon dioxide laser to form the non-through hole 5b until the conductive film 2b is reached. Then, in step S14, the laser machined surface is buffed, and in step S15, the non-through hole 5b. The resin exudation component remaining on the bottom of the resin is removed by desmear treatment. In step S16, electroless copper plating and electrolytic copper plating are applied to the inner surface of the copper foil 3c and the non-through hole 5b on the lower surface of the insulating layer 6 to form a conductive film 2c by copper plating. In step S17, a conductor wiring pattern 7c is formed on the conductive film 2c formed on the copper foil 3c on the lower surface of the insulating layer 6 by the same method as in step S8. In step S18, the conductor wiring pattern 7c is covered with the solder resist 8. Note that an opening is provided in the solder resist 8, and a part of the conductor wiring pattern 7 a necessary for connecting to the semiconductor element 12 using the bonding wire 13 is exposed from the opening on the upper surface of the core substrate 4. On the lower surface of the core substrate 4, a part of the conductor wiring pattern 7 c on which the nickel plating 10 and the gold plating 11 necessary for connection with the solder ball 14 are applied is exposed from the opening.
以上説明したように、本実施例の高周波用プラスチックパッケージとその製造方法によれば、高密度配線設計と小型化が可能であるとともに高周波信号の伝送特性に優れる高周波用プラスチックパッケージを容易に実現できる。 As described above, according to the high-frequency plastic package of this embodiment and the manufacturing method thereof, a high-frequency plastic package that can be designed with high density wiring and can be downsized and has excellent high-frequency signal transmission characteristics can be easily realized. .
本発明の高周波用プラスチックパッケージは上記実施例に限定されるものではなく、種々変形可能である。例えば、図1では非貫通孔5a,5bの内部はそれぞれ絶縁層6であるプリプレグ及びソルダーレジスト8で充填されているが、これらに限定されるものではなく、非貫通孔5a,5bの内部は銅メッキなどの導電被膜2b,2cのみあるいは銅ペーストや銀ペーストなどの導電ペーストで充填された構造とすることができる。また、絶縁層6、銅箔3c及び導体配線パターン2cは一層に限らず、複数層としても良い。具体的には、図2を用いて説明した工程の中で、ステップS17の後にステップS9乃至ステップS17の工程を所望の回数繰返し行うことにより、半導体素子12が実装されないコア基板4の下面側に、複数の絶縁層6、銅箔3c及び導体配線パターン7cが順次積層された構造の多層プリント配線板16が容易に実現される。なお、この場合には非貫通孔5aの下に非貫通孔5bを形成する、いわゆるスタック構造とすることにより高密度配線設計が可能となるため、パッケージの小型化を図ることができる。さらに、コア基板4は内部に複数の導体配線パターンが形成された構造としても良い。 The high-frequency plastic package of the present invention is not limited to the above-described embodiments, and can be variously modified. For example, in FIG. 1, the insides of the non-through holes 5 a and 5 b are filled with the prepreg and the solder resist 8 that are the insulating layers 6, respectively. A structure in which only the conductive coatings 2b, 2c such as copper plating or a conductive paste such as copper paste or silver paste is filled can be employed. The insulating layer 6, the copper foil 3c, and the conductor wiring pattern 2c are not limited to one layer, and may be a plurality of layers. Specifically, in the process described with reference to FIG. 2, steps S9 to S17 are repeated a desired number of times after step S17, so that the semiconductor substrate 12 is not mounted on the lower surface side of the core substrate 4. The multilayer printed wiring board 16 having a structure in which the plurality of insulating layers 6, the copper foil 3c, and the conductor wiring pattern 7c are sequentially laminated is easily realized. In this case, since a high-density wiring design is possible by forming a non-through hole 5b under the non-through hole 5a so as to form a so-called stack structure, the package can be reduced in size. Furthermore, the core substrate 4 may have a structure in which a plurality of conductor wiring patterns are formed.
本発明に係る高周波用プラスチックパッケージとその製造方法は、高周波信号の良好な伝送特性及び高い層間接続信頼性が必要とされる高周波用プラスチックパッケージに適用することができる。 The high-frequency plastic package and the manufacturing method thereof according to the present invention can be applied to a high-frequency plastic package that requires good transmission characteristics of high-frequency signals and high interlayer connection reliability.
1…絶縁性基材 2a,2b,2c…導電被膜 3a,3b,3c…銅箔 4…コア基板 5a,5b…非貫通孔 6…絶縁層 7a,7b,7c…導体配線パターン 8…ソルダーレジスト 9…キャビティ 10…ニッケルメッキ 11…金メッキ 12…半導体素子 13…ボンディングワイヤ 14…半田ボール 15…高周波用プラスチックパッケージ 16…多層プリント配線板 51…多層配線基板 52,52a,52b,52c…コア基板 52’…コア材 53,53a,53b…ビルドアップ配線層 54,54a,54b,54c…導通部 55a,55b,55c…配線層 56…表層パタ−ン 57a,57b…ビア 58a,58b…配線層 59a,59b…絶縁層 DESCRIPTION OF SYMBOLS 1 ... Insulating base material 2a, 2b, 2c ... Conductive film 3a, 3b, 3c ... Copper foil 4 ... Core board 5a, 5b ... Non-through-hole 6 ... Insulating layer 7a, 7b, 7c ... Conductor wiring pattern 8 ... Solder resist DESCRIPTION OF SYMBOLS 9 ... Cavity 10 ... Nickel plating 11 ... Gold plating 12 ... Semiconductor element 13 ... Bonding wire 14 ... Solder ball 15 ... High frequency plastic package 16 ... Multi-layer printed wiring board 51 ... Multi-layer wiring board 52, 52a, 52b, 52c ... Core board 52 '... Core materials 53, 53a, 53b ... Build-up wiring layers 54, 54a, 54b, 54c ... Conducting portions 55a, 55b, 55c ... Wiring layers 56 ... Surface layer patterns 57a, 57b ... Vias 58a, 58b ... Wiring layers 59a 59b ... Insulating layer
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