JP2006147774A - Ferroelectric memory and its manufacturing method, ferroelectric memory device and its manufacturing method, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ferroelectric memory together with its manufacturing method preventing the degradation of characteristic of a ferroelectric capacitor due to electric field from the side of a lower electrode, and to provide an electronic apparatus. <P>SOLUTION: The method is used to manufacture a ferroelectric memory provided with a ferroelectric capacitor which is comprised of a lower electrode 12 formed on a substrate 10, a ferroelectric layer 14 formed as to cover the lower electrode 12, and an upper electrode formed on the ferroelectric layer 14. The lower electrode 12 is formed on the substrate 10, and an insulating material containing Si is formed on the side wall 12a of the lower electrode 12. A ferroelectric material (sol gel layer 14c) containing lead is provided so as to cover the lower electrode 12 and the insulating material (reaction layer 13b), and the ferroelectric material is heated for crystallization, so as to change it into the ferroelectric layer 14. At the same time, the insulating material is dispersed to form a void 13 between the side wall 12a of the lower electrode 12 and the ferroelectric layer 14. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a ferroelectric memory having a ferroelectric capacitor and a manufacturing method thereof, a ferroelectric memory device and a manufacturing method thereof, and an electronic apparatus.

A simple matrix type memory cell array composed of a ferroelectric memory using only a ferroelectric capacitor without a cell transistor has a very simple structure and can obtain a high degree of integration. Expected. As an example of such a memory cell array, a ferroelectric capacitor includes a first signal electrode (lower electrode), a second signal electrode (upper electrode) arranged in a direction crossing the first signal electrode, and at least the above-mentioned A structure including a ferroelectric layer such as PZT disposed in an intersecting region between a first signal electrode and the second electrode is known. (For example, refer to Patent Document 1).
JP 2002-64187 A

  However, in the ferroelectric memory constituting the memory cell array, as shown in FIG. 8, when a voltage is applied to the ferroelectric capacitor 1, the ferroelectric layer 3 is also applied from the side wall surface 2 b of the lower electrode 2. Since an electric field is applied, the characteristics of the ferroelectric capacitor 1 are deteriorated. That is, if only the electric field from the upper surface 2a of the lower electrode 2 as shown by the arrow A in FIG. 8, the ferroelectric capacitor 1 has a good squareness of the hysteresis loop. However, when an electric field from the side wall surface 2a of the lower electrode 2 as shown by an arrow B in FIG. 8 is applied, the hysteresis loop squareness at this portion is not good, and therefore the hysteresis in the entire ferroelectric capacitor 1 is reduced. This is because the squareness of the loop is impaired. Furthermore, due to the electric field from the side wall surface 2b of the lower electrode 2, there is a problem that fatigue characteristics (fatigue characteristics) are deteriorated.

  The present invention has been made in view of the above circumstances, and the object thereof is a ferroelectric memory and a method of manufacturing the same, in which deterioration of characteristics of the ferroelectric capacitor due to an electric field from the side surface of the lower electrode is prevented. Furthermore, another object of the present invention is to provide a ferroelectric memory device including the ferroelectric memory, a manufacturing method thereof, and an electronic device.

  A ferroelectric memory according to the present invention includes a lower electrode formed on a base, a ferroelectric layer formed so as to cover the lower electrode, and an upper electrode formed on the ferroelectric layer. A ferroelectric memory having a ferroelectric capacitor, wherein the ferroelectric layer is made of a ferroelectric material containing lead, and a void portion is formed between a sidewall of the lower electrode and the ferroelectric layer. It is characterized by having.

  According to this ferroelectric memory, since the void portion is formed between the side wall of the lower electrode and the ferroelectric layer, the dielectric constant of the void portion becomes close to 1, so that the void portion The dielectric constant is sufficiently lower than that of the ferroelectric layer formed thereon. Therefore, an electric field from the side wall surface of the lower electrode is almost applied to the void portion by the void portion. Therefore, since the influence of the electric field from the side wall surface of the lower electrode is suppressed in this way, the squareness of the hysteresis loop of the ferroelectric capacitor is improved, and further, the deterioration of fatigue characteristics (fatigue characteristics) can be suppressed. .

In the ferroelectric memory, the lead-containing ferroelectric material is:
Represented by the general formula AB _1-x Nb _x O ₃
A element consists of at least Pb,
B element consists of at least one of Zr, Ti, V, W and Hf,
It is preferable that Nb is contained in the range of 0.05 ≦ x <4.
In this way, the ferroelectric layer has better ferroelectric properties than, for example, Pb (Zr, Ti) O ₃ (PZT).

The ferroelectric memory device of the present invention is characterized in that the ferroelectric memories are arranged in a matrix.
According to this ferroelectric memory device, a simple matrix type memory device composed of a ferroelectric memory using only a ferroelectric capacitor is formed without forming a cell transistor. The degree of integration can be obtained.

  A method of manufacturing a ferroelectric memory according to the present invention includes a lower electrode formed on a base, a ferroelectric layer formed so as to cover the lower electrode, and an upper electrode formed on the ferroelectric layer. A method of manufacturing a ferroelectric memory having a ferroelectric capacitor comprising: a step of forming a lower electrode on the substrate; and a step of forming an insulating material containing Si on a side wall of the lower electrode. A step of providing a ferroelectric material containing lead so as to cover the lower electrode and the insulating material; and the ferroelectric material is crystallized by heat-treating the ferroelectric material, thereby forming a ferroelectric layer And forming a void portion between the side wall of the lower electrode and the ferroelectric layer by diffusing the insulating material, and forming an upper electrode on the ferroelectric layer. It is characterized by having prepared.

  According to this method for manufacturing a ferroelectric memory, an insulating material containing Si is formed on the side wall portion of the lower electrode, and the ferroelectric material is disposed so as to cover the lower electrode and the insulating material, and then the ferroelectric material is formed. The ferroelectric material is crystallized by heat-treating the body material to form a ferroelectric layer, and a void portion is formed between the side wall of the lower electrode and the ferroelectric layer by diffusing the insulating material. Therefore, when the dielectric constant of the void portion is close to 1, the void portion has a dielectric constant sufficiently lower than that of the ferroelectric layer formed thereon. Therefore, as described above, almost all the electric field from the side wall surface of the lower electrode is applied to the void portion by the void portion. Therefore, since the influence of the electric field from the side wall surface of the lower electrode can be suppressed in this way, the squareness of the hysteresis loop of the ferroelectric capacitor is improved, and further, deterioration of fatigue characteristics (fatigue characteristics) is suppressed. You can also.

In the method for manufacturing the ferroelectric memory, the lead-containing ferroelectric material is:
Represented by the general formula AB _1-x Nb _x O ₃
A element consists of at least Pb,
B element consists of at least one of Zr, Ti, V, W and Hf,
It is preferable that Nb is contained in the range of 0.05 ≦ x <4.
In this way, the ferroelectric layer has better ferroelectric properties than, for example, Pb (Zr, Ti) O ₃ (PZT).

The manufacturing method of a ferroelectric memory device according to the present invention is characterized in that the ferroelectric memories obtained by the manufacturing method are arranged in a matrix.
According to this method of manufacturing a ferroelectric memory device, a simple matrix type memory device including a ferroelectric memory using only a ferroelectric capacitor can be obtained without forming a cell transistor. The dielectric memory device has a very simple structure and a high degree of integration.

An electronic apparatus according to the present invention includes the ferroelectric memory or the ferroelectric memory device.
According to this electronic apparatus, as described above, the squareness of the hysteresis loop of the ferroelectric capacitor is improved, and furthermore, the ferroelectric memory in which the deterioration of the fatigue characteristics (fatigue characteristics) is suppressed, or the same is provided. Since the ferroelectric memory device is provided, the memory characteristics are particularly excellent.

The present invention will be described in detail below.
FIG. 1 is a diagram showing an embodiment of a ferroelectric memory device according to the present invention. In FIG. 1, reference numeral 1000 denotes a ferroelectric memory device. The ferroelectric memory device 1000 includes a memory cell array 100 in which the ferroelectric memories of the present invention are arranged in a matrix, and a peripheral circuit unit 200. The peripheral circuit unit 200 includes various circuits for selectively writing or reading information with respect to a ferroelectric memory (memory cell) of the present invention to be described later. For example, the peripheral circuit unit 200 selectively selects the lower electrode 12. A first drive circuit 50 for controlling the upper electrode 16, a second drive circuit 52 for selectively controlling the upper electrode 16, and a signal detection circuit (not shown) such as a sense amplifier. As a specific example of such a peripheral circuit unit 200, a Y gate, a sense amplifier, an input / output buffer, an X address decoder, a Y address decoder, or an address buffer can be raised.

  Next, an embodiment of a ferroelectric memory according to the present invention will be described with reference to FIG. FIG. 2 is a cross-sectional view schematically showing a part of the memory cell array 100 along the line AA in FIG. 1, and reference numeral 15 in FIG. 2 denotes a ferroelectric memory. In the memory cell array 100 shown in FIG. 1, a plurality of lower electrodes (word lines) 12 for row selection and a plurality of upper electrodes (bit lines) 16 for column selection are formed to be orthogonal to each other. Yes. The lower electrode 12 can be a bit line and the upper electrode 16 can be a word line.

  In the ferroelectric memory 15 shown in FIG. 2, the lower electrode 12 is formed in parallel on the substrate 10, and is a single metal such as Pt, Ir, or Ru, or a composite material mainly composed of these metals. It is formed by. When a ferroelectric element in a ferroelectric layer, which will be described later, diffuses into the lower electrode 12 or the upper electrode 16, a composition shift occurs at the interface between the electrode and the ferroelectric layer, and the hysteresis loop has a square shape. Sex is reduced. Therefore, the lower electrode 12 and the upper electrode 16 are required to be dense so that the ferroelectric element does not diffuse. Therefore, in order to increase the denseness of the lower electrode 12 and the upper electrode 16, for example, a method such as sputtering film formation with a gas having a heavy mass at the time of manufacture or a method of dispersing oxides such as Y and La in the noble metal electrode is used. It may be adopted. In this embodiment, the lower electrode 12 is made of platinum (Pt), and the side wall surface 12a is about 40 to 75 ° so that the width gradually increases toward the base 10 side. It is formed in a tapered shape having a taper angle of about 50 °.

A ferroelectric layer 14 is formed so as to cover the lower electrode 12. As will be described later, the ferroelectric layer 14 has a crystal region 14a crystallized in a perovskite crystal structure in the vicinity of a portion in contact with the upper surface (upper surface portion) 12b of the lower electrode. Other than this, Si diffusion that is amorphous without being crystallized, or that includes a crystal layer that is crystallized but is not perovskite type such as pyrochlore type Region 14b is formed.
This ferroelectric layer 14 is formed of a ferroelectric material containing lead, and specifically, Pb (Zr, Ti) O ₃ (PZT) or (Pb, La) (Zr, Ti). It is formed of O ₃ (PLZT) or a material obtained by adding a metal such as niobium (Nb) to these materials.

Here, in particular, a ferroelectric material to which niobium is added can be expressed by the following general formula.
AB _1-x Nb _x O ₃
In this general formula, the A element includes at least Pb, and the B element includes at least one of Zr, Ti, V, W, and Hf. And about niobium (Nb), it mix | blends so that the said x may become the range of (0.05 <= x <4).
Here, the element A in the general formula may be not only Pb but also (Pb _1-y Ln _y ). However, Ln is one or more elements selected from La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu, and y Is preferably in the range of 0 <y ≦ 0.2.
In this embodiment, as a ferroelectric material for forming the ferroelectric layer 14, PbT (Zr, Ti, Ti, PbT, Zr, Ti, doped with Nb in a PZT material made of an oxide containing Pb, Zr, and Ti as constituent elements. Nb) O ₃ (PZTN) is used.

In such a PZTN, Nb is almost the same size as Ti (the ionic radius is close and the atomic radius is the same), the weight is twice, and atoms are removed from the lattice by collisions between atoms due to lattice vibration. It has become difficult. Further, the valence is +5 and stable, and even if Pb is lost, the valence of Pb loss can be compensated by Nb ⁵⁺ . Further, even if Pb loss occurs during crystallization, it is easier to enter small Nb than large O loss.

Further, since Nb also has a +4 valence, it functions sufficiently instead of Ti ⁴⁺ . Furthermore, in fact, Nb has a very strong covalent bond, and Pb is considered to be difficult to escape (H. Miyazawa, E. Natori, S. Miyashita; Jpn. J. Appl. Phys. 39 (2000). 5679).

  So far, Nb doping to PZT has been mainly performed in the Zr-rich rhombohedral region, but the amount is 0.2-0.025 mol% (J. Am. Ceram. Soc, 84 ( 2001) 902; Phys. Rev. Let, 83 (1999) 1347) and so on. It is considered that the reason why Nb could not be doped in a large amount as described above was that the crystallization temperature increased to 800 ° C. or more when Nb was added at, for example, 10 mol%.

Therefore, when forming the ferroelectric layer 14, it is preferable to add PbSiO ₃ silicate at a ratio of 1 to 5 mol%, for example. Thereby, the crystallization energy of PZTN can be reduced. That is, when PZTN is used as the material of the ferroelectric layer 14, the crystallization temperature of PZTN is lowered by adding Nb to the PZT material and adding a silicate such as PbSiO _{3 as} will be described later. It is preferable to do so.

  Between the lower electrode 12 and the ferroelectric layer 14 covering the lower electrode 12, a sidewall-like void is formed between the side wall surfaces (side wall portions) 12 a and 12 a of the lower electrode 12 and the ferroelectric layer 14. A portion 13 is formed. As will be described later, the void portion 13 has pores (voids) formed by diffusing the Si-containing insulating material into the ferroelectric material, and is composed of relatively large pores. It is formed in a state having a large number of small holes (voids), or formed in a state having large holes and small holes. Such a void portion 13 is formed in a state having a large number of small holes as well as a large number of small holes, because the dielectric constant (relative dielectric constant) of the void portion is approximately 1. Even in this case, the void portion 13 has a dielectric constant close to 1, and the dielectric constant is sufficiently lower than that of the ferroelectric layer 14 formed thereon.

  An upper electrode 16 is formed on the ferroelectric layer 14 so as to be orthogonal to the lower electrode 12 as shown in FIG. Similar to the lower electrode 12, the upper electrode 16 is made of a single metal such as Pt, Ir, or Ru, or a composite material mainly composed of these metals. A ferroelectric capacitor is formed by the lower electrode 12, the ferroelectric layer 14, and the upper electrode 16, and the present invention further includes the ferroelectric capacitor and the void portion 13. This ferroelectric memory 15 is configured.

Next, a manufacturing method of the ferroelectric memory device 1000 including the ferroelectric memory 15 having such a configuration will be described.
First, as shown in FIG. 3A, a first conductive layer 17 for forming a lower electrode 12 is formed on a base 10 made of a Si substrate. Here, as the substrate 10, a substrate having an appropriate structure depending on the type of the ferroelectric memory device 1000 such as a structure including a region where a semiconductor element such as a MOS transistor is formed is used.

The first conductive layer 17 is formed, for example, by forming a TiOx layer 17a by depositing TiOx to a thickness of 40 nm, and further forming a Pt layer 17b by depositing Pt to a thickness of 200 nm thereon. can get. Here, the TiOx layer 17a functions as an adhesion layer for satisfactorily bonding the Pt layer 17b on the silicon oxide layer (SiO ₂ layer) formed on the surface layer portion of the substrate 10 made of an Si substrate. .

  As the material for the first conductive layer 17, materials other than Pt can be used as long as they can serve as electrodes of the ferroelectric capacitor as described above. Specifically, as described above, Ir, IrOx, RuOx, SrRuOx, LaSrCoOx, or the like can also be used. The first conductive layer 17 may be a single layer. As a method for forming the first conductive layer 17, a sputtering method is preferably used, but a film forming method such as vacuum deposition or CVD, or a combination of these methods can also be employed.

  Next, a resist mask (not shown) is formed on the entire upper surface of the first conductive layer 17, and a line pattern mask 60 is formed by lithography. A so-called hard mask can also be used as a mask other than the resist. The material of the hard mask 60 is not particularly limited as long as the material can function as a mask when the first conductive layer 17 is patterned, and examples thereof include silicon nitride, silicon oxide, and titanium nitride. it can.

As a formation method when silicon oxide is used as the mask layer, for example, a CVD method is used. The film thickness of the mask layer is preferably about 1.0 to 2 times the film thickness of the lower electrode 12, for example, 400 nm. As a method for etching the mask layer, a known technique can be used. For example, RIE (reactive ion etching) is used. In that case, a mixed gas of CHF ₃ and Ar can be used as an etching gas.

Next, by patterning the first conductive layer 17 using the mask 60, the lower electrode 12 is formed as shown in FIG. 3B, and the resist mask is removed with oxygen plasma or the like. As an etching method, for example, high density plasma dry etching using high density plasma such as ICP (inductively coupled plasma) is used. In that case, a mixed gas of Cl ₂ and Ar can be used as an etching gas, and the etching can be performed with a bias power of 500 W under a low pressure of 1.0 Pa or less. When the lower electrode 12 is formed by such etching, the obtained lower electrode 12 is formed into a tapered shape with the side wall surface 12a having a taper angle of about 50 °. Note that the etching method is not limited to the above method, and RIE or the like can also be used.
When a silicon oxide hard mask is used, patterning can be performed by the dry etching method using a mixed gas of Cl ₂ and O ₂ . Using a hard mask can increase the taper angle compared to using a resist mask. For example, when silicon oxide is used, the angle can be about 70 °. When a hard mask is used as the mask layer 60, the hard mask may be selectively removed thereafter by dry etching or wet etching, or may be removed in an etch back process described later.

Next, a Si-containing insulating material, in this embodiment SiO ₂ , is formed to a thickness of about 600 nm with the lower electrode 12 covered as shown in FIG. 3C by the CVD method, and the SiO ₂ layer 13a is formed. Form. As the Si-containing insulating material, SiON, Si ₃ N ₄ or the like can be used instead of SiO ₂ . Further, SiO ₂ is an illustration as a representative example of silicon oxide represented as SiO _x, it is of course can be used silicon oxide represented by general formula SiO _x.

Subsequently, the SiO ₂ layer 13a is etched back to expose the upper surface portion 12b of the lower electrode 12 as shown in FIG. 4A, and the side wall surface 12a is made of the SiO ₂ layer 13a. A wall-like reaction layer 13b is formed. That is, the Si-containing insulating material is formed in this way and further etched back to adhere the Si-containing insulating material to the side wall portion of the lower electrode 12. The etch back can be performed by dry etching such as RIE. Specifically, CHF ₃ / O ₂ gas can be used with RF power of 10 Pa and 500 W. When silicon oxide is used as the hard mask, the SiO ₂ layer 13a and the hard mask 60 can be removed simultaneously by this etch back process.

Next, as shown in FIG. 4B, the ferroelectric material is disposed so as to cover the lower electrode 12 and the reaction layer 13b. In arranging the ferroelectric material, the sol-gel method is particularly preferably used. In other words, strong in the case of forming the PZTN layer as a dielectric layer 14, for example, PbZrO ₃ sol-gel solution, a sol-gel solution for PbTiO _3, and PbNbO ₃ that the sol-gel solution was mixed for further addition of PbSiO ₃ sol-gel solution for Use what you did. Since the PZTN film contains Nb as a constituent element, the crystallization temperature is high. Therefore, as described above, in order to reduce the crystallization temperature, a sol-gel solution for PbSiO ₃ is further added. In the present embodiment, the sol-gel mixed solution is applied by a spin coating method so as to cover the lower electrode 12 and the reaction layer 13b. Specifically, the sol-gel layer 14c having a thickness of about 150 nm is formed by applying three layers at 2500 rpm.
Note that the method of arranging the ferroelectric material is not limited to the spin coating method using the sol-gel material, and a dipping method, a sputtering method, an MOCVD method, a laser ablation method, or the like can also be used. In that case, a MOD material can be used instead of the sol-gel material.

  Next, heat treatment (RTA treatment) is performed for about 5 to 60 minutes in a temperature range of 550 ° C. to 650 ° C. in an oxygen atmosphere, so that the sol-gel layer 14 c is made the ferroelectric layer 14. As a result of this heat treatment, the sol-gel layer 14c is crystallized into a perovskite crystal structure at the portion in contact with the upper surface 12b of the lower electrode as shown in FIG.

  In the reaction layer 13b on the side wall surface 12a of the lower electrode 12, Si and O diffuse into the sol-gel layer 14c thereon. As a result, the void portion 13 is formed on the side wall surface 12a of the lower electrode 12 due to the diffusion of the elements constituting the reaction layer 13b. As described above, the void portion 13 is composed of relatively large holes, has a large number of small holes (voids), or has a large hole and small holes. It has become. Therefore, the void portion 13 has a dielectric constant close to 1 as described above, and is sufficiently lower than the ferroelectric layer 14.

  In addition, since the elements constituting the reaction layer 13b are diffused in this way, in particular, the part located on the reaction layer 13b in the sol-gel layer 14c, that is, the part in contact with the reaction layer 13b is the same as the Si diffusion region 14b. Become. This Si diffusion region 14b becomes lead glass or amorphous without being crystallized due to the diffusion of Si, or even if it is crystallized, its crystal structure does not become a perovskite type but a pyrochlore type. Become. Therefore, the Si diffusion region 14b is significantly inferior in characteristics as a ferroelectric film compared to the crystal region 14a.

Thereafter, a second conductive layer (not shown) made of Pt is formed on the ferroelectric layer 14 to a thickness of 200 nm, and subsequently the lower electrode 12 is formed in the same manner as the lower electrode 12 is formed. Then, the upper electrode 16 is formed as shown in FIG. Thus, the ferroelectric capacitor according to the present invention is formed, and the ferroelectric memory 15 is obtained. Further, by obtaining the ferroelectric memory 15 in this way, the cross-point type memory cell array 100 as shown in FIG. 1 is formed.
Further, the peripheral circuit unit 200 is formed separately from the memory cell array 100 or by partially sharing the process, thereby obtaining the ferroelectric memory device 1000.

  In the ferroelectric memory 15 obtained in this way, a void portion 13 is formed between the side wall surface 12a of the lower electrode 12 and the ferroelectric layer 14, and this void portion 13 is formed thereon. The dielectric constant is sufficiently lower than that of the ferroelectric layer 14 formed in (1). Therefore, the void portion 13 suppresses the generation of an electric field from the side wall surface 12a of the lower electrode 12, thereby suppressing the influence of the electric field from the side wall surface 12a of the lower electrode 12 to the Si diffusion region 14b. The squareness of the hysteresis loop of the body capacitor is improved, and further, the deterioration of fatigue characteristics (fatigue characteristics) can be suppressed.

Further, since PZTN containing Nb is used as the ferroelectric material, the crystal region 14a in the obtained ferroelectric layer 14 is more in comparison with, for example, Pb (Zr, Ti) O ₃ (PZT). Thus, the ferroelectric memory 15 itself has better characteristics.

  In the ferroelectric memory device 1000 in which such ferroelectric memories 15 are arranged in a matrix, a ferroelectric memory using only a ferroelectric capacitor is formed without forming a cell transistor. Therefore, a high degree of integration can be obtained with a very simple structure.

(Experimental example)
A ferroelectric memory 15 was fabricated according to the steps shown in FIGS. 3 (a) to 3 (c) and FIGS. 4 (a) to 4 (c). For comparison, a ferroelectric memory was manufactured in the same manner as in the manufacturing of the ferroelectric memory 15 except that the reaction layer 13b made of SiO ₂ was not formed.
For each manufactured ferroelectric memory, the squareness of the hysteresis loop of each ferroelectric capacitor was examined. FIG. 5 shows the QV characteristics of each ferroelectric capacitor. In FIG. 5, the characteristic diagram of the ferroelectric memory 15 of the present invention is described as an example, and the characteristic diagram of a conventional ferroelectric memory is described as a conventional example.
As shown in FIG. 5, it was clearly confirmed that the embodiment of the present invention was superior in squareness. Thus, it was found that the example of the present invention was superior in memory characteristics as compared with the conventional example.

  Further, the fatigue characteristics (fatigue characteristics) of the ferroelectric memories of the above-described examples and conventional examples were examined from the relationship between the polarization value of the capacitor and the cycle time. The obtained result is shown in FIG. As shown in FIG. 6, the embodiment of the present invention has a smaller decrease in the standardized polarization value (Pr) with an increase in cycle time than the conventional example. Therefore, the embodiment of the present invention has a lower value than the conventional example. It was found that the fatigue characteristics were also excellent.

  The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention. For example, in the above embodiment, the ferroelectric memory device of the present invention includes the memory cell array 100 in which the ferroelectric memories of the present invention are arranged in a matrix, but the present invention is not limited to this. Without limitation, the present invention can also be applied to conventionally known ferroelectric memory devices such as 1T1C type and 2T2C type.

Next, an example of an electronic apparatus provided with the ferroelectric memory or the ferroelectric memory device as a component will be described.
FIG. 7 is a perspective view showing a mobile phone as an example of such an electronic apparatus. Reference numeral 1001 in FIG. 7 denotes a mobile phone.
Since the cellular phone 1001 (electronic device) includes the ferroelectric memory or the ferroelectric memory device, the memory phone has particularly good memory characteristics and high reliability.

  Examples of other electronic devices include personal computers, liquid crystal devices, electronic notebooks, pagers, POS terminals, IC cards, mini-disc players, liquid crystal projectors, and engineering workstations (EWS), word processors, televisions, viewfinder types or The present invention can be applied to various devices such as a monitor direct-view type video tape recorder, an electronic desk calculator, a car navigation device, a device equipped with a touch panel, a clock, a game machine, and an electrophoresis device.

It is a figure which shows one Embodiment of the ferroelectric memory device of this invention. 1 is a side sectional view showing a schematic configuration of an embodiment of a ferroelectric memory according to the present invention. (A)-(c) is a figure for demonstrating the manufacturing process of a ferroelectric memory. (A)-(c) is a figure for demonstrating the manufacturing process of a ferroelectric memory. It is a graph which shows the QV characteristic of each ferroelectric capacitor. It is a graph which shows a fatigue characteristic. It is a perspective view which shows an example of an electronic device. It is a schematic diagram for demonstrating the subject in the conventional ferroelectric memory.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Base | substrate, 12 ... Lower electrode, 12a ... Side wall surface (side wall part), 12b ... Upper surface (upper surface part),
13 ... void portion, 13a ... SiO ₂ layer, 13b ... reaction layer, 14 ... ferroelectric layer,
14a ... crystal region, 14b ... Si diffusion region, 14c ... sol-gel layer,
15 ... ferroelectric memory, 16 ... upper electrode,
DESCRIPTION OF SYMBOLS 100 ... Memory cell, 1000 ... Ferroelectric memory device

Claims (7)

A ferroelectric having a ferroelectric capacitor comprising a lower electrode formed on a substrate, a ferroelectric layer formed so as to cover the lower electrode, and an upper electrode formed on the ferroelectric layer Memory,
The ferroelectric layer is made of a ferroelectric material containing lead,
A ferroelectric memory, wherein a void portion is formed between a side wall of the lower electrode and a ferroelectric layer. The lead-containing ferroelectric material is:
Represented by the general formula AB _1-x Nb _x O ₃
A element consists of at least Pb,
B element consists of at least one of Zr, Ti, V, W and Hf,
2. The ferroelectric memory according to claim 1, wherein Nb is contained in a range of 0.05 ≦ x <4.   3. A ferroelectric memory device comprising the ferroelectric memories according to claim 1 or 2 arranged in a matrix. A ferroelectric having a ferroelectric capacitor comprising a lower electrode formed on a substrate, a ferroelectric layer formed so as to cover the lower electrode, and an upper electrode formed on the ferroelectric layer A method of manufacturing a memory,
Forming a lower electrode on the substrate;
Forming an insulating material containing Si on the side wall of the lower electrode;
Arranging a ferroelectric material containing lead so as to cover the lower electrode and the insulating material;
The ferroelectric material is crystallized by heat-treating the ferroelectric material to form a ferroelectric layer, and a void is formed between the sidewall of the lower electrode and the ferroelectric layer by diffusing the insulating material. Forming a part;
Forming an upper electrode on the ferroelectric layer;
A method for manufacturing a ferroelectric memory, comprising: The lead-containing ferroelectric material is:
Represented by the general formula AB _1-x Nb _x O ₃
A element consists of at least Pb,
B element consists of at least one of Zr, Ti, V, W and Hf,
5. The method of manufacturing a ferroelectric memory according to claim 4, wherein Nb is contained in a range of 0.05 ≦ x <4.   6. A method of manufacturing a ferroelectric memory device, comprising arranging the ferroelectric memories obtained by the manufacturing method according to claim 4 in a matrix. An electronic apparatus comprising the ferroelectric memory according to claim 1 or 2 or the ferroelectric memory device according to claim 3.

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