JP2006135552A - Phase synchronization circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a phase synchronization circuit by which noises which may disturb viewing can be suppressed even when the phase synchronization circuit is accidentally unlocked. <P>SOLUTION: The phase synchronization circuit 100 finds phase difference between the sound signal frame of a sound signal and the image signal frame of an image signal, and outputs phase error information for synchronization between the sound signal and the image signal corresponding to the sound signal, when a transmitted AV stream is decoded and the sound signal and the image signal are outputted. It has a control means 107 which performs processing for converging the phase error information and synchronizing the sound signal and the image signal when the outputted phase error information is equal to or less than a predetermined threshold value, and exercises control for muting the output of the sound signal when outputted phase error information is equal to or more than a predetermined threshold value. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention compares the phase difference between the audio signal and the video signal and converges the phase error information output based on the comparison in order to synchronize the audio signal in the stream with the video signal corresponding to the audio signal. The present invention relates to a phase synchronization circuit that performs processing.

  In a conventional DVC (Digital Video Camera) or the like, a PLL (Phase Locked Loop) is provided to match (synchronize) the reproduction frequency with the supply rate of audio data in the stream. Here, the configuration of the phase synchronization circuit will be described with reference to FIG. The phase synchronization circuit 20 includes a first frequency divider 21, a second frequency divider 22, a phase comparison unit 23, an LPF (Low Pass Filter) 24 that functions as a loop filter, a 1-bit (bit) DAC (Digital) Analog converter (25) and VCO (Voltage Controlled Oscillator) 26. The VCO 26 controls the output frequency by voltage, and the input / output characteristics are shown in FIG. In relation to the output frequency with respect to the input voltage, the higher the linearity, the better the characteristics. The first frequency divider 21 divides the output frequency (MCK: master clock) output from the VCO 26 by 256 or 384 and outputs the sampling frequency fs. When the master clock is 12.228 MHz, it is 48 kHz if it is divided by 256, and 32 kHz if it is divided by 384. Here, the frequency division is to multiply the period of the input signal by N, and is usually configured using a counter. For example, in the case of N = 5, if 5 pulses are counted and one pulse is output, the frequency division ratio becomes 5.

  The second frequency divider 22 performs frequency division for the number of samples obtained from AFSIZE described later. Here, in the DV format used for DVC, the number of audio data recorded in the stream for one frame of video is managed by a value called AFSIZE. When fs is 32 kHz and NTSC (National Television System Committee), the number of samples that can be recorded in one frame is about 1053 to 1080, and the frequency is divided by 1053 to 1080 accordingly. By passing through the first frequency divider 21 and the second frequency divider 22 described above, a frequency signal for outputting audio data recorded in one frame of video can be obtained.

  The phase comparison unit 23 compares the phase difference between the frequency signal that has passed through the second frequency divider 22 and the frequency signal of the video from the video frame unit 27 of the system, that is, the frequency signal for flowing one video frame. . Here, the video frame unit 27 of the system is a component of a part of the system including the phase synchronization circuit 20, and generates a video frequency signal based on an operation clock. The LPF 24 performs smoothing (averaging) of the phase error information output from the phase comparison unit 23 and subjected to predetermined processing so as to converge the phase error. The concept of the predetermined processing in the phase comparison unit 23 and the phase comparison will be described later. The 1-bit DAC 25 converts the output result output from the LPF 24 into a PWM (Pulse Width Modulation) waveform. By using the PWM signal output from the 1-bit DAC 25, the VCO 26 controls the output frequency. This output frequency is input again to the first frequency divider 21. Finally, feedback is applied until the phase error in the phase comparator 23 becomes zero.

  The concept of phase comparison in the phase comparison unit 23 will be described with reference to FIG. As mentioned above, DVC manages the number of audio data recorded in a stream for one frame of video at the time of shooting (or after-recording) using information called AFSIZE, and synchronizes video and audio during playback. That is, it is necessary to output audio data corresponding to AFSIZE in the time for outputting one frame of video. For this purpose, the frequency of the master clock used for audio output is changed using a phase synchronization circuit so as to eliminate the phase shift from the video signal. . FIG. 4 shows an outline of a method for detecting a phase shift from an image.

  For comparison with a reference video frame signal (video frequency signal) (hereinafter also simply referred to as video frame), the audio frame signal shown in FIG. 4 (audio data recorded for one video frame is output). Frequency signal) (hereinafter also simply referred to as an audio frame). The audio frame is obtained by dividing the master clock by (256 or 384) × AFSIZE by the first frequency divider 21 and the second frequency divider 22 in FIG. 2, and the number of audio frames indicated by AFSIZE. It means the time required to output data. For detection of the phase shift, a counter is used that starts counting from the middle point of the video frame and the count value becomes 0 (when locked) at the switching timing of the video frame. At this time, the value of the counter when the audio frame is switched is 0 if the phase of the video frame is the same, but if there is a phase difference, the amount of deviation is reflected in the counter value. .

In the case of NTSC, the frame period (of video) is a value of 29.97 Hz, and since it cannot have a relationship of an integral multiple of the audio sampling period, the value of AFSIZE for each frame increases or decreases. Accordingly, the period of the audio frame shown in FIG. 4 also changes. The function of the phase comparator 23 is to detect the phase shift caused by the change in AFSIZE using the counter of FIG. As described above, the counting is started from the middle point of the video frame because the values that can be taken as the phase error information are uniform and maximum in the positive direction and the negative direction. Here, the predetermined processing in the phase comparison unit 23 will be described with reference to FIG. In the phase comparison unit 23, a predetermined amount of phase error information, which is a result of comparing the phase difference between the frequency signal (frame signal) that has passed through the second frequency divider 22 and the frequency signal (frame signal) of the video, is predetermined. The processing result is output to the LPF 24 by performing processing such as multiplying by the magnification of, multiplying the limiter, and adding the bias. In FIG. 5, evmul means multiplication, evshft means exponential operation, evlmt and evlmten mean upper and lower limits, and evbias means addition and subtraction. Thus, by adjusting the phase error information, it is possible to adjust the degree of feedback applied after the phase comparison unit 23. By these calculations, the phase error information can be converged abruptly or slowly. When rapid convergence is performed, the time required for convergence itself can be shortened, but the change in the convergence process becomes large, and depending on the degree, it may cause a problem in hearing. As described above, it is not always necessary to perform all the processing in the phase comparison unit 23. The phase synchronization circuit as described above is disclosed in Patent Document 1 and Non-Patent Document 1 below.
JP 2002-185317 A (FIG. 1) http://www.hh.iij4u.or.jp/~tokumi/archive2/PLL.html

  However, the conventional phase synchronization circuit itself does not have a function to make a judgment based on the phase error information. Even when the phase synchronization circuit is unlocked and the phase synchronization circuit is unlocked, the conventional phase synchronization circuit tries to output sound at a frequency that has not converged. Therefore, there was a problem of generating noise that hinders viewing.

  An object of the present invention is to provide a phase synchronization circuit that can suppress the generation of noise that hinders viewing even when the phase synchronization circuit is unlocked. .

  In order to achieve the above object, according to the present invention, when an AV stream sent is decoded and an audio signal and a video signal are output, the audio signal and the video signal corresponding to the audio signal are synchronized. Therefore, in the phase synchronization circuit that compares the phase difference between the audio signal frame of the audio signal and the video signal frame of the video signal and outputs phase error information, the output phase error information is less than or equal to a predetermined threshold value The phase error information is converged so that the audio signal and the video signal are synchronized, and when the output phase error information is larger than a predetermined threshold value, There is provided a phase locked loop circuit having control means for controlling the output to be muted.

  The phase synchronization circuit of the present invention has the above-described configuration, and can suppress generation of noise that hinders viewing even when the phase synchronization circuit is unlocked.

  Hereinafter, an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a configuration diagram showing the configuration of a phase locked loop circuit according to an embodiment of the present invention. A phase locked loop circuit according to an embodiment of the present invention will be described with reference to FIG. As shown in FIG. 1, a phase synchronization circuit (hereinafter also referred to as PLL) 100 includes a first frequency divider 101, a second frequency divider 102, a phase comparison unit 103, an LPF 104, a 1-bit DAC 105, a VCO 106, and a control unit. 107. The component of the phase synchronization circuit 100 and the video frame unit 109 of the system are the same as the component of the conventional phase synchronization circuit 20 and the video frame unit 27 of the system, respectively. The control unit 107 which is a characteristic part of the invention will be described later. Note that the phase comparison unit 103 of the phase synchronization circuit 100 according to the embodiment of the present invention is configured to output phase error information to the control unit 107.

  The control unit 107 receives the phase error information input from the phase comparison unit 103, and outputs a control signal for performing processing such as muting the sound when an abnormality occurs, for example, when the lock error occurs due to a large phase error. . For example, there is a predetermined threshold as an index for determining an abnormality such as unlocking. The control unit 107 determines that there is an abnormality when the phase error information exceeds a predetermined threshold, and outputs a control signal. The audio output block unit 108 performs corresponding processing based on the control signal from the control unit 107. As described above, since the control unit 107 that performs the determination process for the phase error is added to the conventional phase synchronization circuit 20, not only the appropriate audio output can be controlled, but the configuration of the phase synchronization circuit is easy and free. A high degree of setting can be made.

  In the above-described example, the control in the audio output of the DVC has been described. However, the present invention is not limited to this, and can be similarly applied to other mechanisms (devices) using a PLL for phase synchronization. Further, in the above-described example, the response to the unlocking of the clock signal has been described, but it is also possible to perform processing (conversion etc.) on the VCO input signal using the control signal output from the control unit 107.

  Since the phase synchronization circuit according to the present invention can suppress the generation of noise that hinders viewing even when the phase synchronization circuit is unlocked, the audio signal in the stream and the video signal corresponding to the audio signal are In order to achieve synchronization, it is useful for a phase synchronization circuit that compares the phase difference between an audio signal and a video signal and performs processing to converge phase error information output based on the comparison.

It is a figure for demonstrating the phase-locked loop circuit which concerns on embodiment of this invention. It is a figure for demonstrating the phase locked loop circuit used for the conventional DVC etc. It is a figure which shows the input-output characteristic in VCO of the phase-locked loop used for the conventional DVC etc. It is a figure for demonstrating the concept of the phase comparison in the phase comparison part of the phase locked loop circuit used for the conventional DVC etc. It is a figure for demonstrating the process in the phase comparison part of the phase-locked loop used for the conventional DVC etc. FIG.

Explanation of symbols

20 Phase synchronization circuit (PLL)
21 First frequency divider 22 Second frequency divider 23 Phase comparator 24 LPF
25 1bit DAC
26 VCO
27 Video frame part of system 100 Phase synchronization circuit (PLL)
101 First frequency divider 102 Second frequency divider 103 Phase comparison unit 104 LPF
105 1bit DAC
106 VCO
107 Control unit (control means)
108 audio output block 109 system video frame

Claims (1)

When decoding a transmitted AV stream and outputting an audio signal and a video signal, the audio signal frame of the audio signal and the video signal are synchronized in order to synchronize the audio signal and the video signal corresponding to the audio signal. In the phase synchronization circuit that compares the phase difference with the video signal frame and outputs phase error information,
When the output phase error information is equal to or less than a predetermined threshold, the audio signal and the video signal are synchronized by performing processing so as to converge the phase error information, and the output phase error A phase synchronization circuit comprising control means for controlling to mute the output of the audio signal when the information is larger than a predetermined threshold.

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