JP2006135224A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method capable of restraining the oozing of Cu even when columns superposed in respective layers as a seal ring are deviated into horizontal direction with respect to a wiring layer. <P>SOLUTION: First wiring 212 is formed on the element forming region Rlogic of a first liner insulating film 201 deposited on a semiconductor substrate, a first interlayer insulating film 202, and a first cap insulating layer 203 while a first column 214 is formed in a seal ring forming region Rseal. Next, second wiring 226 is formed in the element forming region Rlogic of a second liner insulating film 215, deposited on a first cap insulating film 203, a second interlayer insulating film 216, and a second cap insulating film 217 while a second column 228, wider than the width of the first column and covering the upper surface of the first column, is formed in the seal ring forming region Rseal. According to this method, the oozing of Cu can be restrained even when the columns superposed in respective layers are deviated into horizontal direction with respect to the wiring layer. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a seal ring structure and a manufacturing method thereof.

  In the semiconductor process, first, semiconductor elements are successively formed on a wafer, and an IC circuit having a predetermined function is formed. Thereafter, the wafer is cut into chips along a lattice-shaped dicing line that surrounds the IC circuit. At this time, a protective film called a passivation film is formed on the surface of each chip cut in chip units as means for protecting the surface of the semiconductor device and avoiding the influence of the external atmosphere. However, a protective film is not formed on the diced side wall. Therefore, multiple layers of insulating films such as a silicon oxide film, a TEOS film, and an SOG film are exposed on the side wall, and are oxidized and corroded by contaminants from the outside. Further, when damage or cracks are generated in the insulating film at the time of cutting, moisture penetrates into the element from the damages or cracks. Here, in a multilayer wiring structure using the Cu damascene method, a low dielectric constant film is used as an interlayer insulating film in order to suppress capacitance between wirings. Since the Young's modulus is small and the strength is low, the occurrence of damage and cracks at the time of cutting is particularly remarkable. As a result, the metal film is oxidized and corroded, and moisture permeates into the semiconductor element. This causes a malfunction of the semiconductor device and the reliability of the semiconductor element is lowered.

  In order to prevent metal film oxidation / corrosion and to prevent moisture from penetrating into the semiconductor element from the cut part, dummy patterns (hereinafter referred to as pillars) are stacked from the lower layer to the upper layer so as to surround the chip along the dicing line. In other words, a so-called seal ring structure is employed (see, for example, Patent Document 1). In recent years, with the miniaturization and high integration of structures in semiconductor devices, the resistance of wiring has been reduced, and copper (Cu) having a relatively low resistance has been widely used as a wiring material. Cu is also frequently used in the structure.

  FIG. 8 is a cross-sectional view showing a semiconductor device having a conventional seal ring structure. In the figure, the left shows the element formation region Rlogic, and the right shows the seal ring formation region Rseal. Further, a scribe line region (not shown) exists further to the right of the seal ring formation region Rseal.

  In the element formation region Rlogic, a first liner insulating film 101 formed on a semiconductor substrate (not shown) on which elements such as transistors are formed, and a low dielectric constant formed on the first liner insulating film 101 are formed. The first interlayer insulating film 102 which is a rate film, the first cap insulating film 103 formed on the first interlayer insulating film 102, the first cap insulating film 103 and the first interlayer insulating film 102 The first wiring 112 made of the first barrier metal film 110a and the first Cu film 111a embedded in the formed wiring trench (not shown), and the first wiring 112 and an element such as a transistor are electrically connected. A first connection plug 113 integrally formed at the bottom of the first wiring 112 so as to be connected electrically, and a second liner formed on the first cap insulating film 103 including the first wiring 112 Insulating film 1 5, a second interlayer insulating film 116 which is a low dielectric constant film formed on the second liner insulating film 115, and a second cap insulating film 117 formed on the second interlayer insulating film 116, , A second barrier metal film 124a and a third Cu film 125a embedded in a wiring trench (not shown) formed in the second cap insulating film 117 and the second interlayer insulating film 116. A wiring 126 and a second connection plug 127 formed integrally with the bottom of the second wiring 126 so as to electrically connect the second wiring 126 and the first wiring 112 are formed.

  The seal ring formation region Rseal includes a first liner insulating film 101 formed on a semiconductor substrate (not shown) and a first low dielectric constant film formed on the first liner insulating film 101. Interlayer insulating film 102, first cap insulating film 103 formed on first interlayer insulating film 102, first cap insulating film 103, first interlayer insulating film 102, and first liner insulating film 101 The first pillar 114 made of the second barrier metal film 110b and the second Cu film 111b formed so as to penetrate the first cap 114, and the first cap insulating film 103 including the first pillar 114 2 liner insulating film 115, second interlayer insulating film 116 which is a low dielectric constant film formed on second liner insulating film 115, and second interlayer insulating film 116 formed on second interlayer insulating film 116. Cap insulation 117, the second cap insulating film 117, the second interlayer insulating film 116, and the second liner insulating film 115 are formed so as to penetrate the first supporting column 114 and have the same width as the first supporting column 114. A second support column 128 made of a fourth barrier metal film 124b and a fourth Cu film 125b is formed in contact with the upper surface of 114.

  Hereinafter, a method of manufacturing a semiconductor device having a conventional seal ring structure will be described with reference to the drawings.

  9 (a) to 9 (f) and FIGS. 10 (a) to 10 (f) are cross-sectional views showing a manufacturing process of a semiconductor device having a conventional seal ring structure.

  First, as shown in FIG. 9A, a first liner insulating film 101 is deposited by a CVD method on a silicon substrate (not shown) on which a semiconductor element such as a transistor is formed. Next, a first interlayer insulating film 102 which is a low dielectric constant film is deposited on the first liner insulating film 101 by a CVD method. Next, a first cap insulating film 103 is deposited on the first interlayer insulating film 102 by a CVD method.

  Next, as shown in FIG. 9B, the first through hole 105a is formed in the element formation region Rlogic on the first cap insulating film 103 by photolithography, and the first through hole 105a is formed in the seal ring formation region Rseal. A resist mask 104 having an opening for forming two through holes 105b is formed. Next, a first through hole 105a that penetrates the first cap insulating film 103 and the first interlayer insulating film 102 is formed in the element forming region Rlogic by dry etching, and the first cap is formed in the seal ring forming region Rseal. A second through-hole 105b that penetrates the insulating film 103 and the first interlayer insulating film 102 is formed. Thereafter, the resist mask 104 is removed by ashing.

  Next, as shown in FIG. 9C, a resist 106 is embedded in the first through hole 105 a and the second through hole 105 b, and then the first through hole is formed on the first cap insulating film 103. An ARC film 107 is deposited so as to fill the hole 105a and the second through hole 105b.

  Next, as shown in FIG. 9D, a resist mask 108 having an opening for forming the first wiring groove 109 in the element formation region Rlogic is formed on the ARC film 107 by photolithography. Next, part of the first cap insulating film 103 and the first interlayer insulating film 102 is removed by dry etching, and the first wiring trench 109 connected to the first through hole 105a in the element formation region Rlogic. Form. Thereafter, the resist mask 108, the ARC film 107, and the resist 106 are removed by ashing.

  Next, as shown in FIG. 9E, the first liner insulating film 101 at the bottom of the first through hole 105a and the second through hole 105b is removed by a dry etching method.

  Next, as shown in FIG. 9F, a first barrier metal for preventing Cu diffusion so as to cover the first through hole 105a, the first wiring groove 109, and the second through hole 105b by sputtering. (Not shown) is deposited. Subsequently, a first Cu (not shown) is formed by metal plating so as to bury the first through hole 105a, the first wiring groove 109, and the second through hole 105b on the first barrier metal. ). Thereafter, the first Cu and the first barrier metal are polished by CMP (Chemical Mechanical Polishing), and the first through hole 105a, the first wiring groove 109, and the second through hole 105b are polished. The first barrier metal and the first Cu are left inside, and the first cap insulating film 103 is exposed in a portion other than the first through hole 105a, the first wiring groove 109, and the second through hole 105b. As a result, the first wiring 112 made of the first barrier metal film 110a and the first Cu film 111a is formed in the element formation region Rlogic, and the second barrier metal film 110b and the second wiring are formed in the seal ring formation region Rseal. First pillars 114 made of two Cu films 111b are formed. At this time, the first wiring 112 and a semiconductor element such as a transistor are electrically connected by a first connection plug 113 formed integrally at the bottom of the first wiring 112.

  Next, as shown in FIG. 10A, a second liner insulating film 115 is deposited on the first cap insulating film 103 including the first wiring 112 and the first support pillar 114 by a CVD method. . Next, a second interlayer insulating film 116 that is a low dielectric constant film is deposited on the second liner insulating film 115 by CVD. Next, a second cap insulating film 117 is deposited on the second interlayer insulating film 116 by CVD.

  Next, as shown in FIG. 10B, a third through hole 119a is formed in the element formation region Rlogic on the second cap insulating film 117 by photolithography, and the third through hole 119a is formed in the seal ring formation region Rseal. A resist mask 118 having an opening for forming four through holes 119b is formed. At this time, the opening for forming the fourth through hole 119b is formed with the same width as the opening for forming the second through hole 105b. Next, a third through hole 119a that penetrates through the second cap insulating film 117 and the second interlayer insulating film 116 is formed in the element forming region Rlogic by dry etching, and the second cap is formed in the seal ring forming region Rseal. A fourth through hole 119b penetrating the insulating film 115 and the second interlayer insulating film 116 is formed. Thereafter, the resist mask 118 is removed by ashing.

  Next, as shown in FIG. 10C, a resist 120 is embedded in the third through hole 119a and the fourth through hole 119b, and then the third through hole is formed on the second cap insulating film 117. An ARC film 121 is deposited so as to fill the hole 119a and the fourth through hole 119b.

  Next, as shown in FIG. 10D, a resist mask 122 having an opening for forming the second wiring groove 123 in the element formation region Rlogic is formed on the ARC film 121 by photolithography. Next, a part of the second cap insulating film 117 and the second interlayer insulating film 116 is removed in the element formation region Rlogic by a dry etching method to form a second wiring groove connected to the third through hole 119a. 123 is formed. Thereafter, the resist mask 122, the ARC film 121, and the resist 120 are removed by ashing.

  Next, as shown in FIG. 10E, the second liner insulating film 115 at the bottom of the third through hole 119a and the fourth through hole 119b is removed by a dry etching method.

  Next, as shown in FIG. 10F, a second barrier metal for preventing Cu diffusion so as to cover the third through hole 119a, the second wiring groove 123, and the fourth through hole 119b by sputtering. (Not shown) is deposited. Subsequently, a second Cu (not shown) is formed by metal plating so as to fill the third through hole 119a, the second wiring groove 123, and the fourth through hole 119b on the second barrier metal. ). Thereafter, the second Cu and the second barrier metal are polished by a CMP method, and the second barrier metal and the first barrier metal in the third through hole 119a, the second wiring groove 123, and the fourth through hole 119b are polished. The second cap insulating film 116 is exposed in portions other than the third through hole 119a, the second wiring groove 123, and the fourth through hole 119b. As a result, the second wiring 126 made of the third barrier metal film 124a and the third Cu film 125a is formed in the element formation region Rlogic, and the fourth barrier metal film 124b and the second wiring 126 are formed in the seal ring formation region Rseal. Second pillars 128 made of four Cu films 125b are formed. At this time, the second wiring 126 and the first wiring 112 are electrically connected by the second connection plug 127 integrally formed at the bottom of the second wiring 126. The second support column 128 has the same width as the first support column 114, and the bottom surface of the second support column 128 and the top surface of the first support column 114 are in contact with the wiring layer in the horizontal direction. .

A semiconductor device having a seal ring structure as shown in FIG. 8 is formed by the processes of FIGS. 9A to 10F.
JP 2004-79596 A

  However, the following problems occur in a semiconductor device having a conventional seal ring structure. In a semiconductor device having a conventional seal ring structure, the upper surface of the first column 114 and the bottom surface of the second column 128 are in contact with each other with the same width. In other words, the width of the first support column 114 and the width of the second support column 128 are the same, and the wall surface of the second barrier metal film 110b that is the side wall of the first support column 114 and the side wall of the second support column 128. And the wall surface of the fourth barrier metal film 124b is formed so as to be continuous in a direction perpendicular to the wiring layer. Here, the barrier metal film is provided to prevent Cu diffusion, and the second Cu film 111b is surrounded by the second barrier metal film 110b on the bottom and side surfaces thereof, and the fourth barrier metal film on the top surface. 124b is covered. A seal ring structure in which pillars are stacked like a wall surrounding a chip in each layer has, for example, an interface between an insulating film and an insulating film such as an interface between the first cap insulating film 103 and the second liner insulating film 115. There are many interfaces between the barrier metal film and the insulating film, such as the interface between the fourth barrier metal film 124b and the second liner insulating film 115. And in the periphery of the support | pillar in which many interfaces of different materials exist in this way, the adhesiveness of films | membranes is weak. Therefore, when a force is applied in the horizontal direction to the wiring layer by CMP, a film shift at the insulating film-insulating film interface tends to occur, and accordingly, the wiring is connected in the vertical direction with respect to the wiring layer of the seal ring structure. The barrier metal film is also displaced in the horizontal direction. Also, annealing after deposition of the low dielectric constant film may cause a film shift due to a difference in thermal expansion coefficient between the barrier metal film and the insulating film. As a result, the wall surface of the second barrier metal film 110b and the wall surface of the fourth barrier metal film 124b that are vertically connected to each other are displaced in the horizontal direction with respect to the wiring layer, and further, the second barrier metal film 110b and the fourth barrier metal film Thus, the upper surface of the second Cu film 111b above the first wiring trench 109 is not blocked by the fourth barrier metal film 124b. At this time, the phenomenon that the second Cu film 111b oozes out and diffuses to the interface between the first cap insulating film 103 and the second liner insulating film 115 on the element forming region Rlogic side, thereby reducing the reliability of the element. Occurs.

  The present invention provides a highly reliable semiconductor device that suppresses the seepage of Cu even when the pillars stacked in each layer are displaced in the horizontal direction with respect to the wiring layer by CMP of the upper layer or annealing after film deposition. The purpose is to provide.

  A semiconductor device according to the present invention includes a first insulating film formed on a semiconductor substrate, a first wiring embedded in a first wiring groove formed in the first insulating film, and a first wiring A first pillar embedded in the first through-hole formed in the insulating film; a second insulating film formed on the first insulating film; and a second insulating film formed on the second insulating film. In the semiconductor device having the second wiring buried in the wiring trench and the second pillar buried in the second through hole formed in the second insulating film, the bottom surface of the second pillar is At least a part of the upper surface of the first support column and a part of the upper surface of the first insulating film on the element formation region side are covered.

  Thereby, even if the struts stacked in each layer are displaced in the horizontal direction with respect to the wiring layer, it is possible to suppress Cu from seeping out at least toward the element formation region.

  In the semiconductor device according to the present invention, the width of the second column is wider than the width of the first column, and the bottom surface of the second column covers the entire top surface of the first column.

  The semiconductor device according to the present invention has a third support column embedded in a third through hole formed in the second insulating film, and the bottom surface of the second support column is at least the first support column. A part of the upper surface on the element formation region side is covered, and the bottom surface of the third support column covers at least a part of the upper surface on the scribe line side of the first support column.

  In the semiconductor device according to the present invention, the first support column is made of barrier metal and copper.

  In the semiconductor device according to the present invention, the first insulating film includes at least a low dielectric constant film.

  The method for manufacturing a semiconductor device according to the present invention includes a step (a) of forming a first wiring groove and a first through hole in a first insulating film formed on a semiconductor substrate, and a first wiring groove. (B) embedding the first wiring in the first through hole and embedding the first support pillar in the first through hole, and forming the second insulating film on the first insulating film after the step (b) (C), a step (d) of forming a second wiring groove and a second through hole in the second insulating film, and the second wiring is embedded in the second wiring groove, and the second through hole is formed. A step (e) of embedding the second support column, wherein the bottom surface of the second support column is a part of the upper surface of the first support column and the first insulating film at least on the element formation region side of the first support column Cover a part of the top surface of.

  Thereby, even if the struts stacked in each layer are displaced in the horizontal direction with respect to the wiring layer, it is possible to suppress Cu from seeping out at least toward the element formation region.

  In addition, in the method of manufacturing a semiconductor device according to the present invention, in the step (d), the second through hole is connected to the second insulating film at the upper part on the element forming region side of the first support column. In the step (e), a third through-hole connected at the upper part of the first column on the scribe line region side is formed. At the same time as the second wiring and the second column are embedded, A third column is embedded in the third through hole.

  Thereby, even if the struts stacked in each layer are displaced in the horizontal direction with respect to the wiring layer, it is possible to suppress Cu from seeping out at least toward the element formation region, and further, the second strut And the third support column have a low dielectric constant film, so that the dielectric constant can be reduced and the wiring capacitance can be reduced.

  In the method for manufacturing a semiconductor device according to the present invention, the bottom surface of the third support column covers a part of the top surface of the first support column on the scribe line region side.

  In the method for manufacturing a semiconductor device according to the present invention, the first support column is made of a barrier metal and copper.

  In the method for manufacturing a semiconductor device according to the present invention, the first insulating film includes at least a low dielectric constant film.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, even if the pillars stacked in each layer as the seal ring are displaced in the horizontal direction with respect to the wiring layer, the seepage of Cu can be suppressed. .

(First embodiment)
FIG. 1 is a cross-sectional view showing the semiconductor device according to the first embodiment. In the figure, the left shows the element formation region Rlogic, and the right shows the seal ring formation region Rseal. Further, a scribe line region (not shown) exists further to the right of the seal ring formation region Rseal.

  In the element formation region Rlogic, a first liner insulating film 201 formed on a semiconductor substrate (not shown) on which elements such as transistors are formed, and a low dielectric constant formed on the first liner insulating film 201 are formed. The first interlayer insulating film 202, which is an index film, the first cap insulating film 203 formed on the first interlayer insulating film 202, the first cap insulating film 203, and the first interlayer insulating film 202 The first wiring 212 made of the first barrier metal film 210a and the first Cu film 211a embedded in the formed wiring trench (not shown), and the first wiring 212 and an element such as a transistor are electrically connected. A first connection plug 213 formed integrally with the first wiring 212 so as to be connected electrically, and a second liner insulating film formed on the first cap insulating film 203 including the first wiring 212 215 and A second interlayer insulating film 216, which is a low dielectric constant film formed on the second liner insulating film 215, a second cap insulating film 217 formed on the second interlayer insulating film 216, A second wiring 226 made of a third barrier metal film 224a and a third Cu film 225a embedded in a wiring groove (not shown) formed in the cap insulating film 217 and the second interlayer insulating film 216; A second connection plug 227 formed integrally with the second wiring 226 is formed so as to electrically connect the second wiring 226 and an element such as a transistor.

  The seal ring formation region Rseal includes a first liner insulating film 201 formed on a semiconductor substrate (not shown) and a first low dielectric constant film formed on the first liner insulating film 201. The interlayer insulating film 202, the first cap insulating film 203 formed on the first interlayer insulating film 202, the first cap insulating film 203, the first interlayer insulating film 202, and the first liner insulating film 201 The first pillar 214 made of the second barrier metal film 210b and the second Cu film 211b formed so as to penetrate the first cap insulating film 203 and the first cap insulating film 203 including the first pillar 214 2 liner insulating film 215, a second interlayer insulating film 216 that is a low dielectric constant film formed on second liner insulating film 215, and a second interlayer insulating film 216 formed on second interlayer insulating film 216. Cap insulation 217, the second cap insulating film 217, the second interlayer insulating film 216, and the second liner insulating film 215, and wider than the width of the first column 214, A fourth barrier metal film 224b and a second pillar 228 made of the fourth Cu film 225b are formed to cover the upper surface of the pillar 214.

  In the semiconductor device according to the first embodiment, since the width of the second support column 228 is wider than the width of the first support column 214, the second barrier metal film 210 b on the upper portion of the first support column 214. And the first liner insulating film 215 are sufficiently covered with the bottom surface of the second support column 228, that is, the fourth barrier metal film 224b. As a result, even if the pillars stacked in each layer by CMP of the upper layer or annealing after film deposition are displaced in the horizontal direction with respect to the wiring layer, the second Cu film 211b becomes the fourth barrier metal film 224b. Since it is not exposed without being covered with copper, the seepage of Cu can be suppressed.

  Although the dual damascene structure has been described in the present embodiment, the present invention can also be applied to the case where a single damascene structure is used.

(Method for Manufacturing Semiconductor Device According to First Embodiment)
The semiconductor device manufacturing method according to the first embodiment will be described below with reference to the drawings.

  FIGS. 2A to 2F and FIGS. 3A to 3F are cross-sectional views illustrating manufacturing steps of the semiconductor device having the seal ring structure of the first embodiment.

  First, as shown in FIG. 2A, a first liner insulating film 201 is deposited to a thickness of 100 nm, for example, on a silicon substrate (not shown) on which a semiconductor element such as a transistor is formed by CVD. . Here, as the first liner insulating film 201, for example, SiC is used. Next, a first interlayer insulating film 202 is deposited, for example, to a thickness of 500 nm on the first liner insulating film 201 by CVD. Here, as the first interlayer insulating film 202, for example, a SiOC film or a SiOF film which is a low dielectric constant film is used. Next, a first cap insulating film 203 is deposited, for example, to a thickness of 100 nm on the first interlayer insulating film 202 by CVD. Here, as the first cap insulating film 203, for example, FSG is used.

  Next, as shown in FIG. 2B, the first through hole 205a is formed in the element formation region Rlogic on the first cap insulating film 203 by photolithography, and the first through hole 205a is formed in the seal ring formation region Rseal. A resist mask 204 having an opening for forming two through holes 205b is formed. Next, a first through hole 205a that penetrates the first cap insulating film 203 and the first interlayer insulating film 202 is formed in the element formation region Rlogic by dry etching, and the first cap is formed in the seal ring formation region Rseal. A second through hole 205b that penetrates the insulating film 203 and the first interlayer insulating film 202 is formed. Thereafter, the resist mask 204 is removed by ashing.

  Next, as illustrated in FIG. 2C, a resist 206 is embedded in the first through hole 205 a and the second through hole 205 b, for example, with a thickness of 300 nm, and then on the first cap insulating film 203. Then, an ARC film 207 is deposited so as to fill the first through hole 205a and the second through hole 205b.

  Next, as shown in FIG. 2D, a resist mask 208 having an opening for forming the first wiring groove 209 in the element formation region Rlogic is formed on the ARC film 207 by photolithography. Next, a part of the first cap insulating film 203 and the first interlayer insulating film 202 is removed in the element formation region Rlogic by a dry etching method to form a first wiring trench connected to the first through hole 205a. 209 is formed. Thereafter, the resist mask 208, the ARC film 207, and the resist 206 are removed by ashing.

  Next, as shown in FIG. 2E, the first liner insulating film 201 at the bottom of the first through hole 205a and the second through hole 205b is removed by a dry etching method.

  Next, as shown in FIG. 2 (f), a first barrier metal for preventing Cu diffusion so as to cover the first through hole 205a, the first wiring groove 209, and the second through hole 205b by sputtering. (Not shown) is deposited, and then the first through hole 205a, the first wiring groove 209, and the second through hole 205b are embedded on the first barrier metal by metal plating. First Cu (not shown) is deposited. Thereafter, the first Cu and the first barrier metal are polished by a CMP method, and the first barrier metal and the first barrier metal in the first through hole 205a, the first wiring groove 209, and the second through hole 205b are polished. The first cap insulating film 203 is exposed in portions other than the first through hole 205a, the first wiring groove 209, and the second through hole 205b. As a result, the first wiring 212 made of the first barrier metal film 210a and the first Cu film 211a is formed in the element formation region Rlogic, and the second barrier metal film 210b and the second wiring are formed in the seal ring formation region Rseal. First pillars 214 made of two Cu films 211b are formed. At this time, the first wiring 212 and a semiconductor element such as a transistor are electrically connected by a first connection plug 213 integrally formed at the bottom of the first wiring 212.

  Next, as shown in FIG. 3A, a second liner having a thickness of, for example, 100 nm is formed on the first cap insulating film 203 including the first wiring 212 and the first support column 214 by a CVD method. An insulating film 215 is deposited. Here, as the second liner insulating film 215, for example, SiC is used. Next, a second interlayer insulating film 216 having a thickness of, for example, 500 nm is deposited on the second liner insulating film 215 by CVD. Here, as the second interlayer insulating film 216, for example, a SiOC film or a SiOF film which is a low dielectric constant film is used. Next, a second cap insulating film 217 having a thickness of 100 nm, for example, is deposited on the second interlayer insulating film 216 by CVD. Here, as the second cap insulating film 217, for example, FSG is used.

  Next, as shown in FIG. 3B, the third through hole 219a is formed in the element formation region Rlogic on the second cap insulating film 217 by photolithography, and the second through hole 219a is formed in the seal ring formation region Rseal. A resist mask 218 having an opening for forming four through holes 219b is formed. At this time, the opening for forming the fourth through hole 219b is formed with a wider width than the opening for forming the second through hole 205b. For example, if the width of the opening for forming the second through hole 205b is 150 nm, the width of the opening for forming the fourth through hole 219b is 200 nm. Next, a third through hole 219a that penetrates through the second cap insulating film 217 and the second interlayer insulating film 216 is formed in the element forming region Rlogic by dry etching, and the second through hole is formed in the seal ring forming region Rseal. A fourth through hole 219b penetrating through the cap insulating film 217 and the second interlayer insulating film 216 is formed. Thereafter, the resist mask 218 is removed by ashing.

  Next, as shown in FIG. 3C, a resist 220 is embedded in the third through hole 219a and the fourth through hole 219b, for example, with a thickness of 300 nm, and then on the second cap insulating film 217. Then, an ARC film 221 is deposited so as to fill the third through hole 219a and the fourth through hole 219b.

  Next, as shown in FIG. 3D, a resist mask 222 having an opening for forming the second wiring trench 223 in the element formation region Rlogic is formed on the ARC film 221 by photolithography. Next, a part of the second cap insulating film 217 and the second interlayer insulating film 216 is removed in the element formation region Rlogic by a dry etching method to form a second wiring groove connected to the third through hole 219a. 223 is formed. Thereafter, the resist mask 222, the ARC film 221 and the resist 220 are removed by ashing.

  Next, as shown in FIG. 3E, the second liner insulating film 215 at the bottom of the third through hole 219a and the fourth through hole 219b is removed by a dry etching method.

  Next, as shown in FIG. 3F, a second barrier metal for preventing Cu diffusion so as to cover the third through hole 219a, the second wiring groove 223, and the fourth through hole 219b by sputtering. (Not shown) is deposited, and then the third through hole 219a, the second wiring groove 223, and the fourth through hole 219b are embedded on the second barrier metal by metal plating. Second Cu (not shown) is deposited. Thereafter, the second Cu and the second barrier metal are polished by the CMP method, and the second barrier metal and the second barrier metal in the third through hole 219a, the second wiring groove 223, and the fourth through hole 219b are polished. The second cap insulating film 217 is exposed in portions other than the third through hole 219a, the second wiring groove 223, and the fourth through hole 219b. As a result, the second wiring 226 made of the third barrier metal film 224a and the third Cu film 225a is formed in the element formation region Rlogic, and the fourth barrier metal film 224b and the second barrier metal film 224b are formed in the seal ring formation region Rseal. Second pillars 228 made of four Cu films 225b are formed. At this time, the second wiring 226 and the first wiring 212 are electrically connected by a second connection plug 227 integrally formed at the bottom of the second wiring 226. The second support column 228 is wider than the first support column 214, and the bottom surface of the second support column 228 covers the upper surface of the first support column 214.

  2A to 3F, a semiconductor device having a seal ring structure as shown in FIG. 1 is formed.

(Modification of the first embodiment)
FIG. 4 is a cross-sectional view showing a semiconductor device according to a modification of the first embodiment. In the figure, the left shows the element formation region Rlogic, and the right shows the seal ring formation region Rseal. Further, a scribe line region (not shown) exists further to the right of the seal ring formation region Rseal.

  In the element formation region Rlogic, a first liner insulating film 201 formed on a semiconductor substrate (not shown) on which elements such as transistors are formed, and a low dielectric constant formed on the first liner insulating film 201 are formed. The first interlayer insulating film 202, which is an index film, the first cap insulating film 203 formed on the first interlayer insulating film 202, the first cap insulating film 203, and the first interlayer insulating film 202 The first wiring 212 made of the first barrier metal film 210a and the first Cu film 211a embedded in the formed wiring trench (not shown), and the first wiring 212 and an element such as a transistor are electrically connected. A first connection plug 213 formed integrally with the first wiring 212 so as to be connected electrically, and a second liner insulating film formed on the first cap insulating film 203 including the first wiring 212 215 and A second interlayer insulating film 216, which is a low dielectric constant film formed on the second liner insulating film 215, a second cap insulating film 217 formed on the second interlayer insulating film 216, A second wiring 226 made of a third barrier metal film 224a and a third Cu film 225a embedded in a wiring groove (not shown) formed in the cap insulating film 217 and the second interlayer insulating film 216; A second connection plug 227 formed integrally with the second wiring 226 is formed so as to electrically connect the second wiring 226 and an element such as a transistor.

  The seal ring formation region Rseal includes a first liner insulating film 201 formed on a semiconductor substrate (not shown) and a first low dielectric constant film formed on the first liner insulating film 201. The interlayer insulating film 202, the first cap insulating film 203 formed on the first interlayer insulating film 202, the first cap insulating film 203, the first interlayer insulating film 202, and the first liner insulating film 201 The first pillar 214 made of the second barrier metal film 210b and the second Cu film 211b formed so as to penetrate the first cap insulating film 203 and the first cap insulating film 203 including the first pillar 214 2 liner insulating film 215, a second interlayer insulating film 216 that is a low dielectric constant film formed on second liner insulating film 215, and a second interlayer insulating film 216 formed on second interlayer insulating film 216. Cap insulation 217, the second cap insulating film 217, the second interlayer insulating film 216, and the second liner insulating film 215, and wider than the width of the first column 214, A second pillar 228 made of a fourth barrier metal film 224b and a fourth Cu film 225b is formed to cover at least the upper surface of the pillar 214 on the element formation region Rlogic side.

  In the semiconductor device according to the modification of the first embodiment, the width of the second support column 228 is wider than the width of the first support column 214, and the second support column 228 is more element than the first support column 214. By projecting to the formation consideration region Rlogic side, the interface between the second barrier metal film 210b and the first liner insulating film 203 on at least the element formation region Rlogic side of the first support column 214 is the second support column 228. Is sufficiently covered with the fourth barrier metal film 224b. As a result, even if the pillars stacked in each layer are displaced in the horizontal direction with respect to the wiring layer by CMP of the upper layer or annealing after film deposition, the second Cu film 211b is formed on the element formation region Rlogic side. No barrier metal film 224b is exposed and exposed, so that it is possible to suppress the seepage of Cu to the element formation region Rlogic side.

  The manufacturing method of the semiconductor device according to the modification of the first embodiment is basically the same as the manufacturing method shown in FIGS. 2A to 3F of the first embodiment. Is omitted.

(Second Embodiment)
FIG. 5 is a sectional view showing a semiconductor device according to the second embodiment. In the figure, the left shows the element formation region Rlogic, and the right shows the seal ring formation region Rseal. Further, a scribe line region (not shown) exists further to the right of the seal ring formation region Rseal.

  The element formation region Rlogic includes a first liner insulating film 301 formed on a semiconductor substrate (not shown) on which elements such as transistors are formed, and a low dielectric formed on the first liner insulating film 301. A first interlayer insulating film 302 that is an index film, a first cap insulating film 303 formed on the first interlayer insulating film 302, a first cap insulating film 303, and a first interlayer insulating film 302; The first wiring 312 made of the first barrier metal film 310a and the first Cu film 311a embedded in the formed wiring trench (not shown), and the first wiring 312 and an element such as a transistor are electrically connected. A first connection plug 313 integrally formed with the first wiring 312 so as to be connected electrically, and a second liner insulating film formed on the first cap insulating film 303 including the first wiring 312 315 and A second interlayer insulating film 316 that is a low dielectric constant film formed on the second liner insulating film 315, a second cap insulating film 317 formed on the second interlayer insulating film 316, and a second A second wiring 326 composed of a third barrier metal film 324a and a third Cu film 325a embedded in a wiring groove (not shown) formed in the cap insulating film 317 and the second interlayer insulating film 316; A second connection plug 327 formed integrally with the second wiring 326 is formed so as to electrically connect the second wiring 326 and an element such as a transistor.

  The seal ring formation region Rseal includes a first liner insulating film 301 formed on a semiconductor substrate (not shown) and a first low dielectric constant film formed on the first liner insulating film 301. Interlayer insulating film 302, first cap insulating film 303 formed on first interlayer insulating film 302, first cap insulating film 303, first interlayer insulating film 302, and first liner insulating film 301 The first support column 314 made of the second barrier metal film 310b and the second Cu film 311b formed so as to penetrate the first cap insulating film 303, and the first support insulating film 303 formed on the first cap insulating film 303 including the first support column 314. 2 liner insulating films 315, a second interlayer insulating film 316 that is a low dielectric constant film formed on the second liner insulating film 315, and a second interlayer insulating film 316 formed on the second interlayer insulating film 316. Cap insulation 317, a second cap insulating film 317, a second interlayer insulating film 316, and a second liner insulating film 315 are formed to penetrate the fourth cap insulating film 315 and cover the upper surface of the first support column 314 on the element forming region Rlogic side. The second pillar 328 made of the barrier metal film 324b and the fourth Cu film 325b, the second cap insulating film 317, the second interlayer insulating film 316, and the second liner insulating film 315 are formed to penetrate. A third support column 329 made of a fifth barrier metal film 324c and a fifth Cu film 325c is formed so as to cover the upper surface of the first support column 314 on the scribe line region side.

  In the semiconductor device according to the second embodiment, since the second support 328 is provided, the second barrier metal film 310b and the first liner insulating film 303 on the upper side of the first support 314 on the element formation region Rlogic side are provided. Is sufficiently covered by the bottom surface of the second support column 328, that is, the fourth barrier metal film 324b, and the third support column 329 is provided so that the first support column 314 has an upper portion on the scribe line region side. The interface between the second barrier metal film 310b and the first liner insulating film 303 is sufficiently covered with the bottom surface of the third support column 329, that is, the fifth barrier metal film 324c. As a result, even if the pillars stacked in each layer are displaced in the horizontal direction with respect to the wiring layer by CMP of the upper layer or annealing after film deposition, the second Cu film 311b is formed on the element formation region Rlogic side. Since no barrier metal film 324b is exposed and exposed, Cu exudation can be suppressed. In addition, the semiconductor device according to the second embodiment has a structure having a low dielectric constant film between the second support column 328 and the third support column 329, and therefore has a lower dielectric constant than that of the first embodiment. The rate can be increased, and the wiring capacity can be reduced.

  Although the dual damascene structure has been described in the present embodiment, the present invention can also be applied to the case where a single damascene structure is used.

(Method for Manufacturing Semiconductor Device According to Second Embodiment)
A method for manufacturing a semiconductor device according to the second embodiment will be described below with reference to the drawings.

  FIGS. 6A to 6F and FIGS. 7A to 7F are cross-sectional views illustrating a manufacturing process of a semiconductor device having the seal ring structure of the second embodiment.

  First, as shown in FIG. 6A, a first liner insulating film 301 is deposited to a thickness of, for example, 100 nm on a silicon substrate (not shown) on which a semiconductor element such as a transistor is formed by a CVD method. . Here, as the first liner insulating film 301, for example, SiC is used. Next, a first interlayer insulating film 302 is deposited to a thickness of, for example, 500 nm on the first liner insulating film 301 by CVD. Here, as the first interlayer insulating film 302, for example, a SiOC film or a SiOF film which is a low dielectric constant film is used. Next, a first cap insulating film 303 is deposited to a thickness of, for example, 100 nm on the first interlayer insulating film 302 by a CVD method. Here, as the first cap insulating film 303, for example, FSG is used.

  Next, as shown in FIG. 6B, a first through hole 305a is formed in the element formation region Rlogic on the first cap insulating film 303 by photolithography, and the first through hole 305a is formed in the seal ring formation region Rseal. A resist mask 304 having an opening for forming two through holes 305b is formed. Next, a first through hole 305a that penetrates the first cap insulating film 303 and the first interlayer insulating film 302 is formed in the element forming region Rlogic by dry etching, and the first through hole 305a is formed in the seal ring forming region Rseal. A second through-hole 305b that penetrates through the cap insulating film 303 and the first interlayer insulating film 302 is formed. Thereafter, the resist mask 304 is removed by ashing.

  Next, as illustrated in FIG. 6C, a resist 306 is embedded in the first through hole 305 a and the second through hole 305 b, for example, with a thickness of 300 nm, and then on the first cap insulating film 303. Then, an ARC film 307 is deposited so as to fill the first through hole 305a and the second through hole 305b.

  Next, as illustrated in FIG. 6D, a resist mask 308 having an opening for forming the first wiring groove 309 in the element formation region Rlogic is formed on the ARC film 307 by photolithography. Next, a part of the first cap insulating film 303 and the first interlayer insulating film 302 is removed in the element formation region Rlogic by a dry etching method to form a first wiring trench connected to the first through hole 305a. 309 is formed. Thereafter, the resist mask 308, the ARC film 307, and the resist 306 are removed by ashing.

  Next, as shown in FIG. 6E, the first liner insulating film 301 at the bottom of the first through hole 305a and the second through hole 305b is removed by a dry etching method.

  Next, as shown in FIG. 6 (f), a first barrier metal for preventing Cu diffusion so as to cover the first through hole 305a, the first wiring groove 309, and the second through hole 305b by sputtering. (Not shown) is deposited, and then the first through hole 305a, the first wiring groove 309 and the second through hole 305b are embedded on the first barrier metal by metal plating. First Cu (not shown) is deposited. Thereafter, the first Cu and the first barrier metal are polished by a CMP method, and the first barrier metal and the first barrier metal in the first through hole 305a, the first wiring groove 309, and the second through hole 305b are polished. The first cap insulating film 303 is exposed in portions other than the first through hole 305a, the first wiring groove 309, and the second through hole 305b. As a result, the first wiring 312 including the second barrier metal film 310a and the first Cu film 311a is formed in the element formation region Rlogic, and the second barrier metal film 310b and the second wiring are formed in the seal ring formation region Rseal. First pillars 314 made of one Cu film 311b are formed. At this time, the first wiring 312 and a semiconductor element such as a transistor are electrically connected by a first connection plug 313 integrally formed at the bottom of the first wiring 312.

  Next, as shown in FIG. 7A, a second liner having a thickness of, for example, 100 nm is formed on the first cap insulating film 303 including the first wiring 312 and the first support column 314 by CVD, for example. An insulating film 315 is deposited. Here, as the second liner insulating film 315, for example, SiC is used. Next, a second interlayer insulating film 316 having a thickness of, for example, 500 nm is deposited on the second liner insulating film 315 by CVD. Here, as the second interlayer insulating film 316, for example, a SiOC film or a SiOF film which is a low dielectric constant film is used. Next, a second cap insulating film 317 having a thickness of, for example, 100 nm is deposited on the second interlayer insulating film 316 by CVD. Here, as the second cap insulating film 317, for example, FSG is used.

  Next, as shown in FIG. 7B, the third through hole 319a is formed in the element formation region Rlogic on the second cap insulating film 317 by photolithography, and the second through hole 319a is formed in the seal ring formation region Rseal. A resist mask 318 having an opening for forming the fourth through hole 319b and the fifth through hole 319c is formed. At this time, the openings for forming the fourth through hole 319b and the fifth through hole 319c are the upper part of the upper end of the first support column 314 on the element formation region Rlogic side and the scribe line region of the first support column 314. It is formed so as to cover the upper part of the side. Next, a third through hole 319a that penetrates through the second cap insulating film 317 and the second interlayer insulating film 316 is formed in the element forming region Rlogic by dry etching, and the second through hole 319a is formed in the seal ring forming region Rseal. A fourth through hole 319b and a fifth through hole 319c penetrating through the cap insulating film 317 and the second interlayer insulating film 316 are formed. Thereafter, the resist mask 318 is removed by ashing.

  Next, as shown in FIG. 7C, a resist 320 is buried in the third through hole 319a, the fourth through hole 319b, and the fifth through hole 319c, for example, with a thickness of 300 nm, and then On the second cap insulating film 317, an ARC film 321 is deposited so as to fill the third through hole 319a, the fourth through hole 319b, and the fifth through hole 319c.

  Next, as shown in FIG. 7D, a resist mask 322 having an opening in the element formation region Rlogic is formed on the ARC film 321 by photolithography. Next, a part of the second cap insulating film 317 and the second interlayer insulating film 316 is removed in the element formation region Rlogic by a dry etching method to form a second wiring trench connected to the third through hole 319a. 323 is formed. Thereafter, the resist mask 322, the ARC film 321 and the resist 320 are removed by ashing.

  Next, as shown in FIG. 7E, the second liner insulating film 315 at the bottom of the third through hole 319a, the fourth through hole 319b, and the fifth through hole 319c is removed by dry etching. To do.

  Next, as shown in FIG. 7F, Cu diffusion is performed so as to cover the third through hole 319a, the second wiring groove 323, the fourth through hole 319b, and the fifth through hole 319c by sputtering. A second barrier metal (not shown) for prevention is deposited, and then a third through hole 319a, a second wiring groove 323, a fourth wire are formed on the second barrier metal by metal plating. Second Cu (not shown) is deposited so as to fill the through hole 319b and the fifth through hole 319c. Thereafter, the second Cu and the second barrier metal are polished by CMP, and the second through hole 319a, the second wiring groove 323, the fourth through hole 319b, and the fifth through hole 319c are polished. The second cap insulating film 317 is left in a portion other than the third through hole 319a, the second wiring groove 323, the fourth through hole 319b, and the fifth through hole 319c, leaving the second barrier metal and the first Cu. To expose. As a result, the second wiring 326 made of the third barrier metal film 324a and the third Cu film 325a is formed in the element formation region Rlogic, and the fourth barrier metal film 324b and the second wiring 326 are formed in the seal ring formation region Rseal. The second support column 328 made of the fourth Cu film 325b and the third support column 329 made of the fifth barrier metal film 324c and the fifth Cu film 325c are formed. At this time, the second wiring 326 and the first wiring 312 are electrically connected by a second connection plug 327 integrally formed at the bottom of the second wiring 326. The bottom surface of the second support column 328 covers the upper surface of the first support column 314 on the element formation region Rlogic side, and the bottom surface of the third support column 329 covers the upper surface of the first support column 314 on the scribe line region side. ing.

  6A to 7F, a semiconductor device having a seal ring structure as shown in FIG. 5 is formed.

  The semiconductor device of the present invention can be used in a semiconductor device having a seal ring structure and a manufacturing method thereof.

Sectional drawing which shows the semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the semiconductor device which concerns on the modification of the 1st Embodiment of this invention. Sectional drawing which shows the semiconductor device which concerns on the 2nd Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. Sectional drawing which shows the semiconductor device which has the conventional seal ring structure Sectional drawing which shows the manufacturing process of the semiconductor device which has the conventional seal ring structure Sectional drawing which shows the manufacturing process of the semiconductor device which has the conventional seal ring structure

Explanation of symbols

201 first liner insulating film 202 first interlayer insulating film 203 first cap insulating film 204 resist mask 205a first through hole 205b second through hole 206 resist 207 ARC film 208 resist mask 209 first wiring groove 210a First barrier metal film 210b Second barrier metal film 211a First Cu film 211b Second Cu film 212 First wiring 213 First connection plug 214 First support column 215 Second liner insulating film 216 Second interlayer insulating film 217 Second cap insulating film 218 Resist mask 219a Third through hole 219b Fourth through hole 220 Resist 221 ARC film 222 Resist mask 223 Second wiring groove 224a Third barrier metal film 224b 4th barrier metal 225a 3rd Cu film 225b 4th Cu film 226 2nd wiring 227 2nd connection plug 228 2nd support | pillar 301 1st liner insulation film 302 1st interlayer insulation film 303 1st cap insulation film 304 Resist mask 305a First through hole 305b Second through hole 306 Resist 307 ARC film 308 Resist mask 309 First wiring groove 310a First barrier metal film 310b Second barrier metal film 311a First Cu film 311b Second 2 Cu film 312 1st wiring 313 1st connection plug 314 1st support | pillar 315 2nd liner insulating film 316 2nd interlayer insulating film 317 2nd cap insulating film 318 resist mask 319a 3rd through hole 319b 4th through hole 319c 5th through hole 320 resist 321 ARC film 322 resist mask 323 second wiring groove 324a third barrier metal film 324b fourth barrier metal film 324c fifth barrier metal film 325a third Cu film 325b fourth Cu film 325c fifth Cu film 326 Second wiring 327 Second connection plug 328 Second support 329 Third support

Claims (10)

A first insulating film formed on a semiconductor substrate; a first wiring embedded in a first wiring groove formed in the first insulating film; and a first insulating film formed on the first insulating film. In the first pillar embedded in the first through hole, the second insulating film formed on the first insulating film, and the second wiring groove formed in the second insulating film In a semiconductor device having a buried second wiring and a second support pillar buried in a second through hole formed in the second insulating film,
The semiconductor device according to claim 1, wherein a bottom surface of the second support column covers at least a part of the upper surface of the first support column and a part of the upper surface of the first insulating film on the element formation region side. The semiconductor device according to claim 1,
The width of the second column is wider than the width of the first column, and the bottom surface of the second column covers the entire top surface of the first column. The semiconductor device according to claim 1,
A third support column embedded in a third through hole formed in the second insulating film;
The bottom surface of the second support column covers at least a part of the upper surface of the first support column on the element formation region side,
The bottom surface of the third support column covers at least a part of the upper surface of the first support column on the scribe line side. The semiconductor device according to any one of claims 1 to 3,
The semiconductor device according to claim 1, wherein the first support column is made of a barrier metal and copper. The semiconductor device according to any one of claims 1 to 4,
The semiconductor device, wherein the first insulating film includes at least a low dielectric constant film. Forming a first wiring groove and a first through hole in a first insulating film formed on the semiconductor substrate;
A step (b) of embedding a first wiring in the first wiring groove and embedding a first support in the first through hole;
(C) forming a second insulating film on the first insulating film after the step (b);
Forming a second wiring trench and a second through hole in the second insulating film (d);
A step (e) of embedding a second wiring in the second wiring groove and embedding a second support in the second through hole,
The method of manufacturing a semiconductor device, wherein the bottom surface of the second support column covers at least a part of the upper surface of the first support column and a part of the upper surface of the first insulating film on the element formation region side. In the manufacturing method of the semiconductor device according to claim 6,
In the step (d), the second wiring hole and the second through hole connected to the upper portion of the first support on the element formation region side are formed simultaneously with the second insulating film. Forming a third through hole to be connected at the upper part of the scribe line region side of the one column;
In the step (e), the third pillar is buried in the third through hole at the same time as the second wiring and the second pillar are buried. In the manufacturing method of the semiconductor device according to claim 8,
The method of manufacturing a semiconductor device, wherein the bottom surface of the third support column covers a part of the upper surface of the first support column on the scribe line region side. In the manufacturing method of the semiconductor device of Claims 6-8,
The method of manufacturing a semiconductor device, wherein the first support column is made of a barrier metal and copper. In the manufacturing method of the semiconductor device of any one of Claims 6-9,
The method of manufacturing a semiconductor device, wherein the first insulating film includes at least a low dielectric constant film.

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