JP2006128720A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the deterioration of mechanical strength in entire elements, and to reduce the delay of a signal propagating through wiring. <P>SOLUTION: First and third insulating layers for composing each wiring layer 100 contain a silicon carbonitride film, silicon carbide, and/or silicon oxide. A second insulating layer in a lower wiring layer contains the silicon oxide. A second insulating layer in an upper wiring layer contains fluorinated silicon oxide and/or carbonated silicon oxide. The specific dielectric constant of the second insulating layer in the lower wiring layer is set smaller than that of the second insulating layer in the upper wiring layer. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device in which signal wiring delay is reduced by using an insulating film having low dielectric constant characteristics as an interlayer insulating film, thereby improving element performance.

  Along with the high integration of semiconductor elements and the reduction in chip size, the miniaturization of wiring, the narrowing of pitch, and the multilayering are being promoted. Along with this, there is a tendency that the delay time when the signal propagates through the wiring, that is, the wiring delay increases, which is a serious problem when using an electronic device using a semiconductor element.

  In general, since the speed of a signal propagating through a wiring is determined by the product (RC) of the wiring resistance (R) and the capacitance (C) between the wirings, the wiring resistance is lowered or the capacitance between the wirings is reduced, that is, an interlayer insulating film. It is necessary to reduce the dielectric constant in order to reduce the wiring delay.

  In order to lower the wiring resistance, in high-performance semiconductor elements, the wiring material is being changed from aluminum to copper. In particular, damascene process embedding copper wiring in an interlayer insulating film layer is actively used. It has been broken.

In order to reduce the dielectric constant of an interlayer insulating film, conventionally, a silicon oxide film (SiO ₂ : ratio) formed on the interlayer insulating film of a semiconductor device by using a CVD (Chemical Vapor Deposition) method. An inorganic material such as a dielectric constant of about 4.0) or a silicon nitride film (Si-N: relative dielectric constant of about 7.0) has been used. In recent years, fluorine-added silicon oxide films (Si—O—F: relative dielectric constant of about 3.6) have been adopted one after another as a low dielectric constant material that can follow conventional processes.

  However, the dielectric constant of the fluorine-added silicon oxide film is relatively high, and when this is used as an interlayer insulating film, the effect of reducing the interlayer capacitance is not sufficient. A material with a rate is needed.

  Various materials have been proposed as interlayer insulating film materials having a dielectric constant lower than 3.5, and can be roughly classified into so-called spin-on-glass materials that form films by heating after being applied to a substrate. Studies are also underway on organic materials for film formation and techniques for film formation using CVD.

  Examples of the spin-on-glass material include a material containing a hydrogen silsesquioxane compound or a silsesquioxane methyl compound. A material containing a silsesquioxane hydrogen compound or a silsesquioxane methyl compound as a main component is preferable. In addition, in this specification, a main component means a component with the highest compounding ratio (molar ratio).

The coating solution containing a silsesquioxane hydrogen compound as a main component is obtained by dissolving a compound represented by the general formula (HSiO _3/2 ) _n in a solvent such as methyl isobutyl ketone. This solution is applied to a substrate, subjected to intermediate heating at a temperature of about 100 to 250 ° C., and then heated at a temperature of 350 to 450 ° C. in an inert atmosphere such as a nitrogen atmosphere. Bonds are formed in a ladder structure, and finally an insulating film mainly composed of SiO is formed.

The coating solution containing a silsesquioxane methyl compound as a main component is obtained by dissolving a compound represented by the general formula (CH ₃ SiO _3/2 ) _n in a solvent such as methyl isobutyl ketone. This solution is applied to a substrate, subjected to intermediate heating at a temperature of about 100 to 250 ° C., and then heated at a temperature of 350 to 450 ° C. in an inert atmosphere such as a nitrogen atmosphere. Bonds are formed in a ladder structure, and finally an insulating film mainly composed of SiO is formed.

  As the organic insulating film material, polymer materials such as polyimide, polyparaxylylene, polyarylene ether, polyarylene, benzcyclobutene and polynaphthalene, which are hydrocarbon resins, are known. These materials achieve a low dielectric constant by containing carbon atoms and reducing the density of the film, and by reducing the polarizability of the molecules (monomers) themselves.

  As a technique for further reducing the relative dielectric constant of an interlayer insulating film such as a spin-on-glass film, an organic film, or a CVD film as described above, it is known to form a porous film by forming microvoids in the film. The above materials and processes are disclosed in “International Technology Roadmap for Semiconductors” (1999), pages 163 to 186, JP 2000-340569 A, and JP 2001-274239 A.

  However, in the above-described prior art, in the interlayer insulating film having a characteristic that the relative dielectric constant is less than 3.5, mechanical properties such as hardness and elastic modulus of the insulating film are compared with those of the silicon oxide film and silicon nitride film formed by CVD. It has the problem of low strength.

  In such an insulating film, in order to further reduce the dielectric constant, it is not practical to form a micropore in the film to make it porous, which is in the direction of further degrading mechanical strength. It had been.

  An insulating organic polymer such as polyimide may be used as a means for reducing the relative dielectric constant of the insulating film. An organic polymer is advantageous because its relative dielectric constant is less than 4, but it has the disadvantages that it has a physically low mechanical strength as compared with an inorganic film, and has a high hygroscopicity and moisture permeability. Also, when used as an interlayer insulating film, there are problems in device reliability, such as a decrease in mechanical strength of the device structure and corrosion of wiring due to moisture absorption.

“International Technology Roadmap for Semiconductors” (1999) pp. 163-186 JP 2000-340569 JP 2001-274239 A

  Therefore, in particular, in a multilayer wiring semiconductor element using a damascene structure in which copper wiring with reduced wiring resistance is embedded in an interlayer insulating film layer, the dielectric constant of the entire interlayer insulating film is reduced while suppressing a decrease in mechanical strength of the element structure. The method was examined.

  Based on the technical background described above, the present invention has a laminated structure of a film having a low dielectric constant and a film having a high dielectric constant as described above, and by optimizing the combination and structure of each material. The present invention proposes a method for realizing both electrical characteristics and mechanical characteristics of the insulating film itself.

  In particular, in a semiconductor device having a laminated structure in which a damascene structure in which copper wiring with reduced wiring resistance is embedded in an interlayer insulating film layer is applied, a delay of a signal propagating through the wiring is suppressed while suppressing a decrease in mechanical strength of the interlayer insulating film. A semiconductor device having highly reliable and high performance characteristics reduced as much as possible has been made possible.

  The semiconductor device of the present invention penetrates the first insulating layer, the second insulating layer, the third insulating layer, and the three layers on the substrate on which the transistor element and the semiconductor circuit portion are formed. It is a semiconductor device formed by laminating a plurality of wiring layers each including a formed conductor wiring. At this time, the first and third insulating layers constituting each wiring layer are made of a silicon carbonitride film, silicon carbide, or silicon oxide, and the second of the wiring layers located in the lower layer portion of the wiring layers. This insulating layer contains silicon oxide, and the second insulating layer of the wiring layer located in the upper layer part contains fluorine-added silicon oxide or carbon-added silicon oxide.

  At this time, when copper wiring is used as a constituent element as the conductor wiring, the first insulating film serves as an etching stopper film when opening the insulating film to embed the copper wiring. The third insulating layer serves as a diffusion barrier film for copper wiring.

  Conventionally, a silicon nitride film is used for the etching stopper film and the diffusion barrier film, and in the present invention, a silicon carbonitride film having a relative dielectric constant lower than that of the silicon nitride film (Si—C—N: relative dielectric constant of about 4.6). Further, since a film made of silicon carbide (Si—C: relative dielectric constant of about 4.4) or silicon oxide is used, the relative dielectric constant can be reduced even in the entire wiring layer having a multilayer laminated structure.

  Of the wiring layers, the second insulating layer of the wiring layer located in the upper layer is made of a fluorine-added silicon oxide film or carbon-added silicon oxide film (relative dielectric constant of about 2.9) having a relative dielectric constant smaller than that of the silicon oxide film. Thus, the relative dielectric constant of the entire wiring layer can be reduced as compared with the case where all the second insulating layers constituting the wiring layer are made of silicon oxide.

  In the semiconductor device of the present invention, the second insulating layer of the wiring layer located in the lower layer portion is made of an insulating film material having a relative dielectric constant of less than 3.0, and the second insulating layer of the wiring layer located in the upper layer portion is It was made of a fluorine-added silicon oxide film or a carbon-added silicon oxide film. That is, the constituent components of the second insulating layer are made different between the wiring layer located in the upper layer part and the wiring layer located in the lower layer part so that the relative dielectric constant of the latter insulating film becomes smaller than the former. did.

  Further, in the semiconductor device of the present invention, the second insulating layer of the wiring layer located in the lower layer portion has a characteristic having a relative dielectric constant of less than 3.0, is an insulating film containing SiO, and is in the insulating film More than half of the microvoids present in the sample have a diameter of 0.05 nm or more and 4 nm or less. In the present invention, it is desirable that the main structure of the minute holes has a diameter of 0.05 nm or more and 4 nm or less. In the present invention, a multilayer laminated structure is obtained by using a dielectric film containing SiO, which has a small void in the film, reduces the density of the film, and has a small relative dielectric constant of less than 3.0 as a single film. The relative dielectric constant can be further reduced in the entire wiring layer.

  At this time, the dielectric constant of the insulating film is made lower than the relative dielectric constant of the silicon oxide film by using a method in which minute voids are formed in the insulating film to reduce the density and approach the dielectric constant of vacuum. In particular, an insulating film having an arbitrary dielectric constant can be formed by controlling the size and density of the minute holes.

  However, when the diameter of the micropores increases, the mechanical strength of the insulating film itself as a structure decreases, or the leakage current flowing through the insulating film increases and the dielectric strength voltage characteristic of the insulating film decreases. This problem also arises, and it is necessary to pay close attention to the size of the holes contained in the insulating film.

  Therefore, in the present invention, the range of the hole diameter is controlled to suppress the decrease in the mechanical strength and dielectric strength of the insulating film. At this time, when more than half of the microvoids have a diameter of 0.05 nm or more and 4 nm or less, a highly reliable semiconductor device can be obtained without reducing the film strength of the insulating film.

  The insulating film having microscopic voids is formed of an insulating film mainly containing SiO obtained by heating a film mainly containing a silsesquioxane hydrogen compound or a silsesquioxane methyl compound.

The coating solution containing a silsesquioxane hydrogen compound as a main component is obtained by dissolving a compound represented by the general formula (HSiO _3/2 ) _n in a solvent such as methyl isobutyl ketone. The coating solution containing a silsesquioxane methyl compound as a main component is obtained by dissolving a compound represented by the general formula (CH ₃ SiO _3/2 ) _n in a solvent such as methyl isobutyl ketone.

  These solutions are applied to a substrate, subjected to intermediate heating at a temperature of about 100 to 250 ° C., and then heated at a temperature of 350 to 450 ° C. in an inert atmosphere such as a nitrogen atmosphere, whereby Si—O—Si. Are formed in a ladder structure, and finally an insulating film containing SiO as a main component is formed.

  In an insulating film mainly composed of SiO obtained by heating a film mainly composed of silsesquioxane hydrogen compound or silsesquioxane methyl compound, as a method for controlling the diameter of vacancies existing in the insulating film For example, when a component other than a solvent such as methyl isobutyl ketone is contained in a silsesquioxane compound solution, a trace of the decomposition of this component is formed as a void in the film, and the decomposition behavior changes depending on the film formation temperature. Thus, there is a method of controlling the formation of holes and allowing the hole diameter range to fall within a selective range.

  Examples of the method for applying the insulating film forming solution include spin coating, slit coating, and printing. And since the insulating film is formed by heating this film, even when fine wiring is formed at high density, the step coverage is better than the insulating film by the CVD method, It is advantageous in that the surface step can be eliminated.

  In addition, in order to increase the diameter of the Si wafer, when an insulating film is formed using the CVD method, a large film forming apparatus is required, and the equipment cost greatly affects the element cost. On the other hand, in the present invention, since the insulating film is formed by the coating / heating method, the equipment cost can be greatly reduced, and the great effect of suppressing the investment cost of the production line and further the element cost is expected. it can.

  When an insulating film is formed by a CVD method, an alkyl silane compound or an alkoxysilane compound is used as a main component for a source gas, and finally, an ECR (Electron Cyclotron Resonance) plasma CVD method or the like is used to finally contain SiO as a main component. An insulating film is formed.

  Also in this case, as a method for controlling the diameter of the vacancies existing in the insulating film, for example, a component having a high thermal decomposition temperature is contained as a source gas, and heating at 350 ° C. to 450 ° C. is performed in the film during film formation. There is a technique in which the trace of decomposition of this component is formed as a void.

  In such a method, it is possible to change the decomposition behavior depending on the film forming temperature by selecting various components having a high thermal decomposition temperature. By controlling the formation of the holes, the hole diameter range can be selectively selected. It is possible to fit within the range.

  Further, in the semiconductor device of the present invention, a partition layer (referred to as a guard ring in the present invention) composed of a material for forming a conductor wiring so as to surround the periphery of the element device in order to prevent moisture absorption and moisture permeation from the periphery of the semiconductor device. Is provided around the element device. Thus, according to the present invention, moisture that permeates through the interlayer insulating film from the periphery of the element or the interface between the substrate and the interlayer insulating film can be shielded, and the moisture resistance reliability of the element itself can be improved.

  As described above, in a semiconductor element having a multi-layer laminated wiring using a damascene structure in which copper wiring with reduced wiring resistance is embedded in an interlayer insulating film layer, the relative dielectric constant is smaller than that of a silicon nitride film as an etching stopper film or a diffusion barrier film. By using different films and making the insulating film in the lower and upper layers of the multi-layered structure different, the mechanical strength of the entire device is increased and the dielectric constant of the entire interlayer insulating film is reduced. A semiconductor device can be obtained.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
In the first example, a six-layer wiring semiconductor element having a Cu wiring dual damascene structure having six wiring layers 100 as shown in FIG. 1 was produced.

  On a semiconductor substrate 101 on which a component (not shown) such as a MOS transistor is formed using a generally well-known method, a silicon carbon nitride film 102 serving as a first insulating layer of the first wiring layer 100a is 40 nm thick. And using the CVD method. This first insulating layer becomes an etching stopper film at the opening for forming the wiring pattern.

  Next, a silicon oxide film 103 serving as a second insulating layer of the first wiring layer 100a was formed by a CVD method with a thickness of 400 nm.

  Next, a silicon carbon nitride film 104 serving as a third insulating layer of the first wiring layer 100a was formed by a CVD method with a thickness of 40 nm. This film also serves as an etching stopper film and a Cu diffusion barrier film at the time of opening for forming a wiring pattern as the first insulating layer of the second wiring layer 100b.

  Next, an opening 117 was formed in the silicon carbonitride film 104. The openings are formed by using a photoresist and a dry etching method by forming a resist pattern by a known technique, using an etching gas capable of removing the silicon carbonitride film, using the resist as a mask (FIG. 2A). )). At this time, the opening is the wiring dimension of the first wiring layer 100a.

  Next, using a method similar to the formation of the first wiring layer 100a, the silicon oxide film 105 serving as the second insulating layer of the second wiring layer 100b is 400 nm thick, and the silicon carbon nitride film 106 serving as the third insulating layer is formed. It was formed with a thickness of 40 nm.

  Next, an opening 118 was formed in the silicon carbonitride film (FIG. 2B). The openings were formed using a dry etching method using a photoresist, forming a resist pattern by a known technique, using an etching gas capable of removing the silicon carbonitride film, and using the resist as a mask.

  Next, an opening is formed in the silicon oxide film 105 by a dry etching method using a CF-based gas capable of removing the silicon oxide film using the silicon carbon nitride film as a mask, and the opening 117 of the silicon carbon nitride film 104 is formed thereunder. Exposed.

  Subsequently, an opening was formed in the silicon oxide film 103 using the opening 117 of the silicon carbonitride film 104 as a mask, and the silicon carbonitride film 102 was exposed below the opening.

  Subsequently, the etching gas was switched to remove the silicon carbon nitride film, and the silicon carbon nitride film 102 was removed by dry etching using the opening of the silicon oxide film 103 as a mask to form an opening penetrating the semiconductor substrate 101. At this time, the silicon carbon nitride film 104 is also etched and spreads to the same size as the opening 118 of the uppermost silicon carbon nitride film. As a result, a wiring groove 119 penetrating the semiconductor substrate 101 was formed (FIG. 2C).

  Next, after forming a barrier metal film 120 on the inner surface of the wiring trench 119, Cu 121 was filled using a well-known plating method. In this embodiment, TiN was used as the barrier metal.

  Then, an unnecessary Cu film present on the uppermost silicon carbon nitride film was removed, and the surface was washed to form a connection plug and a wiring at the same time. For removal of the Cu film, it is convenient to use a chemical mechanical polishing method using alumina or silica as abrasive grains and using an abrasive comprising an additive such as a Cu complexing agent or a surfactant. is there.

  In this polishing step, the silicon carbon nitride film 106 corresponding to the uppermost layer was also removed by polishing. Thus, a dual damascene structure in which Cu wiring (including 120 and 121) was formed was produced (FIG. 2D).

  Subsequently, the same process was performed twice to form the third wiring layer 100c to the sixth wiring layer 100f, and a six-layer Cu wiring structure was obtained. At this time, the insulating layers 106, 108, 110, and 112 are made of a silicon carbonitride film formed by a CVD method, and the insulating layers 107 and 109 are made of a silicon oxide film. The insulating layers 111 and 113 are made of a fluorine-added silicon oxide film.

  Next, a silicon nitride film 114 was formed as the uppermost layer, and a multilayer wiring semiconductor device having six layers of Cu wiring 115 was fabricated (FIG. 1).

  As a result, a silicon carbon nitride film having a relative dielectric constant lower than that of the silicon nitride film is used as an etching stopper film and a diffusion barrier film, and fluorine-doped silicon oxide having a relative dielectric constant lower than that of the silicon oxide film in the upper layer portion of the multilayer structure. By using the film, a high-performance semiconductor device having a reduced dielectric constant of the entire interlayer insulating film was obtained.

(Second embodiment)
In the present embodiment, a fluorine-added silicon oxide film is formed on the insulating layers 107 and 109 using the CVD method in the same manner as in the first embodiment. Next, a silicon nitride film 114 was formed as the uppermost layer, and a multilayer wiring semiconductor element provided with six layers of Cu wiring 115 was fabricated.

  As a result, a silicon carbon nitride film having a relative dielectric constant lower than that of the silicon nitride film is used as an etching stopper film and a diffusion barrier film, and the relative dielectric constant of the upper layer portion of the multilayer structure is more than 1/3 of that of the silicon oxide film. By using a small fluorine-added silicon oxide film, a high-performance semiconductor device in which the dielectric constant of the entire interlayer insulating film was lowered was obtained.

(Third embodiment)
In the present example, a silicon carbide film was formed on the insulating layers 102, 104, 106, 108, 110, and 112 by using the CVD method, using the same method as in the first example. Next, a silicon nitride film 114 was formed as the uppermost layer, and a multilayer wiring semiconductor element provided with six layers of Cu wiring 115 was fabricated.

  As a result, a silicon carbide film having a relative dielectric constant lower than that of the silicon nitride film is used as the etching stopper film and the diffusion barrier film, thereby obtaining a high-performance semiconductor device in which the dielectric constant of the entire interlayer insulating film is lowered.

(Fourth embodiment)
In the present example, a silicon carbide film was formed on the insulating layers 102, 104, 106, 108, 110, and 112 by using the CVD method, using the same method as in the second example. Next, a silicon nitride film 114 was formed as the uppermost layer, and a multilayer wiring semiconductor element provided with six layers of Cu wiring 115 was fabricated.

  As a result, a silicon carbide film having a relative dielectric constant lower than that of the silicon nitride film is used as the etching stopper film and the diffusion barrier film, thereby obtaining a high-performance semiconductor device in which the dielectric constant of the entire interlayer insulating film is lowered.

(Fifth embodiment)
Using the same technique as in the first embodiment, in this embodiment, a carbon-added silicon oxide film is formed on the insulating layers 111 and 113 using the CVD method, and a multilayer wiring semiconductor having six layers of Cu wiring 115 is used. An element was produced.

  As a result, a high-performance semiconductor device in which the dielectric constant of the entire interlayer insulating film was lowered was obtained by using a carbon-added silicon oxide film having a relative dielectric constant smaller than that of the silicon oxide film in the upper layer portion of the multilayer structure.

(Sixth embodiment)
In the present embodiment, a carbon-added silicon oxide film is formed on the insulating layers 107, 109, 111, and 113 by using the CVD method, and a six-layer Cu wiring 115 is formed using the same method as in the second embodiment. A multilayer wiring semiconductor device provided was prepared.

  In addition, by using a carbon-added silicon oxide film having a relative dielectric constant smaller than that of the silicon oxide film in the upper layer portion of 1/3 or more of the multilayer structure, a high-performance semiconductor device in which the dielectric constant of the entire interlayer insulating film is lowered can be obtained. It was.

(Seventh embodiment)
In the present example, a silicon carbide film was formed on the insulating layers 102, 104, 106, 108, 110, and 112 by using the CVD method by using the same method as in the fifth example. Next, a silicon nitride film 114 was formed as the uppermost layer, and a multilayer wiring semiconductor element provided with six layers of Cu wiring 115 was fabricated.

  As a result, a silicon carbide film having a relative dielectric constant lower than that of the silicon nitride film is used as the etching stopper film and the diffusion barrier film, thereby obtaining a high-performance semiconductor device in which the dielectric constant of the entire interlayer insulating film is lowered.

(Eighth embodiment)
In the present example, a silicon carbide film was formed on the insulating layers 102, 104, 106, 108, 110, and 112 using the CVD method by using the same method as in the sixth example. Next, a silicon nitride film 114 was formed as the uppermost layer, and a multilayer wiring semiconductor element provided with six layers of Cu wiring 115 was fabricated.

  As a result, a silicon carbide film having a relative dielectric constant lower than that of the silicon nitride film is used as the etching stopper film and the diffusion barrier film, thereby obtaining a high-performance semiconductor device in which the dielectric constant of the entire interlayer insulating film is lowered.

(Ninth embodiment)
In the present embodiment, a carbon-added silicon oxide film is formed on the insulating layers 103, 105, 107, and 109 using the CVD method, and a six-layer Cu wiring 115 is formed using the same method as in the first embodiment. A multilayer wiring semiconductor device provided was prepared.

  As a result, a carbon-added silicon oxide film having a low relative dielectric constant is used as an insulating film in the lower layer portion of the multilayer structure, and a fluorine-added silicon oxide film having a relative dielectric constant smaller than that of the silicon oxide film is used in the upper layer portion of the multilayer structure. By using it, a high-performance semiconductor device having a reduced dielectric constant of the entire interlayer insulating film was obtained.

(Tenth embodiment)
In the present embodiment, a multi-layer wiring semiconductor including a six-layer Cu wiring 115 formed by depositing a carbon-added silicon oxide film using a CVD method for the insulating layers 103 and 105 using the same method as in the second embodiment. An element was produced.

  As a result, a carbon-added silicon oxide film having a low relative dielectric constant is used as an insulating film in the lower layer portion of the multilayer structure, and fluorine having a relative dielectric constant smaller than that of the silicon oxide film in an upper layer portion of 1/3 or more of the multilayer structure. By using the added silicon oxide film, a high-performance semiconductor device in which the dielectric constant of the entire interlayer insulating film was lowered was obtained.

(Eleventh embodiment)
In the present embodiment, a carbon-added silicon oxide film is formed by CVD on the insulating layers 103, 105, 107, and 109 using the same method as in the third embodiment, and six layers of Cu wiring 115 are formed. A multilayer wiring semiconductor device provided was prepared.

  As a result, a carbon-added silicon oxide film having a low relative dielectric constant is used as an insulating film in the lower layer portion of the multilayer structure, and a fluorine-added silicon oxide film having a relative dielectric constant smaller than that of the silicon oxide film is used in the upper layer portion of the multilayer structure. Using a silicon carbide film having a relative dielectric constant lower than that of the silicon nitride film as the etching stopper film and diffusion barrier film, a high performance semiconductor device having a reduced dielectric constant of the entire interlayer insulating film was obtained.

(Twelfth embodiment)
In the present embodiment, a multi-layered wiring semiconductor having a six-layer Cu wiring 115 formed by forming a carbon-added silicon oxide film using a CVD method for the insulating layers 103 and 105 using the same method as in the fourth embodiment. An element was produced.

  As a result, a carbon-added silicon oxide film having a low relative dielectric constant is used as an insulating film in the lower layer portion of the multilayer structure, and fluorine having a relative dielectric constant smaller than that of the silicon oxide film in an upper layer portion of 1/3 or more of the multilayer structure. By using a silicon carbide film having a lower relative dielectric constant than the silicon nitride film as an etching stopper film and diffusion barrier film using an added silicon oxide film, a high-performance semiconductor device with a reduced dielectric constant of the entire interlayer insulating film can be obtained. It was.

(Thirteenth embodiment)
In this embodiment, using a method similar to that in the first embodiment, a methyl isobutyl ketone solution containing a silsesquioxane hydrogen compound as a main component is applied to the insulating layers 103, 105, 107, and 109 using a coating method. Then, the substrate was heated on a hot plate at 100 ° C. for 10 minutes, then at 150 ° C. for 10 minutes, and at 230 ° C. for 10 minutes in a nitrogen atmosphere.

  Furthermore, by heating at 350 ° C. for 30 minutes using a furnace body in a nitrogen atmosphere, a Si—O—Si bond is formed in a ladder structure, and finally pore formation is controlled with SiO as the main component. An insulating film having the minute holes in the film was formed, and a multilayer wiring semiconductor element having six layers of Cu wirings 115 was produced. The opening was formed by a dry etching method using a CF-based gas that can etch SiO.

  In the case of the present embodiment, as shown in FIG. 3, the insulating film has microvoids having distribution characteristics mainly including vacancies having a diameter of 0.05 nm or more and 4 nm or less, and the relative dielectric constant is 2. About three.

  The diameter distribution assumed a spherical scatterer based on X-ray reflection measurement data and diffuse scattering X-ray measurement data obtained by using an X-ray thin film structure analyzer (model: ATX-G) manufactured by Rigaku Corporation. Compared to the theoretical scattering intensity based on the scattering function, the diameter distribution of the scatterer was calculated.

  In addition, the insulating film having the above-described minute holes in the film has a characteristic of Young's modulus of 12Ga. These characteristics are determined by the hardness at the surface layer point of 1/5 of the total film thickness of the same film having a film thickness of 250 nm formed on a Si wafer using an indentation measurement method using Nanoindenter XP manufactured by MTS Systems, USA. The film hardness was determined.

  The Young's modulus is also a value at the surface layer point that is 1/5 of the total film thickness, and is converted based on the Poisson's ratio of 0.17 of fused quartz. A p-TEOS film having a similar film thickness obtained by a similar method has a Young's modulus of 70 Ga.

  From this, the insulating film having the above-described microvoids in the film is a film having a Young's modulus of about 17% of the p-TEOS film, and is lower than the low dielectric constant film described in Japanese Patent Application Laid-Open No. 2000-340569. Thus, a low dielectric constant insulating film having excellent mechanical properties was obtained.

  As a result, an insulating film having a relative dielectric constant of less than 2.5 and excellent film strength is used in the lower layer portion of the multilayer structure, and fluorine-added silicon having a lower relative dielectric constant than the silicon oxide film in the upper layer portion of the multilayer structure. By using the oxide film, a high-performance semiconductor device was obtained while lowering the dielectric constant of the entire interlayer insulating film and suppressing the decrease in mechanical strength of the element structure.

(Fourteenth embodiment)
In the present example, a silicon carbide film was formed on the insulating layers 102, 104, 106, 108, 110, and 112 by using the CVD method by using the same method as in the thirteenth example.

  Next, a silicon nitride film 114 was formed as the uppermost layer, and a multilayer wiring semiconductor element provided with six layers of Cu wiring 115 was fabricated.

  As a result, a silicon carbide film having a relative dielectric constant lower than that of a silicon nitride film is used as an etching stopper film and a diffusion barrier film, and an insulating film having minute vacancies in the film is used to define the hole diameter. A low dielectric constant insulating film having excellent mechanical characteristics can be obtained.

  Further, in the lower layer portion of the multilayer structure, an insulating film having a relative dielectric constant of less than 2.5 and excellent film strength is used as the second insulating layer, and the second insulating layer is used in the upper layer portion of the multilayer structure. By using a fluorine-doped silicon oxide film with a relative dielectric constant smaller than that of the silicon oxide layer, a high-performance semiconductor device can be obtained while lowering the dielectric constant of the entire interlayer insulating film and suppressing the mechanical strength of the element structure. It was.

(15th Example)
In this example, using a method similar to that of the thirteenth example, a methyl isobutyl ketone solution mainly composed of a silsesquioxane hydrogen compound is applied to the insulating layers 103, 105, 107, and 109 using a coating method. Then, the substrate was heated on a hot plate at 100 ° C. for 10 minutes, then at 150 ° C. for 10 minutes, and at 230 ° C. for 10 minutes in a nitrogen atmosphere.

  Furthermore, by heating at 350 ° C. for 30 minutes using a furnace body in a nitrogen atmosphere, a Si—O—Si bond is formed in a ladder structure, and finally pore formation is controlled with SiO as the main component. An insulating film having the minute holes in the film was formed, and a multilayer wiring semiconductor element having six layers of Cu wirings 115 was produced. The opening was formed by a dry etching method using a gas for etching SiO.

  In the case of this example, as shown in FIG. 4, the insulating film has minute vacancies having distribution characteristics mainly including vacancies having a diameter of 0.05 nm to 1 nm, and the relative dielectric constant is 2. It is about 7.

  The diameter distribution is based on the X-ray reflection measurement data and diffuse scattering X-ray measurement data obtained using the X-ray thin film structure analyzer, and compared with the theoretical scattering intensity based on the scattering function assuming a spherical scatterer. It was obtained by calculating the diameter distribution of the body.

  In addition, the insulating film having the above-described minute holes in the film has a characteristic of Young's modulus of 11 Ga. For these characteristics, the indentation measurement method using NanoindenterXP was used to determine the above-mentioned film hardness by the hardness at the surface layer point of 1/5 of the total film thickness for the same film with a film thickness of 250 nm formed on the Si wafer. .

  The Young's modulus is also a value at the surface layer point that is 1/5 of the total film thickness, and is converted based on the Poisson's ratio of 0.17 of fused quartz. A p-TEOS film having a similar film thickness obtained by a similar method has a Young's modulus of 70 Ga.

  From this, the insulating film having the above-described microvoids in the film is a film having a Young's modulus of about 16% of the p-TEOS film, and is lower than the low dielectric constant film described in Japanese Patent Application Laid-Open No. 2000-340569. Thus, a low dielectric constant insulating film having excellent mechanical properties was obtained.

  As described above, an insulating film having a relative dielectric constant of less than 3.0 and excellent film strength is used as the second insulating layer in the lower layer portion of the multilayer laminated structure, and the second insulating layer is used in the upper layer portion of the multilayer laminated structure. By using a fluorine-doped silicon oxide film with a relative dielectric constant smaller than that of the silicon oxide layer, a high-performance semiconductor device can be obtained while lowering the dielectric constant of the entire interlayer insulating film and suppressing the mechanical strength of the element structure. It was.

(Sixteenth embodiment)
In the present example, a silicon carbide film was formed on the insulating layers 102, 104, 106, 108, 110, and 112 by using the CVD method, using the same method as in the fifteenth example. Next, a silicon nitride film 114 was formed as the uppermost layer, and a multilayer wiring semiconductor element provided with six layers of Cu wiring 115 was fabricated.

  As a result, a silicon carbide film having a relative dielectric constant lower than that of a silicon nitride film is used as an etching stopper film and a diffusion barrier film, and an insulating film having minute vacancies in the film is used to define the hole diameter. A low dielectric constant insulating film excellent in mechanical properties was obtained. In the lower layer portion of the multilayer structure, an insulating film having a relative dielectric constant of less than 3.0 and excellent film strength is used as the second insulating layer, and the second insulating layer is used as the second insulating layer in the upper layer portion of the multilayer structure. By using a fluorine-added silicon oxide film having a relative dielectric constant smaller than that of the silicon oxide film, a high performance semiconductor device was obtained while lowering the dielectric constant of the entire interlayer insulating film and suppressing the decrease in mechanical strength of the element structure.

(Seventeenth embodiment)
The seventeenth embodiment is an example applied to the formation of a Cu wiring dual damascene structure, and will be described with reference to the process diagrams of FIGS.

  A silicon carbon nitride film 502 serving as a first insulating layer of a first wiring layer is formed with a thickness of 40 nm on a semiconductor substrate 501 on which a component (not shown) such as a MOS transistor is formed using a generally well-known method. It formed using the CVD method. This first insulating layer becomes an etching stopper film at the opening for forming the wiring pattern.

  Next, a methyl isobutyl ketone solution containing a silsesquioxane hydrogen compound as a main component is formed on a substrate using a coating method, and then in a nitrogen atmosphere using a hot plate at 100 ° C. for 10 minutes, Heating was performed at 150 ° C. for 10 minutes and at 230 ° C. for 10 minutes. Further, by heating at 350 ° C. for 30 minutes using a furnace body in a nitrogen atmosphere, a Si—O—Si bond is formed in a ladder structure, and finally SiO is the main component as shown in FIG. In addition, an insulating film having a relative dielectric constant of about 2.3 in which micro-holes having distribution characteristics mainly including holes having a diameter of 0.05 nm to 4 nm are present, and the second insulating layer of the first wiring layer is formed. 503.

  Next, a silicon carbon nitride film 504 serving as a third insulating layer of the first wiring layer was formed with a thickness of 40 nm using a CVD method. This film also serves as an etching stopper film and a Cu diffusion barrier film at the time of opening the wiring pattern as the first insulating layer of the second wiring layer.

  Next, an opening 517 was formed in the silicon carbon nitride film 504. The openings are formed by using a photoresist and forming a resist pattern by a known technique, using an etching gas capable of removing the silicon carbonitride film, and using a dry etching method with the resist as a mask (FIG. 5A )). At this time, the opening is the wiring dimension of the first wiring layer.

  Next, using the same method as the formation of the second insulating layer 503 of the first wiring layer, it becomes a second insulating layer of the second wiring layer, and has a diameter of 0.05 nm to 4 nm as shown in FIG. An insulating layer 505 having a relative dielectric constant of 2.3 having minute pores having distribution characteristics mainly including vacancies was formed with a thickness of 400 nm, and a silicon carbon nitride film 506 serving as a third insulating layer was formed with a thickness of 40 nm.

  Next, an opening 518 was formed in the silicon carbonitride film (FIG. 5B). The openings were formed using a dry etching method using a photoresist, forming a resist pattern by a known technique, using an etching gas capable of removing the silicon carbonitride film, and using the resist as a mask.

  Next, an opening is formed in the insulating layer 505 by a dry etching method using a gas capable of removing the SiO film having microvoids using the silicon carbonitride film as a mask, and the opening 517 of the silicon carbonitride film 504 is formed therebelow. Is exposed.

  Subsequently, an opening was formed in the insulating layer 503 using the opening 517 of the silicon carbon nitride film 504 as a mask, and the silicon carbon nitride film 502 was exposed below the opening. Subsequently, the etching gas was switched to remove the silicon carbon nitride film, and the silicon carbon nitride film 502 was removed by dry etching using the opening of the insulating layer 503 as a mask to form an opening penetrating the semiconductor substrate 501. At this time, the silicon carbon nitride film 504 is also etched and spreads to the same dimension as the opening 518 of the uppermost silicon carbon nitride film. As a result, a wiring groove 519 penetrating the semiconductor substrate 501 was formed (FIG. 5C).

  Next, after forming a barrier metal film 120 on the inner surface of the wiring trench 119, Cu 121 was filled using a well-known plating method. In this embodiment, TiN was used as the barrier metal.

  Then, by using a chemical mechanical polishing method, an unnecessary Cu film existing on the silicon carbon nitride film as the uppermost layer was removed, and the surface was washed to simultaneously form a connection plug and a wiring. In this polishing step, the silicon carbon nitride film 506 corresponding to the uppermost layer is left without being polished and removed. This produced a dual damascene structure in which Cu wiring (including 520 and 521) was formed (FIG. 5D).

  As described above, a high-performance semiconductor device in which the dielectric constant of the entire interlayer insulating film is reduced by using a film having a low relative dielectric constant for the second insulating layer 503 which is a main constituent layer of the interlayer insulating film layer. can get.

  Although the structure of this embodiment has a structure in which two wiring layers are stacked, a semiconductor device having a multilayer wiring structure can be obtained by repeatedly stacking the wiring layers two or more times.

(Eighteenth embodiment)
Similar to the seventeenth embodiment, in this embodiment, as shown in FIG. 4, the second insulating layer 503 has microscopic holes having a distribution characteristic mainly including holes having a diameter of 0.05 nm to 1 nm. A dual damascene structure in which an SiO insulating film having a relative dielectric constant of about 2.7 in which Cu exists is formed and Cu wiring is formed is manufactured.

  Thus, a high-performance semiconductor device in which the dielectric constant of the entire interlayer insulating film is reduced can be obtained by using a film having a low relative dielectric constant for 503 which is a main constituent layer of the interlayer insulating film layer. Furthermore, a high-performance semiconductor device having a multilayer wiring structure can be easily obtained by repeatedly stacking wiring layers twice or more.

(Nineteenth embodiment)
FIG. 6 is a sectional view of a semiconductor logic device according to the nineteenth embodiment. An element isolation film region 602 is formed on the semiconductor substrate 601 by using known STI (Shallow Trench Isolation), and a MOS transistor 603 is formed in the element isolation film region 602 (the hatching of the transistor portion is easy to see the figure). Omitted). Then, a silicon oxide film 604 of about 50 nm and a BPSG (boron, phosphorus silicate glass) film 605 of about 500 nm are sequentially formed on the surface of the semiconductor substrate 601 using the known CVD method, including the MOS transistor 603. For example, reflow annealing is performed in a nitrogen atmosphere at 800 to 900 ° C.

  Next, after planarizing and polishing the surface of the BPSG film 605 using a chemical mechanical polishing method using silica abrasive grains, a contact hole is formed, and tungsten is buried in the contact hole by a CVD method to conduct the conductive process. A plug 606 is formed. At this time, unnecessary tungsten existing on the surface of the BPSG film 605 is removed by a known etch back method.

  Next, in the same manner as in the seventeenth embodiment, a silicon carbon nitride film 607 serving as a first insulating layer of the first wiring layer was formed to a thickness of 40 nm using a CVD method. This first insulating layer becomes an etching stopper film at the opening for forming the wiring pattern.

  Next, a methyl isobutyl ketone solution containing a silsesquioxane hydrogen compound as a main component is formed on a substrate using a coating method, and then in a nitrogen atmosphere using a hot plate at 100 ° C. for 10 minutes, Heating was performed at 150 ° C. for 10 minutes and at 230 ° C. for 10 minutes. Further, by heating at 350 ° C. for 30 minutes using a furnace body in a nitrogen atmosphere, a Si—O—Si bond is formed in a ladder structure, and finally SiO is the main component as shown in FIG. In addition, an insulating film having a relative dielectric constant of about 2.3 in which micro-holes having distribution characteristics mainly including holes having a diameter of 0.05 nm to 4 nm are present, and the second insulating layer of the first wiring layer is formed. 608.

  Next, a silicon carbon nitride film 609 serving as a third insulating layer of the first wiring layer was formed with a thickness of 40 nm using a CVD method. This film also serves as an etching stopper film and a Cu diffusion barrier film at the time of opening the wiring pattern as the first insulating layer of the second wiring layer.

  Next, an opening was formed in the silicon carbonitride film 609. The openings were formed using a dry etching method using a photoresist, forming a resist pattern by a known technique, using an etching gas capable of removing the silicon carbonitride film, and using the resist as a mask. At this time, the opening is the wiring dimension of the first wiring layer.

  Next, using a method similar to the formation of the second insulating layer 608 of the first wiring layer, the second insulating layer 610 of the second wiring layer is 400 nm thick, and the silicon carbon nitride film 611 to be the third insulating layer is 40 nm. Formed with thickness.

  Next, an opening was formed in the silicon carbonitride film. Then, using this silicon carbonitride film as a mask, an opening is formed in the insulating layer 610 by a dry etching method using a gas capable of removing the SiO film having microvoids, and the silicon carbonitride film 609 is exposed below it. .

  Subsequently, an opening was formed in the insulating layer 608 using the opening of the silicon carbon nitride film 609 as a mask, and the silicon carbon nitride film 607 was exposed below the opening. Then, the etching gas was switched to remove the silicon carbide film, and the silicon carbon nitride film 607 was removed by dry etching using the opening of the insulating layer 608 as a mask to form an opening penetrating the conductive plug 606.

  At this time, the silicon carbon nitride film 609 is also etched and spreads to the same size as the opening of the uppermost silicon carbide film. Thereby, a wiring groove penetrating the conductive plug 606 was formed.

  Next, after forming a barrier metal film on the inner surface of the wiring groove, Cu was filled using a well-known plating method. In this embodiment, TiN was used as the barrier metal. Then, by using a chemical mechanical polishing method, an unnecessary Cu film existing on the silicon carbon nitride film as the uppermost layer was removed, and the surface was washed to simultaneously form a connection plug and a wiring. In this polishing step, the silicon carbide film 611 corresponding to the uppermost layer is left without being removed by polishing. As a result, a dual damascene structure in which a Cu wiring was formed was produced.

  The above process was repeated to form a four-layer wiring structure.

  Subsequently, the same process was repeated to further stack two layers of wiring structures. At this time, the insulating layers 617, 619 and 621 were formed with a thickness of 40 nm using a silicon carbonitride film. The insulating layers 618 and 620 were formed with a thickness of 600 nm using a fluorine-added silicon oxide film. Next, a silicon nitride film 622 was formed as the uppermost layer, and a multilayer wiring semiconductor element provided with six layers of Cu wiring 623 was produced.

  As a result, a silicon carbide film having a relative dielectric constant lower than that of the silicon nitride film is used as the etching stopper film and the diffusion barrier film, and the relative dielectric constant is less than 2.5 as the second insulating layer in the lower layer portion of the multilayer stacked structure. By using an insulating film with excellent film strength and using a fluorine-added silicon oxide film having a relative dielectric constant smaller than that of the silicon oxide film as the second insulating layer in the upper layer portion, the dielectric constant of the entire interlayer insulating film can be reduced. A lowered high-performance semiconductor device was obtained.

(20th embodiment)
FIG. 7 is a cross-sectional view of a resin-sealed semiconductor logic device according to the twentieth embodiment. The semiconductor logic device 701 obtained in the nineteenth embodiment and having the polyimide surface protective film 702 formed except for the bonding pad portion is fixed to a lead frame in a die bonding step provided separately. Thereafter, a gold wire 704 was wired between the bonding pad portion provided in the semiconductor logic device 701 and the external terminal 705 of the lead frame using a wire bonder.

Next, using a silica-containing biphenyl epoxy resin manufactured by Hitachi Chemical Co., Ltd., a resin sealing portion 703 was formed so as to wrap the semiconductor logic device 701, the external terminal 705, and the like. The sealing conditions are a molding temperature of 180 ° C. and a molding pressure of 70 kg / cm ² , but are not limited thereto. Finally, by bending the external terminal 706 into a predetermined shape, a finished product of the resin-encapsulated semiconductor logic device is obtained.

  Part of the interlayer insulation film of resin-sealed semiconductor logic devices uses an insulation film that has a small relative dielectric constant but sufficiently suppresses a decrease in mechanical strength. In the process, a resin-encapsulated product can be obtained without generating cracks in the element due to stress applied to the semiconductor logic element.

  Further, it goes without saying that the same effects as those described in the nineteenth embodiment can be obtained as the characteristics of the semiconductor logic element, and since it is further sealed with resin, it is possible to exhibit stable characteristics against the external environment. .

(Twenty-first embodiment)
FIG. 8 is a cross-sectional view for explaining the twenty-first embodiment, in which the semiconductor logic device described in the nineteenth embodiment is used for manufacturing a product having a wafer level chip size package structure.

  A polyimide insulating film 804 is formed on the uppermost silicon nitride film 802 of the semiconductor logic element 801 so as to expose the bonding pad portion 803. Next, the rearrangement wiring 805 is formed. In this embodiment, the rearranged wiring consists of three layers formed by sputtering TiN, Cu, and Ni, and a wiring pattern is formed by a well-known photolithography technique after the film formation.

  Further thereon, a polyimide insulating film 806 was formed. An under bump metal layer 807 is provided through the polyimide insulating film layer 806 for electrical connection in a partial region of the rearrangement wiring 805. Three under bump metal layers were formed of Cr, Ni, and Au. Solder bumps 808 are formed on the under bump metal layer 807.

  Since the semiconductor logic device itself that can be driven at high speed can be formed on the wafer by the method described in the nineteenth embodiment, the semiconductor logic package device having solder bumps in the wafer state is realized by this embodiment.

  By applying an interlayer insulating film layer having a low dielectric constant, a high-performance semiconductor logic device has already been obtained as compared with conventional products. However, when a package semiconductor product is mounted on a printed circuit board or the like, it is possible to perform signal propagation between the element and the printed circuit board at a high speed by applying the package structure as in this embodiment. It is possible to further draw out the performance of.

(Twenty-second embodiment)
FIG. 9 shows a cross-sectional view (FIG. 9A) and a wafer plan conceptual view (FIG. 9B) of the element end portion for explaining the twenty-second embodiment.

  On the silicon substrate 901, a semiconductor element 906 such as a MOS transistor and a semiconductor circuit portion including these elements are formed, and the wiring layer described above is formed on the substrate 901. And the guard ring layer 905 is arrange | positioned using the material which consists of a conductor which comprises a wiring layer so that this semiconductor element 906 and the semiconductor circuit part containing these elements may be enclosed. The guard ring layer 905 can prevent moisture from entering the semiconductor element 906 and the semiconductor circuit portion including these elements from the outside. The guard ring layer 905 is formed in the process of forming the conductor wiring.

  As a result, in particular, when an insulating film having pores is applied as an interlayer insulating film exhibiting low dielectric constant characteristics, the problem of moisture permeation and adsorption into the hole is solved, and the moisture resistance reliability of the semiconductor element itself is improved. A semiconductor device can be provided.

  As mentioned above, although it demonstrated in detail using the Example, various conditions for achieving this invention and an Example are not limited to these Examples at all.

It is sectional drawing of the semiconductor device of the laminated structure produced in the 1st Example. It is process drawing for demonstrating the semiconductor device produced in the 1st Example. It is a figure for demonstrating the diameter distribution of the hole which exists in an insulating film. It is a figure for demonstrating the diameter distribution of the hole which exists in an insulating film. It is process drawing for demonstrating the semiconductor device of the laminated structure produced in the 17th Example. It is sectional drawing for demonstrating the semiconductor logic device produced in the 19th Example. It is sectional drawing for demonstrating the resin sealing type | mold semiconductor device produced in the 20th Example. It is sectional drawing for demonstrating the wafer level chip size package structure semiconductor device produced in the 21st Example. It is sectional drawing and a top view for demonstrating the semiconductor device which has the guard ring structure produced in the 22nd Example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 ... Semiconductor substrate, 102 ... 1st insulating film of 1 layer wiring layer, 103 ... 2nd insulating film of 1 layer wiring layer, 104 ... 3rd insulating film of 1 layer wiring layer / 1st insulating film of 2 layer wiring layer , 105... Second insulating film of the two-layer wiring layer, 106... Third insulating film of the two-layer wiring layer / First insulating film of the three-layer wiring layer, 107. 3rd insulating film of layer wiring layer / 1st insulating film of 4th layer wiring layer, 109... 2nd insulating film of 4 layer wiring layer, 110... 3rd insulating film of 4 layer wiring layer / 5. Insulating film, 111... Second insulating film of five-layer wiring layer, 112... Third insulating film of five-layer wiring layer / 6 first insulating film of six-layer wiring layer, 113. ... outermost surface passivation film (silicon nitride film), 115 ... conductor wiring layer, 117 ... opening, 118 ... opening, 119 ... wiring groove, 120 ... barrier metal film, 1 DESCRIPTION OF SYMBOLS 1 ... Conductive layer, 501 ... Semiconductor substrate, 502 ... 1st insulating film of 1 layer wiring layer, 503 ... 2nd insulating film of 1 layer wiring layer, 504 ... 3rd insulating film of 1 layer wiring layer / 2 layer wiring layer First insulating film, 505... Second insulating film of two-layer wiring layer, 506... Third insulating film of two-layer wiring layer, 517... Open, 518. ... Conductor layer, 601 ... Semiconductor substrate, 602 ... Element isolation film region, 603 ... MOS transistor, 604 ... Silicon oxide film, 605 ... BPSG (boron, phosphorus, silicate glass) film, 606 ... Conductive plug, 607 ... Single layer wiring First insulating film of layer, 608... Second insulating film of one layer wiring layer, 609... Third insulating film of one layer wiring layer / first insulating film of two layer wiring layer, 610. Insulating film, 611... Third insulating film of two-layer wiring layer, 612... 3 1st insulating film of wiring layer, 613... 2nd insulating film of 3rd wiring layer, 614... 3rd insulating film of 3rd wiring layer / 1st insulating film of 4th wiring layer, 615. 2 insulating film, 616... Third insulating film of 4 layer wiring layer, 617... First insulating film of 5 layer wiring layer, 618... Second insulating film of 5 layer wiring layer, 619. 1st insulating film of film / 6 layer wiring layer, 620... 2nd insulating film of 6 layer wiring layer, 621... 3rd insulating film of 6 layer wiring layer, 622... Outermost surface passivation film (silicon nitride film), 623. Conductor wiring layer, 701 ... semiconductor logic device, 702 ... chip coat film, 703 ... resin sealing part (epoxy resin), 704 ... gold wire, 705 ... lead frame, 706 ... external terminal, 801 ... semiconductor substrate, 802 ... SiN Passivation film, 803 ... bonding pad, 804 ... insulation Film layer, 805 ... rearranged wiring, 806 ... insulating film layer, 807 ... under bump metal layer, 808 ... solder, 901 ... semiconductor substrate, 902 ... passivation film (silicon nitride film), 903 ... scribe line, 904 ... guard ring Layer, 905... Device device peripheral guard ring layer, 906... Semiconductor device.

Claims (12)

A semiconductor device in which a plurality of wiring layers are stacked on a substrate,
The wiring layer is
A first insulating layer, a second insulating layer, and a third insulating layer;
Each including a conductor wiring formed through the first to third insulating layers,
The first insulating layer and the third insulating layer are:
Including at least one of silicon carbonitride film, silicon carbide and silicon oxide,
The second insulating layer of the wiring layer located in the lower layer portion of the wiring layer includes silicon oxide,
The second insulating layer of the wiring layer located in the upper layer portion of the wiring layer includes at least one of fluorine-added silicon oxide and carbon-added silicon oxide. A semiconductor device in which a plurality of wiring layers are stacked on a substrate,
The wiring layer is
A first insulating layer, a second insulating layer, and a third insulating layer;
Each including a conductor wiring formed through the first to third insulating layers,
The first insulating layer and the third insulating layer are:
Including at least one of silicon carbonitride film, silicon carbide and silicon oxide,
The relative dielectric constant of the second insulating layer of the wiring layer located in the lower layer portion of the wiring layer is smaller than the relative dielectric constant of the second insulating layer of the wiring layer located in the upper layer portion of the wiring layer. A semiconductor device characterized by the above.   3. The semiconductor device according to claim 1, wherein a relative dielectric constant of a second insulating layer of the wiring layer located in the lower layer portion of the wiring layer is less than 3.0.   The semiconductor device according to claim 1, wherein a second insulating layer of the wiring layer located in the lower layer portion of the wiring layer has a minute hole.   5. The semiconductor device according to claim 4, wherein a diameter of half or more of the minute holes is 0.05 nm or more and 4 nm or less.   The semiconductor device according to claim 1, wherein a second insulating layer of the wiring layer located in the lower layer portion of the wiring layer contains SiO.   The second insulating layer of the wiring layer located in the lower layer portion of the wiring layer is an insulating film obtained by heating a film containing a silsesquioxane hydrogen compound or a silsesquioxane methyl compound. The semiconductor device according to claim 1.   The semiconductor device according to claim 1, wherein a second insulating layer of the wiring layer located in the lower layer portion of the wiring layer is made of a film containing an alkylsilane compound and an alkoxysilane compound. .   A component of the second insulating layer of the wiring layer located in the lower layer portion of the wiring layer and a component of the second insulating layer of the wiring layer located in the upper layer portion of the wiring layer The semiconductor device according to claim 1, which is different.   10. The first insulating layer of the wiring layer disposed in the upper layer also serves as the third insulating layer of the wiring layer disposed in the lower layer among the adjacent wiring layers. 11. A semiconductor device according to 1. A substrate,
A semiconductor element provided on the substrate;
A wiring layer including a first insulating layer, a second insulating layer made of an insulating film material having a relative dielectric constant of less than 3.0, a third insulating layer, and a conductor wiring;
A semiconductor device comprising: a guard ring layer disposed so as to surround a periphery of the semiconductor element using a material constituting the wiring layer. The second insulating layer is
12. The semiconductor device according to claim 11, wherein the semiconductor device is a silicon oxide film having a micropore having a diameter of 0.05 nm to 4 nm.

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