JP2004031918A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the deterioration of the mechanical strength of the whole elements, and to reduce the delay of a signal propagating through wirings. <P>SOLUTION: A first insulating layer and a third insulating layer configuring each wiring layer 100 contain a silicon carbide/nitride film, silicon carbide and/or silicon oxide, the second insulating layer of a lower wiring layer contains the silicon oxide, and the second insulating layer of an upper wiring layer contains fluorinated silicon oxide and/or carbonated silicon oxide. The relative dielectric constant of the second insulating layer of the lower wiring layer is set so as to be smaller than the relative dielectric constant of the second insulating layer of the upper wiring layer. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device in which a signal wiring delay is reduced by using an insulating film having low dielectric constant characteristics as an interlayer insulating film, thereby improving element performance.
[0002]
[Prior art]
With the increase in the degree of integration of semiconductor elements and the reduction in chip size, finer wiring, narrower pitches, and multilayering are being promoted. Along with this, a delay time when a signal propagates through a wiring, that is, a wiring delay tends to increase, which is a major problem when using an electronic device using a semiconductor element.
Generally, the speed of a signal propagating through a wiring is determined by the product (RC) of the wiring resistance (R) and the capacitance between wirings (C). Therefore, reducing the wiring resistance or reducing the capacitance between wirings, that is, an interlayer insulating film It is necessary to lower the dielectric constant in order to reduce wiring delay.
[0003]
In order to reduce the wiring resistance, in the case of high-performance semiconductor devices, the wiring material is being changed from aluminum to copper, and the process application of the damascene structure, in which copper wiring is buried in the interlayer insulating film layer, has been actively performed. Have been
[0004]
In order to reduce the dielectric constant of an interlayer insulating film, a silicon oxide film (SiO 2) conventionally formed by a CVD (Chemical Vapor Deposition) method is used for an interlayer insulating film of a semiconductor device. ₂ : A relative dielectric constant of about 4.0) or an inorganic material such as a silicon nitride film (Si-N: a relative dielectric constant of about 7.0). As a low dielectric constant material that can follow the conventional process, recently, a fluorine-added silicon oxide film (Si-OF: a relative dielectric constant of about 3.6) has been successively adopted.
[0005]
However, the dielectric constant of the fluorine-doped silicon oxide film is relatively high, and when this is used as an interlayer insulating film, the effect of reducing the interlayer capacitance is not sufficient. A material having a modulus is needed.
[0006]
Various materials have been proposed as interlayer insulating film materials having a relative dielectric constant of less than 3.5, and when roughly classified, a so-called spin-on-glass material, which forms a film by heating after being applied to a substrate, or a similar material. An organic material for forming a film and a technique for forming a film using a CVD method are also being studied.
[0007]
Examples of the spin-on-glass material include a material containing a hydrogen silsesquioxane (Hydrogen Silsesquioxane) compound or a methyl silsesquioxane methyl (Methyl Silsesquioxane) compound. A material containing a silsesquioxane hydrogen compound or a silsesquioxane methyl compound as a main component is preferable. In this specification, the main component refers to a component having the highest blending ratio (molar ratio).
[0008]
The coating solution containing a silsesquioxane hydrogen compound as a main component has a general formula (HSiO _3/2 ) _n Is dissolved in a solvent such as methyl isobutyl ketone. This solution is applied to a substrate, heated intermediately at a temperature of about 100 to 250 ° C., and then heated at a temperature of 350 to 450 ° C. in an inert atmosphere such as a nitrogen atmosphere, thereby forming Si—O—Si. The bond is formed in a ladder structure, and finally an insulating film containing SiO as a main component is formed.
[0009]
A coating solution containing a silsesquioxane methyl compound as a main component has a general formula (CH ₃ SiO _3/2 ) _n Is dissolved in a solvent such as methyl isobutyl ketone. This solution is applied to a substrate, heated intermediately at a temperature of about 100 to 250 ° C., and then heated at a temperature of 350 to 450 ° C. in an inert atmosphere such as a nitrogen atmosphere, thereby forming Si—O—Si. The bond is formed in a ladder structure, and finally an insulating film containing SiO as a main component is formed.
[0010]
As an organic insulating film material, polymer materials such as polyimide, polyparaxylylene, polyarylene ether, polyarylene, benzcyclobutene, and polynaphthalene, which are hydrocarbon resins, are known. These materials achieve a low dielectric constant by reducing the density of the film by containing carbon atoms and by reducing the polarizability of the molecule (monomer) itself.
[0011]
As a technique for further reducing the relative dielectric constant of an interlayer insulating film such as the above-described spin-on-glass film, organic film, or CVD film, it is known to form a porous film by forming minute holes in the film. The above materials and processes are disclosed in "International Technology Roadmap for Semiconductors" (ed. 1999), pp. 163-186, JP-A-2000-340569, and JP-A-2001-274239.
[0012]
However, in the above-described conventional technology, an interlayer insulating film having a characteristic whose relative dielectric constant is lower than 3.5 has a mechanical property such as hardness and elastic modulus of the insulating film, which is lower than that of a silicon oxide film or a silicon nitride film formed by CVD. There is a problem that the strength is essentially low.
[0013]
In such an insulating film, forming pores in the film to make the film porous to further reduce the relative dielectric constant is in the direction of further deteriorating the mechanical strength, and is not realistic. It had been.
[0014]
As a means for lowering the relative dielectric constant of the insulating film, an insulating organic polymer such as polyimide may be used. Organic polymers are advantageous because their relative dielectric constants are less than 4, but they have disadvantages in that they are physically lower in mechanical strength and higher in hygroscopicity and moisture permeability than inorganic films. In addition, when used as an interlayer insulating film, there is a problem in reliability of the device, such as a decrease in mechanical strength of the device structure and corrosion of wiring due to moisture absorption.
[Non-patent document 1]
"International Technology Roadmap for Semiconductors" (1999), pp. 163-186.
[Patent Document 1]
JP 2000-340569 A
[Patent Document 2]
JP 2001-274239 A
[0015]
[Problems to be solved by the invention]
Therefore, in particular, in a multilayer wiring semiconductor element using a damascene structure in which copper wiring with reduced wiring resistance is embedded in an interlayer insulating film layer, the dielectric constant of the entire interlayer insulating film is reduced while suppressing a decrease in mechanical strength of the element structure. The method was examined.
[0016]
Based on the technical background described above, the present invention has a laminated structure of a film having a low dielectric constant and a film having a high dielectric constant as described above, and by optimizing the combination and structure of each material, An object of the present invention is to propose a method for realizing both electrical characteristics and mechanical characteristics of an insulating film itself.
[0017]
In particular, in a semiconductor device having a laminated structure employing a damascene structure in which copper wiring with reduced wiring resistance is embedded in an interlayer insulating film layer, a signal delay propagating through the wiring is suppressed while suppressing a decrease in mechanical strength of the interlayer insulating film. A highly reliable and high-performance semiconductor device with reduced characteristics has been made possible.
[0018]
[Means for Solving the Problems]
The semiconductor device of the present invention has a structure in which a first insulating layer, a second insulating layer, a third insulating layer, and the three insulating layers are formed on a substrate on which a transistor element and a semiconductor circuit portion are formed. This is a semiconductor device formed by laminating a plurality of wiring layers each having the formed conductor wiring. At this time, the first and third insulating layers constituting each wiring layer are made of a silicon carbonitride film, a silicon carbide, or a silicon oxide. The insulating layer of Example 1 contains silicon oxide, and the second insulating layer of the wiring layer located on the upper layer part contains silicon oxide containing fluorine or silicon oxide.
[0019]
At this time, when a copper wiring is used as a conductor wiring, the first insulating film serves as an etching stopper film when the insulating film is opened to bury the copper wiring. Further, the third insulating layer becomes a diffusion barrier film for the copper wiring.
[0020]
Conventionally, a silicon nitride film has been used as an etching stopper film and a diffusion barrier film. In the present invention, a silicon carbonitride film having a lower relative dielectric constant than a silicon nitride film (Si—CN: about 4.6). Since a film made of silicon carbide (Si—C: relative dielectric constant of about 4.4) or silicon oxide is used, the relative dielectric constant of the entire wiring layer having a multilayer structure can be reduced.
[0021]
Among the wiring layers, the second insulating layer of the wiring layer located on the upper layer portion is made of a fluorine-doped silicon oxide film or a carbon-doped silicon oxide film having a relative dielectric constant smaller than that of the silicon oxide film (a relative dielectric constant of about 2.9). Thereby, the relative dielectric constant of the entire wiring layer can be reduced as compared with the case where all the second insulating layers constituting the wiring layer are made of silicon oxide.
[0022]
Further, in the semiconductor device of the present invention, the second insulating layer of the lower wiring layer is made of an insulating film material having a relative dielectric constant of less than 3.0, and the second insulating layer of the upper wiring layer is formed of an insulating film material. It was made of a fluorine-added silicon oxide film or a carbon-added silicon oxide film. That is, the constituent components of the second insulating layer are made different between the wiring layer located in the upper layer portion and the wiring layer located in the lower layer portion so that the relative dielectric constant of the latter insulating film is smaller than that of the former. did.
[0023]
Further, in the semiconductor device of the present invention, the second insulating layer of the lower wiring layer has a characteristic of a relative dielectric constant of less than 3.0, is an insulating film containing SiO, and has Or more of the micropores existing in the sample had a diameter of 0.05 nm or more and 4 nm or less. In the present invention, it is preferable that the main configuration of the micropores has a diameter of 0.05 nm or more and 4 nm or less. According to the present invention, a multi-layer laminated structure is obtained by using a SiO-containing insulating film having a relative dielectric constant of less than 3.0 as a single film by reducing the density of the film by having micropores in the film. In the entire wiring layer, the relative dielectric constant can be further reduced.
[0024]
At this time, the relative permittivity of the insulating film is reduced from the relative permittivity of the silicon oxide film by using a method in which minute holes are formed in the insulating film to lower the density and approach the relative permittivity of vacuum. In particular, by controlling the size and density of the minute holes, an insulating film having an arbitrary relative dielectric constant can be formed.
[0025]
However, as the diameter of the micropores increases, the mechanical strength of the insulating film itself as a structure decreases, or the leakage current flowing through the insulating film increases, thereby lowering the dielectric strength characteristic of the insulating film. The problem described above also newly arises, and it is necessary to pay close attention to the size of the holes contained in the insulating film.
[0026]
Therefore, in the present invention, by controlling the range of the pore diameter, a decrease in the mechanical strength and the dielectric strength of the insulating film is suppressed. At this time, when at least half of the minute holes have a diameter of 0.05 nm or more and 4 nm or less, a highly reliable semiconductor device can be provided without reducing the film strength of the insulating film.
[0027]
The insulating film having microvoids is formed of an insulating film mainly containing SiO, which is obtained by heating a film mainly containing a silsesquioxane hydrogen compound or a silsesquioxane methyl compound.
[0028]
The coating solution containing a silsesquioxane hydrogen compound as a main component has a general formula (HSiO _3/2 ) _n Is dissolved in a solvent such as methyl isobutyl ketone. A coating solution containing a silsesquioxane methyl compound as a main component is represented by the general formula (CH ₃ SiO _3/2 ) _n Is dissolved in a solvent such as methyl isobutyl ketone.
[0029]
These solutions are applied to a substrate, intermediately heated at a temperature of about 100 to 250 ° C., and then heated at a temperature of 350 to 450 ° C. in an inert atmosphere such as a nitrogen atmosphere to obtain Si—O—Si. Are formed in a ladder structure, and finally an insulating film containing SiO as a main component is formed.
[0030]
As a method for controlling the diameter of pores present in an insulating film in an insulating film mainly containing SiO obtained by heating a film mainly containing a silsesquioxane hydrogen compound or a silsesquioxane methyl compound, For example, a solution other than a solvent such as methyl isobutyl ketone is added to a solution of a silsesquioxane compound in a silsesquioxane compound solution, and traces of the decomposition of the component are formed as pores in the film, and the decomposition behavior changes depending on the film formation temperature. By doing so, there is a method of controlling the formation of holes and making it possible to keep the hole diameter range within a selective range.
[0031]
As a method of applying the above-mentioned solution for forming an insulating film, spin coating, slit coating or a printing method may be used. Since the insulating film is formed by heating this film, even if fine wiring is formed at high density, the step coverage is better than that of the insulating film formed by the CVD method. This is advantageous in that surface steps can be eliminated.
[0032]
In addition, in order to increase the diameter of a Si wafer, when an insulating film is formed using a CVD method, a large-sized film forming apparatus is required, and the equipment cost has a large effect on the element cost. On the other hand, in the present invention, since the insulating film is formed by the coating / heating method, the equipment cost can be significantly reduced, and a great effect of suppressing the investment cost of the production line and further the element cost is expected. it can.
[0033]
When an insulating film is formed by a CVD method, an alkylsilane compound or an alkoxysilane compound is used as a main component as a source gas, and finally SiO is used as a main component by an ECR (Electron Cyclotron Resonance) plasma CVD method or the like. An insulating film is formed.
[0034]
Also in this case, as a technique for controlling the diameter of the pores present in the insulating film, for example, a component having a high thermal decomposition temperature is contained as a source gas, and the film is heated at 350 ° C. to 450 ° C. during film formation to form a film. There is a method in which traces of the decomposition of this component are formed as pores.
[0035]
In such a method, it is possible to change the decomposition behavior depending on the film formation temperature by selecting various components having a high thermal decomposition temperature, and thereby selectively control the pore formation, thereby selectively controlling the pore diameter range. Within the optimal range.
[0036]
Further, in the semiconductor device of the present invention, in order to prevent moisture absorption and moisture permeation from the periphery of the semiconductor device, a partition layer (referred to as a guard ring in the present invention) made of a material forming a conductor wiring so as to surround the periphery of the element device. Is provided around the element device. Thus, according to the present invention, the moisture permeating the inside of the interlayer insulating film from around the element or from the interface between the substrate and the interlayer insulating film can be shielded, and the humidity resistance reliability of the element itself can be improved.
[0037]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0038]
(First embodiment)
In the first embodiment, as shown in FIG. 1, a six-layer wiring semiconductor element having a Cu wiring dual damascene structure having six wiring layers 100 was manufactured.
[0039]
A silicon carbonitride film 102 serving as a first insulating layer of a first wiring layer 100a having a thickness of 40 nm is formed on a semiconductor substrate 101 on which constituent elements (not shown) such as MOS transistors are formed by using a generally well-known method. And formed by a CVD method. This first insulating layer becomes an etching stopper film at the time of opening for forming a wiring pattern.
[0040]
Next, a silicon oxide film 103 serving as a second insulating layer of the first wiring layer 100a was formed to a thickness of 400 nm by a CVD method.
[0041]
Next, a silicon carbonitride film 104 serving as a third insulating layer of the first wiring layer 100a was formed to a thickness of 40 nm by a CVD method. This film also serves as an etching stopper film and a Cu diffusion barrier film at the time of opening for forming a wiring pattern as a first insulating layer of the second wiring layer 100b.
[0042]
Next, an opening 117 was formed in the silicon carbonitride film 104. The opening is formed by using a photoresist, forming a resist pattern by a known technique, using an etching gas capable of removing a silicon carbonitride film, and using a resist as a mask and a dry etching method (FIG. 2A )). At this time, the opening has the wiring size of the first wiring layer 100a.
[0043]
Next, using a method similar to that for forming the first wiring layer 100a, a silicon oxide film 105 serving as a second insulating layer of the second wiring layer 100b is formed to a thickness of 400 nm and a silicon carbonitride film 106 serving as a third insulating layer is formed. It was formed with a thickness of 40 nm.
[0044]
Next, an opening 118 was formed in the silicon carbonitride film (FIG. 2B). The openings were formed by using a photoresist, forming a resist pattern by a known technique, using an etching gas capable of removing a silicon carbonitride film, and using a dry etching method with the resist as a mask.
[0045]
Next, an opening is formed in the silicon oxide film 105 by a dry etching method using a CF-based gas capable of removing the silicon oxide film using the silicon carbonitride film as a mask, and an opening 117 of the silicon carbonitride film 104 is formed below the opening. Exposed.
[0046]
Subsequently, an opening was formed in the silicon oxide film 103 using the opening 117 of the silicon carbonitride film 104 as a mask, and the silicon carbonitride film 102 was exposed below the opening.
[0047]
Subsequently, the etching gas was changed to an etching gas capable of removing the silicon carbonitride film, and the silicon carbonitride film 102 was dry-etched and removed using the opening of the silicon oxide film 103 as a mask to form an opening penetrating the semiconductor substrate 101. At this time, the silicon carbonitride film 104 is also etched and spreads to the same size as the opening 118 of the uppermost silicon carbonitride film. Thus, a wiring groove 119 penetrating through the semiconductor substrate 101 was formed (FIG. 2C).
[0048]
Next, after a barrier metal film 120 was formed on the inner surface of the wiring groove 119, Cu 121 was filled using a well-known plating method. In this embodiment, TiN is used as the barrier metal.
[0049]
Then, an unnecessary Cu film existing on the silicon carbonitride film as the uppermost layer was removed, and the surface was washed, thereby simultaneously forming a connection plug and a wiring. For the removal of the Cu film, it is convenient to use a chemical mechanical polishing method using alumina or silica as abrasive grains and a polishing agent comprising an additive such as a Cu complexing agent and a surfactant. is there.
[0050]
In this polishing step, the silicon carbonitride film 106 corresponding to the uppermost layer was also removed by polishing. Thus, a dual damascene structure in which Cu wirings (including 120 and 121) were formed (FIG. 2D).
[0051]
Subsequently, the same process was performed twice to form the third wiring layer 100c to the sixth wiring layer 100f, thereby obtaining a six-layer Cu wiring structure. At this time, the insulating layers 106, 108, 110, and 112 are made of a silicon carbonitride film formed by a CVD method, and the insulating layers 107 and 109 are made of a silicon oxide film. The insulating layers 111 and 113 are made of a fluorine-added silicon oxide film.
[0052]
Next, a silicon nitride film 114 was formed on the uppermost layer, and a multilayer wiring semiconductor device having six layers of Cu wiring 115 was manufactured (FIG. 1).
[0053]
As a result, a silicon carbonitride film having a lower dielectric constant than a silicon nitride film is used as an etching stopper film and a diffusion barrier film, and a fluorine-doped silicon oxide film having a lower dielectric constant than a silicon oxide film is used in an upper layer of the multilayer structure. By using the film, a high-performance semiconductor device in which the dielectric constant of the entire interlayer insulating film was lowered was obtained.
[0054]
(Second embodiment)
In the present embodiment, a fluorine-added silicon oxide film was formed also on the insulating layers 107 and 109 by using the CVD method using the same method as in the first embodiment. Next, a silicon nitride film 114 was formed on the uppermost layer, and a multilayer wiring semiconductor device having six layers of Cu wiring 115 was manufactured.
[0055]
As a result, a silicon carbonitride film having a lower dielectric constant than the silicon nitride film is used as the etching stopper film and the diffusion barrier film, and a dielectric constant higher than that of the silicon oxide film in the upper part of the multilayer structure. By using a small fluorine-added silicon oxide film, a high-performance semiconductor device in which the dielectric constant of the entire interlayer insulating film was lowered was obtained.
[0056]
(Third embodiment)
In this example, a silicon carbide film was formed on the insulating layers 102, 104, 106, 108, 110, and 112 by using the CVD method by using the same method as that in the first example. Next, a silicon nitride film 114 was formed on the uppermost layer, and a multilayer wiring semiconductor device having six layers of Cu wiring 115 was manufactured.
[0057]
As a result, a high-performance semiconductor device in which the dielectric constant of the entire interlayer insulating film is reduced by using a silicon carbide film having a lower dielectric constant than the silicon nitride film as the etching stopper film and the diffusion barrier film is obtained.
[0058]
(Fourth embodiment)
In this example, a silicon carbide film was formed on the insulating layers 102, 104, 106, 108, 110, and 112 by using the CVD method by using the same method as that of the second example. Next, a silicon nitride film 114 was formed on the uppermost layer, and a multilayer wiring semiconductor device having six layers of Cu wiring 115 was manufactured.
[0059]
As a result, a high-performance semiconductor device in which the dielectric constant of the entire interlayer insulating film is reduced by using a silicon carbide film having a lower dielectric constant than the silicon nitride film as the etching stopper film and the diffusion barrier film is obtained.
[0060]
(Fifth embodiment)
In the present embodiment, using a method similar to that of the first embodiment, a carbon-doped silicon oxide film is formed on the insulating layers 111 and 113 by using a CVD method, and a multilayer wiring semiconductor including six Cu wirings 115 is provided. An element was manufactured.
[0061]
Thus, a high-performance semiconductor device in which the dielectric constant of the entire interlayer insulating film is reduced by using a carbon-doped silicon oxide film having a relative dielectric constant smaller than that of the silicon oxide film in the upper layer of the multilayer structure is obtained.
[0062]
(Sixth embodiment)
In the present embodiment, a carbon-added silicon oxide film is formed on the insulating layers 107, 109, 111, and 113 by using the CVD method, using the same method as that of the second embodiment. The multilayer wiring semiconductor device provided was produced.
[0063]
Further, by using a carbon-doped silicon oxide film having a relative dielectric constant smaller than that of the silicon oxide film in an upper layer portion of １ ／ or more of the multilayer structure, a high-performance semiconductor device in which the dielectric constant of the entire interlayer insulating film is reduced can be obtained. Was done.
[0064]
(Seventh embodiment)
In the present embodiment, a silicon carbide film was formed on the insulating layers 102, 104, 106, 108, 110, and 112 by using the CVD method by using the same method as that of the fifth embodiment. Next, a silicon nitride film 114 was formed on the uppermost layer, and a multilayer wiring semiconductor device having six layers of Cu wiring 115 was manufactured.
[0065]
As a result, a high-performance semiconductor device in which the dielectric constant of the entire interlayer insulating film is reduced by using a silicon carbide film having a lower dielectric constant than the silicon nitride film as the etching stopper film and the diffusion barrier film is obtained.
[0066]
(Eighth embodiment)
In this example, a silicon carbide film was formed on the insulating layers 102, 104, 106, 108, 110, and 112 by using the CVD method by using the same method as in the sixth example. Next, a silicon nitride film 114 was formed on the uppermost layer, and a multilayer wiring semiconductor device having six layers of Cu wiring 115 was manufactured.
[0067]
As a result, a high-performance semiconductor device in which the dielectric constant of the entire interlayer insulating film is reduced by using a silicon carbide film having a lower dielectric constant than the silicon nitride film as the etching stopper film and the diffusion barrier film is obtained.
[0068]
(Ninth embodiment)
In the present embodiment, a carbon-added silicon oxide film is formed on the insulating layers 103, 105, 107, and 109 using a CVD method, using the same method as in the first embodiment. The multilayer wiring semiconductor device provided was produced.
[0069]
As a result, a carbon-doped silicon oxide film having a low relative dielectric constant is used as an insulating film in a lower layer portion of the multilayer structure, and a fluorine-doped silicon oxide film having a lower dielectric constant than the silicon oxide film is formed in an upper layer portion of the multilayer structure. By using the same, a high-performance semiconductor device in which the dielectric constant of the entire interlayer insulating film is reduced was obtained.
[0070]
(Tenth embodiment)
In the present embodiment, using the same method as that of the second embodiment, a carbon-doped silicon oxide film is formed on the insulating layers 103 and 105 by using the CVD method, and a multilayer wiring semiconductor including six layers of Cu wiring 115 is provided. An element was manufactured.
[0071]
Accordingly, a carbon-doped silicon oxide film having a low relative dielectric constant is used as an insulating film in a lower layer portion of the multilayer structure, and fluorine having a lower relative dielectric constant than the silicon oxide film is used in an upper layer portion of the multilayer structure of 以上 or more. By using the added silicon oxide film, a high-performance semiconductor device in which the dielectric constant of the entire interlayer insulating film was lowered was obtained.
[0072]
(Eleventh embodiment)
In the present embodiment, a carbon-added silicon oxide film is formed on the insulating layers 103, 105, 107, and 109 using a CVD method, using the same method as in the third embodiment. The multilayer wiring semiconductor device provided was produced.
[0073]
As a result, a carbon-doped silicon oxide film having a low relative dielectric constant is used as an insulating film in a lower layer portion of the multilayer structure, and a fluorine-doped silicon oxide film having a lower dielectric constant than the silicon oxide film is formed in an upper layer portion of the multilayer structure. By using a silicon carbide film having a lower dielectric constant than a silicon nitride film as an etching stopper film and a diffusion barrier film, a high-performance semiconductor device having a reduced dielectric constant of the entire interlayer insulating film was obtained.
[0074]
(Twelfth embodiment)
In the present embodiment, using the same method as in the fourth embodiment, a carbon-added silicon oxide film is formed on the insulating layers 103 and 105 by using the CVD method, and a multilayer wiring semiconductor including six layers of Cu wiring 115 is provided. An element was manufactured.
[0075]
Accordingly, a carbon-doped silicon oxide film having a low relative dielectric constant is used as an insulating film in a lower layer portion of the multilayer structure, and fluorine having a lower relative dielectric constant than the silicon oxide film is used in an upper layer portion of the multilayer structure of 以上 or more. By using a silicon oxide film with an added silicon oxide film and a silicon carbide film with a lower dielectric constant than a silicon nitride film as an etching stopper film and a diffusion barrier film, a high-performance semiconductor device with a reduced dielectric constant of the entire interlayer insulating film is obtained. Was done.
[0076]
(Thirteenth embodiment)
In this embodiment, using a method similar to that of the first embodiment, a coating method of a methyl isobutyl ketone solution containing a silsesquioxane hydrogen compound as a main component is applied to the insulating layers 103, 105, 107, and 109. After being formed on the substrate by using a hot plate in a nitrogen atmosphere, heating was performed at 100 ° C. for 10 minutes, then at 150 ° C. for 10 minutes, and at 230 ° C. for 10 minutes.
[0077]
Further, by heating at 350 ° C. for 30 minutes using a furnace in a nitrogen atmosphere, Si—O—Si bonds are formed in a ladder structure, and finally, the formation of vacancies is controlled using SiO as a main component. An insulating film having micropores formed in the film was formed, and a multilayer wiring semiconductor element having six layers of Cu wiring 115 was manufactured. The openings were formed by a dry etching method using a CF-based gas capable of etching SiO.
[0078]
In the case of the present embodiment, as shown in FIG. 3, the insulating film has fine pores having distribution characteristics mainly including pores having a diameter of 0.05 nm or more and 4 nm or less, and has a relative dielectric constant of 2. It is about 3.
[0079]
The diameter distribution was assumed to be a spherical scatterer based on X-ray reflection measurement data and diffuse scattering X-ray measurement data obtained using an X-ray thin film structure analyzer (model: ATX? G) manufactured by Rigaku Corporation. It was obtained by calculating the diameter distribution of the scatterer in comparison with the theoretical scattering intensity based on the scattering function.
[0080]
Further, the insulating film having the above-described minute holes in the film has a characteristic of a Young's modulus of 12 Ga. These characteristics were determined by the indentation measurement method using Nanoindenter XP manufactured by U.S. MTS Systems Co., Ltd., and the above-mentioned hardness was measured at a surface point of 1/5 of the total film thickness of the same film having a film thickness of 250 nm formed on a Si wafer. The film hardness was determined.
[0081]
The Young's modulus is also a value at a surface point of 1/5 of the total film thickness, and was converted based on the Poisson's ratio of fused quartz of 0.17. A similar film thickness p? The TEOS film has a characteristic of a Young's modulus of 70 Ga.
[0082]
From now on, the insulating film having the micropores in the film is p? A TEOS film having a Young's modulus of about 17% and a low dielectric constant insulating film having more excellent mechanical properties than the low dielectric constant film described in JP-A-2000-340569 was obtained.
[0083]
Thus, in the lower layer of the multilayer structure, an insulating film having a relative dielectric constant of less than 2.5 and excellent in film strength is used, and in the upper layer of the multilayer structure, fluorine-doped silicon having a lower dielectric constant than the silicon oxide film is used. By using the oxide film, a high-performance semiconductor device was obtained while lowering the dielectric constant of the entire interlayer insulating film and suppressing a decrease in mechanical strength of the element structure.
[0084]
(14th embodiment)
In this example, a silicon carbide film was formed on the insulating layers 102, 104, 106, 108, 110, and 112 using a CVD method by using the same method as in the thirteenth example.
[0085]
Next, a silicon nitride film 114 was formed on the uppermost layer, and a multilayer wiring semiconductor device having six layers of Cu wiring 115 was manufactured.
[0086]
As a result, a silicon carbide film having a lower dielectric constant than a silicon nitride film is used as an etching stopper film or a diffusion barrier film, and an insulating film having fine pores in the film is used to define the hole diameter. A low dielectric constant insulating film having excellent mechanical properties can be obtained.
[0087]
Further, in the lower part of the multilayer structure, an insulating film having a relative dielectric constant of less than 2.5 and excellent in film strength is used as a second insulating layer. By using a fluorine-doped silicon oxide film having a relative dielectric constant smaller than that of the silicon oxide film for the layer, a high-performance semiconductor device can be obtained while lowering the dielectric constant of the entire interlayer insulating film and suppressing a decrease in mechanical strength of the element structure. Was.
[0088]
(Fifteenth embodiment)
In this embodiment, using a method similar to that of the thirteenth embodiment, a methyl isobutyl ketone solution containing a silsesquioxane hydrogen compound as a main component is applied to the insulating layers 103, 105, 107, and 109 by a coating method. After being formed on the substrate by using a hot plate in a nitrogen atmosphere, heating was performed at 100 ° C. for 10 minutes, then at 150 ° C. for 10 minutes, and at 230 ° C. for 10 minutes.
[0089]
Further, by heating at 350 ° C. for 30 minutes using a furnace in a nitrogen atmosphere, Si—O—Si bonds are formed in a ladder structure, and finally, the formation of vacancies is controlled using SiO as a main component. An insulating film having micropores formed in the film was formed, and a multilayer wiring semiconductor element having six layers of Cu wiring 115 was manufactured. The openings were formed by a dry etching method using a gas for etching SiO.
[0090]
In the case of this embodiment, as shown in FIG. 4, the insulating film has microvoids having distribution characteristics mainly including pores having a diameter of 0.05 nm or more and 1 nm or less, and has a relative dielectric constant of 2. It is about 7.
[0091]
The diameter distribution is calculated based on the X-ray reflection measurement data and the diffuse scattering X-ray measurement data obtained by using the X-ray thin film structure analyzer, comparing the theoretical scattering intensity with the theoretical scattering intensity based on a scattering function assuming a spherical scatterer. It was determined by calculating the body diameter distribution.
[0092]
Further, the insulating film having the above microvoids in the film has a characteristic of a Young's modulus of 11 Ga. These characteristics were obtained by using an indentation measurement method using Nanoindenter XP, and determining the above film hardness from the hardness at a surface point of 1/5 of the total film thickness of the same film having a thickness of 250 nm formed on a Si wafer. .
[0093]
The Young's modulus is also a value at a surface point of 1/5 of the total film thickness, and was converted based on the Poisson's ratio of fused quartz of 0.17. A similar film thickness p? The TEOS film has a characteristic of a Young's modulus of 70 Ga.
[0094]
From now on, the insulating film having the micropores in the film is p? A TEOS film having a Young's modulus of about 16% and a low dielectric constant insulating film having more excellent mechanical properties than the low dielectric constant film described in JP-A-2000-340569.
[0095]
As described above, in the lower part of the multilayer structure, an insulating film having a relative dielectric constant of less than 3.0 and excellent in film strength is used as the second insulating layer, and the second insulating layer is formed in the upper part of the multilayer structure. By using a fluorine-doped silicon oxide film having a relative dielectric constant smaller than that of the silicon oxide film for the layer, a high-performance semiconductor device can be obtained while lowering the dielectric constant of the entire interlayer insulating film and suppressing a decrease in mechanical strength of the element structure. Was.
[0096]
(Sixteenth embodiment)
In the present embodiment, a silicon carbide film was formed on the insulating layers 102, 104, 106, 108, 110, and 112 by using the CVD method by using the same method as in the fifteenth embodiment. Next, a silicon nitride film 114 was formed on the uppermost layer, and a multilayer wiring semiconductor device having six layers of Cu wiring 115 was manufactured.
[0097]
As a result, a silicon carbide film having a lower dielectric constant than a silicon nitride film is used as an etching stopper film or a diffusion barrier film, and an insulating film having fine pores in the film is used to define the hole diameter. A low dielectric constant insulating film having excellent mechanical properties was obtained. In the lower part of the multilayer structure, an insulating film having a relative dielectric constant of less than 3.0 and excellent in film strength is used as a second insulating layer, and in the upper part of the multilayer structure, a second insulating layer is formed. By using a fluorine-doped silicon oxide film having a lower relative dielectric constant than the silicon oxide film, a high-performance semiconductor device was obtained while lowering the dielectric constant of the entire interlayer insulating film and suppressing a decrease in mechanical strength of the element structure.
[0098]
(Seventeenth embodiment)
The seventeenth embodiment is an example applied to the formation of a Cu wiring dual damascene structure, and will be described with reference to the process diagrams of FIGS.
[0099]
A silicon carbonitride film 502 serving as a first insulating layer of a first wiring layer having a thickness of 40 nm is formed on a semiconductor substrate 501 on which constituent elements (not shown) such as MOS transistors are formed by using a generally well-known method. It was formed using a CVD method. This first insulating layer becomes an etching stopper film at the time of opening for forming a wiring pattern.
[0100]
Next, a methyl isobutyl ketone solution containing a silsesquioxane hydrogen compound as a main component is formed on a substrate by a coating method, and then, in a nitrogen atmosphere, at 100 ° C. for 10 minutes using a hot plate, and then Heating was performed at 150 ° C. for 10 minutes and at 230 ° C. for 10 minutes. Further, by heating at 350 ° C. for 30 minutes using a furnace in a nitrogen atmosphere, a Si—O—Si bond is formed in a ladder structure, and finally SiO is used as a main component as shown in FIG. Forming an insulating film having a relative dielectric constant of about 2.3 in which micropores having distribution characteristics mainly including pores having a diameter of 0.05 nm or more and 4 nm or less exist, and forming a second insulating layer of the first wiring layer. 503.
[0101]
Next, a silicon carbon nitride film 504 serving as a third insulating layer of the first wiring layer was formed to a thickness of 40 nm by a CVD method. This film also serves as an etching stopper film and a Cu diffusion barrier film when forming a wiring pattern as a first insulating layer of the second wiring layer.
[0102]
Next, an opening 517 was formed in the silicon carbonitride film 504. The opening is formed by using a photoresist, forming a resist pattern by a known technique, using an etching gas capable of removing a silicon carbonitride film, and using a resist as a mask and a dry etching method (FIG. 5A )). At this time, the opening has the wiring size of the first wiring layer.
[0103]
Next, using a method similar to that for forming the second insulating layer 503 of the first wiring layer, the second insulating layer of the second wiring layer has a diameter of 0.05 nm or more and 4 nm or less as shown in FIG. An insulating layer 505 having a relative dielectric constant of 2.3 and a silicon carbonitride film 506 serving as a third insulating layer having a thickness of 40 nm was formed so as to have micropores having distribution characteristics mainly including vacancies.
[0104]
Next, an opening 518 was formed in the silicon carbonitride film (FIG. 5B). The openings were formed by using a photoresist, forming a resist pattern by a known technique, using an etching gas capable of removing a silicon carbonitride film, and using a dry etching method with the resist as a mask.
[0105]
Next, an opening is formed in the insulating layer 505 by a dry etching method using a gas capable of removing the SiO film having micropores using the silicon carbonitride film as a mask, and an opening 517 of the silicon carbonitride film 504 is formed thereunder. Is exposed.
[0106]
Subsequently, an opening was formed in the insulating layer 503 using the opening 517 of the silicon carbonitride film 504 as a mask, and the silicon carbonitride film 502 was exposed below the opening. Subsequently, the etching gas was switched to an etching gas capable of removing the silicon carbonitride film, and the silicon carbonitride film 502 was dry-etched and removed using the opening of the insulating layer 503 as a mask, thereby forming an opening penetrating the semiconductor substrate 501. At this time, the silicon carbonitride film 504 is also etched and spreads to the same size as the opening 518 of the uppermost silicon carbonitride film. As a result, a wiring groove 519 penetrating the semiconductor substrate 501 was formed (FIG. 5C).
[0107]
Next, after a barrier metal film 120 was formed on the inner surface of the wiring groove 119, Cu 121 was filled using a well-known plating method. In this embodiment, TiN is used as the barrier metal.
[0108]
Then, an unnecessary Cu film present on the silicon carbide nitride film as the uppermost layer was removed by using a chemical mechanical polishing method, and the surface was washed to form a connection plug and a wiring at the same time. In this polishing step, the silicon carbonitride film 506 corresponding to the uppermost layer was left without being removed by polishing. Thus, a dual damascene structure in which Cu wirings (including 520 and 521) were formed was manufactured (FIG. 5D).
[0109]
As described above, by using a film having a low relative dielectric constant for the second insulating layer 503 which is a main constituent layer of the interlayer insulating film layer, a high-performance semiconductor device in which the dielectric constant of the entire interlayer insulating film is reduced can be realized. can get.
[0110]
Although the structure of this embodiment has a structure in which two wiring layers are stacked, a semiconductor device having a multilayer wiring structure can be obtained by repeatedly stacking the wiring layers two or more times.
[0111]
(Eighteenth embodiment)
As in the seventeenth embodiment, in the present embodiment, as shown in FIG. 4, the second insulating layer 503 has minute holes having a distribution characteristic mainly including holes having a diameter of 0.05 nm or more and 1 nm or less. SiO film with relative dielectric constant of about 2.7 To Then, a dual damascene structure in which a Cu wiring was formed was fabricated.
[0112]
As a result, a high-performance semiconductor device in which the dielectric constant of the entire interlayer insulating film is reduced can be obtained by using a film having a low relative dielectric constant for 503, which is a main constituent layer of the interlayer insulating film layer. Furthermore, a high-performance semiconductor device having a multilayer wiring structure can be easily obtained by repeatedly stacking wiring layers two or more times.
[0113]
(19th embodiment)
FIG. 6 is a sectional view of a semiconductor logic element according to the nineteenth embodiment. An element isolation film region 602 is formed on a semiconductor substrate 601 using a known STI (Shallow Trench Isolation), and a MOS transistor 603 is formed inside the element isolation film region 602 (the hatching in the transistor portion is for easy viewing of the drawing. Omitted). Then, a silicon oxide film 604 of about 50 nm and a BPSG (boron phosphorus silicate glass) film 605 of about 500 nm are sequentially formed on the surface of the semiconductor substrate 601 including the MOS transistor 603 by using a known CVD method. For example, reflow annealing is performed in a nitrogen atmosphere at 800 to 900 ° C., for example.
[0114]
Next, after the surface of the BPSG film 605 is planarized and polished by using a chemical mechanical polishing method using silica abrasive grains, a contact hole is formed, and tungsten is buried in the contact hole by a CVD method to form a conductive film. A plug 606 is formed. At this time, unnecessary tungsten existing on the surface of the BPSG film 605 has been removed by a known etch-back method.
[0115]
Next, in the same manner as in the seventeenth embodiment, a silicon carbonitride film 607 to be a first insulating layer of a first wiring layer was formed to a thickness of 40 nm by a CVD method. This first insulating layer becomes an etching stopper film at the time of opening for forming a wiring pattern.
[0116]
Next, a methyl isobutyl ketone solution containing a silsesquioxane hydrogen compound as a main component is formed on a substrate by a coating method, and then, in a nitrogen atmosphere, at 100 ° C. for 10 minutes using a hot plate, and then Heating was performed at 150 ° C. for 10 minutes and at 230 ° C. for 10 minutes. Further, by heating at 350 ° C. for 30 minutes using a furnace in a nitrogen atmosphere, a Si—O—Si bond is formed in a ladder structure, and finally SiO is used as a main component as shown in FIG. Forming an insulating film having a relative dielectric constant of about 2.3 in which micropores having distribution characteristics mainly including pores having a diameter of 0.05 nm or more and 4 nm or less exist, and forming a second insulating layer of the first wiring layer. 608.
[0117]
Next, a silicon carbonitride film 609 serving as a third insulating layer of the first wiring layer was formed to a thickness of 40 nm by a CVD method. This film also serves as an etching stopper film and a Cu diffusion barrier film when forming a wiring pattern as a first insulating layer of the second wiring layer.
[0118]
Next, an opening was formed in the silicon carbonitride film 609. The openings were formed by using a photoresist, forming a resist pattern by a known technique, using an etching gas capable of removing a silicon carbonitride film, and using a dry etching method with the resist as a mask. At this time, the opening has the wiring size of the first wiring layer.
[0119]
Next, using a method similar to that for forming the second insulating layer 608 of the first wiring layer, the second insulating layer 610 of the second wiring layer is formed to a thickness of 400 nm, and the silicon carbonitride film 611 to be the third insulating layer is formed to a thickness of 40 nm. It was formed thick.
[0120]
Next, an opening was formed in the silicon carbonitride film. Then, an opening is formed in the insulating layer 610 by a dry etching method using a gas capable of removing the SiO film having micro holes using the silicon carbonitride film as a mask, and the silicon carbonitride film 609 is exposed below the opening. .
[0121]
Subsequently, an opening was formed in the insulating layer 608 using the opening of the silicon carbonitride film 609 as a mask, and the silicon carbonitride film 607 was exposed below the opening. Then, the etching gas was switched to an etching gas capable of removing the silicon carbide film, and the silicon carbonitride film 607 was dry-etched and removed using the opening of the insulating layer 608 as a mask to form an opening penetrating the conductive plug 606.
[0122]
At this time, the silicon carbonitride film 609 is also etched and spreads to the same size as the opening of the uppermost silicon carbide film. Thus, a wiring groove penetrating through the conductive plug 606 was formed.
[0123]
Next, after a barrier metal film was formed on the inner surface of the wiring groove, Cu was filled using a well-known plating method. In this embodiment, TiN is used as the barrier metal. Then, an unnecessary Cu film present on the silicon carbide nitride film as the uppermost layer was removed by using a chemical mechanical polishing method, and the surface was washed to form a connection plug and a wiring at the same time. In this polishing step, the silicon carbide film 611 corresponding to the uppermost layer was left without being removed by polishing. As a result, a dual damascene structure in which Cu wiring was formed was manufactured.
[0124]
The above steps were repeated to form a four-layer wiring structure.
Subsequently, the same steps were repeated to further build up a two-layer wiring structure. At this time, the insulating layers 617, 619, and 621 were formed with a thickness of 40 nm using a silicon carbonitride film. Further, the insulating layers 618 and 620 were formed with a thickness of 600 nm using a fluorine-added silicon oxide film. Next, a silicon nitride film 622 was formed on the uppermost layer, and a multilayer wiring semiconductor device including six layers of Cu wiring 623 was manufactured.
[0125]
As a result, a silicon carbide film having a lower dielectric constant than the silicon nitride film is used as the etching stopper film and the diffusion barrier film. By using an insulating film having excellent film strength and using a fluorine-added silicon oxide film having a lower relative dielectric constant than the silicon oxide film as the second insulating layer in the upper layer, the dielectric constant of the entire interlayer insulating film can be reduced. A reduced high-performance semiconductor device was obtained.
[0126]
(20th embodiment)
FIG. 7 is a sectional view of a resin-sealed semiconductor logic device according to a twentieth embodiment. The semiconductor logic device 701 obtained in the nineteenth embodiment and having the polyimide surface protective film 702 except for the bonding pad portion is fixed to a lead frame in a separately provided die bonding step. Thereafter, a gold wire 704 was provided between the bonding pad portion provided on the semiconductor logic device 701 and the external terminal 705 of the lead frame using a wire bonder.
[0127]
Next, using a silica-containing biphenyl-based epoxy resin manufactured by Hitachi Chemical Co., Ltd., a resin sealing portion 703 was formed so as to surround the semiconductor logic device 701, the external terminals 705, and the like. The sealing conditions are a molding temperature of 180 ° C. and a molding pressure of 70 kg / cm. ² However, the present invention is not limited to this. Finally, by bending the external terminal 706 into a predetermined shape, a completed resin-sealed semiconductor logic device is obtained.
[0128]
As a part of the interlayer insulating film of the resin-sealed semiconductor logic device, an insulating film having a small relative dielectric constant but sufficiently suppressing a decrease in mechanical strength is used. In the process, a resin-encapsulated product can be obtained without causing cracks inside the element due to stress applied to the semiconductor logic element.
[0129]
Needless to say, the same effects as described in the nineteenth embodiment can be obtained as the characteristics of the semiconductor logic element. Further, since the semiconductor logic element is sealed with resin, it is possible to exhibit stable characteristics with respect to an external environment. .
[0130]
(Twenty-first embodiment)
FIG. 8 is a sectional view for explaining the twenty-first embodiment, in which the semiconductor logic element described in the nineteenth embodiment is used for manufacturing a product having a wafer level chip size package structure.
[0131]
A polyimide insulating film 804 is formed on the uppermost silicon nitride film 802 of the semiconductor logic element 801 so as to expose the bonding pad 803. Next, a rearranged wiring 805 is formed. In the present embodiment, the rearranged wiring is composed of three layers formed by sputtering of TiN, Cu, and Ni, and a wiring pattern is formed by a well-known photolithography technique after the formation.
[0132]
Further, a polyimide insulating film 806 was formed thereon. An under-bump metal layer 807 for electrically connecting a part of the rearranged wiring 805 through the polyimide insulating film layer 806 was provided. The under bump metal layer was formed of three layers of Cr, Ni and Au. On this under bump metal layer 807, a solder bump 808 is formed.
[0133]
Since the semiconductor logic element itself capable of high-speed driving can be formed on a wafer by the method described in the nineteenth embodiment, this embodiment realizes a semiconductor logic package device having solder bumps in a wafer state.
[0134]
By applying an interlayer insulating film layer having a low dielectric constant, a semiconductor logic element having higher performance than conventional products has already been obtained. However, when a package semiconductor product is mounted on a printed circuit board or the like, by applying the package structure as in the present embodiment, it is possible to perform signal propagation between the element and the printed circuit board at a high speed, and to realize a semiconductor logic element. It is possible to further bring out the performance of.
[0135]
(Twenty-second embodiment)
FIG. 9 shows a sectional view of an element end portion (FIG. 9A) and a conceptual plan view of a wafer (FIG. 9B) for explaining the twenty-second embodiment.
[0136]
A semiconductor element 906 such as a MOS transistor and a semiconductor circuit portion including these elements are formed on a silicon substrate 901, and the wiring layer described above is formed on the substrate 901. A guard ring layer 905 is arranged so as to surround the semiconductor element 906 and a semiconductor circuit portion including these elements, using a material made of a conductor forming a wiring layer. The guard ring layer 905 can prevent the penetration of moisture from the outside into the semiconductor element 906 and the semiconductor circuit portion including these elements. The guard ring layer 905 is formed in a step of forming a conductor wiring.
[0137]
This solves the problem of permeation and adsorption of moisture into holes, especially when an insulating film having holes is used as an interlayer insulating film exhibiting low dielectric constant characteristics, and improves the humidity resistance reliability of the semiconductor element itself. A semiconductor device can be provided.
[0138]
Although the present invention has been described in detail with reference to the embodiments, the present invention and various conditions for achieving the embodiments are not limited to these embodiments.
[0139]
【The invention's effect】
As described above, in a semiconductor device having a multi-layer stacked wiring employing a damascene structure in which a copper wiring having a reduced wiring resistance is embedded in an interlayer insulating film layer, a relative dielectric constant smaller than a silicon nitride film as an etching stopper film or a diffusion barrier film. By using different films, and by making the insulating films in the lower layer and the upper layer different from each other in the multilayer laminated structure, the mechanical strength of the entire device is increased, and the dielectric constant of the entire interlayer insulating film is reduced. A semiconductor device can be obtained.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor device having a stacked structure manufactured in a first embodiment.
FIG. 2 is a process chart for explaining the semiconductor device manufactured in the first embodiment.
FIG. 3 is a diagram for explaining a diameter distribution of holes existing in an insulating film.
FIG. 4 is a diagram for explaining a diameter distribution of holes existing in an insulating film.
FIG. 5 is a process chart for explaining a semiconductor device having a laminated structure manufactured in a seventeenth embodiment.
FIG. 6 is a cross-sectional view for explaining a semiconductor logic device manufactured in a nineteenth embodiment.
FIG. 7 is a cross-sectional view illustrating a resin-sealed semiconductor device manufactured in a twentieth embodiment.
FIG. 8 is a sectional view for explaining a semiconductor device having a wafer level chip size package structure manufactured in a twenty-first embodiment.
9A and 9B are a cross-sectional view and a plan view illustrating a semiconductor device having a guard ring structure manufactured in a twenty-second embodiment.
[Explanation of symbols]
101: semiconductor substrate; 102: first insulating film of a single-layer wiring layer; 103: second insulating film of a single-layer wiring layer; 104: third insulating film of a single-layer wiring layer / first insulating film of a two-layer wiring layer .., 105: a second insulating film of a two-layer wiring layer; 106, a third insulating film of a two-layer wiring layer / a first insulating film of a three-layer wiring layer; 107, a second insulating film of a three-layer wiring layer; 3rd insulating film of the 4th wiring layer, 1st insulating film of the 4th wiring layer, 110th second insulating film of the 4th wiring layer, 110th 3rd insulating film of the 4th wiring layer / 1st of the 5th wiring layer Insulating film, 111 ... second insulating film of five-layer wiring layer, 112 ... third insulating film of five-layer wiring layer, first insulating film of six-layer wiring layer, 113 ... second insulating film of six-layer wiring layer, 114 ... Outermost surface passivation film (silicon nitride film), 115... Conductor wiring layer, 117... Opening, 118... DESCRIPTION OF SYMBOLS 1 ... Conductor layer, 501 ... Semiconductor board, 502 ... 1st insulating film of 1st wiring layer, 503 ... 2nd insulating film of 1st wiring layer, 504 ... 3rd insulating film of 1st wiring layer / 2 wiring layers 505, a second insulating film of a two-layer wiring layer, 506, a third insulating film of a two-layer wiring layer, 517, an opening, 518, an opening, 519, a wiring groove, 520, a barrier metal film, 521 … Conductor layer, 601 semiconductor substrate, 602 element isolation film area, 603 MOS transistor, 604 silicon oxide film, 605 BPSG (boron phosphorus silicate glass) film, 606 conductive plug, 607 single layer wiring 608... Second insulating film of one-layer wiring layer, 609... Third insulating film of one-layer wiring layer / first insulating film of two-layer wiring layer, 610. Insulating film, 611 ... third insulating film of two-layer wiring layer, 612 ... 3 A first insulating film of a wiring layer; 613... A second insulating film of a three-layer wiring layer; 614... A third insulating film of a three-layer wiring layer / 4 a first insulating film of a four-layer wiring layer; 2 insulating films, 616... Third insulating film of four-layer wiring layer, 617... First insulating film of five-layer wiring layer, 618... Second insulating film of five-layer wiring layer, 619. The first insulating film of the film / 6-layer wiring layer, the second insulating film of 620... 6-layer wiring layer, the third insulating film of 621... 6-layer wiring layer, 622... The outermost surface passivation film (silicon nitride film), 623. Conductor wiring layer, 701: semiconductor logic device, 702: chip coat film, 703: resin sealing portion (epoxy resin), 704: gold wire, 705: lead frame, 706: external terminal, 801: semiconductor substrate, 802: SiN Passivation film, 803: bonding pad, 804: insulation Film layer, 805: rearranged wiring, 806: insulating film layer, 807: under bump metal layer, 808: solder, 901: semiconductor substrate, 902: passivation film (silicon nitride film), 903: scribe line, 904: guard ring Layer, 905: Guard ring layer around the element device, 906: Semiconductor element.

Claims (12)

A semiconductor device in which a plurality of wiring layers are stacked on a substrate,
The wiring layer,
A first insulating layer, a second insulating layer, and a third insulating layer;
A conductor wiring formed through the first to third insulating layers,
The first insulating layer and the third insulating layer,
Silicon carbonitride film, including at least one of silicon carbide and silicon oxide,
A second insulating layer of a wiring layer located in a lower layer portion of the wiring layer includes silicon oxide;
A semiconductor device, wherein a second insulating layer of a wiring layer located in an upper layer portion of the wiring layer contains at least one of a fluorine-doped silicon oxide and a carbon-doped silicon oxide. A semiconductor device in which a plurality of wiring layers are stacked on a substrate,
The wiring layer,
A first insulating layer, a second insulating layer, and a third insulating layer;
A conductor wiring formed through the first to third insulating layers,
The first insulating layer and the third insulating layer,
Silicon carbonitride film, including at least one of silicon carbide and silicon oxide,
The relative dielectric constant of the second insulating layer of the wiring layer located in the lower layer of the wiring layer is smaller than the relative dielectric constant of the second insulating layer of the wiring layer located in the upper layer of the wiring layer. A semiconductor device characterized by the above-mentioned. 3. The semiconductor device according to claim 1, wherein a relative dielectric constant of a second insulating layer of the wiring layer located in the lower layer portion of the wiring layer is less than 3.0. 4. 4. The semiconductor device according to claim 1, wherein a second insulating layer of the wiring layer located in the lower part of the wiring layer has minute holes. 5. The semiconductor device according to claim 4, wherein a diameter of at least half of the minute holes is 0.05 nm or more and 4 nm or less. The semiconductor device according to claim 1, wherein a second insulating layer of the wiring layer located in the lower layer portion of the wiring layer contains SiO. The second insulating layer of the wiring layer located in the lower layer portion of the wiring layer is an insulating film obtained by heating a film containing a silsesquioxane hydrogen compound or a silsesquioxane methyl compound. The semiconductor device according to claim 1. 7. The semiconductor device according to claim 1, wherein the second insulating layer of the wiring layer located in the lower layer portion of the wiring layer is formed of a film containing an alkylsilane compound or an alkoxysilane compound. 8. . The component of the second insulating layer of the wiring layer located in the lower layer of the wiring layer and the component of the second insulating layer of the wiring layer located in the upper layer of the wiring layer are 9. The semiconductor device according to claim 1, wherein the semiconductor device is different. 10. The adjacent wiring layer, wherein a third insulating layer of a lower wiring layer also functions as a first insulating layer of a higher wiring layer. 3. The semiconductor device according to claim 1. Board and
A semiconductor element provided on the substrate,
A first insulating layer, a second insulating layer made of an insulating film material having a relative dielectric constant of less than 3.0, a wiring layer including a third insulating layer and a conductor wiring,
A semiconductor device, comprising: a guard ring layer disposed around a periphery of the semiconductor element using a material forming the wiring layer. The second insulating layer includes:
12. The semiconductor device according to claim 11, wherein the semiconductor device is a silicon oxide film having micropores therein having a diameter of 0.05 nm or more and 4 nm or less.

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