JP2006119364A - Level conversion circuit and flat panel display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a level conversion circuit for enhancing a conversion speed by suppressing a consumption current, and to provide a flat panel display device provided with the level conversion circuit. <P>SOLUTION: The level conversion circuit comprises a constant current source IS, a pair of differential transistors Q1 and Q2 connected to the constant current source IS and performing voltage-current conversion to an input signal to be sharply transited in a complement relationship in a power source voltage range of 0-5 V, active loads M1-M6 connected to the pair of the differential transistors Q1 and Q2, and output parts M7-M10 for generating output voltage to be transited in the power source voltage range of 0-20 V by corresponding to output states of the active loads M1-M10. In particular, the level conversion circuit is further provided with current path generating circuits R1, CM1 and DL for generating an auxiliary current path increasing differential current made to flow to the pair of the differential transistors Q1 and Q2 in only a prescribed period from transition start of the input signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a level conversion circuit that generates an output signal in a power supply voltage range different from an input signal in order to drive, for example, a motor, a display panel, and the like, and in particular, performs voltage-current conversion of the input signal to obtain this output signal. The present invention relates to a level conversion circuit and a flat display device provided with the level conversion circuit.

  For example, a field emission display (FED) panel includes a plurality of scanning lines extending in the horizontal (horizontal) direction, a plurality of signal lines extending in the vertical (vertical) direction intersecting these scanning lines, and the scanning lines and the signal lines. A plurality of display pixels arranged in the vicinity of the intersection position (see, for example, Patent Document 1). Each display pixel includes a surface conduction electron-emitting device and a red (R), green (G), or blue (B) phosphor that emits light by an electron beam emitted from the electron-emitting device. A Y driver and an X driver are arranged around the FED panel. The Y driver is connected to one end of the plurality of scanning lines, and sequentially drives the plurality of scanning lines by a scanning signal. The X driver is connected to one end of the plurality of signal lines, and drives the plurality of signal lines with a drive signal having a pulse width corresponding to the gradation level of the video signal while each scanning line is driven. Each display pixel emits light with a luminance corresponding to the pixel voltage between the corresponding signal line and the corresponding scanning line.

In the Y driver, for example, a shift register is provided for shifting the timing pulse and outputting a selection signal to the scanning line corresponding to the holding position of the timing pulse. This shift register is a logic circuit using CMOS transistors, and makes a selection signal transition in a first power supply voltage range of about 0 to 5V. On the other hand, the scanning signal needs to transition in the second power supply voltage range of about 0 to 20V. For this reason, the selection signal is converted into a scanning signal by a level conversion circuit as shown in FIG. This level conversion circuit temporarily converts the voltage of an input signal that transitions in the first power supply voltage range into a current by a differential pair using bipolar (or MOS) transistors Q1 and Q2, respectively, and LD (Lateral Double-diffused) MOS The output end voltage VO is controlled by mirroring these currents by an active load using the transistors M1 to M6 and further folding and synthesizing the current. The output unit using the LDMOS transistors M7 to M10 corresponds to the output end voltage VO. To generate an output signal that transitions in the second power supply voltage range.
JP 2002-221933 A

  FIG. 8 shows operation waveforms of the level conversion circuit shown in FIG. This is a signal supplied from the input signal φ1 and φbar input terminal IN to the differential pair via the inverter. When these signals φ1 and φbar transition, a differential current (for example, PD1 current) flows to one side of the differential pair, and the current mirror circuit serving as an active load changes with the change in the gate-source voltage (PD1VGS). The mirror current corresponding to is output. The output terminal voltage V0 is determined based on the output state of the active load. In order to increase the conversion speed of the level conversion circuit and shorten the response time Tpd shown in FIG. 8, it is necessary to increase the differential conversion gain Av and the folding current mirror ratio. Since the differential conversion gain Av has a relationship Av = gm × ro with respect to the mutual conductance gm of the differential pair and the output resistance ro of each stage, it is only necessary to increase either the mutual conductance gm or the output resistance ro. However, since the element that can increase the gain when the element size is constant is only the transconductance gm, it is necessary to increase the differential current regardless of whether the differential pair is a MOS or bipolar element. Increasing the differential current in the level conversion circuit results in increased current consumption in the steady state.

  For example, a level conversion circuit as shown in FIG. 9 can be considered as a measure for increasing the differential conversion gain Av without increasing the current consumption. In this level conversion circuit, a positive feedback circuit PFB is added to the level conversion circuit shown in FIG. In this case, since the positive feedback circuit PFB performs positive feedback in the dynamic differential conversion operation region, the differential conversion gain Av can be increased to some extent without increasing the differential current. However, this strategy is effective for the conversion of low slew rate input signals such as analog signals that transition relatively slowly, but for the conversion of high slew rate input signals such as digital signals that transition sharply. There is no meaning to this, and it is impossible to make use of the performance in this circuit system, and the operation in the positive feedback circuit PFB is accelerated only with a conversion gain that is twice the mirror ratio of the reference current. When the parasitic capacitance of the next stage drive element is large, there is a limit to speeding up. To purely increase the conversion speed of an input signal with a high slew rate, it is necessary to flow a differential current that charges and discharges the parasitic capacitance of the current mirror circuit in a very short time.

  In general, the Y driver of the FED panel is composed of an IC group including a very large number of level conversion circuits, as shown in FIG. Conventionally, since the conversion speed of the level conversion circuit and the current consumption of the entire IC are in a trade-off relationship, it is difficult to suppress the current consumption and increase the conversion speed.

  An object of the present invention is to provide a level conversion circuit capable of suppressing the current consumption and increasing the conversion speed, and a flat display device including the level conversion circuit.

  According to the present invention, a constant current source and a pair of differential transistors that are connected in common to the constant current source and perform voltage-current conversion on an input signal that changes sharply in a complementary relationship in the first power supply voltage range. An active load connected to the pair of differential transistors, an output unit that generates an output voltage that transitions in the second power supply voltage range corresponding to the output state of the active load, and a predetermined value from the start of transition of the input signal There is provided a level conversion circuit including a current path generation circuit for generating an auxiliary current path for increasing a differential current flowing in a pair of differential transistors only for a period.

  Further, according to the present invention, a plurality of scanning lines, a plurality of signal lines intersecting with the plurality of scanning lines, a plurality of scanning lines and a plurality of signal lines are arranged at the intersecting positions, and a pair of scanning lines and signals are respectively provided. A plurality of display pixels driven in accordance with a voltage between the lines, a scanning line driver for sequentially driving the plurality of scanning lines, and a video signal based on each of the plurality of scanning lines being driven by the scanning line driver. The scanning line driver is connected to the constant current source and the constant current source in common and is connected to the constant current source in a complementary relationship in the first power supply voltage range. A pair of differential transistors that perform voltage-current conversion, an active load connected to the pair of differential transistors, and an output voltage that transitions in a second power supply voltage range corresponding to the output state of the active load. Planar display having a level conversion circuit for each scanning line including an output section and a current path generation circuit for generating an auxiliary current path for increasing a differential current flowing in the pair of differential transistors for a predetermined period from the start of transition of the input signal An apparatus is provided.

  In these level conversion circuits and flat display devices, the current path generation circuit generates an auxiliary current path that increases the differential current flowing through the pair of differential transistors for a predetermined period from the start of the input signal transition. The differential current increasing from the start of signal transition can be completed in a shorter time, and the level conversion speed can be increased. In addition, since the increase in the differential current is limited to a predetermined time, the differential current flowing after the completion of the state transition is reduced by determining the predetermined time based on the time required for the state transition of the active load. , Overall current consumption can be suppressed.

  Hereinafter, a field emission display (FED) device according to an embodiment of the present invention will be described with reference to the drawings. This FED device is, for example, a flat display device having a 720P high-vision XGA resolution in which the number of color display pixels is horizontal: vertical = 1280: 720.

  FIG. 1 schematically shows a circuit configuration of the FED apparatus. The FED device includes an FED panel 1, an X driver 2, a Y driver 3, and a video processing circuit 4. The FED panel 1 has m (= 720) scanning lines Y (Y1 to Ym) extending in the horizontal (horizontal) direction, and n (= 1280 × 3) extending in the vertical (vertical) direction intersecting these scanning lines Y1 to Ym. ) Signal lines X (X1 to Xn), and m × n (= about 2.76 million) display pixels PX arranged in the vicinity of the intersection positions of the scanning lines Y1 to Ym and the signal lines X1 to Xn. Each color display pixel is constituted by three display pixels PX adjacent in the horizontal direction. In this color display pixel, the three display pixels PX emit red light (R), green (G), and blue (B) emitted by the surface conduction electron-emitting devices 11 and the electron beams emitted from the electron-emitting devices 11, respectively. Of the phosphor 12. Each scanning line Y is used as a scanning electrode connected to the electron emitting element 11 of the display pixel PX on the corresponding horizontal line, and each signal line X is used as a signal electrode connected to the electron emitting element 11 of the display pixel PX on the corresponding column. Used.

  The X driver 2, the Y driver 3, and the video processing circuit 4 are arranged around the FED panel 1 as a display driving circuit. The X driver 2 is a signal line driver connected to one end of the signal lines X1 to Xn, and the Y driver 3 is a scanning line driver connected to one end of the scanning lines Y1 to Ym. The video processing circuit 4 processes an RGB video signal supplied from an external signal source in a digital format. The Y driver 3 sequentially drives the scanning lines Y1 to Ym using the scanning signal, and the X driver 2 drives the signal lines X1 to Xn while each of the scanning lines Y1 to Ym is driven by the Y driver 3.

  The X driver 2 samples and holds a video signal for one horizontal line supplied from the video processing circuit 4 in synchronization with the horizontal synchronization signal HD, and one horizontal line output from the line memory 20 in parallel. A drive signal generation unit 21 that generates n PWM drive signals respectively corresponding to video signals for lines is included. The drive signal generator 21 generates n pulse width modulation circuits 22 each generating a pulse signal having a pulse width proportional to the gradation level of the video signal of the corresponding pixel, and pulses of the pulse signal from each corresponding pulse width modulation circuit 22. It includes n output buffers 23 that output the reference voltage Vref from the drive reference voltage terminal to the signal lines X1 to Xn as PWM drive signals for a period equal to the width. The pulse width modulation circuit 22 and the output buffer 23 constitute a drive signal output unit for one signal line X.

  When the display pixels PX of each horizontal line are driven via the signal lines X1 to Xn, light emission currents flow through the electron-emitting devices 11 of the display pixels PX except for those that display black among the display pixels PX, Further, all of these light emission currents flow to the Y driver 3 through one scanning line Y.

  The Y driver 3 shifts the vertical synchronizing signal VD every horizontal scanning period and outputs it from one of the m output terminals, and a selection pulse output as a scanning signal from these m output terminals. Each of them includes m output buffers 32 that output scanning signals to the scanning lines Y1 to Ym for each horizontal scanning period in response. In each electron-emitting device 11, discharge occurs when the sum of the voltage Vx (= Vref + ΔV) of the signal electrode and the voltage Vy of the scanning electrode exceeds the threshold, and the electron beam emitted thereby causes the phosphor 12 to be discharged. Excited.

  In the Y driver 3, m output buffers 32 are configured by the IC group described with reference to FIG. 10, and each output buffer 32 includes a level conversion circuit that generates a scanning signal voltage Vy for one scanning line Y. Including.

  FIG. 2 is for explaining the basic configuration of the level conversion circuit. The level conversion circuit includes CMOS inverters IV1 and IV2, a constant current source IS, bipolar transistors Q1 and Q2, LDMOS transistors M1 to M10, a MOS transistor CM1, a resistor R1, and a one-shot delay line DL. The inverters IV1 and IV2 operate with a power supply voltage between the power supply terminals GND1 (= 0V) and VDD1 (= 5V). The inverter IV1 inverts the selection signal from the output terminal of the shift register 31, and the inverter IV2 further inverts the selection signal inverted by the inverter IV1. Bipolar transistors Q1 and Q2 are connected to a constant current source IS as a differential pair for converting the voltages of the input signals φ1 and φ1 from the inverters IV1 and IV2 into currents, respectively. These differential pairs are connected to an active load composed of LDMOS transistors M1 to M6. Transistors M1 and M2 constitute a current mirror circuit for transistor Q1, and transistors M3 and M5 constitute a current mirror circuit for transistor Q2. The transistors M4 and M6 are current mirror circuits that fold back the mirror current obtained by the transistors M1 and M2. The transistor M5 is connected in series with the transistor M6 between the power supply terminals GND2 (= 15V) and VDD2 (= 20V), and outputs the output voltage VO from these connection points. The transistors M7 and M8 constitute an inverter that inverts the output voltage and switches the transistor M9. The transistor M9 is connected in series with the transistor M10 between the power supply terminals GND1 and VDD2, and the transistor M10 is switched by the output of the inverter IV1. The voltage Vy of the scanning signal is output from the connection point OUT of these transistors M9 and M10. The resistor R1 and the MOS transistor CM1 are connected in parallel with the constant current source IS between the differential pair and the power supply terminal GND1. The one-shot delay line DL is connected between the power supply terminals GND and VDD1, and operates to make the MOS transistor CM1 conductive for a predetermined time from the start of transition of the signals φ1 and φ1 bar output from the inverters IV1 and IV2.

  That is, this level conversion circuit has a structure in which a resistor R1, a MOS transistor CM1, and a one-shot delay line DL are added to the level conversion circuit shown in FIG. The resistor R1 and the MOS transistor CM1 form a current path in parallel with the constant current source IS when the transistor CM1 becomes conductive under the control of the one-shot delay line DL, and increases the differential current flowing through the differential pair. The conduction period of the transistor CM1 is limited to a predetermined period by the one-shot delay line DL, and this predetermined period almost coincides with the time required for the output voltage VO of the active load to be inverted with the transition of the signals φ1 and φ1 bar. Is preset.

  That is, the resistor R1 and the MOS transistor CM1 function as a current path generation circuit that generates an auxiliary current path that increases the differential current flowing through the pair of differential transistors for a predetermined period from the start of transition of the input signals φ1 and φ1 bar. The state transition of the active load is completed in a shorter time by the differential current increasing from the start of the transition of the input signals φ1 and φ1 bar, and the level conversion speed is increased. Further, the increase in the differential current is limited only to a predetermined time, and the differential current that flows after the completion of the state transition is reduced, thereby suppressing the overall current consumption.

  In FIG. 2, in order to explain the basic configuration of the level conversion circuit, the differential pair is composed of bipolar transistors Q1 and Q2. However, in practice, the structure shown in FIG.

  In FIG. 3, the differential pair is composed of MOS transistors DM1 and DM2, and is further connected to an active load via bipolar transistors Q3 and Q4 biased by a power supply terminal VDD1. In this case, the series circuit of the resistor R1 and the MOS transistor CM1 is connected between the connection point of the transistors DM2 and Q4 and the power supply terminal GND1, and the series circuit of the resistor R2 and the MOS transistor CM2 is connected to the connection point of the transistors DM1 and Q3 and the power supply terminal. Connected between GND1. The MOS transistors CM1 and CM2 are switched by control signals φ2 and φ2 bar from the one-shot delay line DL, respectively. These control signals φ2 and φ2 are for conducting the MOS transistors CM2 and CM1 for a predetermined time from the start of transition of the signals φ1 and φ1, respectively.

  FIG. 4 shows the operation of this level conversion circuit. When the input signals φ1 and φ1 are inverted, the current flowing through the differential pair is switched. The control signals φ2 and φ2 are inverted with the same phase as the input signals φ1 and φ1. Here, when the input signal φ1 becomes high level and the input signal φ1 bar becomes low level, the control signal φ2 becomes high level, and the control signal φ2 bar also becomes low level. At this time, the transistor DM1 and the transistor CM2 are turned on, and the transistor DM2 and the transistor CM1 are turned off. During this operation, the current flowing through the transistor CM2 is added to the differential current (PD1 current). Specifically, a current of (V1-Vbe) / R is added. Here, V1 is the voltage of the power supply terminal VDD1 with respect to the power supply terminal GND1, Vbe is the base-emitter voltage of the transistor Q3, and R is the resistance value of the resistor R2. This added current needs to be set to a value that causes the current mirror circuit as a load to operate at a sufficiently high speed. When the output voltage VO of the active load is sufficiently inverted, the one-shot delay line DL changes the control signal from the high level to the low level and turns off the transistor CM2. As a result, only the differential current flows to the active load as a steady-state holding current. This holding current only needs to be a sufficiently small value to maintain the output logic.

  Conversely, when the input signal φ is at a low level and the input signal φ1 bar is at a high level, the transistor DM2 and the transistor CM1 are turned on, and the transistor DM1 and the transistor CM2 are turned off. In this case, the current flowing through the transistor CM1 is added to the differential current in the same manner as described above.

  The above-described one-shot delay line DL can be configured by an overlap circuit combining, for example, an RS flip-flop that responds to transitions of the input signals φ1 and φ1 and a delay circuit having a delay time equal to a predetermined time. Control signals φ2 and φ2 bars can be obtained. The generation of the one-shot pulse that becomes the control signals φ2 and φ2 bars is basically a digital control operation, but the delay circuit is composed of analog parts such as a resistor and a capacitor for obtaining a delay time by a time constant as shown in FIG. It is also possible to obtain logic circuits in cascade as shown in FIG.

  In this embodiment, the current path generation circuits DL, R1, CM1, R2, and CM2 generate auxiliary current paths that increase the differential current flowing through the pair of differential transistors for a predetermined period from the start of transition of the input signals φ1 and φ1 bar. To do. The state transition of the active loads M1 to M6 is completed in a shorter time by the differential current that increases from the start of the transition of the input signals φ1 and φ1 bar, and the level conversion speed can be increased. In addition, since the increase in the differential current is limited to a predetermined time, the differential current flowing after the completion of the state transition is determined by determining the predetermined time based on the time required for the state transition of the active loads M1 to M6. This can reduce the overall current consumption.

  In addition, this invention is not limited to the above-mentioned embodiment, It can deform | transform variously in the range which does not deviate from the summary.

  In the above-described embodiment, the input signals φ1 and φ1 bars are digital signals that transition steeply in a complementary relationship. However, the signals may not only transition steeply in a complementary relationship but may also transition slowly. In some cases, a positive feedback circuit PFB as shown in FIG. 9 can be connected to the differential pair.

  Further, the above-described current path generation circuit can be applied even when the second power supply voltage range is set to a level difference smaller than the first power supply voltage range, and the current consumption is increased while the level conversion speed is increased. It works effectively to reduce

It is a figure showing roughly the circuit composition of the FED device concerning one embodiment of the present invention. FIG. 2 is a diagram for explaining a basic configuration of a level conversion circuit provided in the output buffer shown in FIG. 1. FIG. 3 is a diagram showing a configuration of a level conversion circuit that operates more stably than the basic configuration shown in FIG. 2. FIG. 4 is a waveform diagram showing an operation of the level conversion circuit shown in FIG. 3. FIG. 5 is a diagram showing a first configuration example of a one-shot delay line shown in FIG. 4. FIG. 5 is a diagram illustrating a second configuration example of the one-shot delay line illustrated in FIG. 4. It is a figure which shows the structure of the conventional level conversion circuit. FIG. 8 is a waveform diagram showing an operation of the level conversion circuit shown in FIG. 7. It is a figure which shows the structural example which added the positive feedback circuit to the level conversion circuit shown in FIG. It is a figure for demonstrating that the Y driver of a FED panel requires a very large number of level conversion circuits.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... FED panel, 2 ... X driver, 3 ... Y driver, 4 ... Image processing circuit, 11 ... Surface conduction type electron-emitting device, 12 ... Phosphor, Y ... Scan line, PX ... Display pixel, IS ... Constant current source , IV1, IV2 ... CMOS inverter, DL ... one-shot delay line, Q1, Q2 ... bipolar transistor, Q3, Q4 ... bipolar transistor, M1-M10 ... LDMOS transistor, CM1, CM2 ... MOS transistor, R1, R2 ... resistor.

Claims (17)

A constant current source, a pair of differential transistors that are connected in common to the constant current source and perform voltage-current conversion on an input signal that changes sharply in a complementary relationship in the first power supply voltage range, and a pair of differential transistors An active load connected to the transistor, an output unit that generates an output voltage that transitions in the second power supply voltage range corresponding to the output state of the active load, and a pair of differentials for a predetermined period from the start of transition of the input signal A level conversion circuit comprising: a current path generation circuit for generating an auxiliary current path for increasing a differential current flowing in the transistor. 2. The level conversion circuit according to claim 1, wherein the second power supply voltage range has a level difference larger than that of the first power supply voltage range. The level conversion circuit according to claim 2, wherein the differential transistor includes a pair of bipolar transistors. 4. The level conversion circuit according to claim 3, wherein the auxiliary current path is a series circuit of a switch element and a resistor connected in parallel to the constant current source. 5. The level conversion according to claim 4, wherein the current path generation circuit includes a one-shot delay line that generates a one-shot pulse for conducting the switch element for the predetermined period in response to transition of the input signal. circuit. 3. The level conversion circuit according to claim 2, wherein the differential transistor includes a pair of MOS transistors. The auxiliary current path is a series circuit of a first switch element and a first resistor connected in parallel to the constant current source and one MOS transistor, and a second circuit connected in parallel to the constant current source and the other MOS transistor. The level conversion circuit according to claim 6, wherein the level conversion circuit is a series circuit of a switch element and a second resistor. The current path generation circuit includes a one-shot delay line that generates a one-shot pulse for conducting one of the first and second switch elements for the predetermined period in response to transition of the input signal. Item 8. The level conversion circuit according to Item 7. A plurality of scanning lines, a plurality of signal lines intersecting with the plurality of scanning lines, and arranged at positions where the plurality of scanning lines and the plurality of signal lines intersect with each other. A plurality of display pixels that are driven correspondingly, a scanning line driver that sequentially drives the plurality of scanning lines, and the scanning line driver that drives each of the plurality of scanning lines based on the video signal. A signal line driver for driving a plurality of signal lines, and the scanning line driver is connected in common to the constant current source and the constant current source, and for an input signal that changes sharply in a complementary relationship in the first power supply voltage range. A pair of differential transistors that perform voltage-current conversion, an active load connected to the pair of differential transistors, and an output power that transitions in a second power supply voltage range corresponding to the output state of the active load. A level conversion circuit including a current path generation circuit for generating an auxiliary current path for increasing a differential current flowing in a pair of differential transistors for a predetermined period from the start of transition of an input signal for each scanning line A flat display device comprising: The flat display device according to claim 9, wherein the display pixel includes a surface conduction electron-emitting device that emits an electron beam. The flat panel display according to claim 9, wherein the second power supply voltage range has a level difference larger than the first power supply voltage range. The flat display device according to claim 11, wherein the differential transistor includes a pair of bipolar transistors. The flat display device according to claim 12, wherein the auxiliary current path is a series circuit of a switch element and a resistor connected in parallel to the constant current source. 14. The planar display according to claim 13, wherein the current path generation circuit includes a one-shot delay line that generates a one-shot pulse for conducting the switch element for the predetermined period in response to transition of the input signal. apparatus. The flat display device according to claim 11, wherein the differential transistor includes a pair of MOS transistors. The auxiliary current path is a series circuit of a first switch element and a first resistor connected in parallel to the constant current source and one MOS transistor, and a second circuit connected in parallel to the constant current source and the other MOS transistor. The flat display device according to claim 15, wherein the flat display device is a series circuit of a switch element and a second resistor. The current path generation circuit includes a one-shot delay line that generates a one-shot pulse for conducting one of the first and second switch elements for the predetermined period in response to transition of the input signal. Item 17. A flat display device according to Item 16.

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