JP2006116082A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine by which random number values for lottery can be generated in irregular timing and fraudulent action can be prevented. <P>SOLUTION: A random number generating circuit is equipped with 8-bit counter ICs 301, 302 counting in a substantial constant cycle and capable of outputting count values, not inverted buffer ICs 303 to 306 capable of generating a plurality of random values from the count values, a 4 bit counter IC 307 selecting random number values for lottery from a plurality of random number value based on the M1 signals output from a CPU 200 in irregular intervals and capable of obtaining the random number values for the lottery, an XOR gate 309, inverter ICs 308, 310. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a gaming machine represented by a slot machine, and more particularly to prevention of fraud.

  In recent years, a gaming table including a random number generator capable of generating a plurality of random values and a control unit that performs lottery using a random number for lottery acquired from the random number generator has been widely known. In such a game machine, for example, internal lottery determination of a winning combination is performed using a random number for lottery acquired from a random number generator when a start lever is operated.

  However, the random number generator generally uses a counter IC that updates values by periodically counting values in a predetermined range (for example, 0 to 65537). For this reason, a low-frequency treatment device or the like has been modified to synchronize the cycle in which electrical stimulation is output to the electrical pad affixed to the arm and the random number generation cycle of the slot machine, and use the movement of the arm muscles by electrical stimulation. By operating the start lever, illegal activities such as consecutive jackpots have occurred.

  As one means for solving such a problem, for example, Patent Document 1 discloses a technique in which a counter circuit is multi-staged and divided into upper multiple bits and lower multiple bits to reverse the bit arrangement.

JP 2000-24286 A

  However, in such a known game machine, as shown in FIG. 14, although the winning times of the random numbers for lottery can be distributed within the synchronization of the random numbers, the random numbers for lottery are changed at predetermined intervals. Therefore, the player can grasp the winning timing of the jackpot and the like, and still has the possibility of cheating.

  The present invention has been made to solve such a problem, and it is possible to generate random numbers for lottery at irregular timings and to prevent illegal acts in advance. The purpose is to provide.

  The present invention is a game machine comprising: a random number generator capable of generating a plurality of random values; and a control unit that performs lottery using lottery random values acquired from the random number generator, wherein the random number The generating unit counts at a substantially constant period and outputs a count value, a random value generation unit capable of generating the plurality of random number values from the count value, and an unequal from the control unit The random number value selecting means that selects the lottery random number value from the plurality of random number values based on a control signal output at intervals and makes it possible to acquire the lottery random value is provided. It is a thing.

  According to the present invention, it is possible to generate random numbers for lottery at irregular timings while using a counting unit that counts at a substantially constant cycle, thereby preventing fraud.

  The counting means includes one or a plurality of counters having a plurality of outputs capable of outputting the count value as binary data, and a plurality of the random value generation means are provided for each counter, and A buffer having a plurality of inputs capable of inputting the binary data; the input of the buffer and the output of the counter are connected to be different between the plurality of buffers; If a specific buffer is selected from the buffers, and the random number for lottery value can be acquired, the random number value for lottery to be generated can be distributed while preventing the illegal act. The effect can be further enhanced.

  In this case, the counting means includes a plurality of the counters, and if the outputs of at least two counters are connected to the input of the buffer, the lottery random numbers to be generated can be further dispersed.

  The counting means includes a counter having a plurality of outputs capable of outputting the count value as binary data, and the random value generating means includes a plurality of buffers provided for each output of the counter. The random value selection means is configured to select a specific buffer from the plurality of buffers and generate the lottery random value while having a simple circuit configuration. The random numbers for lottery to be distributed can be distributed, and the effect of preventing fraud can be further enhanced.

  Furthermore, if the buffer is a three-state buffer that can be switched between a conductive state and a high-impedance state, the counter and the plurality of buffers can be connected by a common signal line, and the circuit configuration can be further simplified. It becomes possible to.

  In this case, the buffer is switched between the conductive state and the high impedance state by a select signal output from the random value selection means, and the random number value for lottery is controlled when the conductive state is set. If it is possible to output to the data bus connected to the section, it is possible to quickly select and acquire the random number for lottery.

  In addition, the control unit includes a CPU, and if the control signal is an M1 signal output from the CPU, it is not necessary to newly generate a special control signal, and a lottery random value generation timing is generated. Can be made more irregular.

  Furthermore, the random number generation unit can hold the count value based on a latch signal input from the control unit, and can acquire the lottery random number value based on a chip select signal input from the control unit. If it is comprised, it becomes possible to adjust easily the timing which hold | maintains a count value, and the timing which acquires the random number value for lottery. Therefore, for example, if the random number value for lottery is acquired after a predetermined time after the count value is held, the random number value for lottery will not be in an electrically unstable state, It becomes possible to acquire a numerical value reliably.

  According to the gaming machine according to the present invention, it is possible to generate random numbers for lottery at irregular timings, and it has an excellent effect that fraud can be prevented in advance.

  Hereinafter, slot machines according to Embodiments 1 to 3 of the present invention will be described in detail with reference to the drawings.

  As shown in FIG. 1, in the center of the slot machine 100 according to the first embodiment of the present invention, there are three reels (left reel 110, middle reel 111, right reel) having a plurality of types of symbols arranged on the outer peripheral surface. The reel 112 is housed and can be rotated inside the slot machine 100. In the first embodiment, each symbol is printed on a belt-like member at an appropriate interval (for example, 21 symbols), and this belt-like member is attached to a predetermined circular frame member to constitute each reel 110 to 112. When viewed from the player, the symbols on the reels 110 to 112 are generally displayed three in the vertical direction from the symbol display window 113 so that a total of nine symbols can be seen. Then, by rotating the reels 110 to 112, the combination of symbols that can be seen by the player varies. In the first embodiment, three reels are provided in the center of the slot machine 100. However, the number of reels and the installation position of the reels are not limited to this.

  In addition, a backlight (not shown) for illuminating each symbol displayed on the symbol display window 113 is disposed on the back of each reel 110 to 112. It is desirable that the backlight is shielded for each symbol so that the individual symbols can be illuminated evenly. In the slot machine 100, an optical sensor (not shown) including a light projecting unit and a light receiving unit is provided in the vicinity of each of the reels 110 to 112. The light projecting unit and the light receiving unit of the optical sensor are provided. A light-shielding piece of a certain length provided on the reel passes between them. Based on the detection result of this sensor, the position of the symbol on the reel in the rotation direction is determined, and the reels 110 to 112 are stopped so that the target symbol is displayed on the winning line 114.

  The winning line display lamp 120 is a lamp that indicates an effective winning line. An effective pay line is determined in advance by the number of game media (in the first embodiment, medals are assumed) inserted into the slot machine 100. Of the five winning lines 114, for example, when one medal is inserted, the middle horizontal winning line is valid, and when two medals are inserted, the upper horizontal winning line and the lower horizontal winning line are added. When three medals are inserted and three medals are inserted, the five added with the right-down winning line and the upper-right winning line become effective as the winning line. Note that the number of winning lines 114 is not limited to five.

  The start lamp 121 is a lamp that informs the player that the reels 110 to 112 are in a state of being able to rotate. The re-game lamp 122 is a lamp for notifying the player that the current game can be re-played (the medal need not be inserted) when winning a re-game which is one of the winning combinations in the previous game. . The notification lamp 123 is a lamp that informs the player that a specific winning combination (specifically, a bonus such as a big bonus or a regular bonus) is won internally in an internal lottery described later. The medal insertion lamp 124 is a lamp that notifies that a medal can be inserted. The reel panel lamp 128 is an effect lamp. The medal insertion buttons 130 and 131 are buttons for inserting a predetermined number of medals stored electronically in the slot machine 100.

  In the first embodiment, every time the medal insertion button 131 is pressed, a maximum of three are inserted one by one, and when the medal insertion button 130 is pressed, three are inserted. The medal slot 134 is an slot for a player to insert a medal when starting a game. That is, the medal can be inserted electronically by the medal insertion button 130 or 131, or an actual medal can be inserted from the medal insertion slot 134. The payout number display 125 is a display for displaying the number of medals to be paid out to the player as a result of winning a winning combination.

  The game number display 126 is a display for displaying the number of games during the big bonus game (in the BB game), the number of winnings of a predetermined winning combination, and the like. The stored number display 127 is a display for displaying the number of medals electronically stored in the slot machine 100. The start operation unit 135 is a unit for starting the rotation of the reels 110 to 112. When a desired number of medals is inserted into the medal insertion slot 134 and the start operation unit 135 is operated, an internal lottery of a winning combination and the rotation of the reels 110 to 112 are started.

  The stop button unit 136 is provided with stop buttons 137 to 139. The stop buttons 137 to 139 are button-type switches for individually stopping the reels 110 to 112 that have started rotating by the operation of the start operation unit 135. Note that a light emitter may be provided inside each stop button 137 to 139, and when the stop button 137 to 139 can be operated, the light emitter may be turned on to notify the player.

  The storage / settlement button 132 settles a medal electronically stored in the slot machine 100 and discharges it to the tray 210 from the medal payout outlet 155, and the four or more sheets inserted into the medal slot 134. This is a button for switching between a storage function for electronically storing up to 50 medals and medals obtained by winning.

  The door key 140 is a hole into which a key for unlocking the front door 102 of the slot machine 100 is inserted. The medal payout exit 155 is a payout exit for paying out medals. The medal tray 210 is a container for collecting medals paid out from the medal payout opening 155.

  The medal tray 210 employs a tray that can emit light in the first embodiment, and may be hereinafter referred to as a tray lamp.

  The sound hole 160 is a hole for outputting the sound of a speaker provided inside the slot machine 100 to the outside. The upper lamp 150, the side lamp 151, the center lamp 152, the waist lamp 153, and the lower lamp 154 are decorative lamps for exciting games. The rendering device 170 includes a liquid crystal display device that displays various types of information.

<Main control unit>
Next, the configuration of the control unit of the slot machine 100 will be described in detail with reference to FIG.

  The slot machine 100 includes a main control unit that controls the central part of the game, and a sub-control unit (not shown) that controls various devices in accordance with signals transmitted from the main control unit. The sub-control unit performs, for example, processing related to effects such as control of the effect device 170. However, in the first embodiment, since it is not directly related to prevention of fraud against random lottery, the description is omitted and main control is performed. The part will be described.

  The main control unit includes a CPU 200 that is an arithmetic processing unit for controlling the whole, a data bus and an address bus for the CPU 200 to transmit and receive signals to and from each IC and each circuit, and has the following configuration: . The clock circuit 202 divides the clock signal oscillated from the crystal oscillator 201 and supplies it to the CPU 200. For example, when the frequency of the crystal oscillator 201 is 12 MHz, the divided clock signal is 6 MHz. The CPU 200 operates by receiving the clock signal divided by the clock circuit 202 as a system clock. The CPU 200 is connected to a timer circuit 203 for setting a monitoring cycle for constantly monitoring the states of sensors and switches, which will be described later, and a transmission cycle of motor drive pulses, via a bus.

  The timer circuit 203 determines a fixed interrupt time based on the received frequency division data, and transmits an interrupt request to the CPU 200 for each interrupt time. In response to this interrupt request, the CPU 200 executes monitoring of each sensor and transmission of drive pulses. For example, when the system clock of the CPU 200 is set to 6 MHz, the frequency division value of the timer circuit 203 is set to 1/256, and the data for frequency division of the ROM 204 is set to 44, the reference time for this interrupt is 256 × 44 ÷ 6 MHz = 1. It becomes 877 ms and becomes a fixed cycle.

  Also connected to the CPU 200 are a program for controlling each IC, a lottery data used in the internal lottery of the winning combination, a ROM 204 for storing reel stop positions, and a RAM 205 for storing temporary data. Has been. Other storage means may be used for these ROM 204 and RAM 205.

  The CPU 200 is connected to an input interface 206 for receiving an external signal. The medal acceptance sensor 207, the stop button sensor 208, and the start operation detection are detected via the input interface 206 every interrupt time of the interrupt cycle described above. The state of the sensor 209 or the like is detected, and the detection result of each sensor is monitored.

  Two medal acceptance sensors 207 are installed in the passage inside the medal insertion slot 134 and detect whether or not a medal has passed. The start operation detection sensor 209 is installed in the start operation unit 135 and detects a start operation by the player. The stop button sensor 208 is installed in each of the stop buttons 137 to 139 and detects the operation of the stop button by the player.

  An index sensor 217 is connected to the input interface 219. The index sensor 217 is installed at a predetermined position on the mounting base of each of the reels 110 to 112, and becomes H level each time the light shielding piece provided on the reel passes through the index sensor 217. When detecting this signal, the CPU 200 determines that the reel has made one rotation and resets the rotational position information of the reel to zero.

  The output interface 218 includes a reel motor driving unit 213 for driving the reel and a hopper motor for driving a hopper (a device for paying out medals accumulated in the bucket from the medal payout outlet 155, not shown). A driving unit 214, a game lamp 215 (specifically, a winning line display lamp 120, a start lamp 121, a re-playing lamp 122, an announcement lamp 123, a medal insertion lamp 124, etc.), and a 7-segment display 216 (payout number display) Device 125, game number display 126, stored number display 127, etc.). An output interface 210 for transmitting a command to the sub control unit is connected to the data bus of the CPU 200.

  In addition, a random number generation circuit 220 is connected to the CPU 200 via a data bus. The random number generation circuit 220 is for generating a plurality of random number values, and the random number for lottery acquired from the random number generation circuit 220 is used for random lottery such as an internal lottery of a winning combination (details will be described later).

<Random number generator>
Next, the random number generation circuit 220 according to the first embodiment will be described in detail with reference to FIG. FIG. 3 is a diagram showing a circuit configuration of the random number generation circuit 220.

  The random number generation circuit 220 according to the first embodiment includes two 8-bit counter ICs 301 and 302, four non-inverting buffers IC 303 to 306, and one 4-bit counter IC 307.

  The 8-bit counter ICs 301 and 302 are 8-bit binary counters, and for example, HD74HC590 can be applied. The 8-bit counter ICs 301 and 302 have CLK input, / CCLKEN input, / CCLR input, RCLK input, and / G input as inputs, and QA to QH outputs as outputs, Has RCO output. In the first embodiment, the / RCO output of the 8-bit counter IC 302 is not connected.

The CLK input is a clock signal input serving as a reference for counting up. In the first embodiment,
A clock signal with a substantially constant period oscillated from the crystal oscillator 211 is input.

  The / CCLKEN input is an enable signal input for selecting enable / disable of count-up, and the 8-bit counter ICs 301 and 302 are input to the CLK input when the input signal to the / CCLKEN input is at a low level. Counting up from 0 to 65535 is performed in synchronization with the rising edge of the clock signal. In the first embodiment, the / CCLKEN input of the 8-bit counter IC 301 is connected to the ground (0 V), and the 8-bit counter IC 301 always counts up in synchronization with the rising edge of the clock signal. .

  On the other hand, the / CCLKEN input of the 8-bit counter IC302 is connected to the / RCO output of the 8-bit counter IC301, and the output signal from the / RCO output of the 8-bit counter IC301 becomes low level. 1 (when the count value of the 8-bit counter IC 301 reaches the upper limit). That is, two counter ICs 301 and 302 constitute a 16-bit binary counter. The counter IC 301 is a lower 8-bit binary counter, and the counter IC 302 is an upper 8-bit binary counter. In the first embodiment, the QA output of the counter IC 301 is LSB (Least Significant Bit), and the QH output of the counter IC 302 is MSB (Most Significant Bit).

  The / CCLR input is a counter reset input, and the 8-bit counter ICs 301 and 302 can be reset by inputting a low level signal. In the first embodiment, the / CCLR input is connected to the power supply (Vcc), the high level signal is input to the / CCLR input, and the 8-bit counter ICs 301 and 302 have their count values reset after the power is turned on. It always comes to count up without having to.

  The / G input is an enable signal input for the three-state output circuit. When a low level signal is input to the / G input, the output to the QA to QH outputs is enabled, and the rise of the signal input to the RCLK input In synchronization with the edge, binary data (binary data) of the count value is output to the QA to QH outputs. In the first embodiment, the / G input of the 8-bit counter IC 301 is connected to the chip select output CS0 of the CPU 200, and the / G input of the 8-bit counter IC 302 is connected to the chip select output CS1 of the CPU 200. By outputting a chip select signal via the circuit 212, selection of the 8-bit counters IC301 and IC302 (selection of lower 8 bits and upper 8 bits) is possible. The RCK inputs of the 8-bit counter ICs 301 and 302 are connected to the latch clock output RCK of the CPU 200. When a latch signal is input from the CPU 200 via the address decode circuit 212, the count value at that time is held. It is output to the QA to QH outputs of the 8-bit counter ICs 301 and 302.

  The QA to QH outputs of the 8-bit counter IC 301 are connected in this order to the A1 to A8 inputs of the non-inverted buffer IC 303, and are also connected to the A1 to A8 inputs of the non-inverted buffer IC 304 by changing the bit arrangement. ing. As described above, in the first embodiment, the A1 to A8 inputs of the non-inverting buffer ICs 303 and 304 and the QA to QH outputs of the 8-bit counter IC 301 are connected differently between the two non-inverting buffer ICs 303 and 304. . Note that the replacement of the bit arrangement is not limited to the example of the circuit configuration shown in FIG.

  Similarly, the QA to QH outputs of the 8-bit counter IC 302 are connected in this order to the A1 to A8 inputs of the non-inverting buffer IC 305, and the bit arrangement is changed to the A1 to A8 inputs of the non-inverting buffer IC 306. Is also connected. That is, the A1 to A8 inputs of the non-inverting buffer ICs 305 and 306 and the QA to QH outputs of the 8-bit counter IC 302 are connected differently between the two non-inverting buffer ICs 305 and 306.

  The four non-inverting buffers IC 303 to 306 are three-state non-inverting buffers, and for example, HD74HC541 can be applied. The non-inverting buffer ICs 303 to 306 are configured to have A1 to A8 inputs, Y1 to Y8 outputs, and / G1 input and / G2 input which are three-state control inputs.

  The non-inverting buffer ICs 303 to 306 are in a high impedance (Hi-Z) state when a high level signal is input to either the / G1 input or the / G2 input, while the / G1 input and the / G2 input When a low level signal is input to both, the conductive state is established, and signals input to the A1 to A8 inputs can be output from the Y1 to Y8 outputs. In the first embodiment, the / G2 input of the non-inverting buffer ICs 303 and 304 is supplied to the chip select output CS0 of the CPU 200, and the / G2 input of the non-inverting buffer ICs 305 and 306 is supplied to the chip select output CS1 of the CPU 200, respectively. The CPU 200 can select the non-inverting buffer ICs 303 and 304 and the non-inverting buffer ICs 305 and 306 by outputting a chip select signal. The / G1 signal of the non-inverting buffer ICs 303 to 306 is connected to an output destination of a 4-bit counter IC 307 described later.

  The 4-bit counter IC 307 is a 4-bit binary counter, and for example, HD74HC393 can be applied. The 4-bit counter IC 307 has a / CK input and a CLR input as inputs, and QA to QD outputs as outputs. In the first embodiment, the QC output and QD output of the counter IC 307 are not connected.

The / CK input is a clock signal input serving as a reference for counting up. In the first embodiment,
The / M1 signal output from the CPU 200 is input. From the QA to QD outputs of the 4-bit counter IC 307, the binary value of the count value is synchronized with the rising edge of the / M1 signal input to the / CK input. Data is output.

  Here, the / M1 signal that triggers the count-up of the 4-bit counter IC 307 will be described with reference to FIG. The / M1 signal output from the CPU 200 is a signal for fetching (reading) the operation code stored in the ROM 204 into the instruction analysis register (instruction register) inside the CPU 200, and is substantially the same as the rising edge of the clock T1 in the fetch cycle. The signal falls at the same time and rises almost simultaneously with the rising edge of the clock T3. The / M1 signal is always output at least once when each instruction is executed by the CPU 200. For example, when the CPU 200 executes an instruction of only the first operation code (for example, NOP (No Operation) instruction), the / M1 signal is output only once at the time of execution of the instruction, but it has up to the second operation code. When an instruction (for example, an ADD (summation) instruction) is executed, the / M1 signal is output twice when the instruction is executed. In addition, the number of machine cycles constituting one instruction differs depending on the instruction. For this reason, the / M1 signal is always output when the instruction is executed by the CPU 200, but the output interval is not constant, and the output interval is not constant according to the instruction executed by the CPU 200 (depending on the state of the slot machine 100). It is a signal that changes regularly.

  Returning to FIG. 3, the CLR input is a counter reset input, and the 4-bit counter IC 307 can be reset by inputting a high-level signal. In the first embodiment, the CLR input is connected to the ground (0 V), and a low-level signal is input to the CLR input. The 4-bit counter IC 307 is always reset without being reset after the power is turned on. A count-up is performed.

  The QA output is connected to the / G1 input of the non-inverting buffer IC 303 and also connected to the / G1 input of the non-inverting buffer IC 304 via the inverter IC 308. The output signal from the QA output is the non-inverting buffer IC 303. And IC 304 function as a select signal for selecting one of them.

  The QA output and QB output are connected to the input of an XOR (exclusive OR) gate 309. The output of the XOR gate 309 is connected to the / G1 input of the non-inverting buffer IC 305 and is connected to the / G1 input of the non-inverting buffer IC 306 via the inverter IC 310. The output signal from the XOR gate 309 is , And functions as a select signal for selecting one of the non-inverting buffers IC305 and IC306.

  FIG. 5 shows the state of the QA output and QB output of the 4-bit counter IC 307 and the non-inverting buffers IC 303 to 306 selected based on the QA output and the QB output (a low level signal is input to the / G1 input). It is a truth table showing combinations.

  In the random number generation circuit 220 according to the first embodiment, as shown in FIG. 5, one of the non-inverted buffer ICs 303 and 304 and the non-inverted buffer IC 305 are combined according to the combination of the QA output and the QB output based on the / M1 signal. And 306 are selected, and the lower 8 bits and the upper 8 bits of the random value are determined. The CPU 200 acquires the lower 8 bits and the upper 8 bits of the random number value by controlling the chip select signal. As a result, the patterns of random number values acquired by the CPU 200 are four patterns as shown in FIGS. 6A to 6D, and these four patterns are input to the / CK input of the 4-bit counter IC 307. Are selected at irregular intervals based on the M1 / M1 signal.

<Game execution processing>
Next, the game execution process of the main control unit will be described with reference to FIG. FIG. 7 is a flowchart showing the flow of the game execution process of the main control unit.

  The basic control of the game is performed mainly by the CPU 200, and the game process shown in FIG. Hereinafter, this game process will be described.

  After the power is turned on and various initialization processes are performed, in step S101, a process relating to medal reception is performed. Here, it is checked whether or not medals have been inserted, and the winning line display lamp 120 is turned on according to the number of medals inserted. It is not necessary to insert a medal when winning the re-game in the previous game.

  In step S102, processing related to accepting a game start operation is performed. Here, it is checked whether or not the start operation unit 135 has been operated. If it is determined that the start operation unit 135 has been operated, the number of inserted medals is determined, and an effective pay line 114 is determined. In response to the operation of the start operation unit 135, a latch signal is generated from the latch clock output RCK of the CPU 200, and the random number generation circuit 220 keeps the count value constantly updated. As a result, a plurality of (four in the first embodiment) random number values generated based on the count value are held. In the first embodiment, the random number value is held when the start operation unit 135 is operated. However, the present invention is not limited to this, and for example, each of the stop buttons 137 to 139 is pressed. The random number value may be held in response to this.

  In step S103, a symbol lottery process is performed based on the random number for lottery acquired from the random number generation circuit 220 (details will be described later).

  In step S104, rotation of all reels 110 to 112 is started. At this time, one reel stop control table is selected by referring to the reel stop control table selection table stored in the ROM 204 on the basis of the symbol drawing lottery result in step S103.

  In step S105, the stop buttons 137 to 139 can be received. When any one of the stop buttons is pressed, one of the reels 110 to 112 corresponding to the pressed stop button is selected as the reel stop selected in step S104. Stop based on the control table.

  In step S106, a winning determination is performed. Here, it is determined that the winning combination is won when the symbol combination corresponding to the winning combination that has been won internally or the winning combination with the flag carried over is displayed on the activated winning line 114.

  In step S107, if any winning combination with payout is won, the number of medals corresponding to the winning combination is paid out.

  As described above, one game is completed, and the game progresses by repeating this thereafter.

<Design lottery processing>
Next, the symbol lottery process (step S103) in the above-described game execution process will be described with reference to FIG. FIG. 8 is a flowchart showing the flow of the symbol lottery process in the game execution process.

  In step S201, the current gaming state (for example, a general game or a bonus game) is acquired.

  In step S202, the top address of the symbol lottery data index used for symbol lottery is set.

  In step S203, a lottery data index is set according to the gaming state. Then, the lottery number and the lottery data offset for each game state are set with reference to the lottery data index, and then the start address of the lottery data used for the lottery is set from these set values and the lottery data index.

  In step S204, a chip select signal is generated from the chip select outputs CS0 and CS1 of the CPU 200, and a lottery random value is acquired from the plurality of random values held in step S102 of the game execution process. For example, when the random number value changes in four patterns as shown in FIG. 6, at the timing indicated by the arrow 1 in FIG. 6, when QA output = QB output = Low, 1022 becomes QA output = When Hi and QB output = Low, 24767 is used as the random number value for lottery. 24767 when QA output = Low and QB output = Hi, and 959 when QA output = QB output = HiLow. Obtained by. Similarly, at the timing indicated by the arrow 2 in FIG. 6, from the four numerical values 26623, 63743, 63743, 26623, and at the timing indicated by the arrow 3 in FIG. 6, 65533, 65531, 65533, 65531. From these four numerical values, one random number for lottery is obtained according to the state of the QA output and the QB output based on the / M1 signal (see FIG. 6E).

  In step S205, the random number lottery process for the winning combination is performed using the random number for lottery acquired in step S204 and the winning combination lottery table stored in the ROM 204. Further, an effect lottery for selecting an effect mode of the slot machine 100 is also performed, and the selected effect is executed. Further, on the basis of the random number for lottery acquired in step S204, a symbol drawing lottery when selecting the reel stop control table and a mode transition lottery when determining the number of rights and the like are performed.

  In step S206, a symbol lottery result code is set according to the result of random lottery, and the process is terminated.

  According to the slot machine 100 according to the first embodiment, the random number generation circuit 220 (random number generation unit) counts at a substantially constant period and outputs 8-bit counter ICs 301 and 302 (counting means) that can output the count value. ), Non-inverted buffer ICs 303 to 306 (random number generation means) capable of generating a plurality of random values from the count value, and the / M1 signal (control signal) output at unequal intervals from the CPU 200 (control unit). And a 4-bit counter IC 307, an XOR gate 309, and inverter ICs 308 and 310 (random number selection means) that can select a random number for lottery from a plurality of random numbers and obtain the random number for lottery. It is possible to generate random numbers for lottery at irregular timings and to prevent fraud.

  In particular, the counting means of the slot machine 100 according to the first embodiment includes an 8-bit counter IC 301 (302) having a plurality of QA to QH outputs capable of outputting a count value as binary data, and a random value generation means Includes a plurality of non-inverted buffer ICs 303 and 304 (305 and 306) each provided with a plurality of A1 to A7 inputs, each of which is provided for each 8-bit counter IC 301 (302) and capable of inputting binary data. The A1 to A7 inputs of the inverting buffer ICs 303 and 304 (305 and 306) and the QA to QH outputs of the 8-bit counter IC 301 (302) are connected differently between the non-inverting buffer ICs 303 and 304 (305 and 306), Random value selection means is specified from a plurality of non-inverting buffer ICs 303 and 304 (305 and 306) Since the random number value for lottery can be acquired by selecting the buffer, the random number value for lottery to be generated can be distributed even with a simple circuit configuration, and the effect of preventing fraud is further enhanced. Can do.

  Further, since the non-inverting buffer ICs 303 to 306 are three-state buffers that can be switched between a conductive state and a high impedance state, an 8-bit counter IC 301 (302) and a plurality of non-inverting buffer ICs 303 and 304 (305 and 306). Can be connected by a common signal line, and the circuit configuration can be further simplified.

  Further, the non-inverting buffer ICs 303 to 306 are switched between the conductive state and the high impedance state by the select signal output from the random value selection means, and when the conductive state is set, the random number value for lottery is sent to the control unit. Since the data can be output to the connected data bus, the random number for lottery can be quickly acquired by the control unit.

  Furthermore, since the control unit includes the CPU 200 and the control signal is the / M1 signal output from the CPU 200, it is not necessary to newly generate a special control signal, and the generation timing of the random number for lottery is set. Can be more irregular. In the first embodiment, the / M1 signal is used as a control signal output at unequal intervals from the control unit. However, the present invention is not limited to this, and for example, output from the CPU 200 as a control signal. Memory request signal, IO request signal, read signal, write signal, refresh signal, wait signal, bus request signal, bus acknowledge signal, at least one address bus signal, at least one data bus signal, etc. It may be used.

  Further, the random number generation circuit 220 is configured to hold a count value based on a latch signal input from the CPU 200 and to acquire a lottery random number value based on a chip select signal input from the CPU 200. The timing for holding the count value and the timing for acquiring the random number for lottery can be easily adjusted. As described above, in the first embodiment, the lottery random value is acquired in the symbol lottery process after the count value and the plurality of random number values are held in response to the operation of the start operation unit 135. The random number value does not become electrically unstable, and the random number for lottery can be reliably acquired.

  Next, a slot machine according to Embodiment 2 of the present invention will be described with reference to FIGS.

  The slot machine according to the second embodiment is obtained by changing the circuit configuration of the random number generation circuit 220 in the slot machine 100 according to the first embodiment. Since the configuration other than the random number generation circuit is the same as that of the slot machine according to the first embodiment, other description is omitted.

  As shown in FIG. 9, the random number generation circuit according to the second embodiment includes two 8-bit counter ICs 401 and 402, eight non-inverting buffers IC 403 to 410, one 4-bit counter IC 411, and one 3to8. And a line recorder IC 412. Since the 8-bit counter ICs 401 and 402, the non-inverting buffer ICs 403 to 410, and the 4-bit counter IC 411 are the same as those in the first embodiment, the description thereof is omitted.

  The 3to8 line recorder IC 412 is an IC that decodes one of the eight output lines / Y0 to / Y7 in accordance with the input conditions of the three select inputs A, B, and C and the three enable inputs G1, / G2A, and / G2B. For example, 74HC138 or the like can be adopted.

  In the random number generation circuit according to the second embodiment, the QA to QH outputs of the 8-bit counter IC 401 are connected in this order to the A1 to A8 inputs of the non-inverting buffer IC 403 and are selected from the QA to QH outputs. These four outputs are connected to the non-inverting buffer ICs 405 to 410, respectively. The QA to QH outputs of the 8-bit counter IC 402 are connected to the A1 to A8 inputs of the non-inverting buffer IC 404 in this order, and four outputs selected from the QA to QH outputs are not These are connected to the inverting buffer ICs 405 to 410, respectively.

  The QA output and QB output of the 4-bit counter IC411 are connected to the select inputs A and B of the 3to8 line recorder IC 412, respectively, and the four output lines / Y0 to / Y3 of the 3to8 line recorder IC412 are not connected. The inverting buffer ICs 403 to 410 are connected to the / G1 input.

  In the random number generation circuit according to the second embodiment, as shown in FIG. 10, two are selected from the non-inverted buffer ICs 403 to 410 according to the combination of the QA output and the QB output based on the / M1 signal, and lottery randomness is generated. The lower 8 bits and upper 8 bits of the numerical value are determined. The CPU 200 acquires the lower 8 bits and the upper 8 bits of the random lottery value by controlling the chip select signal. As a result, the patterns of random number values acquired by the CPU 200 are four patterns as shown in FIGS. 11A to 11D, and these four patterns are input to the / CK input of the 4-bit counter IC411. Are selected at irregular intervals based on the M1 / M1 signal.

  For example, when the random number value changes in four patterns as shown in FIG. 11, at the timing indicated by the arrow 1 in FIG. 11, when QA output = QB output = Low, 2000 becomes QA output = Hi. When the QB output is Low, 21642 is obtained by the CPU 200 as the random number value for lottery, as 26642 when QA output = Low and QB output = Hi, and 28824 when QA output = QB output = Hi. To be acquired. Similarly, at the timing of the arrow 2 in FIG. 11, four numerical values of 30001, 50420, 53057, and 23689, and at the timing of the arrow 3 in FIG. 11, four numerical values of 65533, 57343, 65408, and 32767 are used. Thus, one random number for lottery is acquired in accordance with the state of the QA output and the QB output based on the / M1 signal (see FIG. 11 (e)).

  According to the slot machine of the second embodiment, the counting means includes a plurality of 8-bit counter ICs (two in the second embodiment), and a plurality of 8-bit counter ICs 401 are input to the non-inverting buffer ICs 405 to 410. Since the outputs of the counters 402 and 402 are connected, the generated random number values can be further dispersed.

  Next, a slot machine according to Embodiment 3 of the present invention will be described with reference to FIGS.

  The slot machine according to the third embodiment is obtained by changing the circuit configuration of the random number generation circuit 220 in the slot machine 100 according to the first embodiment. Since the configuration other than the random number generation circuit is the same as that of the slot machine according to the first embodiment, other description is omitted.

  As shown in FIG. 12, the random number generation circuit according to the third embodiment includes two 4-bit counter ICs 501 and 502, one flip-flop IC 503, one 3to8 line recorder IC 504, and 16 non-inverting buffers. 505 to 520 and one non-inverting buffer IC 521. Since the 4-bit counter ICs 501 and 502 and the 3to8 line recorder IC 504 are the same as those in the first and second embodiments, description thereof is omitted. Further, for convenience of explanation, the signal output to the data bus of the CPU 200 is 4 bits. However, it is needless to say that an 8-bit signal can be actually generated as in the first and second embodiments.

  The flip-flop IC 503 has D1 to D8 inputs and Q1 to Q8 outputs, and is configured to output signals input to the D1 to D8 inputs from the Q1 to Q8 outputs in synchronization with the rising edge of the CLK input. For example, 74HC273 or the like can be adopted. The non-inverting buffers 505 to 520 are three-state non-inverting buffers.

  In the random number generation circuit according to the third embodiment, the QA output to QD output of the 4-bit counter IC 501 are connected to the four non-inverting buffers of the non-inverting buffers 505 to 520 via the flip-flop IC 503, respectively. In addition, the A1 input to A4 input of the non-inverting buffer IC 521 are connected to the four non-inverting buffers of the non-inverting buffers 505 to 520, respectively. That is, the QA output to QD output of the 4-bit counter IC 501 and the A1 input to A4 input of the non-inverting buffer IC 521 are combined and connected in a matrix through the non-inverting buffers 505 to 520.

  The QA output to QC output of the 4-bit counter IC 502 are connected to the non-inverting buffers 505 to 520 as three-state control signals via the 3to8 line recorder IC 504.

  In the random number generation circuit according to the third embodiment, the non-inverting buffers 505 to 520 are switched between the conductive state and the high impedance state based on the states of the QA output to QC output of the 4-bit counter IC 502, and the flip-flop IC 503. Q1 output to Q4 output (QA output to QD output of the 4-bit counter IC 501) and A1 input to A4 input of the non-inverting buffer IC 506 are switched. In this random number generation circuit, as shown in FIG. 13, one non-inversion buffer IC 521 has one non-inversion buffer IC 521 for each input by a combination of QA output to QC output based on the / M1 signal. The reverse buffer is selected, and a random number for lottery is output to the data bus of the CPU 200.

  According to the slot machine according to the third embodiment, the counting unit includes a 4-bit counter IC 501 having a plurality of QA outputs to QD outputs capable of outputting the count value as binary data, and the random value generation unit includes: It includes a plurality of non-inverting buffers 505 to 520 arranged for each output QA output to QD output of the 4-bit counter IC 501, and the random number data selecting means is a specific one of the plurality of non-inverting buffers 505 to 520. Since the random number value for lottery can be acquired by selecting the buffer, the random number value for lottery to be generated can be distributed even with a simple circuit configuration, and the effect of preventing fraud is further enhanced. Can do.

  The slot machine according to the present invention is not limited to the structure of the slot machine according to the first to third embodiments. Therefore, for example, in the first to third embodiments, an example of a slot machine using medals (coins) as a game medium is shown. However, the present invention is not limited to this, and for example, a game ball (for example, The present invention can also be applied to a slot machine (so-called pacilot) using a pachinko ball as a game medium.

  The non-inverting buffer (IC) is not limited to the three-state buffer (IC).

  The present invention can be applied to game machines represented by slot machines and the like.

1 is an external front view of a slot machine according to Embodiment 1 of the present invention. Circuit block diagram of main controller in the slot machine The figure which shows the circuit structural example of the random number generation circuit in the slot machine Timing chart showing the timing of various control signals in the control unit of the slot machine Truth table showing combinations of counter outputs in the slot machine and combinations of non-inverting buffer ICs selected based on the outputs The figure which shows the example of the random number value which is generated by the random number generation circuit in the same slot machine Flow chart showing game execution processing in the slot machine A flowchart showing the symbol lottery process in the slot machine The figure which shows the example of the random number generation circuit in the slot machine which concerns on Example 2 of this invention. Truth table showing combinations of counter outputs in the slot machine and combinations of non-inverting buffer ICs selected based on the outputs The figure which shows the example of the random number value which is generated by the random number generation circuit in the same slot machine The figure which shows the circuit structural example of the random number generation circuit in the slot machine which concerns on Example 3 of this invention. Truth table showing the status of each counter output in the slot machine and the combination of non-inverting buffers selected based on each output The figure which shows typically the appearance of occurrence of big hit (BB: big bonus) in the conventional slot machine

Explanation of symbols

100: Slot machine 301, 302, 401, 402: 8-bit counter IC
303 to 306, 403 to 410, 521, non-inverting buffer IC
307, 411, 501, 502 ... 4-bit counter IC
308, 310 ... Inverter IC
309 ... XOR gate 412, 504 ... 3to8 line recorder IC
503 ... flip-flop IC
505 to 520... Non-inverting buffer

Claims (8)

A game machine comprising: a random number generator capable of generating a plurality of random values; and a controller for performing lottery using the random number for lottery acquired from the random number generator,
The random number generator is
Counting means capable of counting at a substantially constant cycle and outputting a count value;
Random number generation means capable of generating the plurality of random values from the count value;
Random number selection means for selecting the random number for lottery from the plurality of random values based on a control signal output at unequal intervals from the control unit, and enabling acquisition of the random number for lottery. A game stand characterized by that. In claim 1,
The counting means includes one or a plurality of counters having a plurality of outputs capable of outputting the count value as binary data,
The random number generation means includes a plurality of buffers for each of the counters, and includes a buffer having a plurality of inputs capable of inputting the binary data, and the inputs of the buffers and the outputs of the counters Connected differently between the buffers,
The gaming table, wherein the random value selection means is configured to select a specific buffer from the plurality of buffers and to acquire the lottery random value. In claim 2,
The counting means includes a plurality of the counters,
A gaming table, wherein the output of at least two counters is connected to the input of the buffer. In claim 1,
The counting means includes a counter having a plurality of outputs capable of outputting the count value as binary data;
The random value generation means includes a plurality of buffers arranged for each output of the counter,
The gaming table, wherein the random value selection means is configured to select a specific buffer from the plurality of buffers and to acquire the lottery random value. In any of claims 2 to 4,
The game machine according to claim 1, wherein the buffer is a three-state buffer capable of switching between a conductive state and a high impedance state. In claim 5,
The buffer is switched between the conductive state and the high impedance state by a select signal output from the random value selection means, and the lottery random value is connected to the control unit when the buffer is in the conductive state. A game table characterized in that it can be output to a designated data bus. In any one of Claims 1 thru | or 6.
The control unit includes a CPU,
The gaming table, wherein the control signal is an M1 signal output from the CPU. In any one of Claims 1 thru | or 7,
The random number generation unit is configured to hold the count value based on a latch signal input from the control unit and to acquire the lottery random value based on a chip select signal input from the control unit A game table characterized by being made.