JP2006114806A - Circuit board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit board that enables proper noise removal by a noise removing component by efficiently conducting heat radiated by the noise removing component mounted on a wiring board. <P>SOLUTION: Even when a laminated capacitor MC etc. (noise removing component) mounted on a signal trace 2 generates heat, the heat can efficiently be radiated from an internal electrode electrically connected to the heat radiating conductor RC of the laminated capacitor MC etc., directly to a heat radiating conductor RC and shield components 80 and 90 connected thereto, and consequently component characteristics of the laminated capacitor MC etc. are prevented from changing with the heat to obtain stable noise removal effect. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a circuit board configured by mounting a noise removing component and a shield component on a wiring board provided with an electronic circuit capable of performing a predetermined function.

  When an electronic circuit capable of performing a predetermined function using an electronic component such as an IC is provided on a wiring board, a noise removing component for preventing noise disturbance from occurring in the electronic circuit is mounted on the wiring board. Further, a shield component for preventing leakage of electromagnetic waves from the electronic circuit and intrusion of electromagnetic waves into the electronic circuit may be mounted on the wiring board.

As the noise removal component, an electronic component corresponding to the type of noise, such as a multilayer capacitor or a multilayer varistor, is used. In this noise elimination component, the signal external electrode is connected to the signal trace of the wiring board, and the ground external electrode is connected to the ground trace of the wiring board. On the other hand, various shapes such as a box shape and an L shape are used as shield parts. Regardless of its shape, this shield component is connected at any part to the ground trace of the wiring board.
Japanese Patent Laid-Open No. 11-102839

  By the way, the above-mentioned noise removing component tends to have heat due to its role, and the component characteristics may change due to this heat, and the desired noise removal may not be performed properly. Usually, cooling is performed by blowing air from a fan, but the effect cannot be obtained so much because heat from the noise removing component cannot be efficiently performed. In other words, in order for the noise removal component to properly perform the desired noise removal, it is necessary to devise a device that can efficiently dissipate heat from the noise removal component.

  The present invention was created in view of the above circumstances, and relates to a circuit board in which a noise removing component and a shield component are mounted on a wiring board provided with an electronic circuit capable of performing a predetermined function, and is mounted on the wiring board. Another object of the present invention is to provide a circuit board that can appropriately perform noise removal by the noise removing component by efficiently performing heat radiation from the noise removing component.

  In order to achieve the above object, the present invention is a circuit board in which a noise removing component and a shielding component are mounted on a wiring board provided with an electronic circuit capable of exhibiting a predetermined function, and there are two types of noise removing components. A laminated chip in which the above internal electrodes are arranged to face each other in a predetermined order, two or more external electrodes provided on one surface of the laminated chip and electrically connected to each type of internal electrode, and on the other surface of the laminated chip A heat-dissipating conductor that is electrically connected to at least one type of internal electrode, and the external electrode that is electrically connected to the heat-dissipating conductor is connected to the ground trace of the wiring board via the internal electrode among the two or more external electrodes; The external electrode is connected to the signal trace of the wiring board, and the heat radiation conductor is connected to the shield component.

  According to the present invention, it is possible to efficiently dissipate heat from the noise removing component mounted on the wiring board and properly perform the desired noise removal by the noise removing component, thereby causing noise disturbance in the electronic circuit. Can be reliably prevented.

  The above object and other objects, structural features, and operational effects of the present invention will become apparent from the following description and the accompanying drawings.

[First Embodiment]
1 to 18 relate to a first embodiment of the present invention, FIG. 1 is a top view of a circuit board, FIG. 2 is a perspective view of a portion indicated by P1, P4, and P5 in FIG. 1, and FIG. 4 is a perspective view of the parts indicated by P2 and P3, FIG. 4 is a perspective view of the parts indicated by P6 and P7 in FIG. 1, FIG. 5 is a diagram excluding the shield parts and noise removing parts from FIG. 1, and FIG. FIG. 7 is an exploded perspective view of the parts indicated by P1, P4, and P5, FIG. 7 is an exploded perspective view of the parts indicated by P2 and P3 in FIG. 1, and FIGS.

  The circuit board shown in FIG. 1 has a high-frequency power amplifier circuit provided on a wiring board. In FIG. 1, 1 is a wiring board, 20, 30 and 40 are connectors, 50 is an IC chip constituting a PLL circuit, and 60 is An IC chip constituting the mixer circuit, 70 an IC chip constituting the amplifier circuit, 80 a shield part for the IC chip 50, and 90 a shield part for the IC chips 60 and 70. In FIG. 1, four types of electronic components, a multilayer capacitor MC, a multilayer varistor MV, a multilayer capacitor array MCA, and a multilayer varistor array MVA, are used as noise eliminating components.

  As shown in FIGS. 1 and 5, the wiring substrate 1 includes signal traces 2, 3, and 4 from the connector 20 to the IC chip 50, a signal trace 5 from the IC chip 50 to the IC chip 60, and a connector 30. The signal trace 6 leading from the IC chip 60, the signal traces 7, 8 leading from the connector 30 to the IC chip 70, the signal trace 9 leading from the IC chip 60 to the IC chip 70, and the signal trace 10 leading from the IC chip 70 to the connector 40 Is formed. The term “signal trace” used in the claims is also used to include a trace corresponding to a power supply line.

  Further, as shown in FIGS. 1 and 5, a substantially rectangular frame-shaped ground trace 11 surrounding the IC chip 60 and a substantially rectangular ground trace 112 surrounding the IC chips 70 and 80 are formed on the wiring board 1. ing. The ground trace 11 is provided with gaps 11a, 11b, and 11c for avoiding interference with the signal traces 2, 4, and 5, and the ground trace 12 is for avoiding interference with the signal traces 6, 7, 8, and 5. Clearances 12a, 12b, 12c, and 12d are provided.

  The multilayer capacitors MC and multilayer varistors MV used as noise removing parts have the same basic dimensions (width, thickness and height), and as shown in FIGS. 2 and 6, there are three on the bottom surface of the body having a rectangular parallelepiped shape. It has external electrodes E1 to E3, and has a heat radiation conductor RC on the upper surface of the main body. Out of the three external electrodes E1 to E3, the two external electrodes E1 and E3 on both sides are ground external electrodes, and the central one external electrode E2 is a signal external electrode. The ground external electrodes E1 and E3 of the multilayer capacitor MC on the IC chip 60 side are connected to the ground trace 11 by soldering or the like, and the signal external electrode E2 is connected to the signal trace 2 by soldering or the like. Further, the multilayer capacitor MC on the IC chip 70, 80 side and the ground external electrodes E1, E3 of the multilayer varistor MV are connected to the ground trace 12 by soldering or the like, and the signal external electrode E2 is soldered to the signal trace 8 or 10 Etc. are connected.

  Further, the multilayer capacitor array MCA and the multilayer varistor array MVA used as noise eliminating components have the same basic dimensions (width, thickness and height), and the respective heights are the same as those of the multilayer capacitor MC and the multilayer varistor MV. And as shown in FIG. 7, it has the four external electrodes E1-E4 of the lower surface of the main body which forms a rectangular parallelepiped shape, and has the thermal radiation conductor part RC on the upper surface of a main body. Out of the four external electrodes E1 to E4, the two external electrodes E1 and E4 on both sides are ground external electrodes, and the central two external electrodes E2 and E3 are signal external electrodes. The ground external electrodes E1 and E4 of the laminated varistor array MVA on the IC chip 60 side are connected to the ground trace 11 by soldering or the like, and the signal external electrodes E2 and E3 are connected to the signal traces 3 and 4 by soldering or the like. Yes. Further, the ground external electrodes E1 and E4 of the multilayer capacitor array MCA on the IC chip 70 and 80 side are connected to the ground trace 12 by soldering or the like, and the signal external electrodes E2 and E3 are soldered to the signal traces 6 and 7 or the like. Connected by.

  The shield component 80 has a shape including a rectangular ceiling surface and four wall surfaces provided along four sides of the ceiling surface. A space 81 (FIG. 1) that can avoid contact with the signal trace 2 at a position overlapping the multilayer capacitor MC on the wall surface of the shield component 80, and that has a rectangular shape that is the same as or slightly larger than the longitudinal sectional shape of the multilayer capacitor MC. 2, and FIG. 2 and FIG. 6), and contact with the signal traces 3 and 4 can be avoided at a position overlapping the laminated varistor array MVA, and the vertical cross-sectional shape of the laminated varistor array MVA coincides with or slightly A space 82 (see FIGS. 1, 3 and 7) having a large rectangular shape is formed, and a rectangular shape or a semicircular shape capable of avoiding contact with the signal trace 5 at a position overlapping the signal trace 5 The fine void 83 is formed.

  In the drawing, the wall height of the shield component 80 is larger than the height of the multilayer capacitor MC and the multilayer varistor array MVA, but the wall height matches the height of the multilayer capacitor MC and the multilayer varistor array MVA. May be used as the shield part 80. In this case, the upper edges of the cavities 81 and 82 coincide with the inner surface of the ceiling surface.

  The shield component 80 is placed on the ground trace 11 so that the multilayer capacitor MC fits in the space 81 on the wall surface and the multilayer varistor array MVA fits in the space 82, and then the lower end of the wall surface is grounded. The trace 11 is connected by soldering SC or the like, the upper edge of the void 81 is connected to the heat radiation conductor RC of the multilayer capacitor MC by soldering SC or the like, and the upper edge of the void 82 is heat radiation conductor of the multilayer varistor array MVA. It is mounted on the wiring board 1 by being connected to RC by soldering SC or the like, and the IC chip 50 is covered in a non-contact manner in the mounted state. When the shield component 80 is mounted, the wall space 81 is substantially closed by the multilayer capacitor MC, and the wall space 82 is substantially blocked by the multilayer varistor array MVA.

  The shield component 90 has a shape including a rectangular ceiling surface and four wall surfaces provided along four sides of the ceiling surface. The positions of the multilayer capacitor MC and the multilayer varistor MV that overlap the wall surface of the shield component 90 can avoid contact with the signal traces 8 and 10, and coincide with or slightly coincide with the longitudinal sectional shapes of the multilayer capacitor MC and the multilayer varistor MV. A large rectangular space 91 (see FIGS. 1, 2 and 6) is formed, and contact with the signal traces 6 and 7 can be avoided at a position overlapping the multilayer capacitor array MCA. A void 92 (see FIGS. 1, 3, and 7) that is coincident with the longitudinal cross-sectional shape of the array MCA or that has a slightly larger rectangular shape is formed, and further, the signal trace 5 A rectangular or semicircular fine void 93 that can avoid contact is formed.

  In the drawing, the shield component 90 has a wall surface height higher than that of the multilayer capacitor MC, multilayer varistor MV, and multilayer capacitor array MCA, but the wall surface height is the multilayer capacitor MC, multilayer varistor MV, and multilayer capacitor. The one that matches the height of the array MCA may be used as the shield part 80, and the upper edges of the cavities 91 and 92 in this case coincide with the inner side surface of the ceiling surface.

  The shield component 90 is placed on the ground trace 12 so that the multilayer capacitor MC and the multilayer varistor MV fit in the two spaces 91 on the wall surface, and the multilayer capacitor array MCA fits in the space 92. After that, the lower end of the wall surface is connected to the ground trace 12 by soldering SC or the like, and the upper edge of each void 91 is connected to the multilayer capacitor MC and the heat radiation conductor RC of the multilayer varistor MV by soldering SC or the like. The upper edge of 92 is mounted on the wiring board 1 by being connected to the heat radiation conductor RC of the multilayer capacitor array MCA by soldering SC or the like, and covers the IC chips 60 and 70 in a non-contact manner. In the state where the shield component 90 is mounted, each void 91 on the wall surface is substantially blocked by the multilayer capacitor MC and the multilayer varistor MV, and the void 92 on the wall surface is substantially blocked by the multilayer capacitor array MCA.

  In FIG. 2 and FIG. 3, the shield parts 80 and 90 are connected to the heat dissipating conductor portions RC of the noise removing parts (multilayer capacitor MC, multilayer varistor MV, multilayer capacitor array MCA and multilayer varistor array MVA) by soldering SC or the like. For this purpose, the end of each noise removing component in the thickness direction is projected outward from the wall surface of the shield component 80, 90. However, there is no particular limitation on the protruding amount, and the protruding amount is set to zero. Also, connection by soldering or the like is sufficiently possible.

  Here, specific structures of the multilayer capacitor MC, the multilayer varistor MV, the multilayer capacitor array MCA, and the multilayer varistor array MVA used as noise removing components will be described with reference to FIGS.

  8A to 8D show a specific structure of the noise removing component 100 applicable to the multilayer capacitor MC and the multilayer varistor MV, in which 101 is a multilayer chip having a rectangular parallelepiped shape, and 102 is the first structure. Reference numeral 1 denotes an internal electrode, 103 denotes a second internal electrode, 104 denotes a first external electrode, 105 denotes a second external electrode, 106 denotes a third external electrode, and 107 denotes a heat radiating conductor. In the noise removing component 100, the vertical direction in FIG. 8A is the component height, the external electrode arrangement direction is the component width, and the internal electrode stacking direction is the component thickness.

  The multilayer chip 101 has a configuration in which first internal electrodes 102 and second internal electrodes 103 are alternately arranged to face each other via a dielectric layer or a varistor layer. In the drawing, the number of layers of the first internal electrode 102 and the second internal electrode 103 is set to 5, but the number of layers of each internal electrode may be arbitrarily increased or decreased.

  The first internal electrode 102 has a rectangular shape, the upper edge is exposed on the upper surface of the multilayer chip 101, both edges in the width direction are at inner positions away from the two side surfaces in the width direction of the multilayer chip 101, and the lower edge is the multilayer chip It is in an inner position away from the lower surface of 101. Further, the first internal electrode 102 has strip-like lead portions 102 a at both ends in the width direction of the lower edge, and the lower edge of each lead portion 102 a is exposed on the lower surface of the multilayer chip 101.

  The second internal electrode 103 has substantially the same rectangular shape as the first internal electrode 102, the upper edge is at an inner position away from the upper surface of the multilayer chip 101, and both edges in the width direction are the two lateral sides of the multilayer chip 101. The lower edge is at an inner position away from the lower surface of the laminated chip 101. The second internal electrode 103 has a strip-like lead portion 103 a at the center in the width direction of the lower edge, and the lower edge of the lead portion 103 a is exposed on the lower surface of the multilayer chip 101.

  The first to third external electrodes 104 to 106 are formed in a strip shape in the thickness direction on the lower surface of the multilayer chip 101 at intervals in the width direction. The first external electrode 104 is connected to the lower edge of one extraction electrode 102a of the first internal electrode 102, the second external electrode 105 is connected to the lower edge of the extraction electrode 103a of the second internal electrode 103, and the third external electrode 106 is connected to the lower edge of the other extraction electrode 102 a of the first internal electrode 102.

  The heat radiating conductor 107 is formed so as to cover the entire top surface of the multilayer chip 101. The heat radiating conductor 107 is connected to the upper edge of the first internal electrode 102.

  8E is an equivalent circuit diagram when the structure of the noise elimination component 100 shown in FIGS. 8A to 8D is applied to the multilayer capacitor MC, and FIG. FIG. 9 is an equivalent circuit diagram when the structure of the noise removal component 100 shown in FIGS. 8A to 8D is applied to a multilayer varistor MV.

  When the structure of the noise removal component 100 is applied to the multilayer capacitor MC, the portion excluding the internal electrode of the multilayer chip 101 is made of a dielectric ceramic such as barium titanate, and the structure of the noise removal component 100 is applied to the multilayer varistor MV. The portion of the laminated chip 101 excluding the internal electrode is made of a semiconductor ceramic such as zinc oxide. In any case, the first and second inner electrodes 102 and 103, the first to third outer electrodes 104 to 106, and the heat radiating conductor 107 are made of a metal such as silver or nickel.

  FIGS. 9A and 9B show a first modification of the noise removal component 100 shown in FIGS. 8A to 8D. This noise removal component 100-1 is shown in FIG. A difference from the noise removing component 100 shown in FIGS. 8A to 8D is that a heat radiating conductor 108 is provided over the top surface of the multilayer chip 101 and two side surfaces in the width direction adjacent to the top surface, and both side surface portions are provided. The lower end of the first external electrode 104 is connected to the first external electrode 104 and the third external electrode 106. In this structure, in addition to the upper surface portion of the heat radiating conductor portion 108, both side surface portions can be connected to the side edges of the cavities 81 and 91 of the shield parts 80 and 90 by soldering SC or the like.

  Although not shown, the heat radiating conductor 108 may be provided across the top surface of the multilayer chip 101 and two side surfaces in the thickness direction adjacent to the top surface, or the width direction adjacent to the top surface of the multilayer chip 101 and the top surface. Two side surfaces and two side surfaces in the thickness direction (four side surfaces) may be provided, or the upper surface of the laminated chip 101 and three side surfaces among the two side surfaces in the width direction and the two side surfaces in the thickness direction adjacent to the top surface. Alternatively, it may be provided over the upper surface of the laminated chip 101 and one of the two side surfaces in the width direction and the two side surfaces in the thickness direction adjacent to the upper surface.

  FIGS. 10A and 10B show a second modification of the noise removal component 100 shown in FIGS. 8A to 8D. This noise removal component 100-2 is shown in FIG. The difference from the noise removing component 100 shown in FIGS. 8A to 8D is that a heat radiating conductor 109 is provided on two side surfaces in the width direction of the multilayer chip 101, and the lower ends of both side portions are connected to the first external electrode 104. The point is that it is connected to the third external electrode 106, and the point that the upper edge of the first internal electrode 102 ′ is located on the inner side away from the upper surface of the multilayer chip 101, and its both side edges are connected to the heat radiating conductor 109. In this structure, the heat radiating conductor 109 can be connected to the side edges of the cavities 81 and 91 of the shield parts 80 and 90 by soldering SC or the like.

  Although not shown in the drawings, each heat radiating conductor 109 may have a portion that goes around two side surfaces or one side surface in the thickness direction of the multilayer chip 101. Further, the heat dissipating conductor 109 is only one side in the width direction, and the side edge of the first internal electrode 102 ′ where the heat dissipating conductor 109 does not exist is positioned on the inner side away from the side in the width direction of the multilayer chip 101. Also good.

  FIG. 11 shows a third modification of the noise removal component 100 shown in FIGS. 8A to 8D. This noise removal component 100-3 is shown in FIGS. 8A to 8D. The difference from the noise removing component 100 shown in FIG. 5 is that one lead portion 102a is excluded from the first internal electrode 102 ″, and one of the first external electrode 104 and the third external electrode 106 (the third external electrode in the drawing). 106) is a dummy external electrode, which is not a useful external electrode and need not necessarily be connected to the ground trace.

  12A to 12D show a specific structure of a noise removing component 200 applicable to the multilayer capacitor array MCA and the multilayer varistor array MVA. 201 in the figure is a multilayer chip having a rectangular parallelepiped shape, 202 Is the first internal electrode, 203 is the second internal electrode, 204 is the third internal electrode, 205 is the first external electrode, 206 is the second external electrode, 207 is the third external electrode, 208 is the fourth external electrode, and 209 is It is a heat radiating conductor part. In this noise elimination component 200, the vertical direction in FIG. 12A is the component height, the external electrode arrangement direction is the component width, and the internal electrode stacking direction is the component thickness.

  In the multilayer chip 201, the first internal electrode 202 and the second and third internal electrodes 203 and 204 existing in the same layer different from the first internal electrode 202 are alternately opposed to each other through a dielectric layer or a varistor layer. It has the composition arranged. In the drawing, the number of layers in which the first internal electrode 202 exists is 5 and the number of layers in which the second and third internal electrodes 203 and 204 exist is 5. However, the number of both layers can be arbitrarily increased or decreased. Good.

  The first internal electrode 202 has a rectangular shape, the upper edge is exposed on the upper surface of the multilayer chip 201, both edges in the width direction are at inner positions away from the two side surfaces in the width direction of the multilayer chip 201, and the lower edge is the multilayer chip It is in an inner position away from the lower surface of 201. Further, the first internal electrode 202 has a strip-like lead part 202 a at both ends in the width direction of the lower edge, and the lower edge of each lead part 202 a is exposed on the lower surface of the multilayer chip 201.

  The second and third internal electrodes 203 and 204 have a rectangular shape whose width direction dimension is about ½ of the first internal electrode 202, and are arranged in the same layer so that there is a gap between them. The second and third internal electrodes 203 and 204 have strip-like lead portions 203 a and 204 a at one end in the width direction of the lower edge, and the lower edges of the lead portions 203 a and 204 a are exposed on the lower surface of the multilayer chip 201. .

  The first to fourth external electrodes 205 to 208 are formed in a strip shape in the thickness direction at intervals in the width direction on the lower surface of the multilayer chip 201. The first external electrode 205 is connected to the lower edge of one extraction electrode 202a of the first internal electrode 202, the second external electrode 206 is connected to the lower edge of the extraction electrode 203a of the second internal electrode 203, and the third external electrode 207 is connected to the lower edge of the extraction electrode 204 a of the third internal electrode 204, and the fourth external electrode 208 is connected to the lower edge of the other extraction electrode 202 a of the first internal electrode 202.

  The heat radiating conductor 209 is formed so as to cover the entire top surface of the multilayer chip 201. The heat radiating conductor portion 209 is connected to the upper edge of the first internal electrode 202.

  12E is an equivalent circuit diagram when the structure of the noise elimination component 200 shown in FIGS. 12A to 12D is applied to the multilayer capacitor array MCA, and FIG. FIG. 13 is an equivalent circuit diagram when the structure of the noise removal component 200 shown in FIGS. 12A to 12D is applied to a multilayer varistor array MVA.

  When the structure of the noise removal component 200 is applied to the multilayer capacitor array MCA, the portion excluding the internal electrode of the multilayer chip 201 is made of a dielectric ceramic such as barium titanate, and the structure of the noise removal component 200 is applied to the multilayer varistor array MVA. In this case, the portion excluding the internal electrode of the multilayer chip 201 is made of a semiconductor ceramic such as zinc oxide. In any case, the first to third internal electrodes 202 to 204, the first to fourth external electrodes 205 to 208, and the heat radiation conductor portion 209 are made of a metal such as silver or nickel.

  FIGS. 13A and 13B show a first modification of the noise removal component 200 shown in FIGS. 12A to 12D. This noise removal component 200-1 is shown in FIG. A difference from the noise removal component 200 shown in FIGS. 12A to 12D is that a heat radiation conductor 210 is provided over the upper surface of the multilayer chip 201 and two side surfaces in the width direction adjacent to the upper surface, and both side surface portions are provided. This is in that the lower end of the first electrode is connected to the first external electrode 205 and the fourth external electrode 208. In this structure, in addition to the upper surface portion of the heat radiating conductor portion 210, both side surface portions can be connected to the side edges of the cavities 82 and 92 of the shield parts 80 and 90 by soldering SC or the like.

  Although not shown, the heat radiating conductor 210 may be provided across the top surface of the multilayer chip 201 and two side surfaces in the thickness direction adjacent to the top surface, or the width direction adjacent to the top surface of the multilayer chip 201 and the top surface. Two side surfaces and two side surfaces in the thickness direction (four side surfaces) may be provided, or the upper surface of the laminated chip 201 and the three side surfaces of the two side surfaces in the width direction and the two side surfaces in the thickness direction adjacent to the top surface. Alternatively, it may be provided over the upper surface of the laminated chip 201 and one of the two side surfaces in the width direction and the two side surfaces in the thickness direction adjacent to the upper surface.

  FIGS. 14A and 14B show a second modification of the noise removal component 200 shown in FIGS. 12A to 12D. This noise removal component 200-2 is shown in FIG. A difference from the noise removing component 200 shown in FIGS. 12A to 12D is that a heat radiating conductor 211 is provided on two side surfaces in the width direction of the multilayer chip 201, and the lower ends of both side portions are connected to the first external electrode 205. The point is that it is connected to the fourth external electrode 208, and the point that the upper edge of the first internal electrode 202 ′ is located on the inner side away from the upper surface of the multilayer chip 201, and its both side edges are connected to the heat radiating conductor 211. In this structure, the heat radiating conductor 211 can be connected to the side edges of the voids 82 and 92 of the shield parts 80 and 90 by soldering SC or the like.

  Although not shown in the drawings, each heat radiating conductor 211 may have a portion that wraps around the two side surfaces or one side surface of the multilayer chip 201 in the thickness direction. Further, the heat dissipating conductor portion 211 is only one side surface in the width direction, and the side edge of the first internal electrode 202 ′ where the heat dissipating conductor portion 211 does not exist is positioned on the inner side away from the width direction side surface of the multilayer chip 201. Also good.

  FIG. 15 shows a third modification of the noise removal component 200 shown in FIGS. 12 (A) to 12 (D). This noise removal component 200-3 is shown in FIGS. 12 (A) to 12 (D). The difference from the noise elimination component 200 shown in FIG. 5 is that one lead portion 202a is excluded from the first internal electrode 202 ″, and one of the first external electrode 205 and the fourth external electrode 208 (the fourth external electrode in the figure). 208) is a dummy external electrode, which is not a useful external electrode and need not necessarily be connected to the ground trace.

  FIGS. 16A to 16F show a specific structure of a noise removing component 300 applicable to the multilayer capacitor array MCA and the multilayer varistor array MVA. In FIG. 16, 301 denotes a multilayer chip having a rectangular parallelepiped shape, 302 Is the first internal electrode, 303 is the second internal electrode, 304 is the third internal electrode, 305 is the fourth internal electrode, 306 is the first external electrode, 307 is the second external electrode, 308 is the third external electrode, and 309 is The fourth external electrode 310 is a heat radiating conductor. In this noise elimination component 300, the vertical direction in FIG. 16A is the component height, the external electrode arrangement direction is the component width, and the internal electrode stacking direction is the component thickness.

  In the multilayer chip 301, the first internal electrode 302, the second internal electrode 303, the third internal electrode 304, and the fourth internal electrode 305 are illustrated in FIG. 16F through a dielectric layer or a varistor layer. It has the structure arranged facing in order and thickness direction. In the drawing, the number of layers of each of the first internal electrode 302, the second internal electrode 303, the third internal electrode 304, and the fourth internal electrode 305 is two. May increase or decrease.

  The first internal electrode 302 has a rectangular shape, the upper edge is exposed on the upper surface of the multilayer chip 301, both edges in the width direction are at inner positions away from the two side surfaces in the width direction of the multilayer chip 301, and the lower edge is the multilayer chip It is in the inner position away from the lower surface of 301. The first internal electrode 302 has a strip-shaped lead portion 302 a at one end in the width direction of the lower edge, and the lower edge of the lead portion 302 a is exposed on the lower surface of the multilayer chip 301.

  The second internal electrode 303 has substantially the same rectangular shape as the first internal electrode 302, the upper edge is at an inner position away from the upper surface of the multilayer chip 301, and both edges in the width direction are two side surfaces in the width direction of the multilayer chip 301. The lower edge is at an inner position away from the lower surface of the laminated chip 301. Further, the second internal electrode 303 has a strip-like lead portion 303 a closer to the side edge than the center of the lower edge, and the lower edge of the lead portion 303 a is exposed on the lower surface of the multilayer chip 301.

  The third internal electrode 304 has substantially the same rectangular shape as the first internal electrode 302, the upper edge is at an inner position away from the upper surface of the multilayer chip 301, and both edges in the width direction are two side surfaces in the width direction of the multilayer chip 301. The lower edge is at an inner position away from the lower surface of the laminated chip 301. The third internal electrode 304 has a strip-shaped lead portion 304 a closer to the side edge than the center of the lower edge, and the lower edge of the lead portion 304 a is exposed on the lower surface of the multilayer chip 301.

  The fourth internal electrode 305 has substantially the same rectangular shape as the first internal electrode 302, the upper edge is exposed on the upper surface of the multilayer chip 301, and both edges in the width direction are the inner sides away from the two side surfaces in the width direction of the multilayer chip 301. The lower edge is at an inner position away from the lower surface of the laminated chip 301. The fourth internal electrode 305 has a strip-shaped lead part 305 a at one end in the width direction of the lower edge, and the lower edge of the lead part 305 a is exposed on the lower surface of the multilayer chip 301.

  The first to fourth external electrodes 306 to 306 are formed in a strip shape in the thickness direction on the lower surface of the multilayer chip 301 at intervals in the width direction. The first external electrode 306 is connected to the lower edge of the extraction electrode 302a of the first internal electrode 302, the second external electrode 307 is connected to the lower edge of the extraction electrode 303a of the second internal electrode 303, and the third external electrode 308 is The third internal electrode 304 is connected to the lower edge of the extraction electrode 304a, and the fourth external electrode 309 is connected to the lower edge of the extraction electrode 305a of the fourth internal electrode 305.

  The heat radiating conductor 310 is formed so as to cover the entire top surface of the multilayer chip 301. The heat radiating conductor 310 is connected to the upper edge of the first internal electrode 302 and the upper edge of the fourth external electrode 305.

  Incidentally, FIG. 16G is an equivalent circuit diagram when the structure of the noise elimination component 300 shown in FIGS. 16A to 16F is applied to the multilayer capacitor MC, and FIG. FIG. 17 is an equivalent circuit diagram when the structure of the noise removal component 300 shown in FIGS. 16A to 16F is applied to a multilayer varistor MV.

  When the structure of the noise removal component 300 is applied to the multilayer capacitor array MCA, the portion excluding the internal electrode of the multilayer chip 301 is made of a dielectric ceramic such as barium titanate, and the structure of the noise removal component 300 is applied to the multilayer varistor array MVA. In this case, the portion excluding the internal electrode of the multilayer chip 301 is made of a semiconductor ceramic such as zinc oxide. In any case, the first to fourth inner electrodes 302 to 305, the first to fourth outer electrodes 306 to 309, and the heat radiating conductor 310 are made of a metal such as silver or nickel.

  FIGS. 17A to 17C show a first modification of the noise removal component 300 shown in FIGS. 16A to 16F. This noise removal component 300-1 is shown in FIG. A difference from the noise elimination component 300 shown in FIGS. 16A to 16F is that a heat radiating conductor portion 311 is provided across the top surface of the multilayer chip 301 and two side surfaces in the width direction adjacent to the top surface. Is that the lower end of the first external electrode 306 is connected to the first external electrode 306 and the fourth external electrode 309. In this structure, in addition to the upper surface portion of the heat radiating conductor portion 311, both side surface portions can be connected to the side edges of the cavities 82 and 92 of the shield parts 80 and 90 by soldering SC or the like.

  Although not shown, the heat radiating conductor 311 may be provided across the upper surface of the multilayer chip 301 and two side surfaces in the thickness direction adjacent to the upper surface, or the width direction adjacent to the upper surface of the multilayer chip 301 and the upper surface. It may be provided over two side surfaces and two side surfaces in the thickness direction (four side surfaces), or over the top surface of the laminated chip 301 and three of the two side surfaces in the width direction and the two side surfaces in the thickness direction adjacent to the top surface. Alternatively, it may be provided over the upper surface of the laminated chip 301 and one of the two side surfaces in the width direction and the two side surfaces in the thickness direction adjacent to the upper surface.

  18A to 18C show a second modification of the noise removal component 300 shown in FIGS. 16A to 16F, and the noise removal component 300-2 is shown in FIG. A difference from the noise elimination component 300 shown in FIGS. 16A to 16F is that a heat radiating conductor portion 312 is provided on two side surfaces in the width direction of the multilayer chip 301, and lower ends of both side surface portions are connected to the first external electrode 306. A point connected to the fourth external electrode 309, a point where the upper edge of the first internal electrode 302 ′ is positioned on the inner side away from the upper surface of the multilayer chip 301, and both side edges thereof are connected to the heat radiation conductor part 312, The upper edge of the internal electrode 305 ′ is located on the inner side away from the upper surface of the multilayer chip 301, and both side edges thereof are connected to the heat radiating conductor portion 312. In this structure, the heat radiating conductor 312 can be connected to the side edges of the voids 82 and 92 of the shield parts 80 and 90 by soldering SC or the like.

  Although not shown in the drawings, each of the heat radiating conductor portions 312 may have a portion that goes around two side surfaces or one side surface in the thickness direction of the multilayer chip 301. Further, the heat dissipating conductor part 312 has only one side surface in the width direction, and the side edge of the first internal electrode 302 ′ and the side edge of the fourth internal electrode 305 ′ on the side where the heat dissipating conductor part 312 does not exist are You may make it locate in the inner side away from.

  In the circuit board shown in FIG. 1, the connector 20 and the IC chip 50 are connected by the multilayer capacitor MC and the multilayer varistor array MVA mounted on the signal traces 2, 3, and 4 between the connector 20 and the IC chip 50. The multilayer capacitor array MCA and the multilayer capacitor mounted on the signal traces 6, 7, and 8 between the connector 30 and the IC chip 60 and the IC chip 70 can remove noise from signals (including power supply signals) flowing between them. Noise can be removed from a signal (including a power supply signal) flowing between the connector 30 and the IC chip 60 and the IC chip 70 by the capacitor MC, and the capacitor MC is mounted on the signal trace 10 between the connector 40 and the IC chip 70. From the signal flowing between the connector 40 and the IC chip 70 by the laminated varistor MV, It can be removed. In addition, the shielding can be performed by the shielding component 80 that covers the IC chip 50 and the shielding component 90 that covers the IC chips 60 and 70.

  Further, the multilayer capacitor MC and multilayer varistor array MVA mounted on the signal traces 2, 3, 4 between the connector 20 and the IC chip 50, and the signal trace 6 between the connector 30, the IC chip 60, and the IC chip 70. Even if the multilayer varistor MV mounted on the signal line 10 between the connector 40 and the IC chip 70 has heat, the multilayer capacitor array MCA and multilayer capacitor MC mounted on the Heat can be directly transferred from the internal electrode conducting to the heat radiating conductor portion RC to the heat radiating conductor portion RC and the shield components 80 and 90 connected to the heat radiating conductor portion RC. Therefore, it is possible to obtain a stable noise removal effect by preventing the component characteristics from being changed by heat.

  Further, each noise removing component (multilayer capacitor MC, multilayer varistor MV, multilayer capacitor array MCA and multilayer varistor array MVA) has at least one internal electrode thereof conducted to the shield components 80 and 90 via the heat radiation conductor RC, In addition, since it is mounted on the wiring board 1 so as to substantially block the voids 81, 82, 91, 92 on the wall surfaces of the shield parts 80, 90, the ESL (equivalent series inductance) of each noise removing part is reduced. And excellent isolation characteristics can be obtained.

  Furthermore, each noise removing component (multilayer capacitor MC, multilayer varistor MV, multilayer capacitor array) mounted on the wiring board 1 so as to substantially block the voids 81, 82, 91, 92 on the wall surfaces of the shield components 80, 90. MCA and multi-layer varistor array MVA) have an internal electrode surface parallel to the wall surface of the shield component, and the internal electrode can be used as a part of the wall surface of the shield component. can do.

  In the first embodiment described with reference to FIGS. 1 to 18, the multilayer capacitor MC and the multilayer varistor array MVA are used as the noise removal component on the IC chip 50 side, and the noise removal component on the IC chips 60 and 70 side is used. Although the multilayer capacitor MC, the multilayer varistor MV, and the multilayer capacitor array MCA are used, the multilayer capacitor MC and the multilayer varistor MV can be replaced, and the multilayer capacitor array MCA and the multilayer varistor array MVA can be replaced.

  In the first embodiment described with reference to FIGS. 1 to 18, the longitudinal sections of the noise removing components (multilayer capacitor MC, multilayer varistor MV, multilayer capacitor array MCA, and multilayer varistor array MVA) are included in the shield components 80 and 90. Although the cavities 81, 82, 91, and 92 having the same or slightly larger rectangular shape are provided, the cavities shown in FIGS. 19 to 22 can be used instead. 19 to 22 illustrate the cavities 81 and 91 for the multilayer capacitor MC and the multilayer varistor MV for convenience of explanation, the cavities 82 and 91 for the multilayer capacitor array MCA and the multilayer varistor array MVA are illustrated. It goes without saying that the same configuration can be adopted for 92.

  19 (A) and 19 (B) show a first modification of the void shape. The difference from the first embodiment is that the protrusions projecting outward or inward at the upper edges of the voids 81 and 91. FIG. It exists in the point which provided piece 81a, 91a. In this void configuration, the contact area between the heat radiation conductor part and the shield part is increased by the projecting pieces 81a and 91a in the noise removal part having the heat radiation conductor part on the upper surface, so that the noise removal part is changed to the shield part. Heat conduction can be performed more efficiently.

  FIGS. 20 (A) and 20 (B) show a second modification of the void shape. The difference from the first embodiment is that the protrusions projecting outward or inward from the side edges of the voids 81 and 91. FIG. The point is that the pieces 81b and 91b are provided. In this void configuration, the contact area between the heat radiation conductor part and the shield part is increased by the projecting pieces 81b and 91b in the noise removal part having the heat radiation conductor part on the upper surface or the side surface in the width direction. Heat conduction to the shield component can be performed more efficiently.

  FIGS. 21 (A) and 21 (B) show a third modification of the void shape. The difference from the first embodiment is that the upper and side edges of the voids 81 and 91 are on the outside or inside. This is in the point where overhanging U-shaped projecting pieces 81c and 91c are provided. In this void configuration, noise removal parts having a heat radiation conductor part on the upper surface or the side surface in the width direction have a contact area between the heat radiation conductor part and the shield part increased by the U-shaped projecting pieces 81c and 91c to remove noise. Heat conduction from the component to the shield component can be performed more efficiently.

  22 (A) and 22 (B) show a fourth modified example of the void shape. The difference from the first embodiment is that the sizes of the voids 81 ′ and 91 ′ are longitudinally cut in the noise removing component. The noise removing component is mounted so as to be smaller than the surface shape and to close the voids 81 ′ and 91 ′ with one side surface in the thickness direction. In this void shape, the size of the voids 81 'and 91' can be made as small as possible to enhance the shielding effect.

  Furthermore, in 1st Embodiment described with reference to FIGS. 1-18, what has a ceiling surface was shown as the shielding components 80 and 90, but when a circuit board is integrated in a flame | frame, it can replace a ceiling surface. In the case where the parts to be arranged are arranged on the upper side of the shield parts 80 and 90, as shown in FIG. 23, it is also possible to use a frame-shaped part composed of four wall surfaces as the shield parts 80-1 and 90-1. It is. 24 is a perspective view of parts indicated by P1, P4 and P5 in FIG. 23, FIG. 25 is a perspective view of parts indicated by P2 and P3 in FIG. 23, and FIG. 26 is a perspective view of parts indicated by P6 and P7 in FIG. FIG.

  Furthermore, in the first embodiment described with reference to FIGS. 1 to 18, the shield parts 80 and 90 having the ceiling surface and the four wall surfaces are shown, but when the circuit board is incorporated in the frame, As shown in FIG. 27, in the case where the substitute part of the ceiling surface is arranged on the upper side of the circuit board and the substitute part of the wall surface is arranged on the side of each shield part 80, 90, It is also possible to use L-shaped or U-shaped ones as the shield parts 80-2 and 90-2 when viewed from the upper surface composed of two wall surfaces or three wall surfaces.

  Although illustration is omitted, depending on the state in which the circuit board is incorporated in the frame, a shape excluding one, two or three of the wall surfaces of the shield parts 80 and 90 can be used as the shield part.

  Furthermore, in the first embodiment described with reference to FIG. 1 to FIG. 18, in the multilayer capacitor array MCA having four external electrodes and the multilayer varistor array MVA, both sides 2 of the four external electrodes E1 to E4 are arranged. The two external electrodes E1 and E4 were used as ground external electrodes, and the two central external electrodes E2 and E3 were used as signal external electrodes. However, in the structure of the multilayer capacitor array MCA and the multilayer varistor array MVA, FIG. As shown in FIG. 28A and FIG. 28B, two external electrodes E2, E4 (or E1, E3) are used as ground external electrodes, and the other two external electrodes E1, E3 (or E2, E4) are used as signals. It can also be used as an external electrode. In this case, one of the two external electrodes E1, E2 located at the end is connected to the signal trace 3, 6 or 4, 7, so that the external electrode does not contact the ground traces 11, 12 and the shield part. In addition, the widths of the voids 82 'and 92' may be slightly enlarged so that a gap is formed.

  Furthermore, in the first embodiment described with reference to FIGS. 1 to 18, the voids 81, 82, 91, and 92 are formed so that one noise removing component fits into the wall surfaces of the shield components 80 and 90. However, when two noise removal components can be mounted side by side, the two noises as shown in FIGS. 29 (A) and 29 (B) except for the case of adopting the space configuration shown in FIG. The voids 84 and 94 having a width corresponding to the width of the removal component are formed on the wall surfaces of the shield components 80 and 90, and the two noise removal components arranged in parallel are fitted into the voids 84 and 94. A simple structure may be adopted.

  In this case, when the connection form shown in FIG. 28 is adopted for the multilayer capacitor array MCA having four external electrodes and the multilayer varistor array MVA, as shown in FIG. 30A and FIG. It is preferable that the widths 84 and 94 are slightly enlarged so that a gap is formed between the noise removal components arranged side by side.

  Furthermore, in the first embodiment described with reference to FIGS. 1 to 18, the multilayer capacitor MC, the multilayer varistor MV, the multilayer capacitor array MCA, and the multilayer varistor array MVA, which are noise elimination components, have the same height. However, even when different noise removing parts are used, if the height of the recess is matched with the height of each noise removing part, the void form of the first embodiment and FIGS. The void form shown in 21 can be adopted as appropriate. In the case of adopting the space configuration shown in FIG. 22, it is not necessary to match the height of the space with these noise removing parts even when different heights are used.

[Second Embodiment]
FIGS. 31 to 34 relate to the second embodiment of the present invention, FIG. 31 is a top view of the circuit board, FIG. 32 is a diagram in which the shield component is excluded from FIG. 31, and FIG. FIG. 34 is an exploded perspective view of the circuit board shown in FIG. 31, excluding the multilayer capacitor MC).

  The circuit board shown in FIG. 31 is obtained by providing a microprocessor on a wiring board. In FIG. 31, reference numeral 1001 denotes a wiring board, and reference numeral 1200 denotes an LSI chip 1200 constituting the microprocessor. The one using the capacitor MC is shown.

  As shown in FIG. 33, the wiring board includes a total of 20 signal traces 1002 to 1021 extending radially from the LSI chip 1200, a total of 16 ground traces 1101 provided so as to surround the LSI chip 1200, and a total of 4 grounds. A trace 1102 is formed.

  The multilayer capacitor MC used as the noise removing component is the same as that described in the first embodiment, is arranged so as to surround the LSI chip 1200, and connects the signal external electrode E2 to the signal traces 1002 to 1021 by soldering or the like. The ground external electrodes E1 and E3 are connected to the ground traces 1101 and 1102. As can be seen from FIGS. 32 and 34, the arrangement form of the multilayer capacitors MC is a rectangular frame shape, the number of multilayer capacitors MC located on each side of the rectangle is 5, and one side in the thickness direction faces the LSI chip 1200 side. Are mounted side by side without any gaps.

  The shield component 1300 has a rectangular plate shape, and the periphery of the lower surface thereof is connected to the heat radiating conductor portion RC of the multilayer capacitor MC arranged in a rectangular frame shape by soldering or the like.

  In the circuit board shown in FIG. 31, noise is removed from input / output signals (including power supply signals) of the LSI chip 1200 by a plurality of multilayer capacitors MC mounted on signal traces 1002 to 1021 around the LSI chip 1200. can do. In addition, shielding can be performed by covering the LSI chip 1200 with the multilayer capacitor MC and rectangular plate-shaped shielding component 1300 arranged in a rectangular frame shape.

  Further, even when a plurality of multilayer capacitors MC mounted on the signal traces 1002 to 1021 around the LSI chip 1200 have heat, the heat of each multilayer capacitor MC is directly transmitted from the internal electrode that conducts heat to the heat radiating conductor RC. The heat radiation conductor RC and the shield parts 80 and 90 connected to the heat conduction conductor RC can be transmitted to efficiently dissipate heat, thereby preventing the component characteristics of each multilayer capacitor MC from being changed by heat and stable noise. A removal effect can be obtained.

  Further, each multilayer capacitor MC is mounted so that one type of internal electrode thereof is electrically connected to the shield component 1300 via the heat radiation conductor RC and surrounds the LSI chip 1200 without a gap. Excellent isolation characteristics can be obtained by reducing the ESL (equivalent series inductance) of the MC.

  Furthermore, each multilayer capacitor MC arranged so as to surround the LSI chip 1200 has the internal electrode surface direction parallel to the component arrangement direction, and each internal electrode can be used as the wall surface of the shield component 1300. An excellent shielding effect can be exhibited.

  In the second embodiment described with reference to FIGS. 31 to 34, the multilayer capacitor MC is used as the noise removing component. However, a multilayer varistor MV may be used instead of the multilayer capacitor MC. If the signal trace pattern is changed, either the multilayer capacitor array MCA or the multilayer varistor array MVA can be used. The multilayer capacitor MC, the multilayer varistor MV, the multilayer capacitor array MCA, and the multilayer varistor array MVA are used together. It is also possible.

  Further, in the second embodiment described with reference to FIGS. 31 to 34, a plurality of multilayer capacitors MC are arranged around the IC chip 1200 in a rectangular frame shape, but shown in FIGS. A component arrangement form may be adopted.

  35 to 37 show a first modification of the component arrangement form. FIG. 35 is a top view of the component circuit, FIG. 36 is a diagram in which the shield component is excluded from FIG. 35, and FIG. FIG. This first modified example is different from the second embodiment in that one side of the multilayer capacitor MC and the signal traces 1017 to 1021 arranged in a rectangular frame shape are excluded, and instead of the excluded signal traces 1017 to 1021. The wall 1301 is provided on one side of the shield part 1300-1 corresponding to the portion excluding the multilayer capacitor MC and the lower edge of the wall is connected to the ground trace 1103 by soldering or the like. In the point.

  FIG. 38 shows a second modification of the component arrangement form. The difference from the second embodiment is that the multilayer capacitor MC and the signal traces 1012 to 1021 arranged in a rectangular frame shape are excluded. In addition to the excluded signal traces 1012 to 1021, an L-shaped ground trace 1104 is provided as viewed from above, and walls 1301 and 1302 are provided on two sides of the shield part 1300-2 corresponding to the portion excluding the multilayer capacitor MC. The lower edge of each wall surface is connected to the ground trace 1104 by soldering or the like.

  Although not shown, the multilayer capacitor MC and the signal traces 1007 to 1021 arranged in a rectangular frame shape are excluded, and a U-shaped ground trace is used instead of the excluded signal traces 1007 to 1021. In addition, a component arrangement may be employed in which wall surfaces are provided on three sides of the shield component corresponding to the portion excluding the multilayer capacitor MC, and the lower edge of each wall surface is connected to the ground trace by soldering or the like.

1 is a top view of a circuit board according to a first embodiment of the present invention. It is a perspective view of the site | part shown by P1, P4, and P5 in FIG. It is a perspective view of the site | part shown by P2, P3 in FIG. It is a perspective view of the site | part shown by P6 and P7 in FIG. It is the figure which excluded the shield component and the noise removal component from FIG. It is a disassembled perspective view of the site | part shown by P1, P4, and P5 in FIG. It is a disassembled perspective view of the site | part shown by P2, P3 in FIG. It is a figure which shows the specific structure of the noise removal components applicable to a multilayer capacitor and a multilayer varistor. It is a figure which shows the 1st modification of the noise removal components shown in FIG. It is a figure which shows the 2nd modification of the noise removal components shown in FIG. It is a figure which shows the 3rd modification of the noise removal components shown in FIG. It is a figure which shows the specific structure of the noise removal component applicable to a multilayer capacitor array and a multilayer varistor array. It is a figure which shows the 1st modification of the noise removal components shown in FIG. It is a figure which shows the 2nd modification of the noise removal components shown in FIG. It is a figure which shows the 3rd modification of the noise removal components shown in FIG. It is a figure which shows the specific structure of the noise removal component applicable to a multilayer capacitor array and a multilayer varistor array. It is a figure which shows the 1st modification of the noise removal components shown in FIG. It is a figure which shows the 2nd modification of the noise removal components shown in FIG. It is a figure which shows the 1st modification of a void form. It is a figure which shows the 2nd modification of a void form. It is a figure which shows the 3rd modification of a void form. It is a figure which shows the 4th modification of a void form. It is a figure which shows the shape modification of a shield component. It is a perspective view of the site | part shown by P1, P4, and P5 in FIG. It is a perspective view of the site | part shown by P2, P3 in FIG. It is a perspective view of the site | part shown by P6 and P7 in FIG. It is a figure which shows the other shape modification of a shield component. It is a figure which shows the modification of a component arrangement | positioning form. It is a figure which shows the other modification of a components arrangement | positioning form. It is a figure which shows the further another modification of a component arrangement | positioning form. It is a top view of the circuit board concerning a 2nd embodiment of the present invention. It is the figure which excluded the shield component from FIG. It is the figure which excluded the noise removal component from FIG. FIG. 32 is an exploded perspective view of the circuit board shown in FIG. 31. It is a top view of the component circuit which shows the 1st modification of a component arrangement | positioning form. It is the figure which excluded the shield component from FIG. It is a principal part side view of FIG. It is a figure which shows the 2nd modification of a component arrangement | positioning form.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Wiring board, 2-10 ... Signal trace, 11, 12 ... Ground trace, 50, 60, 70 ... IC chip, 80, 80-1, 80-2, 90, 90-1, 90-2 ... Shield component , 81, 81 ′, 82, 82 ′, 84, 91, 91 ′, 92, 92 ′, 94... Empty space, 81 a, 81 b, 81 c, 91 a, 91 b, 91 c. Multilayer varistor, MCA ... Multilayer capacitor array, MVA ... Multilayer varistor array, RC ... Heat dissipation conductor, E1-E4 ... External electrode, 100, 100-1, 100-2, 100-3 ... Noise elimination component, 101 ... Multilayer chip , 102, 102 ', 102 "... first internal electrode, 103 ... second internal electrode, 104 ... first external electrode, 105 ... second external electrode, 106 ... third external electrode, 107, 108, 109 ... radiating conductor Part, 00, 200-1, 200-2, 200-3 ... noise elimination component, 201 ... laminated chip, 202, 202 ', 202 "... first internal electrode, 203 ... second internal electrode, 204 ... third internal electrode, 205 ... first external electrode, 206 ... second external electrode, 207 ... third external electrode, 208 ... fourth external electrode, 209, 210, 211 ... radiation conductor, 300,300-1,300-2 ... noise removal Components 301... Multilayer chip 302, 302 ′ first internal electrode 303 303 second internal electrode 304 ... third internal electrode 305 305 ′ fourth internal electrode 306 ... first external electrode 307 2nd external electrode, 308 ... 3rd external electrode, 309 ... 4th external electrode, 310, 311, 312 ... Radiation conductor part, 1001 ... Wiring board, 1002-1021 ... Signal trace, 1101, 1102, 1103, 1 04 ... ground trace, 1200 ... LSI chip, 1300,1300-1,1300-2 ... shield parts.

Claims (8)

A circuit board comprising a noise removing component and a shield component mounted on a wiring board provided with an electronic circuit capable of performing a predetermined function,
The noise removing component includes a laminated chip in which two or more types of internal electrodes are arranged to face each other in a predetermined order, two or more external electrodes provided on one surface of the laminated chip and electrically connected to the internal electrodes of each type, A heat-dissipating conductor portion that is provided on the other surface of the multilayer chip and is electrically connected to at least one type of internal electrode; Connected to the trace, other external electrodes are connected to the signal trace of the wiring board, and the heat dissipation conductor is connected to the shield component,
A circuit board characterized by that. The shield component includes at least one wall connected to the ground trace and having a space for avoiding contact with the signal trace;
The noise removal component is mounted on the wiring board so as to substantially block the void in the wall surface of the shield component.
The circuit board according to claim 1. The noise elimination component is composed of two or more noise elimination components arranged in parallel, and is mounted on the wiring board so as to substantially block the void of the wall surface of the shield component by the two or more noise elimination components.
The circuit board according to claim 2. The noise elimination component is fitted in the space on the shield component wall.
The circuit board according to claim 2, wherein the circuit board is provided. At the edge of the void of the wall surface of the shield part, a projecting piece for increasing the contact area with the heat radiation conductor part of the noise elimination part is provided.
The circuit board according to any one of claims 2 to 4, wherein: The noise removal component is in a direction in which the direction of the surface of the internal electrode is parallel to the wall surface of the shield component.
The circuit board according to any one of claims 2 to 5, wherein: The noise removing component has at least a heat radiating conductor portion on a surface facing one surface of the multilayer chip, and a plurality of the noise removing components are mounted side by side on the wiring board,
The lower surface of each shield component is connected to the heat dissipating conductor of each noise removal component mounted side by side.
The circuit board according to claim 1. The plurality of noise removal components are in an orientation in which the direction of the surface of the internal electrode is parallel to the component arrangement direction.
The circuit board according to claim 7.

Images