JP5937190B2 - Circuit board - Google Patents

Description

Embodiments described herein relate generally to a circuit board .

  In circuit boards such as motherboards and modules on which electronic parts such as semiconductor parts are mounted, mutual interference between elements due to electromagnetic waves caused by circuit operation and noise propagating to the ground plane and power supply plane may cause the circuit board to malfunction. There is. The malfunction of the circuit board due to mutual interference, noise or the like appears particularly prominently when the circuit board is downsized, that is, the mounting layout area of the electronic component is reduced.

  In order to prevent malfunction of the circuit board due to mutual interference, noise, or the like, for example, an interval between mounted electronic components is increased, or a filter circuit using the electronic components is added to the circuit board. However, the enlargement between electronic components and the addition of a filter circuit hinder downsizing of the circuit board.

  On the other hand, a method may be used in which a semiconductor component that is easily affected by electromagnetic waves or an entire electronic circuit on a circuit board that is easily affected by electromagnetic waves is covered with a metal casing. This method physically protects semiconductor parts and electronic circuits and blocks harmful electromagnetic waves from the outside.

  In addition, since an effect of reducing the circuit area is higher than when a filter circuit is formed using electronic components, it has been devised to provide an EBG (Electromagnetic Band Gap) structure in a dielectric circuit board.

JP 2009-218966 A

  The problem to be solved by the present invention is to provide a circuit board that achieves both miniaturization and suppression of malfunction due to mutual interference of elements, noise, and the like.

  A circuit board according to an embodiment is a circuit board on which a plurality of electronic components are mounted on a printed wiring board, and a semiconductor device mounted on the printed wiring board, and the opposite side of the printed wiring board to the semiconductor device The semiconductor device has an operating frequency outside the cutoff band of the first EBG structure, and the first EBG structure is connected to the ground of the printed wiring board or An electrode unit connected to a power source, wherein an operating frequency of the circuit board is within a cutoff band of the first EBG structure, and the first EBG structure is formed of a first conductor; A patch portion that is provided substantially parallel to the electrode portion and is formed of a second conductor and is 10 mm square or less; an insulating layer provided between the electrode portion and the patch portion; and the patch portion in the insulating layer; Above It is provided between the pole portion, a mushroom structure and a via connected to the patch portion and the electrode portion.

It is a schematic diagram of the semiconductor component of 1st Embodiment. 1 is a schematic cross-sectional view of a circuit board on which a semiconductor component according to a first embodiment is mounted. It is a figure which shows the electromagnetic field analysis result of 1st Embodiment. It is a figure which shows the effect | action of the semiconductor component and circuit board of 1st Embodiment. It is a schematic diagram of the semiconductor component of 2nd Embodiment.

  In this specification, the “semiconductor device” is not only a semiconductor chip including an SOC (system on chip) but also, for example, a plurality of semiconductor chips are bonded with a resin, and a mutual wiring layer is formed between the chips. It is a concept that also includes semiconductor parts to be connected, so-called pseudo SOC (pseudo system on chip).

  In this specification, “semiconductor component” is a concept including not only a semiconductor package in which a semiconductor device is sealed but also a so-called bare chip in a state in which the semiconductor device is not sealed.

  In this specification, “electronic component” is a concept including all electronically functioning components such as semiconductor components and passive components such as an antenna, a capacitor, and a resistor.

  In this specification, a “printed wiring board” is a board on which a printed wiring of a conductor is formed, and means a so-called bare board in which no electronic component is mounted.

  In this specification, the “circuit board” means a state in which electronic components are mounted on a printed wiring board.

  Further, in this specification, the “stop band” of the EBG structure is defined by, for example, a frequency band in which S21, which indicates an insertion loss, is −20 dB or less, that is, a cutoff amount (insertion loss) is larger than −20 dB. It shall be.

(First embodiment)
The semiconductor component of the present embodiment is a semiconductor component including a semiconductor device and a first EBG structure formed on the semiconductor device. The operating frequency of the semiconductor device is outside the cutoff band of the first EBG structure.

  In addition, the circuit board of the present embodiment is a circuit board on which a plurality of electronic components are mounted on a printed wiring board. The semiconductor component is mounted on a printed wiring board and includes a semiconductor device and a first EBG structure formed on the semiconductor device. The operating frequency of the semiconductor device is outside the cutoff band of the first EBG structure. Then, the first EBG structure is connected to the ground or power source of the printed wiring board.

  The ground of the printed wiring board means a ground surface or ground wiring, or a ground potential applied to them. Moreover, the power supply of a printed wiring board means a power supply surface or power supply wiring, or the power supply potential given to them.

  The semiconductor component according to the present embodiment has the above-described configuration, and is mounted on a printed wiring board. By connecting the ground or power supply and the first EBG structure, for example, a special filter circuit is not provided. Stabilize the circuit board ground and power supply. Therefore, by using this semiconductor component, it is possible to form a circuit board that achieves both miniaturization and suppression of malfunction due to mutual interference of elements, noise, and the like.

  In addition, the circuit board of the present embodiment has the above-described configuration, so that, for example, a new electronic component is mounted on a printed wiring board and a filter circuit is not provided, thereby stabilizing the ground and power supply of the circuit board. Therefore, it is possible to realize a circuit board that achieves both miniaturization and suppression of malfunction due to mutual interference of elements and noise.

  In the semiconductor component of the present embodiment, the first EBG structure has a cutoff band different from the operating frequency of the semiconductor device, so that not only the electromagnetic wave harmful to the semiconductor component itself is blocked, but other than the semiconductor component itself, For example, it is possible to block electromagnetic waves in a frequency band that is harmful to a circuit board on which semiconductor components are mounted.

  FIG. 1 is a schematic diagram of a semiconductor component of the present embodiment. FIG. 1A is a schematic cross-sectional view of a semiconductor component, and FIG. 1B is a schematic perspective view of a first EBG structure.

  The semiconductor component 100 includes a semiconductor device 10 at a lower portion and a first EBG structure 12 formed on the semiconductor device 10. A case will be described as an example where the semiconductor device 10 is a semiconductor component in which a plurality of semiconductor chips are bonded with a resin and the mutual chips are connected by a wiring layer, that is, a so-called pseudo SOC (pseudo system on chip).

  The pseudo SOC 10 includes a plurality of semiconductor chips 14a to 14e. The semiconductor chips 14 a to 14 e are bonded with a resin 16. The semiconductor chips 14 a to 14 e are electrically connected by, for example, a multilayer wiring layer 18.

  A first EBG structure 12 is provided on the pseudo SOC 10. In FIG. 1A, a region surrounded by a dotted line is one unit of the first EBG structure 12. This one unit is regularly arranged.

  FIG. 1B is a schematic perspective view of the first EBG structure 12 of the present embodiment. The first EBG structure 12 includes an electrode portion 20 formed of a first conductor and a patch portion 22 provided substantially parallel to the electrode portion 20 and formed of a second conductor. In addition, an insulating layer 24 provided between the electrode portion 20 and the patch portion 22 is provided. A via 26 that connects the electrode unit 20 and the patch unit 22 is provided. The first EBG structure 12 has a so-called mushroom structure.

  The electrode unit 20 is a reference surface, for example, a ground surface or a power supply surface. The electrode unit 20 is connected to the ground or power source of the printed wiring board when the semiconductor component 10 is mounted on the printed wiring board. The first conductor is, for example, a metal such as aluminum (Al) or gold (Au).

  The patch part 22 is formed of a second conductor. The second conductor is a metal such as aluminum (Al) or gold (Au), for example. The shape of the patch part 22 is not particularly limited, and may be a quadrangle, a circle, or other shapes.

  The size of the patch unit 22 is optimized to obtain a desired stop band (stop band region). The size of the patch portion 22 is desirably 10 mm square or less from the viewpoint of reducing the size of the semiconductor component.

  The insulating layer 24 is, for example, an organic resin.

  The via 26 is formed of a conductor. The conductor used is not particularly limited, and may be a metal, a semiconductor, or a conductive resin. The via 26 is provided between the patch part 22 and the electrode part 20 in the insulating layer 24, and is connected to the patch part 22 and the electrode part 20.

  FIG. 2 is a schematic cross-sectional view of a circuit board 200 on which the semiconductor component 10 of the present embodiment is mounted. On the circuit board 200, a plurality of electronic components 32 a, 32 b, 32 c and the semiconductor component 100 are mounted on the printed wiring board 30. The electronic components 32a, 32b, and 32c are, for example, semiconductor components such as logic LSIs and memories, or passive components such as capacitors, resistors, and coils. The plurality of electronic components 32 a, 32 b, 32 c and the semiconductor component 100 are mounted on the printed wiring board 30 by, for example, bump portions 34. The circuit board 200 is a motherboard, for example.

  The printed wiring board 30 has a structure in which an insulating layer 36 such as a resin, a metal ground surface 38, and a metal power supply surface 40 are laminated. In the insulating layer 36, for example, a through via 42 is provided, and the ground surface 38 and the power supply surface 40 are configured to be connectable to the semiconductor component 100 and the electronic components 32a, 32b, and 32c. FIG. 2 shows a cross section in which the ground plane 38 and the semiconductor product 100 are connected via the through via 42 and the bump portion 34.

  The semiconductor component 100 includes a semiconductor device 10 and a first EBG structure 12. The semiconductor component 100 is mounted such that the first EBG structure 12 is on the opposite side of the printed wiring board 30 with the semiconductor device 10 interposed therebetween. Thereby, the first EBG structure 12 also functions as a physical protective layer of the semiconductor device. That is, the first EBG structure 12 also has a function as a housing of the semiconductor device 12.

  For example, the electrode part 20 of the first EBG structure 12 is electrically connected to the ground surface 38 of the printed wiring board 30. The operating frequency of the semiconductor device 10 is outside the cutoff band of the first EBG structure 12, and the operating frequency (transmission frequency) of the circuit board 200 is within the cutoff band of the first EBG structure 12. A first EBG structure is designed.

  The first EBG structure 12 functions as a stop band filter that blocks a frequency harmful to the operation of the circuit board 200 by blocking the operating frequency (transmission frequency) of the circuit board 200. In the circuit board 200 of the present embodiment, a region above the semiconductor 100 mounted on the circuit board 200, that is, a dead space is used as a filter circuit for the circuit board 200. Accordingly, it is not necessary to separately provide a filter circuit composed of electronic components on the circuit board 200, and the circuit board 200 can be downsized.

  In the first EBG structure 12, the operating frequency of the semiconductor device 10 is outside the cut-off band of the first EBG structure 12, and the operating frequency (transmission frequency) of the circuit board 200 is the first EBG structure 12. It is designed to be within the stopband. For this reason, the effect of the first EBG structure 12 stabilizing the operation of the semiconductor device 10 itself is not great, but the influence of the electromagnetic waves in the cutoff band of the first EBG structure 12 on the semiconductor device 10 can be reduced. Needless to say.

  FIG. 3 is a diagram illustrating an electromagnetic field analysis result of the circuit board according to the present embodiment. This is a result obtained by simulation. In the first EBG structure 12, the patch portions 22 are arranged in a matrix of 5 rows and 5 columns at 3 mm square and 1 mm intervals. The patch part 22 is connected to the electrode part 20 which is a reference surface by a via 26 having a length of 0.5 mm. And the electrode part 20 shall be connected with the ground surface 38 of the printed wiring board 30 in which the semiconductor product 100 is mounted.

  In FIG. 3, the horizontal axis represents the frequency of the transmission signal, and the vertical axis represents the S parameter (S21). A dotted line is a characteristic when the semiconductor product 100 to be mounted does not include the first EBG structure 12, and a solid line is a transmission characteristic when the first EBG structure 12 is provided.

  As indicated by the dotted line, in the absence of the first EBG structure 12, for example, only -1 dB insertion loss can be seen at 10 GHz. Therefore, for example, when noise of 10 GHz rides on the ground surface of the printed wiring board 30 connected to the first EBG structure 12, this noise cannot be blocked.

  On the other hand, as shown by the solid line, when the first EBG structure 12 is present, it can be seen that the circuit board 200 functions as a 10 GHz stopband filter with a cutoff amount of −40 dB. Therefore, for example, when the circuit board 200 has an operating frequency of 10 GHz, it can be said that the first EBG structure 12 serves as a stopband filter that blocks frequencies harmful to the operation of the circuit board 200.

  FIG. 4 is a diagram illustrating the operation of the semiconductor component and the circuit board according to the present embodiment. 4A is a schematic top view of the circuit board when the semiconductor component does not have the first EBG structure 12, and FIG. 4B is a schematic top view of the circuit board when the first EBG structure 12 is present. Indicates.

  As shown in FIG. 4A, electronic components 32a, 32b, 32c, 32d, 32e, 32f, 32g, 32h, and 32i and semiconductor components 100a and 100b are mounted on a printed wiring board 30 to form a circuit board. It shall be. In this circuit board, in order to suppress mutual interference of signals, the electronic components are arranged in consideration of the signal flow from the input to the output indicated by the dotted arrows in the drawing. For this reason, large-sized electronic components are arranged so that interference due to signals does not occur. Accordingly, the distance between the electronic components 32a, 32b, 32c, 32d, and 32e positioned on the upper side in the drawing and the electronic components 32f, 32g, 32h, and 32i positioned on the lower side in the drawing is maintained by the distance indicated by the solid arrows in the drawing. ing.

  On the other hand, in FIG. 4B, the first EBG structure 12 is provided on the upper parts of the semiconductor components 100a and 100b, and is disposed at a place where interference between electronic components is predicted due to, for example, noise propagating on the ground surface. Then, for example, the first EBG structure 12 is connected to the ground surface of the printed wiring board. Thereby, for example, it is possible to block the noise propagating on the ground surface from the electronic components 32a, 32b, 32c, 32d, and 32e located on the upper side in the drawing by the semiconductor components 100a and 100b. Therefore, the distance between the electronic components 32a, 32b, 32c, 32d, and 32e located on the upper side in the drawing and the electronic components 32f, 32g, 32h, and 32i located on the lower side in the drawing is compared with the case of FIG. And can be made smaller.

  As described above, the first EBG structure 12 formed on the semiconductor device 10 functions as a stop band filter of the circuit board 100, so that it is possible to block noise propagating on the ground plane of the circuit board 100. It becomes. Therefore, the distance between the electronic components mounted on the circuit board can be shortened. Therefore, the circuit board can be downsized.

  In the present embodiment, the first EBG structure 12 is formed using the same material in the same process as the multilayer wiring layer 18 of the pseudo SOC by using the semiconductor device 10 as the pseudo SOC. Is possible. Therefore, there is an advantage that the first EBG structure can be easily formed on the semiconductor component 100.

  However, the semiconductor device 10 is not necessarily limited to the pseudo SOC, and may be an SOC, a single logic LSI, a memory, or the like. In this case, for example, the first EBG structure 12 is not formed by the same process as the semiconductor device 10, but is formed by, for example, a process of bonding the semiconductor device 10 and the first EBG structure formed separately. It doesn't matter.

  Further, the case where the first EBG structure 12 is connected to the ground surface 38 of the printed wiring board 30 has been described as an example. However, the first EBG structure 12 may be connected to the power supply surface 40 of the printed wiring board 30 and may have a function of blocking noise on the power supply surface 40.

  Alternatively, an EBG structure similar to the first EBG structure may be further laminated to form two layers, and one may be connected to the ground surface 38 of the printed wiring board 30 and the other to the power supply surface 40.

  Further, the case where the first EBG structure 12 is a mushroom type has been described as an example. From the viewpoint of obtaining good blocking characteristics, a mushroom type is preferable, but other structures such as a vialess mosaic structure can also be applied.

(Second Embodiment)
In the semiconductor component and the circuit board according to the present embodiment, the semiconductor component includes the second EBG structure between the first EBG structure and the semiconductor device, and the operating frequency of the semiconductor device is the second EBG structure. This is the same as in the first embodiment except that it is within the cutoff band. Therefore, the description overlapping the first embodiment is omitted.

  FIG. 5 is a schematic diagram of the semiconductor component of the present embodiment. FIG. 5A is a schematic cross-sectional view of a semiconductor component, and FIG. 5B is a schematic perspective view of a second EBG structure.

  The semiconductor component 300 includes a semiconductor device 10, a second EBG structure 42 formed on the semiconductor device 10, and a first EBG structure 12 formed on the second EBG structure 42. . That is, the semiconductor component 300 is different from the first embodiment in that the semiconductor component 300 includes a second EBG structure 42 between the first EBG structure 12 and the semiconductor device 10.

  A case will be described as an example where the semiconductor device 10 is a semiconductor component in which a plurality of semiconductor chips are bonded with a resin and the mutual chips are connected by a wiring layer, that is, a so-called pseudo SOC (pseudo system on chip).

  The pseudo SOC 10 includes a plurality of semiconductor chips 14a to 14e. The semiconductor chips 14 a to 14 e are bonded with a resin 16. The semiconductor chips 14 a to 14 e are electrically connected by, for example, a multilayer wiring layer 18.

  A second EBG structure 42 is provided on the pseudo SOC 10. In FIG. 5A, a region surrounded by the lower dotted line is one unit of the second EBG structure 42. This one unit is regularly arranged.

  The first EBG structure 12 is provided above the second EBG structure 42. In FIG. 5A, a region surrounded by the upper dotted line is one unit of the first EBG structure 12. This one unit is regularly arranged.

  FIG. 5B is a schematic perspective view of the second EBG structure according to the present embodiment. The second EBG structure 42 includes an electrode portion 50 formed of a first conductor and a patch portion 52 provided substantially parallel to the electrode portion 50 and formed of a second conductor. In addition, an insulating layer 24 provided between the electrode portion 20 and the patch portion 22 is provided. The second EBG structure 42 is a so-called vialess mosaic structure.

  The electrode unit 50 is a reference surface, for example, a ground surface or a power supply surface. The electrode unit 50 is connected to the ground or power supply of the printed wiring board when the semiconductor component 10 is mounted on the printed wiring board. The first conductor is, for example, a metal such as aluminum (Al) or gold (Au).

  The patch part 52 is formed of a second conductor. The second conductor is a metal such as aluminum (Al) or gold (Au), for example. The shape of the patch part 52 is not particularly limited, and may be a quadrangle, a circle, or other shapes. Further, for example, the patch sections 52 may be connected by a bridge line.

  The size of the patch unit 52 is optimized to obtain a desired stop band (stop band region). The size of the patch portion 52 is desirably 10 mm square or less from the viewpoint of reducing the size of the semiconductor component.

  The insulating layer 24 is, for example, an organic resin.

  The semiconductor component 300 of the present embodiment is configured such that the operating frequency of the semiconductor device 10 is within the cutoff band of the second EBG structure 42. Therefore, the second EBG structure 42 functions as a stop band filter that cuts off a frequency band that is particularly harmful to the operation of the semiconductor device 10.

  When the semiconductor component 300 is mounted on the circuit board, for example, the electrode unit 20 that is the reference surface of the first EBG structure 12 is electrically connected to the ground surface of the printed wiring board. And the electrode part 50 which is a reference surface of a 2nd EBG structure is also connected with the ground surface of a printed wiring board, for example.

  For example, the operating frequency of the semiconductor device 10 in the semiconductor component 300 may be different from the operating frequency (transmission frequency) of the circuit board on which the semiconductor component 300 is mounted. In such a case, the frequency of electromagnetic waves harmful to the operation of the semiconductor device 10 is different from the frequency of electromagnetic waves harmful to the operation of the circuit board.

  According to the present embodiment, the first EBG structure 12 functions as a stop band filter that blocks a frequency harmful to the operation of the circuit board by blocking the operating frequency (transmission frequency) of the circuit board 200. . In addition, the second EBG structure 42 functions as a stopband filter that blocks a frequency band harmful to the operation of the semiconductor device 10 by blocking the operating frequency of the semiconductor device 10.

  Therefore, the operation of the circuit board can be stabilized and downsized, and the operation of the semiconductor device 10 can be stabilized. When the first EBG structure 12 and the second EBG structure 42 cover the semiconductor device 10 with a metal casing, physical protection of the semiconductor device 10 carried by the metal casing and harmful electromagnetic waves on the semiconductor device 10 are generated. It will be responsible for the blocking function. Further, the first EBG structure has a function of blocking harmful electromagnetic waves with respect to the circuit board.

  As described above, the semiconductor component 300 and the circuit board on which the semiconductor component 300 according to the present embodiment is mounted can block harmful electromagnetic waves inside the semiconductor component and the circuit board outside the semiconductor component.

  Note that the second EBG structure 42 may be connected to the power supply surface of the printed wiring board. Alternatively, for example, the first EBG structure is connected to the power supply surface of the printed wiring board to stabilize the power supply of the circuit board, and the second EBG structure is connected to the ground surface of the printed wiring board to It may be configured to stabilize the ground.

  Further, the case where the second EBG structure 52 has a vialess mosaic structure has been described as an example. This structure is desirable from the viewpoint of simplifying the structure, but other structures such as a mushroom structure can also be applied.

  The embodiments of the present invention have been described above with reference to specific examples. The above embodiment is merely given as an example, and does not limit the present invention. In the description of the embodiment, the description of the circuit board, the semiconductor component, etc. that is not directly necessary for the description of the present invention is omitted, but the elements related to the required circuit board, the semiconductor component, etc. Can be appropriately selected and used.

  In addition, all circuit boards and semiconductor components that include the elements of the present invention and can be appropriately modified by those skilled in the art are included in the scope of the present invention. The scope of the present invention is defined by the appended claims and equivalents thereof.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 12 1st EBG structure 20 Electrode part 22 Patch part 24 Insulating layer 26 Via 30 Printed wiring board 38 Ground surface 40 Power supply surface 50 2nd EBG structure 100 Semiconductor component 200 Circuit board 300 Semiconductor component

Claims (3)

A circuit board on which a plurality of electronic components are mounted on a printed wiring board,
A semiconductor device mounted on the printed wiring board, and a first EBG structure provided on the opposite side of the printed wiring board with respect to the semiconductor device,
An operating frequency of the semiconductor device is outside a cutoff band of the first EBG structure;
The first EBG structure is connected to a ground or a power source of the printed wiring board;
An operating frequency of the circuit board is within a cutoff band of the first EBG structure;
The first EBG structure is
An electrode portion formed of a first conductor;
A patch part that is provided substantially parallel to the electrode part and is formed of a second conductor and is 10 mm square or less;
An insulating layer provided between the electrode portion and the patch portion;
A via provided between the patch portion and the electrode portion in the insulating layer, and connected to the patch portion and the electrode portion;
A circuit board characterized by having a mushroom structure.   The circuit board according to claim 1, wherein the semiconductor device is a pseudo SOC. 3. The first conductor according to claim 1, wherein the first conductor is aluminum (Al) or gold (Au), and the second conductor is aluminum (Al) or gold (Au). Circuit board.