JP2006113568A5 - - Google Patents
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- JP2006113568A5 JP2006113568A5 JP2005267826A JP2005267826A JP2006113568A5 JP 2006113568 A5 JP2006113568 A5 JP 2006113568A5 JP 2005267826 A JP2005267826 A JP 2005267826A JP 2005267826 A JP2005267826 A JP 2005267826A JP 2006113568 A5 JP2006113568 A5 JP 2006113568A5
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- layer
- insulating layer
- interlayer insulating
- electrode layer
- forming
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- 239000010410 layer Substances 0.000 claims 157
- 239000011229 interlayer Substances 0.000 claims 45
- 239000000758 substrate Substances 0.000 claims 12
- 239000012535 impurity Substances 0.000 claims 8
- 239000003566 sealing material Substances 0.000 claims 8
- 239000004065 semiconductor Substances 0.000 claims 8
- 238000004519 manufacturing process Methods 0.000 claims 7
- 239000011810 insulating material Substances 0.000 claims 6
- 230000003796 beauty Effects 0.000 claims 4
- 238000007789 sealing Methods 0.000 claims 4
- 238000000576 coating method Methods 0.000 claims 2
- 239000000463 material Substances 0.000 claims 2
- 238000005192 partition Methods 0.000 claims 2
- WKODDKLNZNVCSL-UHFFFAOYSA-N 1,3,2$l^{2},4$l^{2}-oxazadisiletidine Chemical compound N1[Si]O[Si]1 WKODDKLNZNVCSL-UHFFFAOYSA-N 0.000 claims 1
- 125000000217 alkyl group Chemical group 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 claims 1
- XCCANNJCMHMXBZ-UHFFFAOYSA-N hydroxyiminosilicon Chemical compound ON=[Si] XCCANNJCMHMXBZ-UHFFFAOYSA-N 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
Claims (15)
前記画素領域に不純物領域を含む半導体層を有し、
前記半導体層上にはゲート絶縁層を有し、
前記ゲート絶縁層上にはゲート電極層を有し、
前記ゲート電極層上には第１の層間絶縁層を有し、
前記ゲート絶縁層及び前記第１の層間絶縁層は前記不純物領域に達する第１の開口を有し、
前記第１の開口にソース電極層又はドレイン電極層が設けられ、
前記ソース電極層又は前記ドレイン電極層は、前記第１の層間絶縁層を介して前記ゲート電極層の一部を覆っており、
前記ソース電極層、前記ドレイン電極層、及び前記第１の層間絶縁層上に第２の層間絶縁層を有し、
前記第２の層間絶縁層は前記ソース電極層又は前記ドレイン電極層に達する第２の開口を有し、
前記第２の開口に第１の電極層が設けられ、
前記第１の電極層上に隔壁となる絶縁層及び前記絶縁層と同材料でなるスペーサを有し、
前記接続領域には前記第１の層間絶縁層を有し、
前記第１の層間絶縁層上に配線層を有し、
前記配線層上に、前記配線層に達する第３の開口が設けられた前記第２の層間絶縁層を有し、
前記第３の開口の上端部は、前記絶縁層に覆われており、
前記第３の開口に、前記絶縁層に接して第２の電極層が設けられ、
前記基板は、前記第１の層間絶縁層上に形成されたシール材によって封止基板と貼り合わされ、
前記シール材は前記絶縁層と接しないことを特徴とする表示装置。 Includes a pixel region on a substrate, and a connection region,
A semiconductor layer including an impurity region in the pixel region;
A gate insulating layer on the semiconductor layer;
A gate electrode layer on the gate insulating layer;
A first interlayer insulating layer on the gate electrode layer;
The gate insulating layer and the first interlayer insulating layer have a first opening reaching the impurity region;
A source electrode layer or a drain electrode layer is provided in the first opening;
The source electrode layer or the drain electrode layer covers a part of the gate electrode layer through the first interlayer insulating layer,
A second interlayer insulating layer on the source electrode layer , the drain electrode layer , and the first interlayer insulating layer;
The second interlayer insulating layer has a second opening reaching the source electrode layer or the drain electrode layer ;
First electrode layer is provided in front Stories second opening,
An insulating layer serving as a partition on the first electrode layer and a spacer made of the same material as the insulating layer;
The connection region has the first interlayer insulating layer,
Has a wiring layer on the first interlayer insulating layer,
On the wiring layer, the second interlayer insulating layer provided with a third opening reaching the wiring layer,
Upper portion of the third opening is covered with the insulating layer,
A second electrode layer is provided in the third opening in contact with the insulating layer;
The substrate is bonded to a sealing substrate by a sealing material formed on the first interlayer insulating layer,
The display device, wherein the sealing material is not in contact with the insulating layer.
前記画素領域に不純物領域を含む半導体層を有し、
前記半導体層上にはゲート絶縁層を有し、
前記ゲート絶縁層上にはゲート電極層を有し、
前記ゲート電極層上には第１の層間絶縁層を有し、
前記ゲート絶縁層及び前記第１の層間絶縁層は前記不純物領域に達する第１の開口を有し、
前記第１の開口にソース電極層又はドレイン電極層が設けられ、
前記ソース電極層又は前記ドレイン電極層は、前記第１の層間絶縁層を介して前記ゲート電極層の一部を覆っており、
前記ソース電極層、前記ドレイン電極層、及び前記第１の層間絶縁層上に第２の層間絶縁層を有し、
前記第２の層間絶縁層は前記ソース電極層又は前記ドレイン電極層に達する第２の開口を有し、
前記第２の開口に第１の電極層が設けられ、
前記第１の電極層上に隔壁となる絶縁層を有し、
前記接続領域には前記第１の層間絶縁層を有し、
前記第１の層間絶縁層上に配線層を有し、
前記配線層上に、前記配線層に達する第３の開口が設けられた前記第２の層間絶縁層を有し、
前記第３の開口の上端部は、前記絶縁層に覆われており、
前記第３の開口に、前記絶縁層に接して第２の電極層が設けられ、
前記基板は、前記第１の層間絶縁層上に形成されたシール材によって封止基板と貼り合わされ、
前記シール材は前記絶縁層と接しないことを特徴とする表示装置。 Includes a pixel region on a substrate, and a connection region,
A semiconductor layer including an impurity region in the pixel region;
A gate insulating layer on the semiconductor layer;
A gate electrode layer on the gate insulating layer;
A first interlayer insulating layer on the gate electrode layer;
The gate insulating layer and the first interlayer insulating layer have a first opening reaching the impurity region;
A source electrode layer or a drain electrode layer is provided in the first opening;
The source electrode layer or the drain electrode layer covers a part of the gate electrode layer through the first interlayer insulating layer,
A second interlayer insulating layer on the source electrode layer , the drain electrode layer , and the first interlayer insulating layer;
The second interlayer insulating layer has a second opening reaching the source electrode layer or the drain electrode layer ;
First electrode layer is provided in front Stories second opening,
An insulating layer serving as a partition wall on the first electrode layer;
The connection region has the first interlayer insulating layer,
Has a wiring layer on the first interlayer insulating layer,
On the wiring layer, the second interlayer insulating layer provided with a third opening reaching the wiring layer,
Upper portion of the third opening is covered with the insulating layer,
A second electrode layer is provided in the third opening in contact with the insulating layer;
The substrate is bonded to a sealing substrate by a sealing material formed on the first interlayer insulating layer,
The display device, wherein the sealing material is not in contact with the insulating layer.
接続領域及び前記半導体層上にゲート絶縁層を形成し、
前記ゲート絶縁層上にゲート電極層及び導電層を形成し、
前記ゲート電極層及び前記導電層上に第１の層間絶縁層を形成し、
前記ゲート絶縁層及び前記第１の層間絶縁層に前記不純物領域に達する第１の開口を有し、
前記第１の開口及び前記ゲート電極層の一部を覆ってソース電極層又はドレイン電極層を形成し、
前記第１の層間絶縁層を介して前記導電層上に配線層を形成し、
前記第１の層間絶縁層、前記配線層、前記ソース電極層、及び前記ドレイン電極層上に第２の層間絶縁層を形成し、
前記第２の層間絶縁層に前記ソース電極層又は前記ドレイン電極層に達する第２の開口、及び前記配線層に達する第３の開口を形成し、
前記第２の開口に第１の電極層を形成し、
前記第２の層間絶縁層の前記第３の開口の上端部及び前記第１の電極層の一部を覆って絶縁層を形成し、
前記第１の電極層上に前記絶縁層と同材料でなるスペーサを形成し、
前記第３の開口に、前記絶縁層に接して第２の電極層を形成し、
前記基板と、前記第１の層間絶縁層上に形成したシール材を用いて封止基板とを貼り合わせ、
前記シール材は前記絶縁層に接せずに形成することを特徴とする表示装置の作製方法。 Forming a semiconductor layer having an impurity region in a pixel region on the substrate;
Forming a gate insulating layer on the connection region and the semiconductor layer;
Forming a gate electrode layer and a conductive layer on the gate insulating layer;
The first interlayer insulating layer is formed on the gate electrode So及 beauty said conductive layer,
Has a first opening reaching the impurity regions on the gate insulating layer and the first interlayer insulating layer,
Forming a source electrode layer or a drain electrode layer over a portion of said first apertures及 beauty the gate electrode layer,
Forming a wiring layer on the conductive layer via the first interlayer insulating layer;
Forming a second interlayer insulating layer on the first interlayer insulating layer, the wiring layer, the source electrode layer , and the drain electrode layer;
Forming a second opening reaching the source electrode layer or the drain electrode layer and a third opening reaching the wiring layer in the second interlayer insulating layer;
Forming a first electrode layer in the second opening;
Over a portion of the upper portion and the first electrode layer of the third opening of the second interlayer insulating layer to form an insulating layer,
Forming a spacer made of the same material as the insulating layer on the first electrode layer;
Forming a second electrode layer in contact with the insulating layer in the third opening;
Bonding the substrate and a sealing substrate using a sealing material formed on the first interlayer insulating layer,
The method for manufacturing a display device wherein the sealing material, characterized in that that form without Sesse to the insulating layer.
接続領域及び前記半導体層上にゲート絶縁層を形成し、
前記ゲート絶縁層上にゲート電極層及び導電層を形成し、
前記ゲート電極層及び前記導電層上に第１の層間絶縁層を形成し、
前記ゲート絶縁層及び前記第１の層間絶縁層に前記不純物領域に達する第１の開口を有し、
前記第１の開口及び前記ゲート電極層の一部を覆ってソース電極層又はドレイン電極層を形成し、
前記第１の層間絶縁層を介して前記導電層上に配線層を形成し、
前記第１の層間絶縁層、前記配線層、前記ソース電極層、及び前記ドレイン電極層上に第２の層間絶縁層を形成し、
前記第２の層間絶縁層に前記ソース電極層又は前記ドレイン電極層に達する第２の開口、及び前記配線層に達する第３の開口を形成し、
前記第２の開口に第１の電極層を形成し、
前記第２の層間絶縁層の前記第３の開口の上端部及び前記第１の電極層の一部を覆って絶縁層を形成し、
前記第３の開口に、前記絶縁層に接して第２の電極層を形成し、
前記基板と、前記第１の層間絶縁層上に形成したシール材を用いて封止基板とを貼り合わせ、
前記シール材は前記絶縁層に接せずに形成することを特徴とする表示装置の作製方法。 Forming a semiconductor layer having an impurity region in a pixel region on the substrate;
Forming a gate insulating layer on the connection region and the semiconductor layer;
Forming a gate electrode layer and a conductive layer on the gate insulating layer;
The first interlayer insulating layer is formed on the gate electrode So及 beauty said conductive layer,
Has a first opening reaching the impurity regions on the gate insulating layer and the first interlayer insulating layer,
Forming a source electrode layer or a drain electrode layer over a portion of said first apertures及 beauty the gate electrode layer,
Forming a wiring layer on the conductive layer via the first interlayer insulating layer;
Forming a second interlayer insulating layer on the first interlayer insulating layer, the wiring layer, the source electrode layer , and the drain electrode layer;
Forming a second opening reaching the source electrode layer or the drain electrode layer and a third opening reaching the wiring layer in the second interlayer insulating layer;
Forming a first electrode layer in the second opening;
Over a portion of the upper portion and the first electrode layer of the third opening of the second interlayer insulating layer to form an insulating layer,
Forming a second electrode layer in contact with the insulating layer in the third opening;
Bonding the substrate and a sealing substrate using a sealing material formed on the first interlayer insulating layer,
The method for manufacturing a display device wherein the sealing material, characterized in that that form without Sesse to the insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005267826A JP2006113568A (en) | 2004-09-17 | 2005-09-15 | Display device, and method for manufacturing the same |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004272628 | 2004-09-17 | ||
| JP2005267826A JP2006113568A (en) | 2004-09-17 | 2005-09-15 | Display device, and method for manufacturing the same |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2011265630A Division JP5244958B2 (en) | 2004-09-17 | 2011-12-05 | Method for manufacturing light-emitting display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2006113568A JP2006113568A (en) | 2006-04-27 |
| JP2006113568A5 true JP2006113568A5 (en) | 2008-10-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| JP2005267826A Pending JP2006113568A (en) | 2004-09-17 | 2005-09-15 | Display device, and method for manufacturing the same |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7368233B2 (en) | 2018-03-30 | 2023-10-24 | 京東方科技集團股▲ふん▼有限公司 | Substrates and their manufacturing methods, electronic devices |
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| JP2007335327A (en) * | 2006-06-16 | 2007-12-27 | Konica Minolta Holdings Inc | Organic electroluminescence element, and method for manufacturing the element |
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| JP5266737B2 (en) * | 2007-12-05 | 2013-08-21 | セイコーエプソン株式会社 | Organic EL device and electronic device |
| JP5416987B2 (en) | 2008-02-29 | 2014-02-12 | 株式会社半導体エネルギー研究所 | Film forming method and light emitting device manufacturing method |
| JP5238544B2 (en) | 2008-03-07 | 2013-07-17 | 株式会社半導体エネルギー研究所 | Film forming method and light emitting device manufacturing method |
| US8409672B2 (en) | 2008-04-24 | 2013-04-02 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing evaporation donor substrate and method of manufacturing light-emitting device |
| KR101182234B1 (en) | 2010-05-28 | 2012-09-12 | 삼성디스플레이 주식회사 | Organic light emitting diode display and fabricating method for the same |
| JP5735506B2 (en) | 2010-06-29 | 2015-06-17 | 株式会社Ｊｏｌｅｄ | Manufacturing method of organic light emitting device |
| JP6231281B2 (en) | 2013-01-23 | 2017-11-15 | 株式会社ジャパンディスプレイ | Display device |
| KR102107565B1 (en) * | 2013-12-18 | 2020-05-08 | 삼성디스플레이 주식회사 | Organic light emitting diode display |
| KR102199216B1 (en) | 2014-06-09 | 2021-01-07 | 삼성디스플레이 주식회사 | Organic light-emitting display apparatus |
| JP2017152231A (en) * | 2016-02-25 | 2017-08-31 | 株式会社ジャパンディスプレイ | Display device and method for manufacturing display device |
| US10185190B2 (en) * | 2016-05-11 | 2019-01-22 | Semiconductor Energy Laboratory Co., Ltd. | Display device, module, and electronic device |
| KR102497187B1 (en) * | 2016-05-31 | 2023-02-08 | 엘지디스플레이 주식회사 | Organic Emitting Light Display device having an organic insulating layer |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7368233B2 (en) | 2018-03-30 | 2023-10-24 | 京東方科技集團股▲ふん▼有限公司 | Substrates and their manufacturing methods, electronic devices |
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