JP2002318546A - Light emitting device and method of making the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of making a light emitting device by making the light emitting elements long in life and having a structure which is more hardly deteriorated than heretofore. SOLUTION: The surfaces of anodes exposed after the formation of banks are subjected to flatening and removal of dust by wiping the surfaces by using a porous material, etc., of a PVA(polyvinyl alcohol)-based material. Insulating films are formed to cover the banks and the anodes, by which the ruggedness of the anode surfaces is covered up and the balance of the holes and electrons to be injected into organic compound layers is put into order.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting element having a film containing an organic compound capable of emitting light by applying an electric field (hereinafter referred to as "organic compound layer"), an anode, and a cathode. To a method for manufacturing a light-emitting device. In particular, the present invention relates to a light-emitting device using a light-emitting element whose driving voltage is lower than that of a conventional one and whose element life is longer. Note that a light-emitting device in this specification refers to an image display device or a light-emitting device using a light-emitting element as a light-emitting element.
In addition, a connector such as an anisotropic conductive film ((FPC: Flexible Printed Circuit) or TAB (Tap
e Automated Bonding) tape or TCP (Tape Carri
er Package), a module with a printed circuit board in front of TAB tape or TCP,
Or COG (Chip On Glass) method for light emitting element IC
All the modules on which the (integrated circuit) is directly mounted are also included in the light emitting device.

[0002]

2. Description of the Related Art Light-emitting devices have attracted attention as next-generation flat panel display devices because of their characteristics such as thinness, lightness, high-speed response, and low-voltage DC drive. In addition, since it is a self-luminous type and has a wide viewing angle, visibility is relatively good, and it is considered to be effective as an element used for a display screen of an electric appliance, and is being actively developed.

The light-emitting mechanism of a light-emitting element that emits light by applying an electric field is such that electrons injected from a cathode and holes injected from an anode are applied to an organic compound by applying a voltage across an organic compound layer between electrodes. It is said that a molecular exciton is recombined at an emission center in the layer to form a molecular exciton, and the molecular exciton emits energy and emits light when returning to a ground state. In addition, as a kind of the molecular exciton formed by the organic compound, a singlet excited state and a triplet excited state are possible, but the present specification includes the case where either excited state contributes to light emission. .

[0004] Such light emitting elements are classified into a passive matrix type (simple matrix type) and an active matrix type depending on the driving method. However, QVGA
Since high-definition display having the number of pixels described above is possible, an active matrix type is particularly attracting attention.

An active matrix type light emitting device having a light emitting element has an element structure as shown in FIG. 2, in which a current controlling TFT 202 is formed on a substrate 201 and an interlayer is provided on the current controlling TFT 202. Insulating film 203
Is formed.

The wiring 2 is formed on the interlayer insulating film 203.
An anode (pixel electrode) 205 electrically connected to the TFT 202 is formed by the TFT 04. As a material for forming the anode 205, a transparent conductive material having a large work function is suitable, such as ITO (indium tin oxides) and tin oxide (Sn).
O ₂ ), alloys of indium oxide and zinc oxide (ZnO), semi-permeable films of gold, polyaniline and the like have been proposed. Among them, ITO has a band gap of about 3.75.
eV, which is most often used because it has high transparency in the visible light region.

On the anode 205, an organic compound layer 206 is formed. In the present specification, all layers provided between the anode and the cathode are defined as organic compound layers. The organic compound layer 206 specifically includes a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer, an electron transport layer, and the like. Basically, a light-emitting element has a structure in which an anode / light-emitting layer / cathode are sequentially stacked. In addition to this structure, an anode / a hole injection layer /
It may have a structure in which a light emitting layer / cathode or an anode / hole injection layer / light emitting layer / electron transport layer / cathode are stacked in this order.

After forming the organic compound layer 206, the cathode 207 is formed, whereby the light emitting element 209 is formed. As the cathode, a metal having a small work function (typically, a metal belonging to Group 1 or 2 of the periodic table) is often used. In this specification, such a metal (including an alkali metal and an alkaline earth metal) is referred to as an “alkali metal”.

The anode is formed so as to cover the end of the anode,
At this portion, a bank 208 made of an organic resin material is formed to prevent a short circuit between the cathode and the anode.

Although FIG. 2 shows only light emitting elements formed in one pixel, an active matrix type light emitting device is actually formed by forming a plurality of these in a pixel portion.

[0011]

The anode is an electrode for injecting holes involved in light emission into the organic compound layer. If a crack is generated in the anode, the anode adversely affects the generation of holes or the injected anode. It is considered that the number of holes is reduced and the cracks cause deterioration of the light emitting element itself. Irregularities on the anode surface may adversely affect the generation and injection of holes, decrease the number of injected holes, and cause the cracks to cause deterioration of the light emitting element itself.

Further, the organic compound layer has the property of being easily degraded by oxygen or moisture, but the materials used as the interlayer insulating film are many organic resin materials such as polyimide, polyamide and acrylic. There is a problem that a light emitting element is deteriorated by a gas such as oxygen generated from an interlayer insulating film formed by using the method.

It is an object of the present invention to provide a method for manufacturing a long-life light-emitting element that solves the above-mentioned problem by using a light-emitting element having a structure that is less likely to deteriorate than in the past, and for manufacturing a high-quality light-emitting device.

[0014]

According to the present invention, an interlayer insulating film made of an inorganic insulating film is formed on a TFT formed on an insulator,
Flattening the interlayer insulating film by a CMP method, forming a wiring, forming an anode electrically connected to the TFT through the wiring, forming a resin insulating film covering the anode and the wiring, and etching Forming a bank, performing a plasma treatment on the bank to perform surface modification, wiping the anode, forming an insulating film covering the anode and the bank, and forming an organic compound layer on the insulating film. It is characterized by forming.

[0015] Since the interlayer insulating film is formed of an inorganic insulating film, the problem of deterioration of the light emitting element due to generation of moisture or gas can be solved.

Further, silicon nitride or DL may be formed on the interlayer insulating film.
Since the insulating film made of the C film is formed, it is possible to prevent the alkali metal used for forming the light emitting element from entering the TFT.

Furthermore, by wiping the anode, it is possible to flatten the unevenness of the anode surface and to remove dust on the anode surface.

Further, by forming an insulating film covering the anode and the bank, an effect of balancing the amount of holes and electrons injected into the organic compound layer can be expected.

In another aspect of the invention, after a resin insulating film for forming a bank is formed, an antistatic film is formed, and after being moved to a processing chamber capable of avoiding contamination of an alkali metal or the like, the charging is performed. A bank is formed by removing the prevention film and etching the resin insulating film.

In the above invention, the antistatic film is a film that can be removed by washing with water.

Another aspect of the invention is characterized in that the method includes a step of forming a bank, performing heat treatment on the anode, crystallizing the same, and then performing a plasma treatment on the surface of the bank.

As described above, the surface of the bank is subjected to the plasma treatment to modify the surface to form a cured film, thereby preventing the emission of moisture from the bank and the deterioration of the light emitting element.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A TFT 101 is formed on a substrate 100. The TFT shown here is a TFT for controlling a current flowing to the light-emitting element, and is referred to as a current control TFT 101 in this specification (FIG. 1A).

Next, an interlayer insulating film 102 is formed on the current controlling TFT 101 and flattened. Interlayer insulating film 10
As No. 2, an inorganic insulating film, typically, a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, or a stacked film obtained by combining these is formed by a plasma CVD method or a sputtering method.

Next, in order to flatten the surface of the interlayer insulating film 102, the interlayer insulating film 102 is formed by CMP (Chemical Mecha).
Polishing and flattening by a technique called nical Polish (chemical mechanical polishing) method. After the flattening process, the average thickness of the interlayer insulating film is adjusted to about 1.0 to 2.0 μm. Further, an insulating film made of a silicon nitride film or a DLC film may be formed over the interlayer insulating film 102 that has been subjected to the planarization treatment.

Thereafter, a resist mask having a desired pattern is formed, a contact hole reaching the drain region of the current controlling TFT 101 is formed, and a wiring 103 is formed. As a wiring material, a conductive metal film such as Al or T
In addition to i, a film may be formed by a sputtering method or a vacuum evaporation method using these alloy materials, and then patterned into a desired shape.

Next, a transparent conductive film 104 serving as an anode of the light emitting element is formed. The transparent conductive film 104 is typically formed using indium tin oxide (ITO) or a transparent conductive film in which 2 to 20% of zinc oxide (ZnO) is mixed with indium oxide.

Subsequently, the transparent conductive film 104 is etched to form an anode 105 (FIG. 1B). After that, the bank 106 is formed, and heat treatment is performed at 230 to 350 ° C. Note that in this specification, an insulating film which has an opening over the anode 105 and covers the anode end is referred to as a bank (FIG. 1C).

Next, the surface of the anode 105 is cleaned together with the cleaning liquid by a PVA (polyvinyl alcohol) -based porous material 108.
To perform flattening of the surface of the anode 105 and removal of dust and the like. In this specification, the surface of the anode is PV
A process of wiping using an A (polyvinyl alcohol) -based porous body, flattening, and removing dust is referred to as wiping. Incidentally, reference numeral 107 denotes an axis (FIG. 1).
(D)).

After wiping the surface of the anode, the insulating film 10
9 is formed. As the insulating film 109, an organic resin insulating film selected from polyimide, polyamide, and acrylic is formed with a thickness of 1 to 5 nm by spin coating.

Next, the organic compound layer 1 is formed on the insulating film 109.
10. The cathode 111 is formed. The organic compound layer 110
In addition to the light-emitting layer, a hole injection layer is formed by combining and stacking a plurality of layers such as a hole transport layer, a hole blocking layer, an electron transport layer, an electron injection layer, and a buffer layer. The thickness of the organic compound layer 110 is preferably about 10 to 400 nm (FIG. 1D).

The cathode 111 is formed by an evaporation method after forming the organic compound layer 110. As a material for forming the cathode 111, a film formed by co-evaporation of aluminum and an element belonging to Group 1 or 2 of the periodic table, in addition to MgAg or an Al-Li alloy (alloy of aluminum and lithium), is used. Is also good. The thickness of the cathode 111 is 80 to 20.
About 0 nm is preferable.

Here, the state of the surface of the transparent conductive film by performing the wiping treatment will be described with an atomic force microscope (AFM:
FIGS. 13 to 15 show the results of surface observation using Atomic Force Microscope).

In the surface observation in this embodiment, an ITO film formed on a glass substrate with a thickness of 110 nm and crystallized by heat treatment at 250 ° C. is used as a measurement surface.

FIGS. 13 and 14 show the irregularities on the substrate surface observed by AFM. FIG. 13 shows the result of observing the measurement surface before the wiping treatment, and FIG. 14 shows the result of observing the measurement surface after the wiping treatment.

FIG. 15 shows the average surface roughness (Ra) before and after the wiping treatment using Bellclean (manufactured by Ozu Sangyo) as a PVA-based porous material for wiping. In addition,
The average surface roughness referred to here is a three-dimensional extension of the center line average roughness defined in JIS B0601 so that it can be applied to the surface. As can be seen from FIG. 15, the average surface roughness (Ra) of the surface of the anode 105 is 0.9
nm or less, preferably 0.85 nm or less. From this result, it can be seen that after the wiping treatment, the average surface roughness on the measurement surface is small and the flatness is increased.

[0037]

Embodiment (Embodiment 1) In this embodiment, a light emitting element manufactured by using the present invention will be described. Note that here, an example of a method for simultaneously manufacturing a pixel portion having the light-emitting element of the present invention over the same substrate and a TFT (an n-channel TFT and a p-channel TFT) of a driver circuit provided around the pixel portion is described. This will be described with reference to FIGS.

First, in this embodiment, Corning # 70
A substrate 900 made of glass such as barium borosilicate glass typified by 59 glass or # 1737 glass or aluminoborosilicate glass is used. Note that the substrate 900 is not limited as long as it is a light-transmitting substrate, and a quartz substrate may be used. Further, a plastic substrate having heat resistance enough to withstand the processing temperature of this embodiment may be used.

Next, as shown in FIG.
A base insulating film 901 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate. Although a two-layer structure is used as the base insulating film 901 in this embodiment, a single-layer film of the insulating film or a structure in which two or more insulating films are stacked may be used. As the first layer of the base insulating film 901,
Using plasma CVD, SiH ₄ , NH ₃ , and N ₂ O
Is used as a reaction gas to form a silicon oxynitride film 901a of 10 to 200 nm (preferably 50 to 100 nm). In this embodiment, the silicon oxynitride film 9 having a thickness of 50 nm is used.
01a (composition ratio Si = 32%, O = 27%, N = 24
%, H = 17%). Next, the base insulating film 90
As the first second layer, a plasma CVD
₄ and a silicon oxynitride film 901b formed using N ₂ O as a reaction gas to a thickness of 50 to 200 nm (preferably 100 to 1 nm).
(50 nm). In this embodiment, a 100-nm-thick silicon oxynitride film 901b (composition ratio Si = 3
2%, O = 59%, N = 7%, H = 2%).

Next, the semiconductor layer 9 is formed on the base insulating film 901.
02 to 905 are formed. The semiconductor layers 902 to 905 are
After forming a semiconductor film having an amorphous structure by a known means (sputtering method, LPCVD method, plasma CVD method, or the like), a known crystallization treatment (laser crystallization method, thermal crystallization method, nickel, or the like) The crystalline semiconductor film obtained by performing the thermal crystallization method using a catalyst described above is patterned into a desired shape and formed. These semiconductor layers 902 to 90
5 has a thickness of 25 to 80 nm (preferably 30 to 60 n).
m). Without limitation on the material of the crystalline semiconductor film, preferably silicon (silicon) or silicon germanium _{(Si X Ge 1-X (} X = 0.0001~0.0
2)) It is good to form with an alloy etc. In this embodiment, after a 55 nm amorphous silicon film is formed by using the plasma CVD method, a solution containing nickel is held on the amorphous silicon film. Dehydrogenation of this amorphous silicon film (500 ° C, 1 hour)
After that, thermal crystallization (550 ° C., 4 hours) was performed, and further, a laser annealing process for improving crystallization was performed to form a crystalline silicon film. Then, semiconductor layers 902 to 905 were formed by patterning the crystalline silicon film using a photolithography method.

After the formation of the semiconductor layers 902 to 905, the semiconductor layers 90 to 905 are controlled to control the threshold value of the TFT.
2 to 905 may be doped with a trace amount of an impurity element (boron or phosphorus).

When a crystalline semiconductor film is formed by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, or a YVO ₄ laser can be used. In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly condensed by an optical system and irradiated on a semiconductor film. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is set to 300 Hz, and the laser energy density is set to 100 to 4.
00 mJ / cm ² (typically 200 to 300 mJ / cm
² ). When a YAG laser is used, its second harmonic is used and a pulse oscillation frequency of 30 to 300 kHz is used.
And a laser energy density of 300 to 600 mJ /
cm ² (typically 350 to 500 mJ / cm ² ). And a width of 100 to 1000 μm, for example 400 μ
The laser light condensed linearly at m may be irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser light at this time may be set to 50 to 90%.

Next, a gate insulating film 906 covering the semiconductor layers 902 to 905 is formed. The gate insulating film 906 is formed by a plasma CVD method or a sputtering method and has a thickness of 40 to
The insulating film containing silicon is formed to have a thickness of 150 nm. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N =
7%, H = 2%). Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

When a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) is used by a plasma CVD method.
And O ₂ , a reaction pressure of 40 Pa and a substrate temperature of 300
It can be formed by discharging at a high-frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm ² . The silicon oxide film thus manufactured can obtain favorable characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.

Then, a heat-resistant conductive layer 907 for forming a gate electrode on the gate insulating film 906 is
It is formed with a thickness of 0 nm (preferably 250 to 350 nm). The heat-resistant conductive layer 907 may be formed as a single layer,
If necessary, a laminated structure including a plurality of layers such as two layers or three layers may be employed. Ta, T for the heat-resistant conductive layer
It includes an element selected from i and W, an alloy containing the above element, or an alloy film combining the above elements. These heat-resistant conductive layers are formed by a sputtering method or a CVD method, and it is preferable to reduce the impurity concentration to reduce the resistance, and it is particularly preferable that the oxygen concentration be 30 ppm or less. In this embodiment, the W film is 3
It is formed with a thickness of 00 nm. The W film may be formed by a sputtering method using W as a target, or may be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, it is necessary to lower the resistance in order to use it as a gate electrode, and the resistivity of the W film is 20 μΩc.
m or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when there are many impurity elements such as oxygen in W, the crystallization is inhibited and the resistance is increased. Therefore, in the case of the sputtering method, a W target having a purity of 99.9 to 99.9999% should be used, and a W film should be formed with sufficient care so as not to mix impurities from the gas phase during film formation. Depending on the resistivity 9-20
μΩcm can be realized.

On the other hand, when a Ta film is used for the heat-resistant conductive layer 907, it can be formed by a sputtering method in the same manner. The Ta film uses Ar as a sputtering gas. Also, if an appropriate amount of Xe or Kr is added to the gas during sputtering,
The internal stress of the film to be formed can be relaxed to prevent the film from peeling. The resistivity of the α-phase Ta film is about 20 μΩcm and can be used for the gate electrode.
The resistivity of the a-film was about 180 μΩcm, and was not suitable for use as a gate electrode. Since the TaN film has a crystal structure close to the α phase, if the TaN film is formed under the Ta film,
A phase Ta film is easily obtained. Although not shown, it is effective to form a silicon film doped with phosphorus (P) with a thickness of about 2 to 20 nm under the heat-resistant conductive layer 907. Thereby, the adhesion of the conductive film formed thereon is improved and oxidation is prevented, and at the same time, the heat-resistant conductive layer 90 is formed.
7 and 908 can be prevented from diffusing into the first shape gate insulating film 906 in a small amount. In any case, the heat-resistant conductive layer 907 preferably has a resistivity in the range of 10 to 50 μΩcm.

In this embodiment, a TaN film is formed on the first conductive layer (first conductive film 907), and a W film is formed on the second conductive layer (second conductive film 908) (FIG. 3).
(A)).

Next, a resist mask 909 is formed by using the photolithography technique. And
A first etching process is performed. The first etching process is performed under the first etching condition and the second etching condition.

[0049] using an ICP etching apparatus in this embodiment, using Cl ₂ and CF ₄ O ₂ as etching gas, the gas flow rate is set to 25/25/10, 3.2 W / cm ² at a pressure of 1Pa The RF (13.56 MHz) power is supplied to form plasma. 224 mW / cm ² RF (13.56 MHz) also on the substrate side (sample stage)
Power is applied, thereby applying a substantially negative self-bias voltage. The W film is etched under the first etching condition. Subsequently, without removing the resist mask, the etching conditions were changed to the second etching conditions, and CF ₄ and Cl ₂ were used as etching gases, and the respective gas flow ratios were set to 30/30 (SCCM), and the pressure was set to 1 Pa. In RF (13.56
MHz) by applying power to form plasma. 20 W RF (13.56 MH) also on the substrate side (sample stage)
z) Turn on the power and apply a substantially negative self-bias voltage.

By the first etching process, the conductive layers 910 to 913 having the first tapered shape (the first conductive films 910 a to 913 a having the first tapered shape and the second conductive films 910 b to 910 b having the first tapered shape) are formed. 913b) is formed. The angles of the tapered portions of the conductive layers 910 to 913 are formed to be 15 to 30 degrees. In order to perform etching without leaving a residue, over-etching is performed to increase the etching time at a rate of about 10 to 20%. Since the selectivity of the silicon oxynitride film (gate insulating film 906) to the W film is 2 to 4 (typically 3), the exposed surface of the silicon oxynitride film is etched by about 20 to 50 nm by the over-etching process. (FIG. 3B).

Then, a first doping process is performed to add an impurity element of one conductivity type to the semiconductor layer. Here, a step of adding an impurity element for imparting n-type without removing the resist mask 909 is performed. Semiconductor layers 902 to 90
5, conductive films 910 to 9 having the first tapered shape
13 is used as a mask to add impurities in a self-aligned manner.
N-type impurity regions 914 to 917 are formed. An element belonging to group 15 of the group 15, typically phosphorus (P) or arsenic (As) is used as the impurity element imparting n-type conductivity. Here, phosphorus (P) is used, and the first n-type impurity is doped by ion doping. 1 × 10 ²⁰ to 1 × 10 ²¹ a in the regions 914 to 917
An impurity element imparting n-type is added in a concentration range of toms / cm ³ (FIG. 3B).

Next, a second etching process is performed without removing the resist mask. The second etching is performed under the third etching condition and the fourth etching condition. The second etching process is also performed by an ICP etching apparatus in the same manner as the first etching process, using CF ₄ and Cl ₂ as an etching gas, setting the respective gas flow ratios to 30/30 sccm, and applying RF (1) at a pressure of 1 Pa.
(3.56 MHz) power is supplied to form plasma. 20W RF (13.
56 MHz), and a substantially negative self-bias voltage is applied. With this third etching condition, W
The conductive films 918 to 921 (918a to 921a and 918b to
921b) (FIG. 3C).

Thereafter, the mask made of resist is used as it is, and the fourth etching condition is used. A mixed gas of CF ₄ , Cl ₂ and O ₂ is used as an etching gas, and RF power (13.56 MHz) is applied at a pressure of 1 Pa. ) Power is applied to form plasma. 20 on the substrate side (sample stage)
Apply RF (13.56 MHz) power of W and apply a substantially negative self-bias voltage. The W film is etched under the fourth etching condition to form the second shape conductive film 9.
22-925 (922a-925a and 922b-9)
25b) (FIG. 3D).

Next, a second doping step (addition of an n-type impurity element to the semiconductor layer via the first conductive films 922a to 925a of the second shape) is performed, and the first n-type impurity regions 914 to 917 are formed. And second n-type impurity regions 926 to 929 are formed on the side of the channel formation region in contact with. The second n
The impurity concentration in the type impurity region is 1 × 10 ¹⁶ to 1 ×
It is set to 10 ¹⁹ atoms / cm ³ . This second
In the doping step, the conditions are such that the n-type impurity element is added to the semiconductor layer even through the tapered portions of the first-layer second-shape conductive films 922a to 925a. First-layer second-shape conductive film 9
The second n-type impurity region overlapping with 22a to 925a is Lov
A region (ov means overlapped) and a second n-type impurity region which does not overlap with the first-layer second shape conductive films 922a to 925a are referred to as Loff (off means offset). (FIG. 4A).

Next, as shown in FIG.
Semiconductor layers 902 and 90 to be active layers of channel type TFT
5 has an impurity region 932 (93) having a conductivity type opposite to the one conductivity type.
2a, 932b) and 933 (9323a, 933b)
To form Also in this case, the second shape conductive layers 922 and 9
Using p as a mask, an impurity element imparting p-type is added to form an impurity region in a self-aligned manner. At this time, a semiconductor layer 903 to be an active layer of a later n-channel TFT,
In step 904, masks 930 and 931 made of resist are formed and the entire surface is covered. The p-type impurity regions 932 and 933 formed here are formed by ion doping using diborane (B ₂ H ₆ ), and the concentration of the p-type impurity element in the p-type impurity regions 932 and 933 is 2 × 10 ^{20 to} 2 ×
It is set to 10 ²¹ atoms / cm ³ .

The p-type impurity regions 932 and 933 contain an n-type impurity element in detail, and the concentration of the p-type impurity element in these impurity regions 932 and 933 is n-type. Of the concentration of the impurity element that imparts
Since the p-type impurity region functions as the source region and the drain region of the p-channel TFT by being added so as to be 5 to 3 times, there is no problem.

Thereafter, as shown in FIG. 4C, a first interlayer insulating film 934 is formed on the conductive layers 922 to 925 having the second shape and the gate insulating film 906. The first interlayer insulating film 934 may be formed using a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a stacked film obtained by combining these. In any case, the first interlayer insulating film 934 is formed from an inorganic insulating material. The thickness of the first interlayer insulating film 934 is 100 to 200 nm. In the case where a silicon oxide film is used as the first interlayer insulating film 934,
TEOS and O ₂ are mixed by the plasma CVD method, the reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C., and the high frequency (13.56 MHz) power density is 0.5 to 0.8 W / cm.
² can be formed by discharging. In the case where a silicon oxynitride film is used as the first interlayer insulating film 934, a silicon oxynitride film manufactured from SiH ₄ , N ₂ O, NH ₃ by a plasma CVD method, or SiH ₄ , N ₂ O
May be formed using a silicon oxynitride film formed from the above.
The manufacturing conditions in this case are a reaction pressure of 20 to 200 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (60 MHz) power density of 0.1 to 1.0 W / cm ² . Further, as the first interlayer insulating film 934, SiH ₄ , N ₂
A silicon oxynitride hydride film formed from O and H ₂ may be used. Similarly for silicon nitride film, plasma CVD
It can be produced from SiH ₄ and NH _{3 by the} method.

Then, a step of activating the impurity elements imparting n-type or p-type added at the respective concentrations is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, the oxygen concentration is 1 ppm or less,
Preferably in a nitrogen atmosphere of 0.1 ppm or less 400 ~
The heat treatment is performed at 700 ° C., typically 500 to 600 ° C. In this embodiment, the heat treatment is performed at 550 ° C. for 4 hours.
When a plastic substrate having a low heat-resistant temperature is used as the substrate 900, a laser annealing method is preferably applied.

In this heat treatment step, the catalyst element (nickel) used in the step of crystallizing the semiconductor layer is a highly concentrated element (phosphorus in this embodiment) belonging to Group 15 of the periodic table having a gettering action. By moving (gettering) to the added first n-type impurity region, the concentration of the catalyst element in the channel formation region can be reduced.

Following the activation step, the atmosphere gas is changed
And in an atmosphere containing 3 to 100% hydrogen,
Heat treatment is performed at 450 ° C. for 1 to 12 hours, and the semiconductor layer is
Performing a quenching step. This process involves thermally excited hydrogen
10 in the semiconductor layer¹⁶-10¹⁸/ Cm^ThreeThe dang
This is the step of terminating the ring bond. Other means of hydrogenation
As plasma hydrogenation (water excited by plasma
Element). In any case, semiconductor
The defect density in layers 902-905 is 10¹⁶/ Cm ^ThreeAnd
It is desirable to use hydrogen for 0.01 to 0.
What is necessary is just to give about 1 atomic%.

Then, a second interlayer insulating film 935 made of an inorganic insulating material is formed with an average thickness of 1.0 to 2.0 μm. As the inorganic insulating material, a silicon oxide film or a silicon oxynitride film is formed by a known sputtering method or plasma C method.
What is necessary is just to form using a VD method. Further, when a silicon nitride oxide film is used, the film forming conditions are a pressure of 0.3 torr, a substrate temperature of 400 ° C., and an RF output of 100 using SiH ₄ and N ₂ O as source gases by a plasma CVD apparatus.
W, source gas flow rate is ₄ sccm for SiH ₄ , and 40 for N ₂ O.
It may be formed at 0 sccm.

Next, CMP (Chemical Mechanical Po
Polishing and flattening the interlayer insulating film by a technique called lish (chemical mechanical polishing) method. The CMP method is a method of flattening the surface chemically or mechanically based on the surface of the workpiece. Generally, a platen (Platen or Polishin
g Plate) on which a polishing cloth or polishing pad (hereinafter, collectively referred to as a pad (Pad)) is attached,
The platen and the workpiece are rotated or rocked while supplying the slurry between the workpiece and the pad, and the surface of the workpiece is polished by a combined chemical and mechanical action. Is the way. In this embodiment, the second interlayer insulating film 93 is used.
After the formation of No. 5, the second interlayer insulating film 935 is polished by the CMP method. Known slurry, pad, CMP apparatus, etc. used for the CMP method can be used,
In addition, a polishing method can be performed using a known method. After the planarization process by the CMP method is completed, the average thickness of the second interlayer insulating film 935 is 1.0 to 2.0.
It should be about 0 μm. As shown in FIG. 17, an insulating film 935B made of a silicon nitride film or a DLC film may be provided over the planarized second interlayer insulating film 935. By forming the insulating film 935B in this manner, it is considered that an alkali metal used for forming a light-emitting element can be prevented from entering the TFT through the interlayer insulating film.

Thereafter, a resist mask having a predetermined pattern is formed, and contact holes are formed in the respective semiconductor layers and reach the impurity regions serving as the source region or the drain region. The contact hole is formed by a dry etching method.

Then, a conductive metal film is formed by a sputtering method or a vacuum evaporation method, patterned by a mask, and then etched to form wirings 936 to 942.
Although not shown, in this embodiment, this wiring is formed to a thickness of 50 n.
An alloy film (alloy film of Al and Ti) having a thickness of 500 nm and an alloy film having a thickness of 500 nm was formed.

Next, a transparent conductive film was placed on the
An anode 943 (pixel electrode) is formed by forming a film with a thickness of 20 nm and etching (FIG. 5A). In this embodiment, an indium tin oxide (ITO) film or a transparent conductive film obtained by mixing 2 to 20% of zinc oxide (ZnO) with indium oxide is used as a transparent electrode.

The anode 943 is connected to the drain wiring 942
Current control TFT by overlapping and forming
An electrical connection is formed with the drain region of FIG.
(A)). Here, 180 to 350 with respect to the anode 943.
The heat treatment may be performed at ° C.

Next, as shown in FIG.
A third interlayer insulating film 944 is formed on the third insulating film 3. Here, a processing room (clean room) may be moved to form a light-emitting element. The third interlayer insulating film 944 is used to prevent the TFT substrate from being contaminated by dust in the air or broken.
An extremely thin film 945 having an antistatic effect (hereinafter, referred to as an antistatic film) is formed thereon. The antistatic film 945 is formed from a material that can be removed by washing with water (FIG. 5C).

For the antistatic film, a resin insulating film for forming the bank, a material which can be easily removed without affecting the anode and the wiring is used. As such a material, a material having a degree of conductivity (10 −8 S / m) required for antistatic is suitable. Generally, an organic conductor is used, and a conductive polymer is formed by a spin coating method and a conductive low molecule is formed by a vapor deposition method or the like. Specifically, polyethylene dioxythiophene (abbreviation: PEDOT), polyaniline (abbreviation: PA)
ni), glycerin fatty acid ester, polyoxyethylene alkyl ether, polyoxyethylene alkyl phenyl ether, N, N-bis (2-hydroxyethyl) alkylamine [alkyldiethanolamine], N-2-hydroxyethyl-N-2-hydroxyalkyl Amine [hydroxyalkyl monoethanolamine], polyoxyethylene alkylamine, polyoxyethylene alkylamine fatty acid ester, alkyl diethanol amide, alkyl sulfonate, alkyl benzene sulfonate,
Alkyl phosphates, tetraalkylammonium salts, trialkylbenzylammonium salts, alkyl betaines, alkyl imidazolium betaines and the like can be mentioned. These materials can be easily removed with water or an organic solvent. Further, insulating materials, such as polyimide,
Organic insulators such as acryl, polyamide, polyimide amide, and BCB (benzocyclobutene) can also be used as the antistatic film. These antistatic films are applicable to all embodiments.

When the TFT substrate is carried into a processing room (clean room) for forming a light emitting element, an antistatic film 945 is formed.
Is removed by washing with water, and the third interlayer insulating film 944 is etched to form a bank 946 having an opening at a position corresponding to the pixel (light emitting element). In this embodiment, a bank 946 is formed using a resist. In this embodiment, the thickness of the bank 946 is about 1 μm, and the bank 946 is formed so that a region covering a portion where the wiring and the anode are in contact is tapered (FIG. 6A).

In this embodiment, the bank 946 is used.
Is used, a polyimide film, a polyamide film, an acrylic film, BCB (benzocyclobutene), a silicon oxide film, or the like may be used in some cases. The bank 946 may be an organic substance or an inorganic substance as long as the substance has an insulating property. Note that when the bank 946 is formed using photosensitive acrylic, it is preferable to perform heat treatment at 180 to 350 ° C. after etching the photosensitive acrylic film. In the case of using a non-photosensitive acrylic film, it is preferable to form a bank by performing heat treatment at 180 to 350 ° C. and then etching.

Next, a wiping treatment is performed on the anode surface. In addition,
In this embodiment, the surface of the anode 943 is wiped off with the use of Berglin (manufactured by Ozu Sangyo), thereby flattening the surface of the anode 943 and removing dust adhering to the surface. Pure water is used as the cleaning liquid at the time of wiping, the rotation speed of the shaft around which the berclin is wound is 100 to 300 rpm, and the indentation value is 0.1 to 1.0 mm (FIG. 6A).

Next, an insulating film 947 is formed to cover the bank 946 and the anode 943. The insulating film 947 is formed using an organic resin film of polyimide, polyamide, polyimide amide, or the like with a thickness of 1 to 5 nm by a spin coating method, an evaporation method, a sputtering method, or the like. By forming this insulating film, cracks and the like on the surface of the anode 943 can be covered, and deterioration of the light-emitting element can be prevented.

Next, the organic compound layer 94 is formed on the insulating film 947.
8. A cathode 949 is formed by a vapor deposition method. Although a MgAg electrode is used as the cathode 949 of the light emitting element in this embodiment, other known materials may be used. Note that the organic compound layer 948 includes a hole injection layer, a hole transport layer,
It is formed by combining and laminating a plurality of layers such as an electron transport layer, an electron injection layer, and a buffer layer. The structure of the organic compound layer used in this example will be described in detail below.

In this embodiment, copper phthalocyanine is used as the hole injecting layer, and α-NPD is used as the hole transporting layer, and these are formed by vapor deposition.

Next, a light emitting layer is formed. In this embodiment, an organic compound layer which emits different light is formed by using different materials for the light emitting layer. In this embodiment, red,
An organic compound layer which emits green and blue light is formed. Also,
Since a vapor deposition method is used for all of the film formation methods, it is possible to form a light emitting layer using a different material for each pixel by using a metal mask during film formation.

The light emitting layer that emits red light is formed by adding DC to Alq ₃ .
It is formed using a material doped with M. In addition, Eu complex with N, N'-disalicylidene-1,6-hexanediaminato) zinc (II) (Zn (salhn))
(1,10-phenanthroline) tris (1,3-diphenyl-
Propane-1,3-dionato) Europium (III) (Eu
A material doped with (DBM) ₃ (Phen) or the like can be used, but other known materials can also be used.

The light emitting layer that emits green light can be formed by co-evaporation of CBP and Ir (ppy) ₃ . At this time, it is preferable that the hole blocking layer is laminated using BCP. In addition, aluminum quinolinolato complex (Alq ₃ ) and benzoquinolinolato beryllium complex (BeBq) can be used. Further, quinolinato aluminum complex (Alq ₃ ) using a material such as coumarin 6 or quinacridone as a dopant is also possible, but other known materials can also be used.

Further, the light emitting layer that emits blue light is composed of DPVBi, a distyryl derivative, and N, N'-disalicylidene-1, a zinc complex having an azomethine compound as a ligand.
6-hexanediaminato) zinc (II) (Zn (sal
hn)) and 4,4'-bis (2,2-diphenyl-vinyl)-
Although biphenyl (DPVBi) obtained by doping perylene can be used, other known materials may be used.

Next, an electron transport layer is formed. Note that a material such as a 1,3,4-oxadiazole derivative or a 1,2,4-triazole derivative (TAZ) can be used for the electron transporting layer; however, in this embodiment, 1,2,4- 30 by vapor deposition using a triazole derivative (TAZ)
It is formed with a thickness of about 60 nm.

As described above, an organic compound layer having a laminated structure is formed. Note that the thickness of the organic compound layer 948 in this embodiment is 10 to 400 nm (typically 60 to 1 nm).
The thickness of the cathode 949 may be 80 to 200 nm (typically 100 to 150 nm).

After forming the organic compound layer, the cathode 949 of the light emitting element is formed by a vapor deposition method. In this embodiment, MgAg is used as the conductive film serving as the cathode of the light-emitting element. However, an Al—Li alloy film (an alloy film of aluminum and lithium) or an element belonging to Group 1 or 2 of the periodic table and aluminum are used. It is also possible to use a film formed by a co-evaporation method.

Thus, a light emitting device having a structure as shown in FIG. 6B is completed. The anode 943 and the organic compound layer 9
The portion 950 laminated with the cathode 48 and the cathode 949 is called a light emitting element.

The p-channel TFT 1000 and the n-channel TFT 1001 are the TFTs of the drive circuit 1004 and form a CMOS. Switching TFT1
002 and the current control TFT 1003 are TFTs in the pixel portion.
The TFT of the driver circuit and the TFT of the pixel portion 1005 can be formed over the same substrate.

In the case of a light emitting device using a light emitting element,
The voltage of the power supply of the drive circuit is about 5-6V, and the maximum is 10V
Since the degree is sufficient, deterioration due to hot electrons in the TFT does not cause much problem.

(Embodiment 2) Another example of a process for manufacturing a light emitting device which is different from that of Embodiment 1 will be described with reference to FIGS.

According to the first embodiment, the steps up to the step of forming two layers of conductive films 907 and 908 on the gate insulating film 906 as shown in FIG.

Subsequently, the conductive films 907 and 908 are etched using the masks 909a to 909d to form the first tapered conductive layers 3901 to 3904 (3901a to 3901).
04a and 3901b to 3904b). ICP (Inductively Coupled Pl)
(asma: inductively coupled plasma) etching method is used. The etching gas is not limited, but CF ₄ , Cl _2, and O ₂ are used for etching the W film and the tantalum nitride film. Each gas flow rate is 25/25/10 sccm, and 1 Pa
500W RF (13.56
MHz) power is applied to perform etching. in this case,
The substrate side (sample stage) also has a 150 W RF (13.5
6 MHz) power is applied and a substantially negative self-bias voltage is applied. Due to the first etching condition, mainly W
The film is etched into a predetermined shape.

Thereafter, the etching gases are CF ₄ and Cl ₂
And the respective gas flow rate ratios are 30/30 sccm
And 500 W of RF to the coil-type electrode at a pressure of 1 Pa
(13.56 MHz) Power is supplied to generate plasma, and etching is performed for about 30 seconds. A 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. CF
The mixed gas of ₄ and Cl ₂ etches the tantalum nitride film and the W film at substantially the same rate. Thus, the conductive layers 3901 to 3904 having the first tapered shape are formed. The taper is formed at 45 to 75 °. In order to perform etching without leaving a residue on the second insulating film, 10 to 20%
It is preferable to increase the etching time at a ratio of about. Note that the first tapered conductive layer 3 of the gate insulating film 906 is used.
The area surface not covered by 901 to 3904 is 20 to 50 n
A region thinned by etching by about m is formed (FIG. 19A).

Subsequently, a second etching process is performed as shown in FIG. 19B without removing the masks 909a to 909d. Using CF ₄ , Cl ₂ and O _{2 as} etching gas,
Each gas flow ratio was set to 20/20/20 sccm, and 500 W RF was applied to the coil type electrode at a pressure of 1 Pa.
(13.56 MHz) Power is supplied to generate plasma to perform etching. 20 on the substrate side (sample stage)
RF (13.56 MHz) power of W is applied, and a lower self-bias voltage is applied than in the first etching process.
Under this etching condition, W used as the second conductive film
Etch the film. Thus, the second tapered conductive layers 3905 to 3908 (composed of 3905a to 3908a and 3905b to 3908b) are formed. Second tapered conductive layer 3905 of gate insulating film 906
The surface of the region not covered with 3908 is etched to a thickness of about 20 to 50 nm and becomes thin.

After removing the resist mask, a first doping process for adding an impurity element imparting n-type (n-type impurity element) to the semiconductor layer is performed. The first doping process is performed by an ion doping method in which ions are implanted without performing mass separation. Doping is performed on the second tapered electrode 3
Using 905 to 3908 as a mask, a phosphine (PH ₃ ) gas diluted with hydrogen or a phosphine gas diluted with a rare gas is used, and an n-type impurity region containing a first concentration of an n-type impurity element is formed in the semiconductor films 902 to 905. 3909-3
912 is formed. The first formed by this doping
-Type impurity region 3909 containing n-type impurity element at a concentration of
The phosphorus concentration of ３９3912 is 1 × 10 ¹⁶ -1 × 10 ¹⁷ / cm
^{It is set to 3} (FIG. 19C).

After that, the first masks 3913 and 3915 covering the whole of the semiconductor layers 902 and 905 and the semiconductor layer 904
Upper second tapered conductive layer 3907 and semiconductor layer 90
Forming a second mask 3914 covering a part of the region 4;
A second doping process is performed. In the second doping treatment, an n-type impurity region 3917 containing a second concentration of an n-type impurity element and an n-type impurity region 3917 containing a third concentration of an n-type impurity element are formed in the semiconductor layer 903 through the second tapered conductive layer 3906a. Form impurity regions 3916 and 3918 are formed. The phosphorus concentration of the n-type impurity region 3917 including the second concentration of the n-type impurity element formed by this doping is 1 × 10 ¹⁷ to
The phosphorus concentration of the n-type impurity regions 3916 and 3918 containing the n-type impurity element at 1 × 10 ¹⁹ / cm ³ and the third concentration is 1 × 10 ¹⁹ / cm ³ .
It should be 10 ²⁰ -1 × 10 ²¹ / cm ³ (FIG. 19
(D)).

In this embodiment, as described above, in one doping step, the n-type impurity region containing the second concentration n-type impurity element and the n-type impurity region containing the third concentration n-type impurity element are formed. Although the impurity region is formed, the impurity element may be added in two doping steps.

Subsequently, as shown in FIG. 20A, masks 3919 and 3920 covering the semiconductor layers 903 and 904 are formed, and a third doping process is performed. For doping, diborane (B ₂ H ₆ ) gas diluted with hydrogen or diborane gas diluted with a rare gas is used, and p-type impurity regions 3921 and 3921 containing a first concentration of a p-type impurity element are added to the semiconductor layers 902 and 905.
923 and p-type impurity regions 3922 and 3924 containing the second concentration of the p-type impurity element are formed. First concentration of p
-Type impurity regions 3921 and 3923 containing a p-type impurity element
Contains boron in the concentration range of 2 × 10 ^{20 to} 3 × 10 ²¹ / cm ³ , and the p-type impurity regions 3922 and 3924 containing the second concentration of the p-type impurity element are formed in the second tapered conductive layer. It is formed in a region overlapping with 3905a and 3908a, and contains boron in a concentration range of 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ .

Next, as shown in FIG. 20B, a first interlayer insulating film 3925 made of a silicon nitride film or a silicon oxynitride film is formed to a thickness of 50 nm by a plasma CVD method. In order to activate the added impurity element, heat treatment is performed at 410 ° C. using a furnace. In this heat treatment, the semiconductor film is also hydrogenated with hydrogen released from the silicon nitride film or the silicon nitride oxide film.

The heat treatment may be a heat treatment method using RTA (including an RTA method using gas or light as a heat source) other than the method using a furnace. In the case of performing heat treatment using a furnace, an insulating film which covers the gate electrode and the gate insulating film is formed before the heat treatment in order to prevent oxidation of a conductive film which forms the gate electrode, or an atmosphere during the heat treatment is used. A reduced pressure nitrogen atmosphere may be used. Alternatively, the semiconductor film may be irradiated with light of the second harmonic (532 nm) of a YAG laser. As described above, since there are several methods for activating the impurity element added to the semiconductor layer, the method may be appropriately determined by a practitioner.

Next, a second interlayer insulating film 3926 is formed on the first interlayer insulating film 3925 using an inorganic insulating material.
As the inorganic insulating material, a silicon oxide film or a silicon oxynitride film may be formed by a known sputtering method, a plasma CVD method, or the like. Then, the second interlayer insulating film 3926 is polished and flattened by the CMP method. In addition, after planarization by polishing by the CMP method, the average film thickness is 1.0 to 2.0 μm.
m. Subsequently, a DLC film or a silicon nitride film may be formed as the first insulating film 3927 over the planarized second interlayer insulating film 3926. By forming the first insulating film 3927 in this manner, it is possible to prevent the alkali metal used for forming the light-emitting element from passing through the interlayer insulating film and entering the TFT side, thereby preventing the TFT element from being deteriorated. It is considered possible (FIG. 20C).

Subsequently, a transparent conductive film is formed with a thickness of 80 to 120 nm on the barrier insulating film 3927, and the anode 3928 is formed by etching.
(A)). In the present embodiment, an indium tin oxide (ITO) film or indium oxide was
A transparent conductive film mixed with 0% zinc oxide (ZnO) is used.

Thereafter, a resist mask having a predetermined pattern is formed, and impurity regions 3916 and 391 serving as source regions or drain regions formed in the respective semiconductor layers are formed.
8, 3921, and a contact hole reaching 3923 are formed. The contact hole may be formed by a dry etching method.

Then, a conductive metal film is formed by a sputtering method or a vacuum evaporation method, patterned by a mask, and then etched to form wirings 3929 to 3935. Although not shown, in this embodiment, this wiring is formed of a laminated film of a 50 nm-thick Ti film and a 500 nm-thick alloy film (an alloy film of Al and Ti).

Next, the anode 3928 and the wiring 3929
The third interlayer insulating film 3936 covering the layers 3935 to 3935 is formed. As the third interlayer insulating film 3936, a film made of a resist, polyimide, polyamide, acrylic, or BCB (benzocyclobutene). Any substance having an insulating property such as a silicon oxide film can be used regardless of an organic substance or an inorganic substance. Here, Al used as a cathode material of the light emitting element,
In order to reduce the risk of alkali metal being mixed into the active layer of the TFT from an alkali metal material such as Mg,
When the substrate is moved from a processing chamber for forming a TFT substrate (hereinafter, referred to as a first clean room) to a processing chamber for forming a light-emitting element (hereinafter, referred to as a second clean room) and a manufacturing process is performed. Is assumed.

An ultra-thin film having an antistatic effect (hereinafter, referred to as a thin film) is formed on the third interlayer insulating film 3936 so that the TFT substrate is not contaminated by dust in the air while moving or does not cause electrostatic breakdown due to static electricity. 3937 (referred to as an antistatic film) is formed. Note that the antistatic film 3937 may be formed using a material that can be easily removed, such as washing with water (FIG. 21A).
Alternatively, the semiconductor device is stored and moved in a case where damage due to electrification can be prevented. Note that an inspection of the operation of the TFT substrate formed in the steps up to here may be performed before the movement of the processing chamber. The above process is a process in the first processing chamber (clean room) shown in the flowchart of FIG.

The transfer from the first processing chamber to the second processing chamber may be performed, for example, in a building provided on the same site or in a factory (processing room, for example, a clean room) where the same corporation is interspersed. Movement between plants, or movement of a factory (processing room, for example, a clean room) by different legal persons is conceivable. In any case, the TFT substrate is moved so as not to damage the TFT substrate.

Subsequently, the processing in the second processing room (clean room) shown in the flowchart of FIG. 18 is performed. TFT
When the substrate is carried into the second processing room (clean room), the antistatic film 3937 is removed by washing with water, the third interlayer insulating film 3936 is etched, and the pixel (light emitting element) is removed.
Has an opening at a position corresponding to the wiring 3934 and the anode 3
A bank 3938 is formed so as to cover a portion in contact with 928 and an end of the anode 3928 in a tapered shape. In this embodiment, the thickness is about 1 μm, and the bank 3938 is formed using a resist. Here, the TF moved to the second processing chamber again
An inspection for confirming the operation of the T substrate may be performed.

Subsequently, in order to suppress the deterioration of the light emitting element due to the generation of moisture or gas from the bank 3938, the bank 3
The surface of 938 is covered with a second insulating film 3939 with, for example, a silicon nitride film. This second insulating film 3939 is also referred to as a second barrier insulating film 3939 because it is an insulating film for protecting the light-emitting element from moisture or gas which causes deterioration.

Subsequently, an organic compound layer 3940 is formed on the second insulating film 3939 so as to be in contact with the anode 3928, and a cathode 3941 is formed on the organic compound layer 3940 by an evaporation method. In this embodiment, MgAg is used as the cathode of the light emitting element.
Although an electrode is used, another known material may be used. Note that the organic compound layer 3940 may be stacked in combination with a plurality of layers such as a hole-injection layer, a hole-transport layer, an electron-transport layer, an electron-injection layer, and a buffer layer, in addition to the light-emitting layer.
In this embodiment, it may be formed according to the first embodiment.

Thus, a light emitting device having a structure as shown in FIG. 21B is completed. Note that a portion 3942 in which the anode 3928, the organic compound layer 3940, and the cathode 3941 are stacked is referred to as a light-emitting element.

As described above, the first method for forming the TFT substrate is as follows.
The processing chamber (for example, the first clean room) and the second processing chamber (for example, the second clean room) for forming the light emitting element are different from each other, so that Al, Mg, etc. The active layer of the TFT can be protected from an alkali metal material, and a favorable light emitting device can be provided.

(Embodiment 3) An example in which the surface of the bank 946 is modified by subjecting the surface of the bank 946 to plasma treatment after forming the bank 946 according to the process of the embodiment 1 will be described with reference to FIG.

Although the bank 946 is formed using an organic resin insulating film, it generates moisture and gas, and is likely to generate moisture and gas by heat generated when the light emitting device is actually used. Problem.

Then, after performing the heat treatment, a plasma treatment is performed to modify the surface of the bank 946 as shown in FIG. Plasma treatment is performed in one or more kinds of gases selected from hydrogen, nitrogen, halogenated carbon, hydrogen fluoride, and a rare gas.

As a result, the surface of the bank 946 is densified to form a cured film containing one or more kinds of gas elements selected from hydrogen, nitrogen, carbon halide, hydrogen fluoride, and a rare gas. Generation of gas (oxygen) can be prevented, and deterioration of the light-emitting element can be prevented.

This embodiment can be used in combination with the embodiment and the first and second embodiments.

(Embodiment 4) In this embodiment, the structure of a CMP apparatus used for polishing by the CMP method will be described.

FIG. 11 is a side view of the CMP apparatus of this embodiment.
FIG. 11A is a perspective view of FIG. Reference numeral 1701 denotes a surface plate, which is driven by a drive shaft (a) 1702 in the direction of the arrow.
Or rotate in the opposite direction. Drive shaft (a) 170
The position of 2 is fixed by an arm (a) 703.

A known polishing cloth or pad can be used as the pad 1704 in which the pad 704 is provided on the surface plate 1701. A slurry supply nozzle 1705 for supplying slurry to the pad 1704 is provided. In this embodiment, the slurry is supplied to the slurry supply nozzle 170.
5 to slurry supply position 1 at the center of pad 1704
710. Known materials can be used for the slurry.

Reference numeral 1706 denotes a carrier, which has a function of fixing the active matrix substrate 1707 and rotating it on the pad 1704. The carrier 1706 is rotated by the drive shaft (b) 1708 in the direction of the arrow or in the opposite direction. The drive shaft (b) 708 is the arm (b) 1
The position is fixed by 709.

Note that the surface of the active matrix substrate 1707 on which the insulating film serving as a flattening film is formed
It is held so as to face the 04 side.

Although not provided in the present embodiment, when a polishing cloth is used for the pad 1704, deformation of the polishing cloth at the edge of the active matrix substrate can be suppressed by providing a pad pressure ring. 1.2 times to 1.6 times the polishing pressure of the active matrix substrate 1707
When double the pressure is applied to the pad pressure ring, the surface profile of the polishing cloth changes, resulting in a uniform polishing cloth deformation.

FIG. 12 shows the carrier 1706 shown in FIG.
FIG. The carrier 1706 has a polishing housing 1711, a wafer chuck 1713, and a retainer ring 1712. The wafer chuck 1713 holds the active matrix substrate 1707, and the retainer ring 1712 holds the active matrix substrate 1701.
7 is prevented from coming off during polishing. The polishing housing 1711 includes the wafer chuck 1713 and the retainer ring 1.
712 and a function of applying a polishing pressure.

Since the carrier 1707 needs the functions of pressurization and rotation, it is common practice to have a rotation axis at the center and apply a load along this axis. In the case of the central axis load, the distribution of the load in the plane of the active matrix substrate is highest below the central axis, and it is inevitable that the load decreases toward the periphery. For this purpose, a known auxiliary load mechanism may be incorporated in the polishing housing to uniformly polish the active matrix substrate in the plane.

The CMP method shown in this embodiment is the same as that of the embodiment,
It can be used in combination with Examples 1-3.

Embodiment 5 In FIG. 16A, the substrate 1100 is preferably made of barium borosilicate glass, aluminoborosilicate glass, quartz, or the like. A base insulating film 1101 is provided on the surface of the substrate 100.
To form an inorganic insulating film with a thickness of 10 to 200 nm. An example of a suitable base insulating film is a silicon oxynitride film formed by a plasma CVD method, and is preferably made of SiH ₄ , NH ₃ ,
First silicon oxynitride film 1101 made of N ₂ O
a to a thickness of 50 nm and then SiH ₄ and N ₂ O
The second silicon oxynitride film 1101b manufactured from
One formed to a thickness of 00 nm is applied. The base insulating film 1101 is provided so that alkali metal contained in the glass substrate does not diffuse into a semiconductor film formed thereover. The base insulating film 1101 can be omitted when quartz is used as the substrate.

Next, a silicon nitride film 1102 is formed over the base insulating film 1101. The silicon nitride film 102 further contains oxygen contained in the base insulating film 1101 in order to prevent a catalyst element (typically, nickel) used in a later semiconductor film crystallization step from permeating the base insulating film 1101. It is formed for the purpose of preventing adverse effects. Note that the silicon nitride film 1102 is formed by a plasma CVD method.
It may be formed with a thickness of 5 nm.

Next, an amorphous semiconductor film 1103 is formed over the silicon nitride film 1102. Amorphous semiconductor film 1102
Uses a semiconductor material containing silicon as a main component. Typically, an amorphous silicon film or an amorphous silicon germanium film is applied, and a plasma CVD method or a low pressure CVD method is used.
It is formed to a thickness of 10 to 100 nm by a method or a sputtering method. In order to obtain high quality crystals, the amorphous semiconductor film 11
03, the concentration of impurities such as oxygen and nitrogen is 5 × 10
It is good to reduce it to ¹⁸ / cm ³ or less. These impurities are factors that hinder the crystallization of the amorphous semiconductor and increase the density of trapping centers and recombination centers even after crystallization. For this purpose, it is desirable to use not only a high-purity material gas but also an ultra-high vacuum-compatible CVD apparatus provided with a mirror surface treatment (electric polishing treatment) in the reaction chamber and an oil-free vacuum exhaust system. Note that the layers from the base insulating film 1101 to the amorphous semiconductor film 1103 can be formed continuously without being released to the atmosphere.

Thereafter, a metal element having a catalytic action for promoting crystallization is added to the surface of the amorphous silicon film 1103 (FIG. 16B). Examples of metal elements having a catalytic action for promoting crystallization of a semiconductor film include iron (Fe) and nickel (N
i), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (O
s), iridium (Ir), platinum (Pt), copper (C
u), gold (Au), or the like, and one or more selected from them can be used. Typically, nickel is used, and a nickel acetate solution containing 1 to 100 ppm by weight of nickel is applied with a spinner to form the catalyst-containing layer 1104. In this case, as a surface treatment of the amorphous silicon film 1103, an extremely thin oxide film is formed with an aqueous solution containing ozone, and the oxide film is mixed with hydrofluoric acid and a hydrogen peroxide solution in order to improve the familiarity of the solution. To form a clean surface, and then treat again with an ozone-containing aqueous solution to form an extremely thin oxide film. Since the surface of a semiconductor film such as silicon is hydrophobic in nature, a nickel acetate solution can be uniformly applied by forming an oxide film in this manner.

Of course, the catalyst containing layer 1104 is not limited to such a method, and may be formed by a sputtering method, an evaporation method, a plasma treatment, or the like.

[0127] A heat treatment for crystallization is performed while maintaining the state in which the amorphous silicon film 1103 and the catalyst element-containing layer 1104 are in contact with each other. Examples of the heat treatment include furnace annealing using an electric heating furnace and rapid thermal annealing (Halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure mercury lamp, etc.).
g) The method (hereinafter referred to as RTA method) is adopted.

When the RTA method is used, the lamp light source for heating is turned on for 1 to 60 seconds, preferably 30 to 60 seconds.
It is repeated 1 to 10 times, preferably 2 to 6 times. Although the light emission intensity of the lamp light source is arbitrary, the semiconductor film is instantaneously heated to 600 to 1000 ° C., preferably 650 to 75 ° C.
Heat to about 0 ° C. Even at such a high temperature, the semiconductor film is only instantaneously heated, and the substrate 1100 itself is not distorted and deformed. Thus, the amorphous semiconductor film is crystallized, and FIG.
Although a crystalline silicon film 1105 shown in FIG. 6C can be obtained, crystallization by such a process can be achieved only by providing a catalyst element-containing layer.

When the furnace annealing method is used as another method, one hour at 500 ° C. prior to the heat treatment.
A heat treatment for about an hour is performed to form an amorphous silicon film 1103.
The hydrogen contained in is released. Then, using an electric furnace in a nitrogen atmosphere at 550 to 600 ° C., preferably 5 to 600 ° C.
Heat treatment at 80 ° C. for 4 hours to perform amorphous silicon film 11
03 is crystallized. Thus, a crystalline silicon film 1105 shown in FIG. 16C is formed.

In order to further increase the crystallization ratio (the ratio of the crystal component in the total volume of the film) and repair defects remaining in the crystal grains, the crystalline silicon film 1105 may be irradiated with laser light. It is valid.

In the crystalline silicon film 1105 thus obtained, the catalytic element (nickel in this case) remains at an average concentration exceeding 1 × 10 ¹⁹ / cm ³ . If the catalyst element remains, the characteristics of the TFT may be adversely affected, so that the concentration of the catalyst element in the semiconductor layer needs to be reduced. Therefore, a method for reducing the concentration of the catalytic element in the semiconductor layer following the crystallization step will be described.

First, a thin layer 1106 is formed on the surface of the crystalline silicon film 1105 as shown in FIG.
In this specification, a thin layer 1106 provided over a crystalline silicon film 1105 is a layer provided so that the crystalline silicon film 1105 is not etched when a gettering site is removed later. I do.

The thickness of the barrier layer 1106 is about 1 to 10 nm, and a chemical oxide formed by simply treating with ozone water may be used as the barrier layer. Also,
Chemical oxide can be similarly formed by treating with an aqueous solution in which a hydrogen peroxide solution is mixed with sulfuric acid, hydrochloric acid, nitric acid or the like. As another method, the plasma treatment in an oxidizing atmosphere or the oxidation treatment by generating ozone by ultraviolet irradiation in an oxygen-containing atmosphere may be performed. Further, a barrier layer may be formed by heating to about 200 to 350 ° C. using a clean oven to form a thin oxide film. Alternatively, 1 to 5 nm by a plasma CVD method, a sputtering method, an evaporation method, or the like.
An oxide film of a degree may be deposited to form a barrier layer. In any case, in the gettering step, the catalyst element can move to the gettering site side, and in the gettering site removing step, the etchant does not soak (protects the crystalline silicon film 1105 from the etchant). For example, a chemical oxide film, a silicon oxide film (SiOx), or a porous film formed by treatment with ozone water may be used.

Next, a second semiconductor film containing a rare gas element at a concentration of 1 × 10 ²⁰ / cm ³ or more as a gettering site 1107 by sputtering on the barrier layer 1106 (typically, a non- 25-250n
m. The gettering site 1107 to be removed later is preferably formed with a low density in order to increase the etching selectivity with respect to the crystalline silicon film 1105.

Note that the rare gas element itself is inactive in the semiconductor film, and therefore does not adversely affect the crystalline silicon film 1105. As the rare gas element, one or a plurality of helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe) are used. The present invention is characterized in that these rare gas elements are used as an ion source to form a gettering site, and that a semiconductor film containing these elements is formed and this film is used as a gettering site.

In order to surely achieve gettering, it is necessary to perform a heat treatment thereafter. The heat treatment is performed by a furnace annealing method or an RTA method. When the furnace annealing method is used, 450 to 600 ° C. in a nitrogen atmosphere
For 0.5 to 12 hours. When the RTA method is used, a heating lamp light source is used for 1 to 60 seconds.
It is preferably turned on for 30 to 60 seconds, and it is turned on 1 to 10 times,
Preferably, it is repeated 2 to 6 times. The emission intensity of the lamp light source is arbitrary, but the semiconductor film is
The temperature is set to about 000 ° C, preferably about 700 to 750 ° C.

In the gettering, the catalytic element in the region to be gettered (capture site) is released by thermal energy and moves to the gettering site by diffusion. Therefore, gettering depends on the processing temperature, and the higher the temperature, the faster the gettering proceeds. In this gettering step, the distance that the catalyst element moves during gettering is about the thickness of the semiconductor film, and gettering can be completed in a relatively short time (FIG. 1).
6 (e)).

It should be noted that 1 × 10 ¹⁹
１1 × 10 ²¹ / cm ³ , preferably 1 × 10 ²⁰ -1 × 1
The semiconductor film 1107 containing a rare gas element at a concentration of 0 ²¹ / cm ³ , more preferably 5 × 10 ²⁰ / cm ³ does not crystallize. This is considered to be because the rare gas element is not re-emitted even in the above-mentioned processing temperature range and remains in the film to inhibit crystallization of the semiconductor film.

After the end of the gettering step, the gettering sites 1107 are selectively removed by etching. As an etching method, dry etching without plasma using ClF ₃ , hydrazine, tetraethylammonium hydroxide (chemical formula (C
It can be performed by wet etching using an alkaline solution such as an aqueous solution containing H ₃ ) ₄ NOH). At this time, the barrier layer 1106 functions as an etching stopper. The barrier layer 1106 may be removed with hydrofluoric acid thereafter.

Thus, as shown in FIG. 16F, a crystalline silicon film 1108 in which the concentration of the catalytic element has been reduced to 1 × 10 ¹⁷ / cm ³ or less can be obtained. The crystalline silicon film 1108 thus formed is formed as a thin rod-shaped crystal or a thin flat rod-shaped crystal by the action of a catalyst element, and each crystal grows in a specific direction when viewed macroscopically.

This embodiment can be used in combination with the embodiment and Embodiments 1 to 4.

Embodiment 6 In this embodiment, a method for completing a light-emitting panel manufactured up to FIG. 6B by the manufacturing steps shown in Embodiments 1 to 5 as a light-emitting device will be described in detail with reference to FIG. Will be described.

FIG. 8A is a top view of a light emitting panel in which an element substrate is sealed, and FIG. 8B is a cross-sectional view of FIG. 8A taken along the line AA ′. Reference numeral 801 indicated by a dotted line denotes a source side driver circuit, 802 denotes a pixel portion, and 803 denotes a gate side driver circuit. Reference numeral 804 denotes a sealing substrate, 805 denotes a sealant, and an inside surrounded by the sealant 805 is a space 807.

A wiring (not shown) for transmitting signals input to the source-side drive circuit 801 and the gate-side drive circuit 803 allows a video signal or the like from an FPC (flexible print circuit) 809 serving as an external input terminal. Receive a clock signal. Note that although a state where the FPC is connected to the light-emitting panel is shown here, a module in which an IC (integrated circuit) is directly mounted via the FPC is referred to as a light-emitting device in this specification.

Next, the sectional structure will be described with reference to FIG. A pixel portion 802 and a gate side driver circuit 803 are formed above a substrate 810. The pixel portion 802 is formed by a plurality of pixels including a current control TFT 811 and an anode 812 electrically connected to a drain thereof. .
The gate side driving circuit 803 is an n-channel type TFT 8
13 and p-channel TFT 814 combined CM
It is formed using an OS circuit.

After the banks 815 are formed at both ends of the anode 812, an insulating film 821, an organic compound layer 816, and a cathode 817 are formed on the anode 812.
8 are formed.

Note that the cathode 817 functions as a wiring common to all pixels, and is electrically connected to the FPC 809 via the connection wiring 808.

[0148] Note that a sealing substrate 804 made of glass is pasted together with a sealant 805. Note that an ultraviolet curable resin or a thermosetting resin is preferably used as the sealant 805. Further, if necessary, a spacer made of a resin film may be provided in order to secure an interval between the sealing substrate 804 and the light emitting element 818. The space 807 inside the sealant 805 is filled with an inert gas such as nitrogen or a rare gas. Further, it is desirable that the sealant 805 is a material that does not transmit moisture and oxygen as much as possible.

With the structure described above, the light emitting element is placed in the space 807.
The light emitting element can be completely shut off from the outside by enclosing the light emitting element, and deterioration of the light emitting element due to moisture or oxygen entering from the outside can be prevented. Therefore, a highly reliable light-emitting device can be obtained.

The structure of this embodiment is the same as that of the first embodiment.
It is possible to carry out by combining the configurations of (1) to (5).

(Embodiment 7) Here, a more detailed top structure of a pixel portion of a light emitting device formed by using the present invention is shown in FIG.
FIG. 9A shows a circuit diagram. In FIG.
The switching TFT 702 provided on the substrate is shown in FIG.
Of the switching (n-channel type) TFT 1002. Therefore, for the description of the structure, the description of the switching (n-channel) TFT 1002 may be referred to. The wiring denoted by 703 is a switching T
This is a gate wiring for electrically connecting the gate electrodes 704a and 704b of the FT 702.

Although the present embodiment has a double gate structure in which two channel formation regions are formed, a single gate structure in which one channel formation region is formed or a triple gate structure in which three channel formation regions are formed. good.

The source of the switching TFT 702 is connected to the source wiring 715, and the drain is connected to the drain wiring 705. Further, the drain wiring 705 is electrically connected to the gate electrode 707 of the current controlling TFT 706. Note that the current control TFT 706 is formed using the current control (p-channel type) TFT 1003 in FIG. Therefore, for the description of the structure, the description of the current control (p-channel type) TFT 1003 may be referred to. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.

The source of the current controlling TFT 706 is electrically connected to the current supply line 716, and the drain is electrically connected to the drain wiring 717. The drain wiring 717 is electrically connected to an anode (pixel electrode) 718 indicated by a dotted line. Note that 714 is a light emitting element.

At this time, a storage capacitor (capacitor) is formed in a region indicated by 719. Capacitor 719
Represents the semiconductor film 7 electrically connected to the current supply line 716
20, formed between an insulating film (not shown) in the same layer as the gate insulating film and the gate electrode 707; Further, a capacitor formed by the gate electrode 707, the same layer (not shown) as the first interlayer insulating film, and the current supply line 716 can be used as a storage capacitor.

The structure of this embodiment can be implemented by combining the structures of Embodiments 1 to 6.

(Embodiment 8) In this embodiment, the insulating film 935B formed on the second interlayer insulating film (935, 3926)
An example in which an insulating film other than the DLC film is applied to the first embodiment will be described.

According to the first embodiment or the second embodiment, up to the second interlayer insulating films (935, 3926) are formed. Subsequently, a silicon nitride film 935B is formed over the second interlayer insulating film (935, 3926) as an insulating film 936 by a sputtering method using silicon as a target (FIG. 17). The film formation conditions may be appropriately selected, and particularly preferably, sputtering is performed by using nitrogen (N ₂ ) or a mixed gas of nitrogen and argon as a sputtering gas and applying high-frequency power. The substrate temperature is kept at room temperature, and the heating means may not be used. However, when an organic insulating film is used for the interlayer insulating film, it is preferable to form the film without heating the substrate. In order to sufficiently remove adsorbed or occluded water, it is preferable to perform dehydration by heating at about 50 to 100 ° C. for several minutes to several hours in a vacuum. As an example of film forming conditions, a silicon target of 1 to 2 Ω sq.
a, high-frequency power of 800 W (13.56 MHz), the size of the target is 2 when the diameter is 152.4 mm.
A film formation rate of ４4 nm / min is obtained.

The silicon nitride film thus obtained has a concentration of oxygen and hydrogen as impurity elements in the film of 1 atomic% or less, and has a transmittance of 80% or more in the visible light region. . In particular, it has a transmittance of 80% or more even at a wavelength of 400 nm, indicating the transparency of this film. Further, a dense film can be formed without significantly damaging the surface.

[0160] As described above, a silicon nitride film can be used as the insulating film 935B. Subsequent steps may be performed again according to the first embodiment or the second embodiment.

(Embodiment 9) In this embodiment, an insulating film 935B formed on the second interlayer insulating film (935, 3926) is used.
An example in which an insulating film other than the DLC film is applied will be described.

According to the first or second embodiment, up to the second interlayer insulating film (935, 3926) is formed. Subsequently, using an aluminum nitride (AlN) target on the second interlayer insulating film (935,3926), in an atmosphere of a mixture of argon gas and nitrogen gas, _Al X _{N Y} film 93
5B is formed (FIG. 17). The impurities contained in the Al _X N _y film, particularly oxygen, may be 0 to less than 10 atomic%, and the oxygen concentration is adjusted by appropriately adjusting the sputtering conditions (substrate temperature, source gas and its flow rate, film forming pressure, etc.). can do. Aluminum (A
l) A film may be formed using a target under an atmosphere containing nitrogen gas. Note that the present invention is not limited to the sputtering method, and may use a vapor deposition method or another known technique.

In addition to the AlxNy film, aluminum nitride
Using an argon (AlN) target, argon gas and nitrogen
A formed in an atmosphere in which a raw gas and an oxygen gas are mixed
1N _XO_YA film may be used as the insulating film 935B. Al
The NxOy film contains several atomic% or more of nitrogen, preferably
Should be in the range of 2.5-47.5 atomic%
And sputtering conditions (substrate temperature, source gas and its flow
Amount, film forming pressure, etc.) by appropriately adjusting the nitrogen concentration.
The degree can be adjusted. Aluminum (A
l) Using a target, atmosphere containing nitrogen gas and oxygen gas
The film may be formed under an atmosphere. In addition, it is limited to the sputtering method.
Instead, a vapor deposition method or another known technique may be used.

The above AlxNy film or AlNxOy
The film has high translucency (80% to 91.% transmittance in the visible light region).
3%) and does not hinder light emission from the light emitting element.

As described above, the insulating film 935B is made of AlxN
A y film or an AlNxOy film can be applied. Subsequent steps may be performed again according to the first embodiment or the second embodiment.

Embodiment 10 Since a light emitting device using a light emitting element is of a self-luminous type, it has better visibility in a bright place and a wider viewing angle than a liquid crystal display device. Therefore, it can be used for display portions of various electric appliances.

Electric appliances using the light emitting device manufactured according to the present invention include a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproducing device (car audio, audio component, etc.), a notebook personal computer Computers, game consoles, personal digital assistants (mobile computers, mobile phones, portable game consoles, electronic books, etc.),
An image reproducing device provided with a recording medium (specifically, a device provided with a display device capable of reproducing a recording medium such as a DVD and displaying the image) and the like. In particular, in a portable information terminal in which a screen is often viewed from an oblique direction, since a wide viewing angle is regarded as important, it is preferable to use a light emitting device having a light emitting element. FIG. 10 shows specific examples of these electric appliances.

FIG. 10A shows a display device,
01, a support base 2002, a display unit 2003, a speaker unit 2004, a video input terminal 2005, and the like. The light-emitting device manufactured according to the present invention can be used for the display portion 2003. Since a light-emitting device having a light-emitting element is a self-luminous type, it does not require a backlight and can have a thinner display portion than a liquid crystal display device. The display device includes all information display devices for personal computers, TV broadcast reception, advertisement display, and the like.

FIG. 10B shows a digital still camera, which includes a main body 2101, a display section 2102, an image receiving section 2103,
An operation key 2104, an external connection port 2105, a shutter 2106, and the like are included. The light-emitting device manufactured according to the present invention can be used for the display portion 2102.

FIG. 10C shows a notebook personal computer, which includes a main body 2201, a housing 2202, and a display section 2.
203, keyboard 2204, external connection port 220
5, including a pointing mouse 2206 and the like. The light-emitting device manufactured according to the present invention can be used for the display portion 2203.

FIG. 10D shows a mobile computer, which includes a main body 2301, a display portion 2302, and a switch 230.
3, an operation key 2304, an infrared port 2305, and the like. The light-emitting device manufactured according to the present invention can be used for the display portion 2302.

FIG. 10E shows a portable image reproducing apparatus (specifically, a DVD reproducing apparatus) provided with a recording medium, and includes a main body 2401, a housing 2402, a display portion A 2403, a display portion B 2404, and a recording medium ( DVD, etc.) reading unit 240
5, operation keys 2406, a speaker unit 2407, and the like. The display portion A2403 mainly displays image information and the display portion B2404 mainly displays character information. The light-emitting device manufactured according to the present invention employs these display portions A and B240.
3, 2404. Note that the image reproducing device provided with the recording medium includes a home game machine and the like.

FIG. 10F shows a goggle-type display (head-mounted display).
1, including a display unit 2502 and an arm unit 2503. The light-emitting device manufactured according to the present invention can be used for the display portion 2502.

FIG. 10G shows a video camera, which includes a main body 2601, a display portion 2602, a housing 2603, an external connection port 2604, a remote control receiving portion 2605, and an image receiving portion 260.
6, a battery 2607, a voice input unit 2608, operation keys 2609, and the like. The light-emitting device manufactured according to the present invention can be used for the display portion 2602.

FIG. 10H shows a mobile phone, which includes a main body 2701, a housing 2702, a display portion 2703, a voice input portion 2704, a voice output portion 2705, operation keys 2706,
An external connection port 2707, an antenna 2708, and the like are included.
The light-emitting device manufactured according to the present invention can be used for the display portion 2703. Note that the display portion 2703 displays white characters on a black background, so that power consumption of the mobile phone can be suppressed.

If the emission luminance of the organic material is increased in the future, the light including the output image information can be enlarged and projected by a lens or the like and used for a front-type or rear-type projector.

[0177] The above-mentioned electric appliances are available on the Internet or C
Information distributed through an electronic communication line such as an ATV (cable television) is frequently displayed, and in particular, opportunities to display moving image information are increasing. Since the response speed of the organic material is extremely high, the light-emitting device is preferable for displaying moving images.

[0178] In the light emitting device, since the light emitting portion consumes power, it is preferable to display information so that the light emitting portion is reduced as much as possible. Therefore, when a light emitting device is used for a portable information terminal, particularly a display portion mainly for character information such as a mobile phone or a sound reproducing device, the light emitting portion is driven to form character information with a non-light emitting portion as a background. Is preferred.

As described above, the applicable range of the light-emitting device manufactured by using the present invention is extremely wide, and the light-emitting device can be used for electric appliances in various fields. Further, in the electric appliance of this embodiment, the light emitting devices shown in Embodiments 1 to 9 can be used for a display portion thereof.

[0180]

According to the present invention, the current density in the organic compound layer can be increased by flattening the surface of the anode. Further, the driving voltage can be reduced and the life of the light emitting element can be extended.

Further, when the processing chamber for manufacturing the TFT substrate and the processing chamber for manufacturing the light emitting element are physically separated from each other, and the substrate must be moved, the TFT substrate can be moved to the TF.
It can move without deteriorating the characteristics of T or causing electrostatic breakdown, and furthermore, if the structure of the present invention is applied, the TFT is contaminated by an alkali metal which is a material of a light emitting element, The problem that the light emitting element is deteriorated by moisture or gas can be prevented, and a favorable light emitting device can be realized.

[Brief description of the drawings]

FIG. 1 illustrates an embodiment of a method for manufacturing a light-emitting device.

FIG. 2 illustrates an example of a conventional light emitting device.

FIG. 3 illustrates a manufacturing process of a light-emitting device.

FIG. 4 illustrates a manufacturing process of a light-emitting device.

FIG. 5 illustrates a manufacturing process of a light-emitting device.

FIG. 6 illustrates a manufacturing process of a light-emitting device.

FIG. 7 illustrates an example of a manufacturing process of a light-emitting device.

FIG. 8 illustrates a sealing structure of a light-emitting device.

FIG. 9 illustrates a structure of a pixel portion of a light-emitting device.

FIG. 10 illustrates an example of an electric appliance.

FIG. 11 illustrates an example of a CMP apparatus.

FIG. 12 is an enlarged view of a carrier.

FIG. 13 is a view showing a measurement result by AMF.

FIG. 14 is a view showing a measurement result by AMF.

FIG. 15 is a diagram showing a measurement result by AMF.

FIG 16 illustrates an example of a manufacturing process of a light-emitting device.

FIG. 17 illustrates an example of a manufacturing process of a light-emitting device.

FIG. 18 is a view showing an image of a production process of the present invention.

FIG. 19 illustrates an example of a manufacturing process of a light-emitting device.

FIG. 20 illustrates an example of a manufacturing process of a light-emitting device.

FIG. 21 illustrates an example of a manufacturing process of a light-emitting device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 substrate 101 current controlling TFT 102 interlayer insulating film 103 wiring 105 anode 106 bank 110 organic compound layer 111 cathode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H05B 33/22 H05B 33/22 CZ F term (Reference) 3K007 AB02 AB06 AB11 AB18 BA06 BB07 CB01 CC00 DB03 FA01 GA04 5C094 AA07 AA10 AA24 AA31 AA43 BA03 BA27 CA19 DA09 DA13 DA15 DB01 DB04 EA04 EA05 EA07 EB02 FA01 FA02 FB01 FB02 FB12 FB14 FB15 FB20 JA08 5G435 AA03 AA14 AA16 AA17 BB05 CC09 EE37H01 H05H09

Claims (16)

[Claims] 1. A TFT on an insulator, an interlayer insulating film on the TFT, an anode on the interlayer insulating film, a wiring for electrically connecting the TFT and the anode, the wiring and the anode A bank, an insulating film on the anode and the bank, an organic compound layer on the anode with the insulating film interposed therebetween,
A light emitting device comprising: a cathode on the organic compound layer. 2. The anode according to claim 1, wherein the average surface roughness (Ra) of the anode surface is 0.9 nm or less, preferably 0.8 nm or less.
A light-emitting device having a thickness of 5 nm or less. 3. The light emitting device according to claim 1, wherein the interlayer insulating film is formed of a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. 4. A cured film according to claim 1, wherein said bank is formed by plasma treatment on a surface thereof and contains one or more elements selected from hydrogen, nitrogen, carbon halide, hydrogen fluoride and rare gas. A light emitting device comprising: 5. The light emitting device according to claim 1, further comprising an insulating film made of a silicon nitride film or a DLC film on the interlayer insulating film. 6. A step of forming an interlayer insulating film on a TFT formed on an insulator, a step of flattening the interlayer insulating film by a CMP method, a step of forming a wiring, and a step of forming a wiring through the wiring. Forming an anode electrically connected to the TFT, forming a resin insulating film covering the anode and the wiring, etching to form a bank, performing a heat treatment, Wiping, forming an insulating film covering the anode and the bank, forming an organic compound layer on the insulating film, and forming a cathode on the organic compound layer, A method for manufacturing a light-emitting device, comprising: 7. A step of forming an interlayer insulating film on a TFT formed on an insulator, a step of flattening the interlayer insulating film by a CMP method, a step of forming a wiring, and a step of forming a wiring A step of forming an anode electrically connected to the TFT, a step of performing a first heat treatment, a step of forming a resin insulating film covering the anode and the wiring, and a step of forming a bank by etching; Performing a second heat treatment;
Wiping the anode, forming an insulating film covering the anode and the bank, forming an organic compound layer on the insulating film, and forming a cathode on the organic compound layer And a method for manufacturing a light-emitting device. 8. A step of forming an interlayer insulating film on a TFT formed on an insulator, a step of flattening the interlayer insulating film by a CMP method, a step of forming a wiring, and a step of forming a wiring through the wiring. A step of forming an anode electrically connected to the TFT, a step of performing a first heat treatment, and a step of forming a resin insulating film covering the anode and the wiring and forming a later bank; Performing a second heat treatment, etching the resin insulating film to form a bank, wiping the anode, and forming an insulating film covering the anode and the bank; A method for manufacturing a light-emitting device, comprising: a step of forming an organic compound layer on the insulating film; and a step of forming a cathode on the organic compound layer. 9. A TF formed on a substrate having an insulating surface
Forming an interlayer insulating film on T, flattening the interlayer insulating film by a CMP method, forming a wiring, and forming an anode electrically connected to the TFT via the wiring Performing a step of forming a resin insulating film covering the anode and the wiring; moving a substrate on which the TFT is formed from a first processing chamber to a second processing chamber; A step of forming a bank by etching, a step of performing a heat treatment, a step of performing a plasma treatment on the bank surface, a step of wiping the anode, and a step of forming an insulating film covering the anode and the bank. ,
A method for manufacturing a light-emitting device, comprising: a step of forming an organic compound layer on the insulating film; and a step of forming a cathode on the organic compound layer. 10. A T-shaped substrate formed on a substrate having an insulating surface.
A step of forming an interlayer insulating film on the FT, a step of flattening the interlayer insulating film by a CMP method, a step of forming a wiring, and forming an anode electrically connected to the TFT via the wiring Performing a step of forming a resin insulating film covering the anode and the wiring; moving a substrate on which the TFT is formed from a first processing chamber to a second processing chamber; Heat-treating, etching to form a bank, plasma-treating the bank surface, wiping the anode, forming an insulating film covering the anode and the bank, A method for manufacturing a light-emitting device, comprising: a step of forming an organic compound layer over an insulating film; and a step of forming a cathode over the organic compound layer. 11. The method according to claim 6, further comprising: forming an antistatic film on the resin insulating film; and washing the antistatic film with water to remove the antistatic film. A method for manufacturing a light-emitting device, comprising: 12. The method for manufacturing a light-emitting device according to claim 6, wherein the interlayer insulating film is formed of silicon oxide, silicon oxynitride, or silicon nitride oxide. 13. The method according to claim 6, further comprising, after planarizing the interlayer insulating film, forming an insulating film made of a silicon nitride film or a DLC film on the planarized interlayer insulating film. A method for manufacturing a light-emitting device, comprising: 14. The method according to claim 10, wherein
The method for manufacturing a light-emitting device, wherein the plasma treatment is performed in one or more kinds of gases selected from hydrogen, nitrogen, carbon halide, hydrogen fluoride, and a rare gas. 15. The method for manufacturing a light-emitting device according to claim 6, wherein the step of wiping the anode is performed using a PVA-based porous material. 16. The method for manufacturing a light-emitting device according to claim 6, wherein the step of wiping the anode is a step of flattening the surface of the anode.