JP2006108409A - Semiconductor device and manufacturing method therefor - Google Patents

Semiconductor device and manufacturing method therefor Download PDF

Info

Publication number
JP2006108409A
JP2006108409A JP2004293377A JP2004293377A JP2006108409A JP 2006108409 A JP2006108409 A JP 2006108409A JP 2004293377 A JP2004293377 A JP 2004293377A JP 2004293377 A JP2004293377 A JP 2004293377A JP 2006108409 A JP2006108409 A JP 2006108409A
Authority
JP
Japan
Prior art keywords
semiconductor chip
substrate
adhesive
semiconductor
stepped portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2004293377A
Other languages
Japanese (ja)
Other versions
JP4709521B2 (en
Inventor
Norio Fukazawa
則雄 深澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2004293377A priority Critical patent/JP4709521B2/en
Publication of JP2006108409A publication Critical patent/JP2006108409A/en
Application granted granted Critical
Publication of JP4709521B2 publication Critical patent/JP4709521B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10156—Shape being other than a cuboid at the periphery
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method therefor which make a package crack caused by steam from moisture contained in an adhesive difficult to happen when a semiconductor chip is fixed to a board with the adhesive. <P>SOLUTION: The semiconductor device comprises the board 12, the semiconductor chip 14 which is fixed to the board 12 with the adhesive 18, and a sealing resin 16 which seals the semiconductor chip 14. The semiconductor chip 14 has a stepped part 26 on its side face with lower side larger than the upper side. The adhesive 18 is extended from the stepped part 26 of the semiconductor chip 14 over the board 12, with which the semiconductor chip 14 is in direct contact. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は半導体装置及び半導体装置の製造方法に関する。   The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

半導体チップを接着剤により基板に固定し、封止樹脂により封止してなる半導体装置は公知である。半導体チップはワイヤにより基板に電気的に接続される。従来の半導体装置では、接着剤は基板の表面に塗布され、半導体チップを接着剤の上に載せ、よって接着剤は半導体チップの底面と基板の表面との間に存在して両者を固定している。   A semiconductor device in which a semiconductor chip is fixed to a substrate with an adhesive and sealed with a sealing resin is known. The semiconductor chip is electrically connected to the substrate by wires. In a conventional semiconductor device, the adhesive is applied to the surface of the substrate, and the semiconductor chip is placed on the adhesive, so that the adhesive exists between the bottom surface of the semiconductor chip and the surface of the substrate and fixes both. Yes.

インターポーザと呼ばれる基板を有する半導体装置の場合、半導体装置はさらにマザーボード等の回路基板に搭載される。半導体装置をマザーボード等の回路基板に搭載するときに、半導体装置の基板に設けられたはんだボール等の外部端子を加熱し、リフローさせて回路基板の端子に接続させる。   In the case of a semiconductor device having a substrate called an interposer, the semiconductor device is further mounted on a circuit board such as a mother board. When a semiconductor device is mounted on a circuit board such as a mother board, external terminals such as solder balls provided on the substrate of the semiconductor device are heated and reflowed to be connected to the terminals of the circuit board.

半導体装置が外気にさらされた環境下で比較的に長い期間保管されると、封止樹脂や接着剤が外気中の水分を吸収してしまう。このため、半導体装置を電子機器等の実装基板に実装するために外部端子をリフローすると、封止樹脂や接着剤中に吸収されていた水分が蒸発し、体積の膨張により熱応力が発生し、パッケージクラックを発生させることがある。この現象は、比較的に接着剤が水分を吸収しやすい為、半導体チップの底面と基板の表面との間に存在している接着剤が原因となって生じることが多い。すなわち、蒸気圧応力が集中するポイントが接着剤と半導体チップとの間の界面及び接着剤と基板との間の界面にあるためである。また、この現象はリフローの回数が多くなるほど生じやすくなる。   When the semiconductor device is stored for a relatively long period in an environment exposed to the outside air, the sealing resin and the adhesive absorb moisture in the outside air. For this reason, when the external terminal is reflowed in order to mount the semiconductor device on a mounting substrate such as an electronic device, moisture absorbed in the sealing resin or the adhesive is evaporated, and thermal stress is generated due to the expansion of the volume. Package cracks may occur. This phenomenon is often caused by the adhesive existing between the bottom surface of the semiconductor chip and the surface of the substrate because the adhesive is relatively easy to absorb moisture. That is, the point where the vapor pressure stress is concentrated is at the interface between the adhesive and the semiconductor chip and the interface between the adhesive and the substrate. This phenomenon is more likely to occur as the number of reflows increases.

さらに、電子機器の高性能化に対応するために、半導体チップだけでなく、半導体装置として、低い熱抵抗特性と高い電気的特性を保持していることが要求される。しかし、接着剤が半導体チップと基板の間に存在すると、半導体チップから発生した熱を基板に伝導する妨げとなり、半導体装置として低い熱抵抗特性を実現する上で不利である。   Furthermore, in order to cope with higher performance of electronic devices, it is required that not only a semiconductor chip but also a semiconductor device have low thermal resistance characteristics and high electrical characteristics. However, the presence of the adhesive between the semiconductor chip and the substrate hinders conduction of heat generated from the semiconductor chip to the substrate, which is disadvantageous in realizing low thermal resistance characteristics as a semiconductor device.

さらに、電気的特性の向上のために、半導体チップの一方の面にグランド層や電源供給層を設けられることがあるが、この場合に、半導体チップの底面と基板の表面との間に存在している接着剤が、半導体チップの底面のそのような導電層と基板の回路の一部である導電層との電気的接続を妨げるため、半導体装置として電気的特性を向上する対応をとることができない。   Furthermore, in order to improve electrical characteristics, a ground layer or a power supply layer may be provided on one surface of the semiconductor chip. In this case, it exists between the bottom surface of the semiconductor chip and the surface of the substrate. The adhesive that prevents the electrical connection between such a conductive layer on the bottom surface of the semiconductor chip and the conductive layer that is a part of the circuit of the substrate can be taken to improve the electrical characteristics as a semiconductor device. Can not.

一方、側面に段付き部が設けられた半導体チップを接着剤により基板に固定する提案がある（例えば、特許文献１参照。）。しかし、特許文献１の提案では、段付き部は半導体チップの底面と基板の表面との間に配置された接着剤が半導体チップの側面に這い上がり、さらに半導体チップ上面のワイヤボンディングのための電極を覆ってしまうのを防止するために設けられている。
また、半導体チップの側面に段付き部を設け、この段付き部を利用して半導体チップを接着剤によりリードフレームに固定する提案がある（例えば、特許文献２参照。）。しかし、特許文献２の提案は、半導体チップをリードフレームに嵌め込むためのもので、基板に搭載して樹脂封止を行うものではない。 On the other hand, there is a proposal for fixing a semiconductor chip having a stepped portion on a side surface to a substrate with an adhesive (for example, see Patent Document 1). However, according to the proposal of Patent Document 1, the stepped portion has an adhesive disposed between the bottom surface of the semiconductor chip and the surface of the substrate that crawls up to the side surface of the semiconductor chip, and further, an electrode for wire bonding on the top surface of the semiconductor chip. It is provided to prevent the cover from being covered.
There is also a proposal for providing a stepped portion on the side surface of the semiconductor chip and using the stepped portion to fix the semiconductor chip to the lead frame with an adhesive (see, for example, Patent Document 2). However, the proposal of Patent Document 2 is for fitting a semiconductor chip into a lead frame, and is not mounted on a substrate and resin-sealed.

さらに、複数の半導体チップを１つの基板に搭載する半導体装置の場合、基板の中心部に位置する半導体チップは基板の周辺部から遠いため、その半導体チップについては加熱時に接着剤に含まれる水分の蒸気の逃げ経路が長くなり、単数の半導体チップを１つの基板に搭載する半導体装置と比較し、パッケージクラックの発生が起こりやすい。   Further, in the case of a semiconductor device in which a plurality of semiconductor chips are mounted on a single substrate, the semiconductor chip located at the center of the substrate is far from the peripheral portion of the substrate. The steam escape path becomes longer, and package cracks are more likely to occur than in a semiconductor device in which a single semiconductor chip is mounted on one substrate.

特開平９−１７２０２９号公報Japanese Patent Laid-Open No. 9-172029 特開平２−１７７４４７号公報Japanese Patent Laid-Open No. 2-177447

本発明の目的は、半導体チップが接着剤により基板に固定されている場合に接着剤に含まれる水分の蒸気によるパッケージクラックの発生を起こりにくくした半導体装置及び半導体装置の製造方法を提供することである。   An object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device in which occurrence of package cracks due to moisture vapor contained in the adhesive is less likely to occur when the semiconductor chip is fixed to the substrate with the adhesive. is there.

本発明による半導体装置は、基板と、接着剤により該基板に固定された半導体チップと、該半導体チップを封止する封止樹脂とからなり、該半導体チップはその側面に下部側が上部側よりも大きい段付き部を有し、該接着剤は該半導体チップの段付き部から該基板に跨がって形成され、該半導体チップは該基板に直接接触していることを特徴とするものである。   A semiconductor device according to the present invention comprises a substrate, a semiconductor chip fixed to the substrate by an adhesive, and a sealing resin that seals the semiconductor chip, and the semiconductor chip has a lower side on its side than an upper side. The adhesive has a large stepped portion, the adhesive is formed across the stepped portion of the semiconductor chip from the substrate, and the semiconductor chip is in direct contact with the substrate. .

この構成によれば、半導体チップを接着剤により基板に確実に固定することができるとともに、半導体チップの底面と基板の間に接着剤が実質的に存在しないので、接着剤に起因するパッケージクラックが生じなくなる。   According to this configuration, the semiconductor chip can be reliably fixed to the substrate with the adhesive, and the adhesive is not substantially present between the bottom surface of the semiconductor chip and the substrate, so that there is no package crack caused by the adhesive. No longer occurs.

また、半導体チップと基板間には接着剤がないため、半導体チップの底面がグランドパターンや電源パターンなどの導電層となっている半導体チップを含む半導体装置の場合、半導体チップの底面の導電層と基板の回路の一部である導電層との電気的な接続が可能となり、半導体装置の電気的特性の向上が図れる。また、半導体チップと基板間には接着剤がないため、半導体チップから発生した熱を基板へ伝導することができるので、半導体装置の熱抵抗特性を改善することが可能となる。   In addition, since there is no adhesive between the semiconductor chip and the substrate, in the case of a semiconductor device including a semiconductor chip in which the bottom surface of the semiconductor chip is a conductive layer such as a ground pattern or a power supply pattern, the conductive layer on the bottom surface of the semiconductor chip Electrical connection with a conductive layer which is a part of the circuit of the substrate is possible, and the electrical characteristics of the semiconductor device can be improved. In addition, since there is no adhesive between the semiconductor chip and the substrate, heat generated from the semiconductor chip can be conducted to the substrate, so that the thermal resistance characteristics of the semiconductor device can be improved.

本発明による半導体装置は、基板と、接着剤により該基板に固定された複数の半導体チップと、該複数の半導体チップを封止する封止樹脂とからなり、該複数の半導体チップの中の複数の第１の半導体チップの各々がその側面に下部側が上部側よりも大きい段付き部を有し、該接着剤は該第１の半導体チップの段付き部から該基板にかけて延び、該第１の半導体チップは少なくとも部分的に該基板に直接的に接触しており、他の第２の半導体チップは該第１の半導体チップの段付き部に載っていて該第１の半導体チップを基板に固定させる接着剤により該第１の半導体チップに固定されることを特徴とするものである。   A semiconductor device according to the present invention includes a substrate, a plurality of semiconductor chips fixed to the substrate with an adhesive, and a sealing resin that seals the plurality of semiconductor chips. Each of the first semiconductor chips has a stepped portion on its side surface, the lower side being larger than the upper side, and the adhesive extends from the stepped portion of the first semiconductor chip to the substrate, The semiconductor chip is at least partially in direct contact with the substrate, and the other second semiconductor chip is mounted on the stepped portion of the first semiconductor chip, and the first semiconductor chip is fixed to the substrate. It is fixed to the first semiconductor chip by an adhesive to be applied.

この構成によれば、第１の半導体チップについては、上記したのと同様に第１の半導体チップと基板間には接着剤がないため、パッケージクラックの発生が起こりにくくなる。また、第２の半導体チップは第１の半導体チップの段付き部に載っていて第１の半導体チップを基板に固定させる接着剤により第１の半導体チップに固定されているので、第２の半導体チップと基板間には実質的に接着剤がないため、パッケージクラックの発生が起こりにくくなる。   According to this configuration, since there is no adhesive between the first semiconductor chip and the substrate in the same manner as described above, package cracks are unlikely to occur in the first semiconductor chip. Further, since the second semiconductor chip is mounted on the stepped portion of the first semiconductor chip and is fixed to the first semiconductor chip by an adhesive that fixes the first semiconductor chip to the substrate, the second semiconductor chip Since there is substantially no adhesive between the chip and the substrate, package cracks are less likely to occur.

本発明による半導体装置の製造方法は、常温では固形で、加熱により溶融する接着剤を、側面に下部側が上部側よりも大きい段付き部を有する半導体チップの段付き部に載せ、該半導体チップを基板に搭載し、該接着剤を加熱して溶融させ、よって半導体チップを該接着剤により該基板に固定することを特徴とするものである。   According to the method of manufacturing a semiconductor device of the present invention, an adhesive that is solid at room temperature and melts by heating is placed on a stepped portion of a semiconductor chip having a stepped portion on the side surface, the lower side being larger than the upper side. It is mounted on a substrate, and the adhesive is heated and melted, so that the semiconductor chip is fixed to the substrate with the adhesive.

この構成によれば、上記したのと同様に半導体チップと基板間には接着剤がないため、パッケージクラックの発生が起こりにくくなる。そして、常温では固形の接着剤を用いて半導体チップを基板に簡単且つ確実に固定することができる。   According to this configuration, since there is no adhesive between the semiconductor chip and the substrate as described above, package cracks are less likely to occur. At normal temperature, the semiconductor chip can be easily and reliably fixed to the substrate using a solid adhesive.

本発明によれば、パッケージクラックの発生が起こりにくくした半導体装置を得ることができる。また、パッケージとしての半導体装置の電気特性の向上、パッケージとしての低熱抵抗特性の向上を図ることができる。   According to the present invention, it is possible to obtain a semiconductor device in which generation of package cracks is difficult to occur. In addition, the electrical characteristics of the semiconductor device as a package can be improved, and the low thermal resistance characteristics as a package can be improved.

以下本発明の実施例について図面を参照して説明する。   Embodiments of the present invention will be described below with reference to the drawings.

図１は本発明の第１実施例による半導体装置を示す断面図である。半導体装置１０は、基板１２と、基板１２に搭載された半導体チップ１４と、半導体チップ１４を封止する封止樹脂１６とからなる。   FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention. The semiconductor device 10 includes a substrate 12, a semiconductor chip 14 mounted on the substrate 12, and a sealing resin 16 that seals the semiconductor chip 14.

半導体チップ１４は接着剤１８により基板１２に固定される。公知のように、基板１２は図示しない回路を有し、基板１２の表面には端子が形成されている。レジスト２０が基板１２の表面に設けられており、基板１２の端子はレジスト２０の開口部に配置される。ボンディングワイヤ２２が半導体チップ１４の端子と基板１２の端子とを接続している。外部端子としてのはんだボール２４が基板１２の下側に設けられている。基板１２の端子とはんだボール２４とは基板１２の回路により接続されている。   The semiconductor chip 14 is fixed to the substrate 12 with an adhesive 18. As is well known, the substrate 12 has a circuit (not shown), and terminals are formed on the surface of the substrate 12. A resist 20 is provided on the surface of the substrate 12, and a terminal of the substrate 12 is disposed in an opening of the resist 20. A bonding wire 22 connects the terminal of the semiconductor chip 14 and the terminal of the substrate 12. Solder balls 24 as external terminals are provided on the lower side of the substrate 12. The terminals of the substrate 12 and the solder balls 24 are connected by a circuit of the substrate 12.

図２は図１の半導体チップ１４を示す平面図である。図３は図２の半導体チップ１４を示す側面図である。図１から図３において、半導体チップ１４は上方から見て矩形又は正方形の形状を有し、その側面に下部側１４ｂが上部側１４ａよりも大きい段付き部２６を有する。   FIG. 2 is a plan view showing the semiconductor chip 14 of FIG. FIG. 3 is a side view showing the semiconductor chip 14 of FIG. 1 to 3, the semiconductor chip 14 has a rectangular or square shape when viewed from above, and has a stepped portion 26 on the side surface of which the lower side 14b is larger than the upper side 14a.

接着剤１８は半導体チップ１４の段付き部２６から半導体チップ１４の下部側１４ｂを覆って基板１２（の半導体チップ１４の外側の表面）にかけて延びる。この構成によれば、半導体チップ１４を基板１２に確実に固定することができる。半導体チップ１４の側面に段付き部２６が設けられているので、十分な接着面積が確保され、段付き部２６が基板１２への接着剤１８による固定に対してアンカー効果を提供するため、半導体チップ１４の基板１２への固定は強力なものとなる。   The adhesive 18 extends from the stepped portion 26 of the semiconductor chip 14 to the substrate 12 (the outer surface of the semiconductor chip 14) covering the lower side 14 b of the semiconductor chip 14. According to this configuration, the semiconductor chip 14 can be reliably fixed to the substrate 12. Since the stepped portion 26 is provided on the side surface of the semiconductor chip 14, a sufficient bonding area is ensured, and the stepped portion 26 provides an anchor effect for fixing with the adhesive 18 to the substrate 12. The fixing of the chip 14 to the substrate 12 becomes strong.

半導体チップ１４の底面は基板１２に直接的に接触し、半導体チップ１４の底面と基板１２の間に接着剤が実質的に存在しないので、半導体チップ１４の底面と基板１２の間に接着剤が存在することに起因するパッケージクラックが発生しにくい。半導体チップ１４を基板１２に搭載するときに半導体チップ１４は基板１２に対して位置決めされ且つ押圧保持されているので、半導体チップ１４の底面の外周部に溶融した接着剤がしみ込む可能性はほとんどない。少量の接着剤が半導体チップ１４の底面の外周部にしみ込んだとしても、その接着剤が加熱されたときに生じる水分の蒸気は半導体チップ１４の外側へ逃げやすく、半導体チップ１４の中央部において蒸気圧応力が集中することはなく、パッケージクラックは発生しにくい。   Since the bottom surface of the semiconductor chip 14 is in direct contact with the substrate 12 and there is substantially no adhesive between the bottom surface of the semiconductor chip 14 and the substrate 12, there is no adhesive between the bottom surface of the semiconductor chip 14 and the substrate 12. Package cracks due to the presence are unlikely to occur. Since the semiconductor chip 14 is positioned and pressed against the substrate 12 when the semiconductor chip 14 is mounted on the substrate 12, there is almost no possibility of the molten adhesive soaking into the outer peripheral portion of the bottom surface of the semiconductor chip 14. . Even if a small amount of adhesive penetrates into the outer peripheral portion of the bottom surface of the semiconductor chip 14, moisture vapor generated when the adhesive is heated easily escapes to the outside of the semiconductor chip 14. The pressure stress is not concentrated and package cracks are unlikely to occur.

また、半導体チップ１４と基板１２との間には接着剤がなく、半導体チップ１４と基板１２とが直接的に接触しているため、半導体チップ１４から発生した熱を基板１２へ伝導することができるので、半導体装置１０の熱抵抗特性を改善することが可能となる。
また、半導体チップ１４の底面がグランドパターンや電源パターンなどの導電層となっている半導体チップ１４を含む半導体装置１０の場合、半導体チップ１４の底面の導電層と基板１２の回路の一部である導電層との電気的な接続が可能となり、半導体装置１０の電気的特性の向上が図れる。 Further, since there is no adhesive between the semiconductor chip 14 and the substrate 12 and the semiconductor chip 14 and the substrate 12 are in direct contact, heat generated from the semiconductor chip 14 can be conducted to the substrate 12. Therefore, the thermal resistance characteristics of the semiconductor device 10 can be improved.
Further, in the case of the semiconductor device 10 including the semiconductor chip 14 in which the bottom surface of the semiconductor chip 14 is a conductive layer such as a ground pattern or a power supply pattern, the conductive layer on the bottom surface of the semiconductor chip 14 and a part of the circuit of the substrate 12. Electrical connection with the conductive layer is possible, and the electrical characteristics of the semiconductor device 10 can be improved.

図４は側面に段付き部２６を有する半導体チップ１４を形成する例を示す図である。集積回路を形成した半導体ウエハ２８から半導体チップ１４をダイシングによって個片に分割する。図４（Ａ）では、ダイシングブレード３０を用いて半導体ウエハ２８を半導体チップ１４に完全に個片化しない程度までダイシングし、図４（Ｂ）では、最初に使用したダイシングブレード３０よりも幅の狭いダイシングブレード３２を用いて、半導体ウエハ２８を完全に切断する。図４（Ｃ）はこのようにして側面に段付き部２６が形成された半導体チップ１４を示す。なお、２回目のダイシングは半導体ウエハ２８の反対側から行うこともできる。また、段付き部２６の形成は、その他の方法、例えばエッチングや、半導体チップ個片化分割後に研削により実施してもよい。   FIG. 4 is a view showing an example of forming the semiconductor chip 14 having the stepped portion 26 on the side surface. The semiconductor chip 14 is divided into individual pieces by dicing from the semiconductor wafer 28 on which the integrated circuit is formed. In FIG. 4A, the dicing blade 30 is used to dice the semiconductor wafer 28 to the extent that it is not completely separated into the semiconductor chips 14, and in FIG. 4B, the width is wider than the dicing blade 30 used first. Using the narrow dicing blade 32, the semiconductor wafer 28 is completely cut. FIG. 4C shows the semiconductor chip 14 with the stepped portion 26 formed on the side surface in this way. The second dicing can be performed from the opposite side of the semiconductor wafer 28. The stepped portion 26 may be formed by other methods, for example, etching or grinding after dividing the semiconductor chip into pieces.

図５は半導体チップ１４に付着する前の接着剤１８の状態を示す平面図である。接着剤１８は常温では固形で、加熱により溶融する接着性樹脂からなる。このような接着剤１８は熱溶融型接着剤（例えばポリイミド系樹脂）の中から選択することができる。接着剤１８は常温では半導体チップ１４の段付き部２６に載る形状を有する。より詳細には、接着剤１８は常温では半導体チップ１４の全周に沿って半導体チップ１４の段付き部２６に載る矩形又は正方形の環状の形状を有する。接着剤１８の（各辺の）幅は半導体チップ１４の段付き部２６の幅よりもわずかに大きくする。例えば、半導体チップ１４の段付き部２６の幅が約０．１mmとしたときに、接着剤１８の幅は約０．２mm程度にする。   FIG. 5 is a plan view showing a state of the adhesive 18 before adhering to the semiconductor chip 14. The adhesive 18 is made of an adhesive resin that is solid at room temperature and melts by heating. Such an adhesive 18 can be selected from hot melt adhesives (for example, polyimide resins). The adhesive 18 has a shape that rests on the stepped portion 26 of the semiconductor chip 14 at room temperature. More specifically, the adhesive 18 has a rectangular or square annular shape that rests on the stepped portion 26 of the semiconductor chip 14 along the entire circumference of the semiconductor chip 14 at room temperature. The width (on each side) of the adhesive 18 is slightly larger than the width of the stepped portion 26 of the semiconductor chip 14. For example, when the width of the stepped portion 26 of the semiconductor chip 14 is about 0.1 mm, the width of the adhesive 18 is about 0.2 mm.

図６は接着剤１８が半導体チップ１４の段付き部２６に載せられた状態を示す側面図である。接着剤１８の外縁部は半導体チップ１４の段付き部２６の外縁部よりもわずかに外側に突出している。接着剤１８が溶融するときに、接着剤１８の一部は半導体チップ１４の段付き部２６に載った状態であり、接着剤１８の他の一部は段付き部２６から基板１２の表面に向かって垂れていき、半導体チップ１４を基板１２に固定させる。   FIG. 6 is a side view showing a state in which the adhesive 18 is placed on the stepped portion 26 of the semiconductor chip 14. The outer edge portion of the adhesive 18 protrudes slightly outward from the outer edge portion of the stepped portion 26 of the semiconductor chip 14. When the adhesive 18 melts, a part of the adhesive 18 is placed on the stepped portion 26 of the semiconductor chip 14, and the other part of the adhesive 18 is transferred from the stepped portion 26 to the surface of the substrate 12. The semiconductor chip 14 is fixed to the substrate 12 as it hangs down.

図７は図６の半導体チップ１４を基板１２に搭載する工程の例を示す図である。実施例では、加熱機能をもった保持ツール３４を使用している。ただし、基板１２を支持する支持部材が加熱機能をもち、または、保持ツール３４及び基板１２を支持する支持部材の両者が加熱機能をもつようにすることもできる、また、半導体チップ１４を基板１２に搭載した状態で熱雰囲気中にさらし、接着剤１８を溶融させて固定する方法でもよい。   FIG. 7 is a diagram showing an example of a process for mounting the semiconductor chip 14 of FIG. In the embodiment, a holding tool 34 having a heating function is used. However, the support member that supports the substrate 12 has a heating function, or both the holding tool 34 and the support member that supports the substrate 12 can have a heating function. Alternatively, the adhesive 18 may be melted and fixed by being exposed to a heat atmosphere in a state where the adhesive 18 is mounted.

図７（Ａ）では、保持ツール３４は接着剤１８が段付き部２６に載せられている半導体チップ１４を保持する。図７（Ｂ）では、保持ツール３４は半導体チップ１４を基板１２に対して所定の位置にセットし、半導体チップ１４を基板１２に対して押圧しつつ加熱機能を作動させる。加熱機能の加熱温度は、使用する接着剤の溶融温度に従って、例えば１００℃〜１５０℃程度に設定する。段付き部２６に載せられている接着剤１８は溶融して、段付き部２６を覆い、基板１２に達する。加熱機能を停止し、接着剤１８が固まるまで保持ツール３４で半導体チップ１４を基板１２に対して押圧したままの状態で、保持する。次いで、図７（Ｃ）では、保持ツール３４を基板１２に固定された半導体チップ１４から取り外す。   In FIG. 7A, the holding tool 34 holds the semiconductor chip 14 on which the adhesive 18 is placed on the stepped portion 26. In FIG. 7B, the holding tool 34 sets the semiconductor chip 14 at a predetermined position with respect to the substrate 12 and activates the heating function while pressing the semiconductor chip 14 against the substrate 12. The heating temperature of the heating function is set to about 100 ° C. to 150 ° C., for example, according to the melting temperature of the adhesive to be used. The adhesive 18 placed on the stepped portion 26 melts, covers the stepped portion 26, and reaches the substrate 12. The heating function is stopped, and the semiconductor chip 14 is held while being pressed against the substrate 12 with the holding tool 34 until the adhesive 18 is hardened. Next, in FIG. 7C, the holding tool 34 is removed from the semiconductor chip 14 fixed to the substrate 12.

図７（Ａ）〜（Ｃ）に示すようにして半導体チップ１４を基板１２に固定した後でワイヤボンディングを行って、図１に示すように、ボンディングワイヤ２２により半導体チップ１４の端子と基板１２のボンディング端子が接続される。さらに、封止樹脂１６によって半導体チップ１４を封止する。   As shown in FIGS. 7A to 7C, the semiconductor chip 14 is fixed to the substrate 12 and then wire bonding is performed. As shown in FIG. The bonding terminals are connected. Further, the semiconductor chip 14 is sealed with the sealing resin 16.

図８は半導体チップに付着する前の接着剤の他の形状を示す平面図である。図５の例では、接着剤１８は連続的な環状の形状を有しているのに対して、図８の例では、接着剤１８は不連続的な環状の形状を有している。図８の例では、接着剤１８は矩形の環状の形状の３辺だけに相当する形状を有している。この場合にも、半導体チップ１４は接着剤１８により基板１２に固定され、かつ、半導体チップ１４は基板１２に直接的に接触し、半導体チップ１４と基板１２間には接着剤がないようにすることができる。さらに、接着剤１８は矩形の環状の形状の対向する２辺だけに相当する形状、つまり、２つの独立した短冊状のもの、を有するようにすることができる。   FIG. 8 is a plan view showing another shape of the adhesive before adhering to the semiconductor chip. In the example of FIG. 5, the adhesive 18 has a continuous annular shape, whereas in the example of FIG. 8, the adhesive 18 has a discontinuous annular shape. In the example of FIG. 8, the adhesive 18 has a shape corresponding to only three sides of a rectangular annular shape. Also in this case, the semiconductor chip 14 is fixed to the substrate 12 by the adhesive 18, and the semiconductor chip 14 is in direct contact with the substrate 12 so that there is no adhesive between the semiconductor chip 14 and the substrate 12. be able to. Furthermore, the adhesive 18 can have a shape corresponding to only two opposing sides of a rectangular annular shape, that is, two independent strips.

図９は接着剤１８が半導体チップ１４に塗布される例を示す平面図である。接着剤１８はディスペンサ３６から吐出される熱硬化型の接着剤であり、銀ペーストと呼ばれるものである。接着剤１８はディスペンサ３６から吐出されて接着剤１８の段付き部２６に塗布される。接着剤１８が塗布された半導体チップ１４は例えば図７に示すようにして基板１２に固定されることができる。   FIG. 9 is a plan view showing an example in which the adhesive 18 is applied to the semiconductor chip 14. The adhesive 18 is a thermosetting adhesive discharged from the dispenser 36 and is called a silver paste. The adhesive 18 is discharged from the dispenser 36 and applied to the stepped portion 26 of the adhesive 18. The semiconductor chip 14 to which the adhesive 18 is applied can be fixed to the substrate 12 as shown in FIG. 7, for example.

図１０は本発明の第２実施例による半導体装置を示す断面図である。図１１は図１０の基板を示す断面図である。図１２は図１０の半導体チップが基板に搭載された例を示す断面図である。図１０から図１２においては、図１の例と同様に、半導体装置１０は、基板１２と、接着剤１８により基板１２に固定された半導体チップ１４と、半導体チップ１４の端子と基板１２の端子とを接続するボンディングワイヤ２２と、半導体チップを封止する封止樹脂１６とからなる。半導体チップ１４はその側面に下部側が上部側よりも大きい段付き部２６を有する。接着剤１８は半導体チップ１４の段付き部２６から半導体チップ１４の段付き部２６の下の側面を覆って基板１２の表面にかけて延びる。従って、図１０から図１２の実施例の作用は、図１の実施例と作用と同様である。   FIG. 10 is a sectional view showing a semiconductor device according to a second embodiment of the present invention. FIG. 11 is a cross-sectional view showing the substrate of FIG. 12 is a cross-sectional view showing an example in which the semiconductor chip of FIG. 10 is mounted on a substrate. 10 to 12, similar to the example of FIG. 1, the semiconductor device 10 includes a substrate 12, a semiconductor chip 14 fixed to the substrate 12 with an adhesive 18, a terminal of the semiconductor chip 14, and a terminal of the substrate 12. And a sealing resin 16 for sealing the semiconductor chip. The semiconductor chip 14 has a stepped portion 26 on its side surface, the lower side being larger than the upper side. The adhesive 18 extends from the stepped portion 26 of the semiconductor chip 14 to the surface of the substrate 12 so as to cover the side surface below the stepped portion 26 of the semiconductor chip 14. Accordingly, the operation of the embodiment of FIGS. 10 to 12 is the same as that of the embodiment of FIG.

さらに、図１０から図１２においては、基板１２は半導体チップ１４の下方の位置に貫通孔３８を有する。例えば、貫通孔３８の大きさは直径約０．１mmである。また、半導体チップ１４と基板１２との間に空間４０が形成され、貫通孔３８は空間４０に通じている。従って、この空間４０は貫通孔３８を介して基板１２の外部と連通している。   Further, in FIGS. 10 to 12, the substrate 12 has a through hole 38 at a position below the semiconductor chip 14. For example, the size of the through hole 38 is about 0.1 mm in diameter. Further, a space 40 is formed between the semiconductor chip 14 and the substrate 12, and the through hole 38 communicates with the space 40. Therefore, the space 40 communicates with the outside of the substrate 12 through the through hole 38.

空間４０は基板１２の半導体チップ１４側のレジスト２０の厚さを変化させて基板１２の表面に窪み１２Ａを設けることに備えられている。このレジスト２０は半導体チップ１４の底面の外周部が位置する第１部分２０Ａと、第１部分２０Ａよりも内側に位置する第２部分２０Ｂとを有し、第２部分２０Ｂの厚さが第１部分２０Ａの厚さよりも薄く形成されている。例えば、第１部分２０Ａの厚さが４０μｍ、第２部分２０Ｂの厚さが２０μｍである。レジスト２０の厚さの変化は、例えばレジスト２０を印刷法により形成する場合に、最初に２０μｍの厚さのレジスト材料を全体的に塗布し、次に第１部分２０Ａのみに２０μｍの厚さのレジスト材料を塗布することにより達成される。   The space 40 is provided to provide a recess 12A on the surface of the substrate 12 by changing the thickness of the resist 20 on the semiconductor chip 14 side of the substrate 12. The resist 20 has a first portion 20A where the outer peripheral portion of the bottom surface of the semiconductor chip 14 is located, and a second portion 20B located inside the first portion 20A. The thickness of the second portion 20B is the first. It is formed thinner than the thickness of the portion 20A. For example, the thickness of the first portion 20A is 40 μm, and the thickness of the second portion 20B is 20 μm. For example, when the resist 20 is formed by a printing method, the thickness of the resist 20 is changed by first applying a resist material having a thickness of 20 μm first, and then applying a thickness of 20 μm only to the first portion 20A. This is achieved by applying a resist material.

空間４０は、半導体チップ１４とレジスト２０の第２部分２０Ｂの間に形成される。半導体チップ１４と基板１２の表面にあるレジスト２０の第１部分２０Ａとは直接に接触しており、レジスト２０の第１部分２０Ａは第２部分２０Ｂを囲んでいる。このため、半導体装置１０のワイヤボンディングの後で樹脂封止を行う際に、封止樹脂は空間４０には流入せず、空間４０が維持される。そこで、半導体装置１０を製造した後で半導体装置１０のいずれかの部材が吸湿し、半導体装置１０をマザーボード等の基板に実装する際の加熱により水分が蒸発したとしても、蒸気は基板の貫通孔３８から放出されるため、蒸気圧によるパッケージクラックは生じない。   The space 40 is formed between the semiconductor chip 14 and the second portion 20B of the resist 20. The semiconductor chip 14 and the first portion 20A of the resist 20 on the surface of the substrate 12 are in direct contact with each other, and the first portion 20A of the resist 20 surrounds the second portion 20B. For this reason, when resin sealing is performed after wire bonding of the semiconductor device 10, the sealing resin does not flow into the space 40 and the space 40 is maintained. Therefore, even if any member of the semiconductor device 10 absorbs moisture after the manufacture of the semiconductor device 10 and moisture is evaporated by heating when the semiconductor device 10 is mounted on a substrate such as a mother board, the vapor remains in the through hole of the substrate. As a result, the crack is not generated by the vapor pressure.

図１３から図１５は半導体チップ１４と基板１２の間に空間４０を設けるために窪み１２Ａが形成された基板１２の例を示す平面図である。半導体チップ１４は破線で示されている。図１３においては、窪み１２Ａは十字形状に形成されている。図１４においては、窪み１２Ａは正方形状に形成されている。図１５においては、窪み１２Ａは円形状に形成されている。基板１２の表面の窪み１２Ａの大きさや形状は、半導体チップ１４を基板１２に搭載したときに半導体チップ１４が窪み１２Ａ内に納まらないようにすれば、特に限定されるものではない。   13 to 15 are plan views showing examples of the substrate 12 in which the recess 12A is formed in order to provide the space 40 between the semiconductor chip 14 and the substrate 12. FIG. The semiconductor chip 14 is indicated by a broken line. In FIG. 13, the recess 12A is formed in a cross shape. In FIG. 14, the recess 12A is formed in a square shape. In FIG. 15, the recess 12A is formed in a circular shape. The size and shape of the recess 12A on the surface of the substrate 12 are not particularly limited as long as the semiconductor chip 14 does not fit in the recess 12A when the semiconductor chip 14 is mounted on the substrate 12.

図１６は本発明の第３実施例による半導体装置を示す断面図である。図１７は図１６の半導体チップが基板に搭載された例を示す平面図である。図１６及び図１７においては、半導体装置１０は、基板１２と、基板１２に固定された複数の半導体チップ１４Ｐ，１４Ｑと、複数の半導体チップ１４Ｐ，１４Ｑを封止する封止樹脂１６とからなる。基板１２に固定された複数の半導体チップは、複数の第１の半導体チップ１４Ｐと、第２の半導体チップ１４Ｑとを含む。   FIG. 16 is a sectional view showing a semiconductor device according to a third embodiment of the present invention. FIG. 17 is a plan view showing an example in which the semiconductor chip of FIG. 16 is mounted on a substrate. 16 and 17, the semiconductor device 10 includes a substrate 12, a plurality of semiconductor chips 14P and 14Q fixed to the substrate 12, and a sealing resin 16 that seals the plurality of semiconductor chips 14P and 14Q. . The plurality of semiconductor chips fixed to the substrate 12 include a plurality of first semiconductor chips 14P and a second semiconductor chip 14Q.

複数（本実施例では２個）の第１の半導体チップ１４Ｐの各々は、図１の例の半導体チップ１４と同様に、その側面に下部側が上部側よりも大きい段付き部２６を有し、接着剤１８により基板１２に固定されている。接着剤１８は第１の半導体チップ１４Ｐの段付き部２６から第１の半導体チップ１４Ｐの段付き部２６の下の側面を覆って基板１２の表面にかけて延びる。また、ボンディングワイヤ２２が第１の半導体チップ１４Ｐの端子と基板１２の端子とを接続している。従って、図１６及び図１７の実施例の各第１の半導体チップ１４Ｐと基板１２との関係は、図１の半導体チップ１４と基板１２との関係と同様である。第１の半導体チップ１４Ｐは基板１２に直接接触しており、第１の半導体チップ１４Ｐと基板１２との間に接着剤が存在しない。従って、第１の半導体チップ１４Ｐの接着剤の水分の蒸発に起因するパッケージクラックが防止されている。基板１２は半導体チップ１４Ｐの下方の位置に貫通孔３８を有する。貫通孔３８は蒸気抜きの作用を行う。   Each of the plurality of (two in the present embodiment) first semiconductor chips 14P has a stepped portion 26 on its side surface, the lower side being larger than the upper side, like the semiconductor chip 14 in the example of FIG. It is fixed to the substrate 12 with an adhesive 18. The adhesive 18 extends from the stepped portion 26 of the first semiconductor chip 14P to the surface of the substrate 12 so as to cover the lower surface of the stepped portion 26 of the first semiconductor chip 14P. A bonding wire 22 connects the terminal of the first semiconductor chip 14 </ b> P and the terminal of the substrate 12. Therefore, the relationship between each first semiconductor chip 14P and the substrate 12 in the embodiment of FIGS. 16 and 17 is the same as the relationship between the semiconductor chip 14 and the substrate 12 in FIG. The first semiconductor chip 14P is in direct contact with the substrate 12, and no adhesive is present between the first semiconductor chip 14P and the substrate 12. Therefore, package cracks due to evaporation of moisture in the adhesive of the first semiconductor chip 14P are prevented. The substrate 12 has a through hole 38 at a position below the semiconductor chip 14P. The through-hole 38 performs a steam venting action.

第２の半導体チップ１４Ｑは複数の第１の半導体チップ１４Ｐの段付き部２６に載っていて、第１の半導体チップ１４Ｐを基板１２に固定させる接着剤１８により第１の半導体チップ１４Ｐに固定されている。実施例においては、２つの第１の半導体チップ１４Ｐがほぼ第２の半導体チップ１４Ｑのサイズと同等かそれよりもわずかに大きい間隔をあけて一直線上に配置されている。第２の半導体チップ１４Ｑは２つの第１の半導体チップ１４Ｐのそれぞれ一辺上の段付き部２６に載っていて、第１の半導体チップ１４Ｐを基板１２に固定させるその段付き部２６上の接着剤１８により第１の半導体チップ１４Ｐに固定されている。   The second semiconductor chip 14Q is mounted on the stepped portion 26 of the plurality of first semiconductor chips 14P, and is fixed to the first semiconductor chip 14P by an adhesive 18 that fixes the first semiconductor chip 14P to the substrate 12. ing. In the embodiment, the two first semiconductor chips 14P are arranged on a straight line with an interval substantially equal to or slightly larger than the size of the second semiconductor chip 14Q. The second semiconductor chip 14Q is mounted on the stepped portion 26 on one side of each of the two first semiconductor chips 14P, and the adhesive on the stepped portion 26 that fixes the first semiconductor chip 14P to the substrate 12. 18 is fixed to the first semiconductor chip 14P.

第２の半導体チップ１４Ｑは段付き部２６の高さだけ第１の半導体チップ１４Ｐよりも高い位置にあり、その２辺が２つの第１の半導体チップ１４Ｐに固定されている。第２の半導体チップ１４Ｑの端子はボンディングワイヤ２２Ｘにより第１の半導体チップ１４Ｐの端子に電気的に接続されている。また、封止樹脂１６は図１７に矢印で示されるように第２の半導体チップ１４Ｑと基板１２との間の空間に流れ、封止樹脂１６の一部が第２の半導体チップ１４Ｑと基板１２との間の空間を満たしている。この場合、封止樹脂１６の一部が第２の半導体チップ１４Ｑと基板１２との間の空間に存在しているが、封止樹脂は接着剤に比べると空気中の水分を吸収する量が少ないためパッケージクラックは生じにくい。   The second semiconductor chip 14Q is positioned higher than the first semiconductor chip 14P by the height of the stepped portion 26, and its two sides are fixed to the two first semiconductor chips 14P. The terminals of the second semiconductor chip 14Q are electrically connected to the terminals of the first semiconductor chip 14P by bonding wires 22X. Further, the sealing resin 16 flows into a space between the second semiconductor chip 14Q and the substrate 12 as shown by an arrow in FIG. 17, and a part of the sealing resin 16 is in the second semiconductor chip 14Q and the substrate 12. The space between is filled. In this case, a part of the sealing resin 16 exists in the space between the second semiconductor chip 14Q and the substrate 12, but the sealing resin absorbs moisture in the air compared to the adhesive. Package cracks are less likely to occur because there are few.

この場合、接着剤１８は、第１の半導体チップ１４Ｐを基板１２に固定させ、かつ、第１の半導体チップ１４Ｐを介して第２の半導体チップ１４Ｑを基板１２に固定させる。接着剤１８は、第２の半導体チップ１４Ｑを第１の半導体チップ１４Ｐの段付き部２６上の接着剤１８上に載せた後で加熱され、接着作用を実現する。接着剤１８が接着作用を実現するまで、第１の半導体チップ１４Ｐ及び第２の半導体チップ１４Ｑは図示しないツールによって保持される。なお、第１の半導体チップ１４Ｐは第２の半導体チップ１４Ｑを搭載する際の位置決めガイドとしての作用も有する。   In this case, the adhesive 18 fixes the first semiconductor chip 14P to the substrate 12 and fixes the second semiconductor chip 14Q to the substrate 12 via the first semiconductor chip 14P. The adhesive 18 is heated after placing the second semiconductor chip 14Q on the adhesive 18 on the stepped portion 26 of the first semiconductor chip 14P, thereby realizing an adhesive action. Until the adhesive 18 realizes an adhesive action, the first semiconductor chip 14P and the second semiconductor chip 14Q are held by a tool (not shown). The first semiconductor chip 14P also serves as a positioning guide when mounting the second semiconductor chip 14Q.

図１８は本発明の第４実施例による半導体装置を示す断面図である。図１９は図１８の半導体チップが基板に搭載された例を示す平面図である。図１８及び図１９においては、図１６及び図１７の例と同様に、半導体装置１０は、基板１２と、基板１２に固定された複数の半導体チップ１４Ｐ，１４Ｑと、複数の半導体チップ１４Ｐ，１４Ｑを封止する封止樹脂１６とからなる。基板１２に固定された複数の半導体チップは、複数の第１の半導体チップ１４Ｐと、第２の半導体チップ１４Ｑとを含む。   FIG. 18 is a sectional view showing a semiconductor device according to the fourth embodiment of the present invention. FIG. 19 is a plan view showing an example in which the semiconductor chip of FIG. 18 is mounted on a substrate. 18 and 19, the semiconductor device 10 includes a substrate 12, a plurality of semiconductor chips 14P and 14Q fixed to the substrate 12, and a plurality of semiconductor chips 14P and 14Q, as in the examples of FIGS. And a sealing resin 16 for sealing. The plurality of semiconductor chips fixed to the substrate 12 include a plurality of first semiconductor chips 14P and a second semiconductor chip 14Q.

複数（本実施例では４個）の第１の半導体チップ１４Ｐの各々は、図１の例の半導体チップ１４と同様に、その側面に下部側が上部側よりも大きい段付き部２６を有し、接着剤１８により基板１２に固定されている。接着剤１８は第１の半導体チップ１４Ｐの段付き部２６から第１の半導体チップ１４Ｐの段付き部２６の下の側面を覆って基板１２の表面にかけて延びる。また、ボンディングワイヤ２２が第１の半導体チップ１４Ｐの端子と基板１２の端子とを接続している。従って、図１８及び図１９の実施例の各第１の半導体チップ１４Ｐと基板１２との関係は、図１の半導体チップ１４と基板１２との関係と同様である。第１の半導体チップ１４Ｐは基板１２に直接接触しており、第１の半導体チップ１４Ｐと基板１２との間に接着剤が存在しない。従って、第１の半導体チップ１４Ｐの接着剤の水分の蒸発に起因するパッケージクラックが防止されている。基板１２は半導体チップ１４Ｐ及び第２の半導体チップ１４Ｑの下方の位置に貫通孔３８を有する。貫通孔３８は蒸気抜きの作用を行う。   Each of the plurality of (four in this embodiment) first semiconductor chips 14P has a stepped portion 26 on its side surface, the lower side of which is larger than the upper side, like the semiconductor chip 14 of the example of FIG. It is fixed to the substrate 12 with an adhesive 18. The adhesive 18 extends from the stepped portion 26 of the first semiconductor chip 14P to the surface of the substrate 12 so as to cover the lower surface of the stepped portion 26 of the first semiconductor chip 14P. A bonding wire 22 connects the terminal of the first semiconductor chip 14 </ b> P and the terminal of the substrate 12. Therefore, the relationship between each first semiconductor chip 14P and the substrate 12 in the embodiment of FIGS. 18 and 19 is the same as the relationship between the semiconductor chip 14 and the substrate 12 in FIG. The first semiconductor chip 14P is in direct contact with the substrate 12, and no adhesive is present between the first semiconductor chip 14P and the substrate 12. Therefore, package cracks due to evaporation of moisture in the adhesive of the first semiconductor chip 14P are prevented. The substrate 12 has a through hole 38 at a position below the semiconductor chip 14P and the second semiconductor chip 14Q. The through-hole 38 performs a steam venting action.

第２の半導体チップ１４Ｑは複数の第１の半導体チップ１４Ｐの段付き部２６に載っていて、第１の半導体チップ１４Ｐを基板１２に固定させる接着剤１８により第１の半導体チップ１４Ｐに固定されている。実施例においては、４つの第１の半導体チップ１４Ｐがほぼ第２の半導体チップ１４Ｑのサイズと同等かそれよりもわずかに大きい間隔をあけて互いに直交する２直線上に配置されている。第２の半導体チップ１４Ｑは４つの第１の半導体チップ１４Ｐのそれぞれ一辺上の段付き部２６に載っていて、第１の半導体チップ１４Ｐを基板１２に固定させるその段付き部２６上の接着剤１８により第１の半導体チップ１４Ｐに固定されている。   The second semiconductor chip 14Q is mounted on the stepped portion 26 of the plurality of first semiconductor chips 14P, and is fixed to the first semiconductor chip 14P by an adhesive 18 that fixes the first semiconductor chip 14P to the substrate 12. ing. In the embodiment, the four first semiconductor chips 14P are arranged on two straight lines that are orthogonal to each other with an interval substantially equal to or slightly larger than the size of the second semiconductor chip 14Q. The second semiconductor chip 14Q is mounted on the stepped portion 26 on one side of each of the four first semiconductor chips 14P, and the adhesive on the stepped portion 26 that fixes the first semiconductor chip 14P to the substrate 12. 18 is fixed to the first semiconductor chip 14P.

第２の半導体チップ１４Ｑは段付き部２６の高さだけ第１の半導体チップ１４Ｐよりも高い位置にあり、その４辺が４つの第１の半導体チップ１４Ｐに固定されている。第２の半導体チップ１４Ｑの端子はボンディングワイヤ２２Ｘにより第１の半導体チップ１４Ｐの端子に電気的に接続されている。この場合、第２の半導体チップ１４Ｑはその４辺が４つの第１の半導体チップ１４Ｐの段付き部２６に接着剤１８により固定されるので、樹脂封止の際に封止樹脂１６は第２の半導体チップ１４Ｑと基板１２との間の空間に流れこまず、第２の半導体チップ１４Ｑと基板１２との間には空間４０が形成される。この空間４０は貫通孔３８を介して基板１２の外部と連通している。従って、この実施例においても、第１及び第２の半導体チップ１４Ｐ，１４Ｑのパッケージクラックは生じにくい。   The second semiconductor chip 14Q is higher than the first semiconductor chip 14P by the height of the stepped portion 26, and its four sides are fixed to the four first semiconductor chips 14P. The terminals of the second semiconductor chip 14Q are electrically connected to the terminals of the first semiconductor chip 14P by bonding wires 22X. In this case, since the four sides of the second semiconductor chip 14Q are fixed to the stepped portions 26 of the four first semiconductor chips 14P by the adhesive 18, the sealing resin 16 is used when the resin is sealed. The space 40 is formed between the second semiconductor chip 14Q and the substrate 12 without flowing into the space between the semiconductor chip 14Q and the substrate 12. The space 40 communicates with the outside of the substrate 12 through the through hole 38. Accordingly, also in this embodiment, package cracks of the first and second semiconductor chips 14P and 14Q are unlikely to occur.

接着剤１８は、第１の半導体チップ１４Ｐを基板１２に固定させ、かつ、第１の半導体チップ１４Ｐを介して第２の半導体チップ１４Ｑを基板１２に固定させる。接着剤１８は、第２の半導体チップ１４Ｑを第１の半導体チップ１４Ｐの段付き部２６上の接着剤１８上に載せた後で加熱され、接着作用を実現する。接着剤１８が接着作用を実現するまで、第１の半導体チップ１４Ｐ及び第２の半導体チップ１４Ｑは図示しないツールによって保持される。なお、第１の半導体チップ１４Ｐは第２の半導体チップ１４Ｑを搭載する際の位置決めガイドとしての作用も有する。   The adhesive 18 fixes the first semiconductor chip 14P to the substrate 12 and fixes the second semiconductor chip 14Q to the substrate 12 via the first semiconductor chip 14P. The adhesive 18 is heated after placing the second semiconductor chip 14Q on the adhesive 18 on the stepped portion 26 of the first semiconductor chip 14P, thereby realizing an adhesive action. Until the adhesive 18 realizes an adhesive action, the first semiconductor chip 14P and the second semiconductor chip 14Q are held by a tool (not shown). The first semiconductor chip 14P also serves as a positioning guide when mounting the second semiconductor chip 14Q.

以上説明した実施例は以下の特徴を含む。
（付記１） 基板と、接着剤により該基板に固定された半導体チップと、該半導体チップを封止する封止樹脂とからなり、該半導体チップはその側面に下部側が上部側よりも大きい段付き部を有し、該接着剤は該半導体チップの段付き部から該基板に跨がって形成され、該半導体チップは少なくとも部分的に該基板に直接的に接触していることを特徴とする半導体装置。（１）
（付記２） 該半導体チップはワイヤにより基板に電気的に接続されることを特徴とする付記１に記載の半導体装置。
（付記３） 該接着剤は該半導体チップの全周に沿って設けられることを特徴とする付記１に記載の半導体装置。
（付記４） 該基板は半導体チップが固定された位置に貫通孔を有することを特徴とする付記１に記載の半導体装置。（２）
（付記５） 該基板の表面にはレジストが設けられており、該レジストは半導体チップの底面の外周部が位置する第１部分と、該第１部分よりも内側に位置する第２部分とを有し、該第２部分の厚さが該第１部分の厚さよりも薄く、半導体チップと該第２部分の間に空間が形成され、前記貫通孔は該空間に通じていることを特徴とする付記４に記載の半導体装置。（３）
（付記６） 基板と、接着剤により該基板に固定された複数の半導体チップと、該複数の半導体チップを封止する封止樹脂とからなり、該複数の半導体チップの中の複数の第１の半導体チップの各々がその側面に下部側が上部側よりも大きい段付き部を有し、該接着剤は該第１の半導体チップの段付き部から該基板にかけて延び、該第１の半導体チップは少なくとも部分的に該基板に直接的に接触しており、該複数の半導体チップの中の第２の半導体チップは該第１の半導体チップの段付き部に載っていて該第１の半導体チップを基板に固定させる接着剤により該第１の半導体チップに固定されることを特徴とする半導体装置。（４）
（付記７） 該第１の半導体チップはワイヤにより基板に電気的に接続され、該第２の半導体チップはワイヤにより該第１の半導体チップに電気的に接続されることを特徴とする付記６に記載の半導体装置。
（付記８） 該基板は該第１の半導体チップの下方に貫通孔を有することを特徴とする付記６に記載の半導体装置。
（付記９） 該第２の半導体チップは該複数の第１の半導体チップの間に配置され、該第２の半導体チップと基板の間には封止樹脂が存在することを特徴とする付記７に記載の半導体装置。
（付記１０） 該第２の半導体チップは該複数の第１の半導体チップの間に配置され、該第２の半導体チップと基板の間には空間が存在し、該基板は該空間と外部とを通じさせる貫通孔を有することを特徴とする付記９に記載の半導体装置。
（付記１１） 常温では固形で、加熱により溶融する接着性樹脂からなる接着剤を、側面に下部側が上部側よりも大きい段付き部を有する半導体チップの段付き部に載せ、該半導体チップを基板に搭載し、該接着剤を加熱して溶融させ、よって半導体チップを該接着剤により該基板に固定することを特徴とする半導体装置の製造方法。（５）
（付記１２） 該接着剤は常温では該半導体チップの段付き部に載る形状を有することを特徴とする付記１１に記載の半導体装置の製造方法。
（付記１３） 該接着剤は常温では該半導体チップの全周に沿って該半導体チップの段付き部に載る環状の形状を有することを特徴とする付記１２に記載の半導体装置の製造方法。 The embodiment described above includes the following features.
(Additional remark 1) It consists of a board | substrate, the semiconductor chip fixed to this board | substrate with the adhesive agent, and the sealing resin which seals this semiconductor chip, and this semiconductor chip has a step which the lower side is larger than the upper side in the side surface And the adhesive is formed to extend from the stepped portion of the semiconductor chip to the substrate, and the semiconductor chip is at least partially in direct contact with the substrate. Semiconductor device. (1)
(Supplementary note 2) The semiconductor device according to supplementary note 1, wherein the semiconductor chip is electrically connected to the substrate by a wire.
(Supplementary note 3) The semiconductor device according to supplementary note 1, wherein the adhesive is provided along the entire circumference of the semiconductor chip.
(Supplementary note 4) The semiconductor device according to supplementary note 1, wherein the substrate has a through hole at a position where the semiconductor chip is fixed. (2)
(Supplementary Note 5) A resist is provided on the surface of the substrate, and the resist includes a first portion where the outer peripheral portion of the bottom surface of the semiconductor chip is located, and a second portion located inside the first portion. A thickness of the second portion is smaller than a thickness of the first portion, a space is formed between the semiconductor chip and the second portion, and the through hole communicates with the space. The semiconductor device according to appendix 4. (3)
(Supplementary Note 6) A substrate, a plurality of semiconductor chips fixed to the substrate with an adhesive, and a sealing resin that seals the plurality of semiconductor chips, and a plurality of first chips in the plurality of semiconductor chips. Each of the semiconductor chips has a stepped portion on its side surface, the lower side being larger than the upper side, and the adhesive extends from the stepped portion of the first semiconductor chip to the substrate, and the first semiconductor chip is At least partially in direct contact with the substrate, and a second semiconductor chip of the plurality of semiconductor chips is mounted on a stepped portion of the first semiconductor chip, and the first semiconductor chip is A semiconductor device, wherein the semiconductor device is fixed to the first semiconductor chip with an adhesive fixed to a substrate. (4)
(Supplementary note 7) The supplementary note 6, wherein the first semiconductor chip is electrically connected to the substrate by a wire, and the second semiconductor chip is electrically connected to the first semiconductor chip by a wire. A semiconductor device according to 1.
(Supplementary note 8) The semiconductor device according to supplementary note 6, wherein the substrate has a through-hole below the first semiconductor chip.
(Supplementary Note 9) The supplementary note 7 is characterized in that the second semiconductor chip is disposed between the plurality of first semiconductor chips, and a sealing resin exists between the second semiconductor chip and the substrate. A semiconductor device according to 1.
(Supplementary Note 10) The second semiconductor chip is disposed between the plurality of first semiconductor chips, and there is a space between the second semiconductor chip and the substrate. The semiconductor device according to appendix 9, wherein the semiconductor device has a through hole.
(Additional remark 11) Adhesive which consists of adhesive resin which is solid at normal temperature and fuse | melts by heating is mounted on the step part of the semiconductor chip which has a step part in which the lower side is larger than the upper side in a side surface, and this semiconductor chip is board | substrate A method for manufacturing a semiconductor device, comprising: mounting the semiconductor chip on the substrate and melting the adhesive by heating, whereby the semiconductor chip is fixed to the substrate by the adhesive. (5)
(Additional remark 12) The manufacturing method of the semiconductor device of Additional remark 11 characterized by this adhesive having the shape mounted in the step part of this semiconductor chip at normal temperature.
(Additional remark 13) The manufacturing method of the semiconductor device of Additional remark 12 characterized by this adhesive having the cyclic | annular shape mounted on the step part of this semiconductor chip along the perimeter of this semiconductor chip at normal temperature.

図１は本発明の第１実施例による半導体装置を示す断面図である。FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention. 図２は図１の半導体チップを示す平面図である。FIG. 2 is a plan view showing the semiconductor chip of FIG. 図３は図２の半導体チップを示す側面図である。FIG. 3 is a side view showing the semiconductor chip of FIG. 図４は側面に段付き部を有する半導体チップを形成する例を示す図である。FIG. 4 is a diagram showing an example of forming a semiconductor chip having a stepped portion on the side surface. 図５は使用前の接着剤の例を示す平面図である。FIG. 5 is a plan view showing an example of an adhesive before use. 図６は図５の接着剤が半導体チップの段付き部に載せられた状態を示す側面図である。FIG. 6 is a side view showing a state where the adhesive of FIG. 5 is placed on the stepped portion of the semiconductor chip. 図７は図６の半導体チップを基板に搭載する工程の例を示す図である。FIG. 7 is a diagram showing an example of a process of mounting the semiconductor chip of FIG. 6 on a substrate. 図８は使用前の接着剤の他の例を示す平面図である。FIG. 8 is a plan view showing another example of the adhesive before use. 図９は接着剤が半導体チップに塗布される例を示す平面図である。FIG. 9 is a plan view showing an example in which an adhesive is applied to a semiconductor chip. 図１０は本発明の第２実施例による半導体装置を示す断面図である。FIG. 10 is a sectional view showing a semiconductor device according to a second embodiment of the present invention. 図１１は図１０の基板を示す断面図である。FIG. 11 is a cross-sectional view showing the substrate of FIG. 図１２は図１０の半導体チップが基板に搭載された例を示す断面図である。12 is a cross-sectional view showing an example in which the semiconductor chip of FIG. 10 is mounted on a substrate. 図１３は半導体チップと基板の間に空間を設けるために窪みが形成された基板の例を示す平面図である。FIG. 13 is a plan view showing an example of a substrate in which a recess is formed to provide a space between the semiconductor chip and the substrate. 図１４は半導体チップと基板の間に空間を設けるために窪みが形成された基板の例を示す平面図である。FIG. 14 is a plan view showing an example of a substrate in which a recess is formed in order to provide a space between the semiconductor chip and the substrate. 図１５は半導体チップと基板の間に空間を設けるために窪みが形成された基板の例を示す平面図である。FIG. 15 is a plan view showing an example of a substrate in which a recess is formed to provide a space between the semiconductor chip and the substrate. 図１６は本発明の第３実施例による半導体装置を示す断面図である。FIG. 16 is a sectional view showing a semiconductor device according to a third embodiment of the present invention. 図１７は図１６の半導体チップが基板に搭載された例を示す平面図である。FIG. 17 is a plan view showing an example in which the semiconductor chip of FIG. 16 is mounted on a substrate. 図１８は本発明の第４実施例による半導体装置を示す断面図である。FIG. 18 is a sectional view showing a semiconductor device according to the fourth embodiment of the present invention. 図１９は図１８の半導体チップが基板に搭載された例を示す平面図である。FIG. 19 is a plan view showing an example in which the semiconductor chip of FIG. 18 is mounted on a substrate.

符号の説明Explanation of symbols

１０ 半導体装置
１２ 基板
１４ 半導体チップ
１４Ｐ 第１の半導体チップ
１４Ｑ 第２の半導体チップ
１６ 封止樹脂
１８ 接着剤
２０ レジスト
２２ ボンディングワイヤ
２４ はんだボール
２６ 段付き部
２８ 半導体ウエハ
３０ ダイシングブレード
３２ ダイシングブレード
３４ 保持ツール
３６ ディスペンサ
３８ 貫通孔
４０ 空間 DESCRIPTION OF SYMBOLS 10 Semiconductor device 12 Substrate 14 Semiconductor chip 14P 1st semiconductor chip 14Q 2nd semiconductor chip 16 Sealing resin 18 Adhesive 20 Resist 22 Bonding wire 24 Solder ball 26 Stepped part 28 Semiconductor wafer 30 Dicing blade 32 Dicing blade 34 Holding Tool 36 Dispenser 38 Through hole 40 Space

Claims (5)

基板と、接着剤により該基板に固定された半導体チップと、該半導体チップを封止する封止樹脂とからなり、該半導体チップはその側面に下部側が上部側よりも大きい段付き部を有し、該接着剤は該半導体チップの段付き部から該基板に跨がって形成され、該半導体チップは該基板に直接接触していることを特徴とする半導体装置。   A substrate, a semiconductor chip fixed to the substrate with an adhesive, and a sealing resin that seals the semiconductor chip, the semiconductor chip having a stepped portion on the side surface of which the lower side is larger than the upper side The semiconductor device is characterized in that the adhesive is formed so as to straddle the substrate from the stepped portion of the semiconductor chip, and the semiconductor chip is in direct contact with the substrate. 該基板は半導体チップが固定された位置に貫通穴を有することを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the substrate has a through hole at a position where the semiconductor chip is fixed. 該基板の表面にはレジストが設けられており、該レジストは半導体チップの底面の外周部が位置する第１部分と、該第１部分よりも内側に位置する第２部分とを有し、該第２部分の厚さが該第１部分の厚さよりも薄く、半導体チップと該第２部分の間に空間が形成され、前記貫通孔は該空間に通じていることを特徴とする請求項２に記載の半導体装置。   A resist is provided on the surface of the substrate, and the resist has a first portion where the outer peripheral portion of the bottom surface of the semiconductor chip is located, and a second portion located inside the first portion, 3. The thickness of the second portion is smaller than the thickness of the first portion, a space is formed between the semiconductor chip and the second portion, and the through hole communicates with the space. A semiconductor device according to 1. 基板と、接着剤により該基板に固定された複数の半導体チップと、該複数の半導体チップを封止する封止樹脂とからなり、該複数の半導体チップの中の複数の第１の半導体チップの各々がその側面に下部側が上部側よりも大きい段付き部を有し、該接着剤は該第１の半導体チップの段付き部から該基板にかけて延び、該第１の半導体チップは少なくとも部分的に該基板に直接的に接触しており、該複数の半導体チップの中の第２の半導体チップは該第１の半導体チップの段付き部に載っていて該第１の半導体チップを基板に固定させる接着剤により該第１の半導体チップに固定されることを特徴とする半導体装置。   A substrate, a plurality of semiconductor chips fixed to the substrate by an adhesive, and a sealing resin that seals the plurality of semiconductor chips, and a plurality of first semiconductor chips in the plurality of semiconductor chips Each has a stepped portion on its side surface, the lower side being larger than the upper side, the adhesive extending from the stepped portion of the first semiconductor chip to the substrate, and the first semiconductor chip is at least partially The substrate is in direct contact with the substrate, and a second semiconductor chip of the plurality of semiconductor chips is mounted on a stepped portion of the first semiconductor chip and fixes the first semiconductor chip to the substrate. A semiconductor device, wherein the semiconductor device is fixed to the first semiconductor chip with an adhesive. 常温では固形で、加熱により溶融する接着性樹脂からなる接着剤を、側面に下部側が上部側よりも大きい段付き部を有する半導体チップの段付き部に載せ、該半導体チップを基板に搭載し、該接着剤を加熱して溶融させ、よって半導体チップを該接着剤により該基板に固定することを特徴とする半導体装置の製造方法。   An adhesive made of an adhesive resin that is solid at normal temperature and melts by heating is placed on a stepped portion of a semiconductor chip having a stepped portion on the side that is larger on the lower side than on the upper side, and the semiconductor chip is mounted on a substrate, A method of manufacturing a semiconductor device, wherein the adhesive is heated and melted, whereby the semiconductor chip is fixed to the substrate by the adhesive.
JP2004293377A 2004-10-06 2004-10-06 Semiconductor device and manufacturing method of semiconductor device Expired - Fee Related JP4709521B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004293377A JP4709521B2 (en) 2004-10-06 2004-10-06 Semiconductor device and manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004293377A JP4709521B2 (en) 2004-10-06 2004-10-06 Semiconductor device and manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JP2006108409A true JP2006108409A (en) 2006-04-20
JP4709521B2 JP4709521B2 (en) 2011-06-22

Family

ID=36377768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004293377A Expired - Fee Related JP4709521B2 (en) 2004-10-06 2004-10-06 Semiconductor device and manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JP4709521B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017044492A (en) * 2015-08-24 2017-03-02 京セラ株式会社 Sensor and joint structure

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5279775A (en) * 1975-12-26 1977-07-05 Toshiba Corp Semiconductor device
JPS59181025A (en) * 1983-03-31 1984-10-15 Toshiba Corp Semiconductor device
JPH01179351A (en) * 1987-12-30 1989-07-17 Fujitsu Ltd Plastic-molded semiconductor device and its manufacture
JPH02278857A (en) * 1989-04-20 1990-11-15 Fujitsu Ltd Resin-sealed type semiconductor device
JPH0620627A (en) * 1992-07-02 1994-01-28 Noritake Co Ltd Fluorescent character display tube
JPH07153787A (en) * 1993-11-29 1995-06-16 Mitsubishi Electric Corp Compression-bonded semiconductor device and manufacture thereof
JPH09172029A (en) * 1995-12-19 1997-06-30 Hitachi Ltd Semiconductor chip, manufacturing method thereof and semiconductor device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5279775A (en) * 1975-12-26 1977-07-05 Toshiba Corp Semiconductor device
JPS59181025A (en) * 1983-03-31 1984-10-15 Toshiba Corp Semiconductor device
JPH01179351A (en) * 1987-12-30 1989-07-17 Fujitsu Ltd Plastic-molded semiconductor device and its manufacture
JPH02278857A (en) * 1989-04-20 1990-11-15 Fujitsu Ltd Resin-sealed type semiconductor device
JPH0620627A (en) * 1992-07-02 1994-01-28 Noritake Co Ltd Fluorescent character display tube
JPH07153787A (en) * 1993-11-29 1995-06-16 Mitsubishi Electric Corp Compression-bonded semiconductor device and manufacture thereof
JPH09172029A (en) * 1995-12-19 1997-06-30 Hitachi Ltd Semiconductor chip, manufacturing method thereof and semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017044492A (en) * 2015-08-24 2017-03-02 京セラ株式会社 Sensor and joint structure

Also Published As

Publication number Publication date
JP4709521B2 (en) 2011-06-22

Similar Documents

Publication Publication Date Title
KR100323644B1 (en) Semiconductor device
US8253258B2 (en) Semiconductor device with hollow and throughhole and method of manufacturing same
JP4828164B2 (en) Interposer and semiconductor device
JP2003273145A (en) Semiconductor device
US20100252923A1 (en) Semiconductor device and method of manufacturing same
US8810016B2 (en) Semiconductor device, substrate and semiconductor device manufacturing method
JP2009130195A (en) Semiconductor light emitting device
KR100825784B1 (en) Semiconductor package suppressing a warpage and wire open defects and manufacturing method thereof
US7554194B2 (en) Thermally enhanced semiconductor package
JP2009158801A (en) Method of manufacturing semiconductor device, and semiconductor device
JP2009105209A (en) Electronic device and method of manufacturing the same
JP2008085002A (en) Semiconductor device and its manufacturing method
JP2006339595A (en) Semiconductor device
JP2008140894A (en) Semiconductor device and its manufacturing method
JP4312616B2 (en) Semiconductor device
JP4709521B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP2007258448A (en) Semiconductor device
JP5020051B2 (en) Semiconductor device
JP2009010208A (en) Compound lead frame and semiconductor device using compound lead frame
KR100737217B1 (en) Substrateless flip chip package and fabricating method thereof
JP5289921B2 (en) Semiconductor device and method for manufacturing semiconductor device
JP2013110188A (en) Semiconductor device and manufacturing method of the same
JP2007042702A (en) Semiconductor device
JP2008034446A (en) Semiconductor device, and manufacturing method thereof
JP4863836B2 (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070906

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20080730

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090820

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090825

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091021

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20100706

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101005

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20101013

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110308

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110318

R150 Certificate of patent or registration of utility model

Ref document number: 4709521

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees