JP2006099331A5 - - Google Patents

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Publication number
JP2006099331A5
JP2006099331A5 JP2004283529A JP2004283529A JP2006099331A5 JP 2006099331 A5 JP2006099331 A5 JP 2006099331A5 JP 2004283529 A JP2004283529 A JP 2004283529A JP 2004283529 A JP2004283529 A JP 2004283529A JP 2006099331 A5 JP2006099331 A5 JP 2006099331A5
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Japan
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interrupt
processing
state
main
sub
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JP2004283529A
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English (en)
Japanese (ja)
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JP4345630B2 (ja
JP2006099331A (ja
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Priority to JP2004283529A priority Critical patent/JP4345630B2/ja
Priority claimed from JP2004283529A external-priority patent/JP4345630B2/ja
Priority to CNB2005800014874A priority patent/CN100549964C/zh
Priority to PCT/JP2005/017646 priority patent/WO2006035728A1/ja
Priority to US10/580,848 priority patent/US8584125B2/en
Publication of JP2006099331A publication Critical patent/JP2006099331A/ja
Publication of JP2006099331A5 publication Critical patent/JP2006099331A5/ja
Application granted granted Critical
Publication of JP4345630B2 publication Critical patent/JP4345630B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2004283529A 2004-09-29 2004-09-29 情報処理装置、割り込み処理制御方法、並びにコンピュータ・プログラム Expired - Fee Related JP4345630B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2004283529A JP4345630B2 (ja) 2004-09-29 2004-09-29 情報処理装置、割り込み処理制御方法、並びにコンピュータ・プログラム
CNB2005800014874A CN100549964C (zh) 2004-09-29 2005-09-26 信息处理设备、中断处理控制方法
PCT/JP2005/017646 WO2006035728A1 (ja) 2004-09-29 2005-09-26 情報処理装置、割り込み処理制御方法、並びにコンピュータ・プログラム
US10/580,848 US8584125B2 (en) 2004-09-29 2005-09-26 Apparatuses, methods, and computer-readable media for interrupt control

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004283529A JP4345630B2 (ja) 2004-09-29 2004-09-29 情報処理装置、割り込み処理制御方法、並びにコンピュータ・プログラム

Publications (3)

Publication Number Publication Date
JP2006099331A JP2006099331A (ja) 2006-04-13
JP2006099331A5 true JP2006099331A5 (https=) 2007-10-25
JP4345630B2 JP4345630B2 (ja) 2009-10-14

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Family Applications (1)

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JP2004283529A Expired - Fee Related JP4345630B2 (ja) 2004-09-29 2004-09-29 情報処理装置、割り込み処理制御方法、並びにコンピュータ・プログラム

Country Status (4)

Country Link
US (1) US8584125B2 (https=)
JP (1) JP4345630B2 (https=)
CN (1) CN100549964C (https=)
WO (1) WO2006035728A1 (https=)

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US8180997B2 (en) * 2007-07-05 2012-05-15 Board Of Regents, University Of Texas System Dynamically composing processor cores to form logical processors
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US20100169572A1 (en) * 2008-07-22 2010-07-01 Lsi Corporation Data storage method, apparatus and system for interrupted write recovery
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WO2012086106A1 (ja) * 2010-12-21 2012-06-28 パナソニック株式会社 仮想計算機システム及び仮想計算機システム制御方法
US8695010B2 (en) 2011-10-03 2014-04-08 International Business Machines Corporation Privilege level aware processor hardware resource management facility
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US11755484B2 (en) 2015-06-26 2023-09-12 Microsoft Technology Licensing, Llc Instruction block allocation
US9952867B2 (en) 2015-06-26 2018-04-24 Microsoft Technology Licensing, Llc Mapping instruction blocks based on block size
US10191747B2 (en) 2015-06-26 2019-01-29 Microsoft Technology Licensing, Llc Locking operand values for groups of instructions executed atomically
US10409606B2 (en) 2015-06-26 2019-09-10 Microsoft Technology Licensing, Llc Verifying branch targets
US10175988B2 (en) 2015-06-26 2019-01-08 Microsoft Technology Licensing, Llc Explicit instruction scheduler state information for a processor
US9946548B2 (en) 2015-06-26 2018-04-17 Microsoft Technology Licensing, Llc Age-based management of instruction blocks in a processor instruction window
US10169044B2 (en) 2015-06-26 2019-01-01 Microsoft Technology Licensing, Llc Processing an encoding format field to interpret header information regarding a group of instructions
US10409599B2 (en) 2015-06-26 2019-09-10 Microsoft Technology Licensing, Llc Decoding information about a group of instructions including a size of the group of instructions
US10346168B2 (en) 2015-06-26 2019-07-09 Microsoft Technology Licensing, Llc Decoupled processor instruction window and operand buffer
US10768936B2 (en) 2015-09-19 2020-09-08 Microsoft Technology Licensing, Llc Block-based processor including topology and control registers to indicate resource sharing and size of logical processor
US11126433B2 (en) 2015-09-19 2021-09-21 Microsoft Technology Licensing, Llc Block-based processor core composition register
US11016770B2 (en) 2015-09-19 2021-05-25 Microsoft Technology Licensing, Llc Distinct system registers for logical processors
CN105786607B (zh) * 2016-03-24 2019-11-12 宇龙计算机通信科技(深圳)有限公司 一种多系统的冻结与唤醒方法及装置
US11531552B2 (en) 2017-02-06 2022-12-20 Microsoft Technology Licensing, Llc Executing multiple programs simultaneously on a processor core
US11625267B2 (en) * 2017-08-02 2023-04-11 Felica Networks, Inc. Information processing apparatus and information processing method for changing contents of a process to be performed after an interrupt is detected
JP6814756B2 (ja) * 2018-02-08 2021-01-20 日立オートモティブシステムズ株式会社 ハイパーバイザ、演算装置
CN112286847B (zh) * 2020-11-05 2023-03-10 成都菁蓉联创科技有限公司 一种提升系统外部中断响应速度的方法、装置和控制器
CN119487492A (zh) * 2022-07-19 2025-02-18 三菱电机株式会社 可编程逻辑控制器、定序控制系统及激活状态控制程序

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