JP2006093735A - Substrate extracting method and method of manufacturing electronic component using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a new method of manufacturing an electronic component, which does not consume a material in vain for evaluating the material. <P>SOLUTION: The method of manufacturing electronic component, in which electronic component is formed by performing a plurality of work processes to sample, comprises a process of extracting a part of a surface of the sample at the end of work process and performing at least one of monitoring, inspecting, and analyzing the progress of the work in the work processes to the part of the surface. According to the present invention, the sample such as a wafer can be evaluated without wastefully cutting it, and the production yield of the electronic component is improved. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present application relates to a method for manufacturing an electronic component such as a semiconductor device, and a sample preparation device for realizing the method for manufacturing the electronic component.

  In the manufacture of electronic components such as semiconductor devices such as memories and microcomputers, and magnetic heads of hard disks, it is required to continue to produce good products without hesitation. Since the number of products produced is large, the occurrence of defects in a certain process directly leads to a decrease in product yield and production line shutdown, greatly affecting profitability. However, since it is rare that the product can be produced without any defective product, and a certain amount of defective product is always generated, how to detect defects, foreign matter, processing defects early, and how quickly to take countermeasures is important. It becomes a problem. For this reason, for example, at the manufacturing site of semiconductor devices, careful inspection is performed after a specific process or after the device is completed, and efforts are made to eradicate defective products and to investigate the cause of defective parts. In the actual manufacturing process, in the case of wafers, thoroughly inspect the completed wafer, and if there are abnormal parts such as circuit pattern defects or foreign matter, discard the device or investigate the cause of the abnormality. The method is performed.

JP-A-5-52721

In order to efficiently manage so as not to produce defective products regarding the manufacture of electronic parts as described above, the following problems to be solved remain.
(1) Routine TEM observation (problem of TEM sample preparation)
Usually, a high-resolution scanning electron microscope (hereinafter abbreviated as SEM) is used to observe the appearance of a sample. However, as semiconductors are highly integrated, the object becomes so fine that it cannot be observed with SEM resolution. Yes. Instead of SEM, a transmission electron microscope (hereinafter abbreviated as TEM) with high observation resolution has to be relied upon. In order to continue producing good products, the key point is how easily TEM can be used as a routine work. However, in order to use TEM routinely, there are major problems that need to be solved. It is a sample preparation method.

Cleaving the conventional TEM sample preparation, cutting, and sample such as mechanical grinding with the task of the small pieces, always cleaving forced if the sample is a wafer. Moreover, work that requires skill and time, such as polishing and ion singing, continues. Even if the sample shape was completed, the probability that the pinpoint portion of interest was accurately captured and desired observation was very small.

  Recently, there is an example using focused ion beam (hereinafter abbreviated as FIB) processing. This is by cutting out approximately 3 × 0.1 × 0.5 mm (0.5 mm is the thickness of the wafer) strip-shaped pellets including a region to be observed from a sample such as a wafer using a dicing apparatus. A part of this strip-shaped pellet is FIB processed into a thin wall to obtain a TEM sample. The cross-sectional shape of the FIB-processed TEM observation sample may be an inverted T-shape or an L-shape, and may be variously modified. This is because it is processed into a thin wall shape. Although this method makes it possible to locate a desired observation portion at the μm level, the wafer must still be cleaved.

  As described above, using TEM as a means to monitor the finish of a process in the middle of manufacturing has great advantages in terms of observation and decomposition, but it is cleaved for only a few inspections in relation to TEM sample preparation. The wafer fragments cannot be used in the next process and must be disposed of. Such an expensive large-diameter wafer is very uneconomical because the processes performed so far must be wasted. For example, FIG. 2 shows a state in which wafers are charged in a conventional process and the number of wafers is reduced during inspection in each process. If, for example, four inspections are performed after the processes s3, s6, s8, and s11 from the process s1 to the process s11, since one wafer is consumed for each inspection, the inspection wafers 16A, 16B, 16C, Since 16D is extracted from the lot, if the initial lot 15 is, for example, 10 pieces, the final lot 15′D has 6 pieces. In other words, if the number of inspections is large, the number of final acquired wafers decreases, leading to a decrease in the yield of non-defective parts.

On the other hand, there is a method capable of producing a sample without dividing the wafer. This method is disclosed in Japanese Patent Application Laid-Open No. 05-52721 “a method for separating a sample and a method for analyzing a separated sample obtained by this separation method”. In this method, as shown in FIG. 2, first, the posture of the sample 20 is maintained so that the FIB 29 irradiates the surface of the sample 20 at a right angle, and the FIB 29 is scanned in a rectangular shape on the sample, and a required depth is formed on the sample surface. The square hole 21 is formed (FIG. 3A). Next, the sample is tilted so that the FIB axis with respect to the sample surface is tilted by about 70 ° to form the bottom hole 22. The sample inclination angle is changed by a sample stage (not shown) (FIG. 3B). The orientation of the sample is changed, the sample is placed so that the surface of the sample is again perpendicular to the FIB, and a notch groove 23 is formed (FIG. 2 (c)). A manipulator (not shown) is driven, and the tip of the probe 54 at the tip of the manipulator is brought into contact with a portion where the sample 20 is separated (FIG. 3 (d)). A deposition gas 26 is supplied from the gas nozzle 25, and FIB is locally irradiated to a region including the tip of the probe to form an ion beam assisted deposition film (hereinafter abbreviated as a deposition film 27). The separated portion of the sample in contact with the tip of the probe 24 is connected by a deposition film 26 (FIG. 3 (e)). The remaining part is cut out with FIB 29 (FIG. 3 (f)), and the separated sample 28 is cut out from the sample 20. The cut out separated sample 28 is supported by the connected probe 24 (FIG. 3 (g)). When this separated sample 28 is processed by FIB in the same manner as in the second conventional method and a region to be observed is wall processed, a TEM sample (not shown) is obtained. This is a method of separating a micro sample piece including a desired analysis region from a sample such as a wafer by using FIB processing and a micro sample transport means. Analysis can be performed by introducing a micro sample separated by this method into various analyzers. However, in this method, in order to separate a micro sample, the sample is tilted as much as about 70 ° and the FIB is obliquely irradiated. Considering the distance between the objective lens and the sample required from the FIB focusing property, such a large inclination deteriorates the FIB performance, and it is expected that satisfactory processing cannot be performed. In order to maintain the performance of the FIB device that is normally used, the limit is about 60 °. In addition, it is very difficult mechanically to tilt a large-diameter wafer sample stage having a diameter of 300 mm as much as 70 °. Even if a large inclination of 70 ° is possible, the bottom surface of the extracted sample has an inclination of 70 °, and when placed on a horizontal sample holder, the original sample surface is inclined by 20 ° with respect to the sample holder surface. However, it becomes difficult to form a cross section or wall substantially perpendicular to the wall.
In order to form a cross section or wall that is almost perpendicular to the surface of the sample substrate, it is essential to reduce the inclination of the bottom surface and make the bottom surface parallel to the surface. To this end, the sample inclination must be increased further. However, this has the problem that it becomes more difficult due to the limitations on the apparatus described above.

For this reason, in order to improve the yield of non-defective parts acquisition, it is possible to extract the analysis area without cutting the wafer and with a feasible device configuration as a sample preparation device, suitable for various analysis including TEM. It has been desired to establish a manufacturing method that can be processed into a single sample.
(2) Module process and step-by-step inspection In the manufacturing of electronic components, if the quality is judged at the final stage, it is difficult to investigate the cause of the failure when it occurs. It takes a lot of time and effort to complete a countermeasure product with a revised process condition. On the other hand, it is preferable to monitor and inspect each product in order to realize the early commercialization of good products. However, if each process is inspected one by one for every process, the inspection time will be enormous, and the inspection will take place. The number of devices is enormous, and it is contrary to the objective of making a good product at a low price early.

Therefore, the whole process is divided into several groups (modules) of two (about two or more and less than ten), and one of the wafer lots for which the process of the module is completed is inspected. However, if the wafer is divided and inspected for each inspection as in the prior art, the number of wafers obtained in the final process will be small. For example, if 10 lots are used and there are 5 monitoring locations in the entire process, the number of wafers remaining in the final process is at most 5. Since the good chips are selected from the five wafers, the ratio (yield) of the good chips finally obtained with respect to the initial ten wafers becomes very low. However, according to the device manufacturing method according to the present application, since the new method of (1) is adopted, 10 wafers per lot remain until the final process, and only a few chips can be completely unusable due to an intermediate inspection. . The wafer to be inspected is specified in the lot, and if the chip to be inspected is specified, a minimum of several chips are damaged by the inspection. These specific numerical values differ depending on the manufacturing site. For example, if it is determined that one arbitrary position in the wafer is sufficient, it is determined that one place is sufficient, and the influence of the distribution in the wafer plane must always be checked. If this is the case, there will be five locations, four at the wafer central portion and the peripheral portion at 90 ° pitch.
Thus, it depends on the judgment of the line manager in consideration of the location and number required for the inspection, and the time required for the inspection.

  Incidentally, as a method for performing an inspection monitor by extracting a device to be inspected from a wafer, there is "Japanese Patent Laid-Open No. 4-111338" Device manufacturing method using device punching inspection monitor method ". Japanese Patent Laid-Open No. 4-111338 discloses a method in which a unit device is partially punched from an inspection monitor substrate, and a process inspection monitor is performed using the punched device. The feature of this method is that a device part to be inspected is punched out through the substrate. Accordingly, a through hole remains in the punched substrate. However, a semiconductor process cannot be performed on a wafer having such a through-hole, for example, a dummy unit device is returned to a punching place as described in this known example. Even so, it can be easily determined by those skilled in the art of semiconductor manufacturing that it is impossible to return the punching place without a gap so as to withstand semiconductor manufacturing with submicron processing.

  In view of the above problems, a first object of the present application is to provide a new electronic component manufacturing method that does not waste materials for evaluation, and a second object is to provide the first object. An object of the present invention is to provide an electronic component manufacturing system for achieving the above.

As described above, when monitoring the progress of the process, a portion of only a few μm to 10 μm is extracted from the surface of the wafer where the elements are present without generating large irregularities on the wafer, and this is adapted to various analysis means. Although it is preferable to process into the shape to which it is applied, if the sample preparation apparatus as disclosed in Japanese Patent Laid-Open No. 05-52721 imposes a prohibitive burden, the apparatus cost increases and the apparatus performance decreases. Therefore, a novel micro sample (micro sample) which is a part of the present application that can extract a portion of only several μm to several tens of μm from the surface without crushing the wafer without giving a large load to the structure of the sample preparation device. The above-mentioned problems are solved by applying the manufacturing technology of (2) and adopting a technique for reassessing the manufacturing process and evaluating the wafer sequentially for a series of processes without cleaving the wafer. In other words, the point of the electronic component manufacturing method according to the present application is (a) using a microsampling method in which a microsample of about several tens of μm is extracted from a wafer and processed into a sample most suitable for various analysis means including TEM. In addition, (b) the whole process for manufacturing electronic components is divided into several groups, and a new evaluation method for evaluating a plurality of conventional continuous processes at once is used. In other words, the concept of modular process is adopted.
That is, the module process refers to a series of processes in which a part of an electronic component to be manufactured is collected. When manufacturing a similar electronic component, the entire process is not all the same, but may be repeated frequently or a partially common process may continue. If the series of processes is modularized, the module has versatility and can be applied to the production of other parts. In FIG. 4, it is assumed that the electronic component manufacturing process is continuous from process s1 to process s11. Actually, it goes through more processes, but it is omitted here. In FIG. 4, a group from process s1 to process s4 is a module process m1, and hereinafter, process s4 to s5 is module process m2, process s6 to process s8 is module process m3, and process s9 to process s11 are modules. This is an example of process m4. The above (a) will be described in detail in the third embodiment below.

In other words, in order to achieve the first object, specifically,
(1) An electronic component manufacturing method for forming an electronic component by subjecting a sample to a plurality of processing processes, wherein a part of the surface of the sample is extracted at the end of the processing process, and the processing process is performed on the part of the surface. An electronic component manufacturing method including a step of performing at least one of monitoring or inspection or analysis of the progress of processing in
(2) An electronic component manufacturing method in which a plurality of processing processes are performed on a sample to form an electronic component, and a part of the sample surface is extracted at the end of a plurality of predetermined continuous processing processes. An electronic component manufacturing method including a step of performing at least one of monitoring, inspection or analysis of the progress of the processing in the continuous processing process on the surface, or (3) performing a plurality of processing processes on the sample An electronic component manufacturing method for forming an electronic component, wherein a partial surface of the sample is extracted at the end of a predetermined specific processing process, and processing progress to the specific processing process is performed on the partial surface. Electronic component manufacturing method including a step of performing at least one of monitoring or inspection or analysis, or (4) forming a plurality of processing processes on the sample to form the electronic component An electronic component manufacturing method, wherein the entire processing process up to the completion of the electronic component is divided into a plurality of module processes composed of a plurality of continuous processing processes, and a partial surface of the sample is formed at the end of the module process. An electronic component manufacturing method including a step of extracting and monitoring at least one of inspection or analysis of the progress of processing in the module process on the partial surface, or (5) a plurality of samples An electronic component manufacturing method in which a plurality of processing processes are applied to each sample as a lot to form an electronic component, and the entire processing process up to the completion of the electronic component is a plurality of modules composed of a plurality of continuous processing processes. Divide into processes, and at the end of each module process, extract a part of the surface of a specific sample in the lot, Serial may be used an electronic component manufacturing method comprising the step of performing at least one of monitor or test or analyze the progress of machining with respect to a portion of the surface by the module process.
In any one of the above (1) to (5), (6) the sample is a silicon semiconductor wafer, an epitaxially grown silicon wafer, a wafer having a silicon thin film formed on a substrate, a compound semiconductor wafer, or a magnetic head integrated wafer. Or
(7) The electronic component is any one of a silicon semiconductor device, a compound semiconductor device, a magnetic recording / reproducing head, and a magneto-optical recording / reproducing head, or (8) a partial surface of the sample is extracted. The step of performing includes at least the removal of the sample by irradiation of an energy beam and the attachment of the sample to be extracted to the transport unit, or (9) the inspection is performed in a shape, size, Either a method of judging whether the module process is good or bad by comparing at least one of element distribution, element concentration, impurity distribution, and impurity concentration with a predetermined standard, or (10) The inspection is transparent A scanning electron microscope, a scanning transmission electron microscope, a scanning electron microscope, or a scanning probe microscope, or (11) the monitor Comparing the physical number obtained by irradiating at least one of electron beam, ion beam, X-ray, and laser light at a predetermined location with the predetermined standard one after another, and grasping the achievement level of the module process Or (12) the analysis is performed by elemental analysis using at least one of an electron beam, an ion beam, and an X-ray, and at least one of a predetermined reference element distribution or element concentration, impurity distribution, and impurity concentration. Compare with any of the good or bad, or
(13) The above analysis may clarify the cause of the deviation from at least one of a predetermined reference shape, dimension, element distribution, element concentration, impurity distribution, and impurity concentration at a predetermined location, or (14 ) At least one of the monitor and the data obtained in the inspection or analysis step is stored in at least a computer, or (15) the region obtained by extracting the partial surface is stored in the computer. A method of storing and excluding an electronic component including a region where the partial surface is extracted after completion of the whole processing process, or (16) To prevent contamination by an ion source when extracting the partial surface A rare gas, particularly Ar gas, is used as an ion source. Unlike gallium (Ga), this gas is not a metal, so it is difficult to become a source of contamination.
A method may be used in which the original substrate extracted using this ion source is put into a target module process.
In addition, the specific process in (3) is, in particular, (17) an etching step in which an opening is provided in the sample.
(18) It may be a film forming process in which a film is provided on at least a part of the sample or a hole is filled.
Furthermore, one of the module processes in the above (4) or (5) is a series of processes up to the completion of gate electrode production in the (19) silicon semiconductor memory process, or (20) in the silicon semiconductor memory process. It may be a series of processes from the completion of the production of the gate electrode to the completion of the production of the plug electrode connected to the silicon substrate, or (21) a series of processes for forming the metal wiring in the silicon semiconductor memory process.
In addition, the step of performing at least one of the monitor or inspection or analysis in any one of (1) to (5) above,
(22) the step of evaluating the cross-sectional shape of the contact hole in the semiconductor device, or
(23) a step of evaluating a gate oxide film in a semiconductor device, or
(24) It may be a step of evaluating the operating characteristics of a single transistor in a semiconductor device.
Furthermore, in particular,
(25) In the above (8), the energy beam may be at least one of a focused ion beam, a projection ion beam, an electron beam, and a laser beam,
(26) In the above (15), when the data stored in the computer and the predetermined standard are not satisfied by comparing the data, the computer is subject to the processing conditions of the target module process. May be accompanied by a step of instructing to correct.

In order to achieve the second object,
(27) A focused ion beam irradiation optical system, a secondary particle detector for detecting secondary particles generated from the wafer by the focused ion beam irradiation, a sample stage on which the wafer is placed, and the wafer What is necessary is just a structure which has at least the transfer part which transfers the excised sample which isolate | separated one part surface of this to another member. In particular,
(28) In the above (27), the transport unit may be configured by a mechanism that can move in the XYZ axis directions and a needle-like member that contacts the sample to be extracted.

  By using the electronic component manufacturing method according to the present application, evaluation can be performed without cleaving the wafer, and an expensive wafer is not wasted. As a result, the manufacturing yield of electronic components is improved.

An embodiment of an electronic component manufacturing method according to the present application is an electronic component manufacturing method in which a plurality of processing processes are performed on a sample to form an electronic component. In the processing process, a part including the substrate surface of the sample is extracted, The step of monitoring or inspecting or analyzing the progress of the processing in the above-described processing process on a part including the substrate surface and the part including the substrate surface are removed, and then the substrate is further processed. There is a method of manufacturing a return circuit pattern.
<Embodiment 1>
In this embodiment, the basic flow of the electronic component manufacturing method according to the present application will be described together with the flow of the wafer with reference to FIG.
The lot 1 input to the module process m1 selects a predetermined number of lots 1 as the inspection sample 2 after completion of the module process m1, and the remaining sample 3 stands by. A portion 4 to be inspected is extracted as a microsample 5 from the selected inspection sample 2. The inspection sample 2 from which the minute sample 5 has been extracted is incorporated into the remaining sample 3 again, and is put into the next module process m2 as a lot 1A. Here, the microsample 5 is processed so as to be compatible with various analysis devices 6, sent to the analysis device 6 through the path f, and the portion of interest of the microsample 5 is analyzed. The analysis result is sent to the computer 7 and stored as a database. The stored database is transmitted to the module process m1 or the module process m2 through the communication path h as necessary, and commands such as changing process conditions are given. As described above, a major feature is that the wafer passes through the paths a, b, c, and d during the period from the module process m1 to the module process m2, and the minute sample to be analyzed is extracted during that time. In addition, the number of samples is not decreased by the inspection, and the number of samples of lot 1 to be input to the module process m1 and lot 1 to be input to the module process m2 is the same. In addition, the extraction method (path | route e) of the microsample 5 is explained in full detail in Example 2 below. In the figure, symbols ma and mb indicate paths between module processes.

The basic flow has been described above. Here, the entire module process flow will be described with reference to FIG.
In FIG. 5, reference numerals s21, s22, s23, and s24 denote module processes. First, the number of wafers in one lot 40 put into the module process s21 is, for example, 10 here. The lot that has completed step s21 is divided into an inspection wafer 41A and a remaining wafer group 42A (path a), and the inspection wafer 41A is sent to a sample preparation apparatus (not shown) (path b) for inspection. A micro sample 43A at the μm level is extracted from the wafer 41A for use. The extracted wafer 41A is combined with the original wafer group 42A, or is combined with other wafer groups as a lot 40A (path c) and sent to the next module process m22. The lot 40A at this time is the same as the original lot 40 because the sample was prepared without cleaving the wafer 41A. That is, even if one of the modules is completed and assigned for inspection, it can be sent to the next module process m22 without reducing the number of lots. On the other hand, the extracted microsample 43A is processed into an analysis sample 44A suitable for various analysis apparatuses, for example, TEM (path d), in a sample preparation apparatus, and subjected to various types of analysis, for example, TEM observation. Analysis data such as the observed shape at this time is sent to and stored in a common computer (not shown), and is used for optimization of process conditions and correction of fluctuations in the process m21.

  Hereinafter, the wafer flow after the completion of the module process m22 is the same as the wafer flow after the completion of the module process m21. 41B, 41C, 41D instead of the wafer 41A, and 42B, 42C, 42D instead of the wafer group 42A. The whole process can be understood by replacing 43B, 43C and 43D instead of the micro sample 43A and 44B, 44C and 44D instead of the analysis sample 44A. This process completes the entire electronic component manufacturing process.

  In all the processes, there is a step of inspecting the completeness of each module process. When a defective part is found in a certain module process, the information is immediately calculated by a computer (reference numeral 7 in FIG. 1) that manages this process. And an instruction is transmitted so as to correct the condition of the corresponding process of the corresponding module process, and the generation of the defective portion is improved by correcting the process condition. Also, the inspection location can be obtained without cleaving the wafer, and the extracted wafer is introduced into the next process. Therefore, even after all module processes are completed, the number of wafer lots 40D changes from the first lot 40. There is no wasteful disposal of the wafer, and the economic effect is great.

A sample preparation method for extracting the microsample 43 from the wafer 41 and processing it into a sample suitable for various analysis apparatuses will be described in Example 2, and the sample preparation apparatus will be described in Example 3.
<Embodiment 2>
In this embodiment, a method for extracting a micro sample from a predetermined location on a wafer and processing it into a sample suitable for various analyzers will be described.

  In order to extract a micro sample from a sample substrate, it is essential to separate the micro sample from the substrate, which involves a process of separating the surface that becomes the bottom surface of the extracted sample from the substrate. In the separation method using FIB disclosed in Japanese Patent Application Laid-Open No. 05-52721, since the FIB is incident on the substrate surface from the oblique direction and processed, the ion beam incident angle at the time of separation and the bottom surface of the extracted sample piece are A slope consisting of the processing aspect ratio is added. In the known example, the sample is tilted as much as about 70 ° in order to separate (form a bottom hole).

Considering the distance between the objective lens and the sample required from the FIB focusing property, such a large inclination deteriorates the FIB performance, and it is expected that satisfactory processing cannot be performed. In order to maintain the performance of the FIB device that is normally used, the limit is about 60 °. In addition, it is very difficult mechanically to tilt a large-diameter wafer sample stage having a diameter of 300 mm as much as 70 °. Even if a large inclination of 70 ° is possible, the bottom surface of the extracted sample has an inclination of 70 °, and when placed on a horizontal sample holder, the original sample surface is inclined by 20 ° with respect to the sample holder surface. However, it becomes difficult to form a cross section or wall substantially perpendicular to the wall. In order to form a cross section or wall that is almost perpendicular to the surface of the sample substrate, it is essential to reduce the inclination of the bottom surface and make the bottom surface parallel to the surface. To this end, the sample inclination must be increased further. Rather, this becomes more difficult due to the device limitations described above. Therefore, in order to place the extracted sample as intended in this application on another member (sample holder) and introduce it to another observation device or analysis device, another separation method capable of forming a vertical section must be considered. I must. (However, in Japanese Patent Laid-Open No. 05-52721, the separated sample is not placed on a sample holder, but is observed while attached to the probe of the conveying means, so the shape of the bottom surface does not affect.)
Under such circumstances, the sample preparation method according to the present application can realize extraction of a minute sample without tilting the sample stage extremely greatly. Furthermore, since the thickness of the extracted sample (same as the thickness direction of the wall) can be processed thinly, the wall processing time can be greatly reduced.

  Below, the specific procedure of the sample preparation method by this application is demonstrated. Here, a method for preparing a sample to be observed by TEM will be taken as an example of the sample, and a method for performing everything from marking a portion to be prepared for TEM sample to final wall processing in the FIB apparatus will be described. Further, in order to clarify the procedure, it will be described below with reference to FIG.

  FIG. 6A: In this sample preparation method, an extracted sample including a TEM observation region is first prepared, and thus there is a risk that the formation position of the wall that is the TEM observation portion cannot be specified after extraction from the sample substrate. For this reason, marking for specifying the observation position is required. If the sample is still in the state of a wafer or chip, the position can be determined from CAD data, etc., and the position can be confirmed from the optical microscope image and FIB SIM image. For the marking, for example, marks 130 are applied to both ends forming the observation cross section by FIB processing, laser processing, or the like.

  In this example, two + (plus) marks 130 are provided at intervals of 10 μm across the observation region. The sample stage is rotated and adjusted in advance so that the straight line connecting the two marks 130 is parallel to the tilt axis of the sample stage. Two rectangular holes 132 were provided by FIB 131 on both sides of the two marks 130 on a straight line connecting the two marks 130. The opening size is, for example, about 10 × 7 μm, the depth is about 15 μm, and the interval between both rectangular holes is 30 μm. Both were processed with a large current FIB having a diameter of about 0.15 μm and a current of about 10 nA in order to complete in a short time. The processing time was approximately 7 minutes.

  FIG. 6B: Next, a width of about 2 μm and a length of about 30 μm are separated from the straight line connecting the marks 130 by about 2 μm and intersect with one rectangular hole but not with the other rectangular hole. Then, an elongated vertical groove 133 having a depth of about 10 μm is formed. The scanning direction of the beam 131 is set so as not to fill a vertical groove or a large rectangular hole formed by sputtered particles generated when the FIB irradiates the sample. A small region that does not intersect with one rectangular hole 132 becomes a support portion 134 that supports a sample to be extracted later.

  FIG. 6C: After the steps of FIGS. 6A and 6B, the sample surface is inclined slightly (15 ° in this embodiment). Here, since the straight line connecting the two marks 130 is set parallel to the tilt axis of the sample stage, it is tilted in such a direction that the vertical groove 133 rises. Therefore, the elongated hole having a width of approximately 2 μm, a length of approximately 32 μm, and a depth of approximately 15 μm is formed so as to connect the rectangular holes 132 at a distance of about 2 μm from the straight line connecting the marks 130 and on the opposite side of the elongated groove. A groove 135 is formed. Avoid filling rectangular holes and grooves formed by sputtered particles by FIB irradiation. The oblique groove 135 is formed by the FIB obliquely incident on the sample substrate surface, and intersects the previously formed vertical groove 133. 6A to 6C, the support portion 134 is left and the wedge-shaped extraction sample having a right triangle section with a vertex angle of 15 ° is held in a cantilever state, leaving the mark 130. become. Here, the inclination angle of the sample stage has been described as being 15 °, but it is not limited to 15 °. However, (1) Mechanical structure and strength when tilting the sample stage, (2) Reduction of peripheral processing amount when forming oblique grooves, and shortening the processing time, (3) Substrate after sample extraction (wafer ) Reduction of the remaining holes in (4), (4) Prevention of mechanical strength reduction of the substrate due to the formed holes, (5) Difficult to form deep holes by sputtered particles near the groove bottom when forming oblique grooves Therefore, the sample stage should be inclined as low as possible, the depth of the oblique groove should be reduced, and the inclination angle should be sufficient to satisfy the shortening of the processing time and the miniaturization of the sample to be extracted and the hole to be formed. The inclination angle is preferably 45 ° or less, and more preferably 5 ° or more and 30 ° or less. Therefore, in the method, it is not necessary to make the stage as large as 70 ° as in Japanese Patent Laid-Open No. 05-52721, and it is not necessary to form a through hole in the substrate as in Japanese Patent Laid-Open No. 4-111338, and the necessary part. Can be extracted in a short time without affecting the substrate.

  FIG. 6D: Next, the sample stage is returned to the horizontal position, and the probe 137 at the tip of the transfer means is brought into contact with the end opposite to the support portion 134 of the sample 136 to be extracted. The contact can be detected by the conduction between the sample and the probe 137 and the capacitance change between the two. In addition, in order to avoid damaging the sample 136 and the probe 137 to be extracted by careless pressing of the probe 137, the probe 137 has a function of stopping driving in the + Z direction when the probe 137 contacts the sample. Next, in order to fix the probe 137 to the sample 136 to be extracted, the FIB 131 is scanned while allowing the deposition gas to flow out into an area of about 2 μm square including the tip of the probe 137. In this way, the deposition film 138 is formed in the FIB irradiation region, and the probe 137 and the sample 136 to be extracted are connected.

  6 (e) (f): In order to extract the extracted sample from the sample substrate, the supporting portion 134 is irradiated with FIB and sputtered to release the supporting state. Since the support part 134 is 2 μm square and about 10 μm deep when viewed from above the sample surface, it can be removed by the FIB 131 scan for 2 to 3 minutes.

  The extracted sample 139 connected to the tip of the probe 137 is moved to the sample holder. In practice, the sample stage is moved to move the sample holder into the FIB scanning region. At this time, in order to avoid an unexpected accident, the probe 137 may be retracted in the + Z direction. Here, the sample holder is installed in various forms as will be described later. In this example, it is assumed that the sample holder is installed on a side entry type TEM stage.

  6 (g) (h): When the sample holder enters the FIB scanning area, the movement of the sample stage is stopped, and the probe 137 is moved in the −Z direction (in the direction of the sample stage) to approach the sample holder 140. FIG. When the extracted sample 139 comes into contact with the sample holder 140, the extracted sample 139, the sample holder 140, and the contact portion are irradiated with the FIB 131 while introducing the deposition gas. By this operation, the extracted sample can be connected to the sample holder 140. In this example, the deposition film 142 was formed on the end surface of the extracted sample 139 in the longitudinal direction. The FIB irradiation area is about 3 μm square, part of the deposition film 142 is attached to the sample holder 140 and part is attached to the side of the extracted sample, and both are connected. In order to securely fix the extracted sample 139 to the TEM sample, an elongated groove 141 having a size of about 2 × 25 μm and a depth of about 3 μm is formed in advance by the FIB 131 on the extracted sample fixing surface of the sample holder 140, and the extracted sample is placed in the elongated groove. After the insertion of the 139 by the transfer means, if the deposition film 142 is formed on the end surface of the extracted sample 139, the extracted sample 139 can be reliably fixed.

  In addition, it is desirable that the observation area of the sample be arranged on the rotation center axis of the side entry sample stage. However, since the sample to be fixed is as small as several μm to 20 μm, It is arranged so that the fixed surface is on the axis of the side entry sample stage. With such a configuration, the sample can be easily placed in the observation field.

  At this time, the side entry type sample stage axis is set parallel to the tilt axis of the general-purpose stage. Since it is not necessary to rotate the direction of the sample extracted by this configuration, it is not necessary to provide a complicated mechanism for the transfer means. Furthermore, by installing a side entry type sample stage, it is possible to introduce it into the TEM immediately after processing, and when additional machining is required, there is an effect that processing can be performed immediately in the FIB apparatus.

  FIG. 6 (i): Next, after stopping the introduction of the deposition gas, FIB is irradiated to the deposition film 138 connecting the probe 137 and the extracted sample 139, and the probe 137 is removed by sputtering. The sample 139 can be separated from the sample 139, and the extracted sample 139 stands on the sample holder 140.

  FIG. 6 (j): Finally, FIB irradiation is performed, and finally the observation region is thinly processed so as to become a wall 143 having a thickness of about 100 nm or less to obtain a TEM sample. At this time, since one of the side surfaces in the longitudinal direction of the sample to be extracted is a vertical surface, when determining the FIB irradiation area for wall processing, the vertical surface is used as a reference, so that the wall substantially perpendicular to the sample substrate surface can be obtained. 143 can be formed. Prior to FIB irradiation, an FIB deposit film may be formed on the upper surface including the wall 143 formation region in order to process the wall surface more planarly. This method is already well known. As a result of the above processing, a wall having a width of about 15 μm and a depth of about 10 μm can be formed, and a TEM observation region is completed. As described above, the time from marking to completion of wall processing was shortened to about one hour and 30 minutes compared with the conventional TEM sample preparation method. Further, the size of the extracted sample is as small as about 2 to 4 μm in width, 15 to 30 μm in length, and 15 to 20 μm in height, and is an inspection device formed by punching out a substrate in Japanese Patent Laid-Open No. 4-111338. It can be seen that it is overwhelmingly smaller than the size of.

After wall processing in this manner, the side entry type TEM stage is pulled out and introduced into the TEM sample chamber. At this time, the TEM stage is rotated and inserted so that the electron beam path and the wall surface intersect perpendicularly. Since the subsequent TEM observation technique is well known, the sample preparation procedure omitted here is not limited to the TEM sample but can be used for other analysis and observation techniques.

  The sample preparation method according to the present application and the sample separation method according to Japanese Patent Laid-Open No. 05-52721 are significantly different from each other in (1) the beam irradiation method at the time of sample extraction (separation), and the extracted sample is made as thin as possible. In order to simplify the separation of the bottom surface, the side surface in the longitudinal direction (parallel to the TEM observation surface) is inclined, and (2) the extracted sample is fixed to a sample holder that is a separate member from the transfer means. (3) The target portion can be extracted with a low inclination of 45 ° or less without greatly inclining the sample stage.

  Another difference from the inspection monitoring method disclosed in Japanese Patent Laid-Open No. 4-111338 is that the wafer surface is extracted about 10 μm without punching out the substrate (wafer) and forming a through hole. Since the sample to be extracted is on the micron level, the processing time is very short.

  In this way, by using this sample preparation method, a desired location can be marked on the spot for TEM observation without taking the sample substrate out of the device without manual operation from a device chip or semiconductor wafer. And other samples for analysis / measurement / observation can be prepared.

<Embodiment 3>
FIG. 7 is a schematic configuration diagram of an embodiment of a sample preparation apparatus used when a microsample is extracted from a sample in the electronic component manufacturing method according to the present application and processed into a test piece suitable for various analysis apparatuses.

  The sample preparation device 71 includes a FIB irradiation optical system 72 that processes and observes the sample substrate and the extracted sample, a secondary particle detector 73 that detects secondary electrons and secondary ions emitted from the sample by this FIB irradiation, and FIB irradiation. A deposition gas source 74 for supplying a source material gas for forming a deposition film in a region, a sample stage 75 for mounting a sample substrate 72 such as a semiconductor wafer or a semiconductor chip, and a minute extracted sample obtained by extracting a part of the sample substrate A sample holder 76 for fixing the sample holder, a holder cassette 77 for holding the sample holder, a transfer means 78 for transferring the extracted sample to the sample holder, and the like, and stage control for controlling the position of the sample stage 75 The apparatus 80, the transfer means controller 81 for driving the transfer means 78, the sample holder 76, the sample substrate 82, the transfer means 78, etc. are visualized. The image display means 83, the FIB control device 84 of the FIB irradiation optical system 2, and the like are also configured. In addition, the deposition gas source control device 85, the stage control device 86, the image display means 83, the transfer means control device 81, and the like are calculated. It is controlled by the device 87.

  The FIB irradiation optical system 72 forms an FIB 94 having a diameter of about 10 nm to 1 μm by passing ions emitted from the liquid metal ion source through a beam limiting aperture, a focusing lens, and an objective lens. The FIB 94 is scanned on the sample substrate 82 using a deflector, so that the sample substrate 82 can be processed in a scanning shape from the μm level to the sub-μm level. Processing here refers to a concave portion formed by sputtering, a convex portion formed by FIB assist deposition, or an operation for changing the shape of the sample substrate by combining these. The deposition film formed by FIB irradiation is used to connect the contact portion at the tip of the transfer means 78 and the sample substrate 82 or to fix the extracted sample to the sample holder. In addition, the processing region and the like can be observed by detecting secondary electrons and secondary ions generated during the FIB irradiation with the secondary particle detector 73 and imaging them.

  The sample stage 75 is installed in the sample chamber 88, and the FIB irradiation optical system 73 and the like are also arranged in the vacuum container. A holder cassette 77 carrying a sample holder 76 can be attached to and detached from the sample stage 75, and movement, tilting, and rotation in a three-dimensional (X, Y, Z) direction are controlled by a stage control device 80.

Hereinafter, each part of the sample preparation apparatus 71 according to the present application (the transfer means 78 and its installation location, the installation location of the sample holder 76 and the form of the sample holder 6 itself, the method and means for installing the extracted sample on the sample holder 76, and the sample stage) The details will be described.
The schematic configuration of the extracted sample transfer means will be described. The transfer means 78 is composed of a motor, a gear, a piezoelectric element, etc. in FIG. 7, and has a moving resolution of several μm with a stroke of about 1 μm.

  According to a known technique (Japanese Patent Laid-Open No. 4-111338), the transport means for transporting the separated sample is configured with three bimorph piezoelectric elements corresponding to the XYZ axes, but the installation position of the transport means is unknown. Therefore, it can be read that it is installed on the stage from FIG. 3 of the above publication. Thus, when the transfer means is installed on the sample stage, when the target sample is at the center of a wafer having a diameter of 300 mm, for example, the movement stroke of the transfer means tip is from the transfer means position to the desired location of the sample. Since it is far smaller than the distance, it has a fatal problem that it cannot be reached by the transfer means installed on the sample stage. Furthermore, in the configuration of the above-described bimorph piezoelectric element with three axes, the bimorph piezoelectric element moves so that the other end bends with one end as a fulcrum, and the other end draws an arc according to the applied voltage. That is, in the movement in the XY plane, the probe at the tip of the transport means does not move linearly in one axial direction by the operation of one bimorph piezoelectric element. Accordingly, the three bimorph piezoelectric elements must be controlled in a complicated manner in order to form the fine movement portion with the three bimorph piezoelectric elements and move the probe tip to a desired position. On the other hand, it is sufficient to use a three-axis driving means that can accurately drive linearly. However, if the moving means is configured with a mechanism having a long stroke of 100 μm to several mm and a resolution of the order of μm, the mechanism is It becomes complicated and interferes with other structures such as a secondary particle detector and a deposit gas source around the sample, and this causes another problem.

  In view of the above, in the present application, the transfer means 78 includes a coarse moving portion having a high moving speed and a large stroke in order to realize quick sampling from any arbitrary position even if the sample substrate is a large-diameter wafer. And a fine moving portion having a high moving resolution having a stroke equivalent to the moving resolution of the coarse moving portion, and the entire transfer means is installed independently of the sample stage. I was assigned to move.

  The tip of the transfer means 78 was connected to a probe 68 formed of a thin tungsten wire having a diameter of about 50 μm. By applying a voltage to the bimorph piezoelectric element 67, the tip of the probe 68 finely moves.

The moving means 78 is installed on the ceiling surface of the sample chamber 88 using the space of the sample chamber.
There is an advantage peculiar to this configuration that it can cope with different device configurations.
FIG. 7 shows an example in which the FIB irradiation optical system 72 is installed on the final lens electrode surface of the objective lens. The space of the sample chamber 88 is used, and there is an advantage that the external appearance of the apparatus can be simply summarized without applying an extra device to the outside of the apparatus and being applied to other complicated models.

  Various other arrangement examples are conceivable, but the basic idea of this configuration is that the transfer means is arranged at a position where the sample does not contact the transfer means by moving the sample independently of the sample stage. The sample to be removed should be easily accessible regardless of the central part and the peripheral part of the large-diameter wafer.

  The sample holder 6 is a member for transferring and directly fixing the sample 70 extracted from the sample substrate 82. The sample holder 76 is mounted on the sample stage 75 via a holder cassette 7 or the like that supports the sample holder 76, or the sample stage. It is mounted on a side entry type stage independent of 5. The sample stage refers to a general-purpose large stage on which a wafer can be placed or a small stage to which a device chip can be mounted.

  The sample holder 76 is mounted on a holder cassette 77 that can be easily attached to and detached from the sample stage 75, and further mounted on the sample stage 75, or mounted on a wafer cassette that puts a wafer in a special container and puts it in and out of the apparatus. One or more sample holders 6 may be mounted on one holder cassette 7. The number of holder cassettes 7 that can be installed on the sample stage 5 may be one or more. FIG. 7 shows the case where there is one cassette holder 7 and five sample holders 6. When three extracted samples are fixed to one sample holder, 15 TEM samples are placed in one holder cassette. Can be made.

  The holder cassette 77 can be slidably attached to the sample stage 75 and can be taken out of the vacuum container independently of the sample stage 5 without breaking the vacuum in the sample chamber 88 using an operation rod (not shown). it can. Further, in this method, a large number of TEM samples can be continuously produced from a single sample substrate 5, and a large number can be obtained at a time when taken out of the vacuum vessel. Moreover, since the TEM sample fixed to the sample holder can be held in the storage together with the holder cassette, it is not necessary to exhaust the nerves in handling the small TEM sample. Furthermore, a method is also possible in which a cassette holder in which a large number of samples that have been extracted and have not been wall-finished is fixed is carried into another FIB apparatus and the finishing of the wall machining is performed exclusively.

  The wafer cassette is a dedicated tray for storing a single wafer and does not directly touch the wafer with equipment parts or human hands. Moreover, it can be taken in and out of various process devices as it is, and is also used for movement between devices. As shown in FIG. 10, by making the holder cassette 7 detachable from the wafer cassette 95, it is possible to obtain a plurality of sample holders 6 on which processed TEM samples are mounted at the time of wafer replacement. Further, the correspondence between the wafer cassette 95 and the holder cassette 7, the correspondence between the holder cassette 7 and the sample holder 6 mounted thereon, and the correspondence between the sample holder 6 and the extracted sample 70 fixed thereto are always managed. By doing so, it is possible to easily relate the relationship between the information obtained when performing observation, measurement, analysis, etc., such as TEM observation, and the extraction position of the wafer 12.

<Embodiment example 4>
In the present embodiment, as an example of a module process, a process procedure for a plug forming module will be described, and attention points to be analyzed by extracting a microsample from a predetermined location will be described. FIG. 8A shows a process that is missing from the fabrication of the gate to the completion of plug formation. Reference numerals s101 to s112 denote SiN film deposition, interlayer insulating film coating, interlayer insulating film surface polishing, photoresist coating, exposure, development, interlayer insulating film etching, SiN film etching, ion implantation, ashing, polycrystalline Si embedding, and interlayer insulation. It corresponds to each process performed serially such as film surface polishing.
However, the number of processes in this series of steps is not limited to this number. Through such a series of processes, the plug is completed. FIGS. 8B to 8G are cross-sectional views of the semiconductor device in typical steps in the series of processes shown in FIG. In common with FIGS. (B) to (g), the Si substrate 100 partially has an oxide film region 101, and the gate and 102 have already been formed by the previous process. FIG. (B) shows a state in which an insulating layer SiN film is formed. Next, an interlayer insulating film 104 is applied to the entire surface as shown in FIG. After the post-treatment such as heating is performed on the applied interlayer insulating film 104, the interlayer insulating film 104 is partially dry etched to provide an opening 105 as shown in FIG. Subsequently, the SiN film on the bottom surface of the opening 105 is dry-etched to form a contact hole 106 (FIG. (E)).
Next, polycrystalline Si 107 is buried in the contact hole 106 (FIG. (F)). Finally, the interlayer insulating film 104 and the polycrystalline Si 107 exposed on the surface are planarized by a technique such as chemical mechanical polishing to form a flat surface 108, thereby completing a desired polycrystalline Si plug 109.

  The plug is completed through such a process, but the evaluation of the completed plug has many evaluations such as contact between the plug 109 and the Si substrate, plug shape, plug size, relative position of the plug on the Si substrate, SiN film thickness, and so on. However, if the above evaluation is performed after the completion of processes s3, 6, 9, 12, etc. using the conventional method (Figure (a)), the total evaluation time increases as the number of evaluations increases. In this case, each time the wafer must be cleaved, there is a problem that the remaining wafer of the lot is reduced. Therefore, in this embodiment, the evaluation items are collectively performed in the state shown in FIG. (G) in which the steps from process s1 to s12, that is, the plug module process is completed. For evaluation, a part of the wafer is extracted using a microsampling method, a sample is prepared so that the shape as shown in Fig. (G) can be observed with TEM, and plugging is performed in one observation by TEM observation. Many items such as contact between 109 and the Si substrate, plug shape, plug size, relative position of the plug on the Si substrate, and SiN film thickness can be evaluated at a time. In addition, since the wafer remaining after the microsampling can be input to the next module process, there is an advantage that the number of wafers is not reduced.

  In the present embodiment, the plug module process has been described. However, other module processes, for example, the gate module process from the surface oxidation to the completion of gate fabrication on the first Si substrate, wiring formation, wiring and wiring between the Si substrate, and between the wiring The metal module process for connecting and the like, and the capacitor module process for forming the capacitor may be analyzed by the same method.

The figure for demonstrating the flow of the wafer in the module process in connection with the electronic component manufacturing method by this application. The figure for demonstrating the flow which isolate | separates a micro sample from the conventional sample. The figure for demonstrating the example of a flow in connection with the conventional electronic component manufacturing method. The figure for demonstrating a module process especially by the flow in connection with the electronic component manufacturing method by this application. The figure for demonstrating the flow of the wafer in the module process in connection with the electronic component manufacturing method by this application. The figure for demonstrating the sample preparation method in connection with the electronic component manufacturing method by this application. The schematic block diagram which shows one Embodiment of the sample preparation apparatus concerning the electronic component manufacturing method by this application. The figure for demonstrating the specific example of the module process in connection with the electronic component manufacturing method by this application.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Lot, 2 ... Sample for inspection, 3 ... Sample, 4 ... 5 ... Micro sample, 7 ... Computer, 20 ... Sample, 21 ... Square hole, 22 ... Bottom hole, 23 ... Notch groove, 24 ... Probe, 26 ..., 27 ... Deposition membrane, 29 ... FIB
40 ... Lot, 41 ... Wafer, 42 ... Wafer group, 43 ... Micro sample, 44 ... Analyzed sample, 71 ... Sample preparation apparatus, 72 ... FIB irradiation optical system, 73 ... Secondary particle detector, 74 ... Depo gas source, 75 ... Sample stage, 76 ... Sample holder, 77 ... Holder cassette, 78 ... Transfer means, 80 ... Stage control device, 81 ... Transfer means control device, 82 ... Sample substrate, 83 ... Image display means, 84 ... FIB control device, 85 DESCRIPTION OF SYMBOLS ... Depogas source control apparatus, 86 ... Stage control apparatus, 87 ... Calculation processing apparatus, 88 ... Sample chamber, 100 ... Si substrate, 101 ... Oxide film, 102 ... Gate, 103 ... SiN film, 104 ... Interlayer insulation film, 105 ... Opening, 106 ... Contact hole, 107 ... Polycrystalline Si, 108 ... Flat surface, 109 ... Polycrystalline Si plug.

Claims (11)

  A first processing step of a process of manufacturing a circuit pattern on a substrate, and a part of the substrate manufactured by irradiating a predetermined portion with an ion beam using a part of the pattern manufactured in the processing step after the processing step. And a second process of returning the partially separated substrate to the process of manufacturing a circuit pattern.   2. The electronic component manufacturing method according to claim 1, wherein the step of separating includes a step of relatively rotating the ion beam and the sample stage.   2. The method of manufacturing an electronic component according to claim 1, wherein the step of separating the substrate includes processing so as to leave at least half of the thickness of the sample.   2. The method of manufacturing an electronic component according to claim 1, wherein an argon beam is used as the ion beam.   A step of carrying the sample into the sample chamber and positioning the sample on a sample stage; a step of specifying a position for processing a part of the sample; and a part of the substrate from the sample by irradiating a part of the specified sample with an ion beam A substrate extraction method including a step of separating the substrate and a step of taking the separated substrate out of the sample.   6. The substrate extraction method according to claim 5, wherein the steps of taking out include a step of fixing the separated substrate to a probe, and a step of moving the probe and replacing the substrate with a sample holder.   6. The substrate extraction method according to claim 5, wherein an argon beam is used as the ion beam.   An electronic component manufacturing method for manufacturing an element through a plurality of semiconductor processes using a plurality of substrates, comprising a monitoring substrate for monitoring a process state in the plurality of substrates, and ending the first manufacturing process An electronic component manufacturing method comprising: a step of sometimes extracting a part of the monitoring substrate; a step of starting a second manufacturing process for the extracted monitoring substrate; and a step of inspecting the extracted substrate.   9. The method of manufacturing an electronic component according to claim 8, wherein, as the extracting step, a wedge shape having a width narrowed in a depth direction of the substrate is extracted.   9. The electronic component manufacturing method according to claim 8, wherein the extracting step includes a step of fixing the extracted substrate to a probe, and a step of moving the probe to replace the substrate with a sample holder. 9. The method of manufacturing an electronic component according to claim 8, wherein an ion beam is used in the extracting step.

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