JP2006093252A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can easily control a switching element without making a chip large in size. <P>SOLUTION: The semiconductor device 10 is provided with bonding pads 11 and 12 and a thermosensitive element 14. The thermosensitive element 14 is provided with a first element 14a which is formed so as to connect the bonding pads 11 and 12, a second element 14b which is formed so as to surround the outer circumference of the bonding pad 11 from one end of the first element 14a, and a third element 14c which is formed so as to surround the bonding pad 12 from the other end of the first element 14a in the reverse direction to the direction surrounding the second element 14b, when the semiconductor 10 is viewed from the upper side. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device.

  Currently, semiconductor devices using power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), and the like, which are easy to drive, are widely used as power control switching elements. Some of such semiconductor devices have a built-in function (control unit) for controlling the switching element for the purpose of detecting the state of the switching element.

For example, in Patent Document 1, the temperature of a semiconductor substrate or a switching element is detected in order to prevent component destruction due to heat of the switching element while the switching element unit is operating, and the control unit detects the temperature of the switching element according to the detected temperature. A semiconductor device having a built-in thermal element for controlling the operation of the part has been proposed.
Japanese Patent No. 2701824

  By the way, it is preferable that the thermal element portion is disposed in the vicinity of the switching element portion. This is because the thermal element portion has a role of detecting the temperature of the switching element portion that is a heat generation source. Further, if the thermal element unit is not arranged in the vicinity of the switching element unit, there is a possibility that time loss occurs in the transfer of heat generated in the switching element unit, making it difficult to control the switching element unit. It cannot cope with the temperature change of the part, and in some cases, part deterioration and part destruction occur.

  The bonding pads 51 and 52 have a role as a heat sink. For this reason, if there is a bonding pad between the switching element part and the thermal element part, the difference between the temperature detected by the thermal element part and the temperature of the switching element part is likely to occur, and the temperature of the switching element part is accurately detected. Can not do it.

  For example, as shown in FIG. 8, when the thermal element portion 53 is arranged so as to connect the two bonding pads 51 and 52 arranged at the end portion of the semiconductor device 50, it faces the thermal element portion 53. It is easy to detect the temperature of the switching elements in the surface or in the vicinity, for example, the regions 54 and 55, and the temperature of the switching elements in the regions 56 to 59 is difficult to detect. Therefore, if it is going to raise the precision to detect, the location which arrange | positions a switching element part will be limited. A method of increasing the number of locations where the switching element unit is arranged, that is, the surface where the thermal element unit 53 and the switching element unit face each other, or the adjacent surface (enlarge the effective area) can be considered. The size will increase.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device that can easily detect and control the temperature of the switching element portion without increasing the chip size.
It is another object of the present invention to provide a semiconductor device that can accurately detect the temperature of the switching element portion without increasing the chip size.
Furthermore, the present invention provides a semiconductor device capable of reducing the chip size by devising the arrangement of the heat sensitive element part to increase the face where the heat sensitive element part and the switching element part face each other or the face close to each other. For the purpose.

In order to achieve the above object, a semiconductor device of the present invention includes:
A semiconductor device having a semiconductor region having a switching function, a detection unit for detecting a state of the semiconductor region, and a pair of electrode pads electrically connected to the detection unit,
The detector is
A first element portion formed so as to connect the pair of electrode pads;
A second element portion formed so as to surround the outer periphery of one electrode pad from one end of the first element portion;
A third element portion formed so as to surround the outer periphery of the other electrode pad from the other end of the first element portion, and to surround the second element portion in a direction opposite to the direction surrounding the second element portion; ,
It is characterized by having.

  The second element portion and the third element portion are formed to extend along opposite sides of the pair of electrode pads, respectively, and are formed to extend to adjacent sides so as to surround the electrode pads. It is preferable that

  The first element portion is preferably formed so as to connect the vicinity of the center of the opposing sides of the pair of electrode pads.

  According to the present invention, the temperature of the switching element portion can be easily detected and controlled without increasing the chip size. Further, according to the present invention, the temperature of the switching element unit can be accurately detected without increasing the chip size. Furthermore, according to the present invention, by devising the arrangement of the heat sensitive element part, the surface where the heat sensitive element part and the switching element part face each other or the adjacent face can be increased, and the chip size can be reduced.

  Hereinafter, a semiconductor device according to an embodiment of the present invention will be described. FIG. 1 is a plan view of the semiconductor device of this embodiment.

  For example, as illustrated in FIG. 1, the semiconductor device 10 is formed in a rectangular shape as viewed from above (plan view). The semiconductor device 10 includes bonding pads 11 and 12 as a pair of electrode pads, a switching element part 13 having a switching function, a state of the switching element part 13, for example, a thermal element part 14 as a detection part that detects temperature. It is equipped with. In the present embodiment, the control unit that controls the operation of the switching element unit 13 is formed on a separate substrate from the switching element unit 13.

  The bonding pads 11 and 12 are formed, for example, in a rectangular shape when the semiconductor device 10 is viewed from above. In the present embodiment, the bonding pad 11 is formed on one end side (left side in FIG. 1) of the semiconductor device 10 in the long side direction, and the bonding pad 12 is formed on the other end side (right side in FIG. 1). The bonding pads 11 and 12 may have a non-circular shape such as a square, a circle, or an oval shape in addition to a rectangle.

  As the switching element unit 13, for example, a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor) is used. Details of the configuration will be described later.

  As will be described later, the thermal element 14 is composed of, for example, a polycrystalline silicon (polysilicon) diode. The thermal element unit 14 includes a first element unit 14a formed to connect the two bonding pads 11 and 12 with the semiconductor device 10 viewed from above, and a bonding pad from one end of the first element unit 14a. 11 is formed so as to surround the outer periphery of the bonding pad 12 from the other end of the first element portion 14a and surrounds the second element portion 14b. And a third element portion 14c formed so as to surround in the direction opposite to the direction.

  Here, surrounding in the direction opposite to the direction surrounding the second element portion 14b is formed so that the second element portion 14b extends toward the upper side of the side 11a of the bonding pad 11, as shown in FIG. When the semiconductor device 10 is viewed from above, the third element portion 14c extends toward the lower side of the side 12a of the bonding pad 12 so as to extend in the opposite direction. That means.

  In this way, the second element portion 14b and the third element portion 14c are formed so as to surround the outer periphery of the bonding pads 11 and 12 from the end of the first element portion 14a, and the third element portion 14c is 2 is formed so as to surround in the direction opposite to the direction surrounding the second element portion 14b, the surface (effective area) on which the switching element portion 13 and the thermal element portion 14 can be arranged to face each other is increased. it can. For this reason, the thermal element unit 14 can be disposed in the vicinity of the switching element unit 13, the thermal response from the switching element unit 13 to the thermal element unit 14 is improved, and it takes time to transfer the heat generated from the switching element unit 13. It becomes difficult to cause a loss. As a result, the temperature of the switching element unit 13 can be easily detected and controlled without increasing the chip size. Further, the temperature of the switching element unit 13 can be accurately detected without increasing the chip size. Further, when the effective area is the same, the chip size can be reduced.

  The first element portion 14a only needs to be formed between the two bonding pads 11 and 12 so as to connect them. For example, when the semiconductor device 10 is viewed from above, the bonding pad 11 and the bonding pad are connected. 12 may not be in contact. Further, the first element portion 14a may not be formed so as to connect the bonding pads 11 and 12 in a straight line. For example, you may form so that it may connect in a wave shape.

  The second element portion 14b and the third element portion 14c are formed so as to surround the outer periphery of the bonding pad 11 or the bonding pad 12 from the end of the first element portion 14a, and so as to surround both in the opposite direction. The shape of the bonding pads 11 and 12 is different depending on the shape of the bonding pads 11 and 12.

  For example, when the bonding pads 11 and 12 are formed in a rectangular shape (rectangular shape), as shown in FIG. 1, the first element portion 14 a connects the opposite sides 11 a and 12 a of the bonding pads 11 and 12. Formed as follows. The second element portion 14b is formed to extend upward, for example, along the side 11a that is the outer periphery of the bonding pad 11. The third element portion 14c is formed so as to extend downward, for example, along the side 12a that is the outer periphery of the bonding pad 12.

  Here, the second element portion 14b is preferably formed so as to extend along the side 11a, and further formed so as to extend along the side 11b so as to surround the bonding pad 11. The third element portion 14 c is preferably formed so as to extend along the side 12 a and further so as to extend along the side 12 b so as to surround the bonding pad 12. Thus, the effective area can be further increased by forming the second element part 14b and the third element part 14c so as to extend along the sides 11b and 12b. For this reason, the temperature of the switching element unit 13 can be detected and controlled more easily without increasing the chip size. Further, the temperature of the switching element unit 13 can be detected more accurately without increasing the chip size. Furthermore, when the effective area is the same, the chip size can be further reduced.

  The second element portion 14b and the third element portion 14c are preferably formed so as to be further bent and extended so as to surround the bonding pads 11 and 12.

  Moreover, it is preferable that the thermosensitive element part 14 is formed so as to be point-symmetric when the semiconductor device 10 is viewed from above. For example, when the bonding pads 11 and 12 are formed in a rectangular shape, the first element portion 14a is preferably formed so as to connect the sides 11a and the sides 12a of the two bonding pads 11 and 12 with each other. . Moreover, it is preferable to form the bending part of the thermal element part 14 so that it may curve.

  Next, the configuration of the semiconductor device 10 will be described in detail. 2 is a cross-sectional view taken along line A-A ′ of FIG. 1, and FIG. 3 is a cross-sectional view taken along line B-B ′ of FIG. 1. As shown in FIGS. 2 and 3, the semiconductor device 10 includes a semiconductor substrate 20, a gate insulating film 31, a gate electrode 32, a first insulating film 33, and a polysilicon diode 34 constituting the thermal element 14. Bonding pads 11 and 12, a second insulating film 35, a third insulating film 37, a drain electrode 38, and a source electrode 39.

  The semiconductor substrate 20 includes a drain region 21, a drift region 22, a base region 23, a source region 24, and a P well region 25.

The drain region 21 is composed of an N ⁺ type semiconductor region having an impurity concentration relatively higher than that of the drift region 22. The drift region 22 is formed on the upper surface of the drain region 21. The drift region 22 is composed of an N-type semiconductor region having a lower impurity concentration than the drain region 21.

  Base region 23 is formed on the surface of drift region 22 (semiconductor substrate 20). For example, the base region 23 is formed in a plurality of strips or dots when the semiconductor substrate 20 is viewed from above. The base region 23 is composed of a p-type semiconductor region.

The source region 24 is formed in the surface region of the base region 23, and is formed in an annular shape along the outer peripheral edge of the base region 23, for example. For this reason, the base region 23 is annularly exposed on the outer peripheral side of the source region 24. The source region 24 is composed of an n ⁺ type semiconductor region having an impurity concentration higher than that of the drift region 22.

The P well region 25 is formed in the surface region of the drift region 22. The P well region 25 is composed of a p-type semiconductor region. The P well region 25 mainly has a function of improving the breakdown voltage (drain-source voltage V _DSS ) of the semiconductor substrate 20. The base region 23 and the P well region 25 are often not formed in the same diffusion process.

  The gate insulating film 31 is formed on the upper surface of the base region 23 sandwiched between the source region 24 and the drift region 22. The gate insulating film 31 is made of, for example, a silicon oxide film. The base region 23 sandwiched between the source region 24 and the drift region 22 functions as a channel region and forms a switching element portion.

  The gate electrode 32 is formed on the upper surface of the gate insulating film 31. The gate electrode 32 is made of a conductor film made of a metal such as polysilicon, aluminum, copper, or nickel, and is formed by CVD or the like. When a predetermined voltage (gate voltage) is applied to the gate electrode 32, a channel is formed near the surface of the base region 23.

  The first insulating film 33 is formed on the upper surface of the P well region 25. The first insulating film 33 is made of, for example, a silicon oxide film.

  The polysilicon diode 34 is formed on the upper surface of the first insulating film 33. The polysilicon diode 34 is made of, for example, a diode made of polycrystalline silicon (polysilicon), and constitutes the thermal element unit 14.

  The polysilicon diode 34 includes a P-type region 34a and an N-type region 34b. A PN junction is formed at the interface between the P-type region 34a and the N-type region 34b, and the polysilicon diode 34 constitutes a PN junction diode. In this embodiment, as shown in FIG. 1, the P-type region 34a and the N-type region 34b are formed in parallel in a state viewed from above, and a PN junction is formed in the broken line portion of FIG. Yes. In FIGS. 2 to 4, the P-type region 34 a is painted black to clearly show the P-type region 34 a and the N-type region 34 b of the polysilicon diode 34.

  The bonding pads 11 and 12 are formed on the upper surface of the P well region 25 via the first insulating film 33. Note that a connection conductor (not shown) made of, for example, a bonding wire is connected to the bonding pads 11 and 12, and this connection conductor is connected to the control unit.

  The second insulating film 35 covers the upper surface of the polysilicon diode 34, the upper surface of the first insulating film 33 where the polysilicon diode 34 is not formed, and the gate electrode 32 so as to cover the gate electrode 32 and the polysilicon diode 34. It is formed on the upper surface of the gate electrode 32, the upper surface of the gate insulating film 31 where the gate electrode 32 is not formed, and so on. The second insulating film 35 is formed from, for example, a silicon oxide film.

  In the second insulating film 35, an opening 35a is formed at a position corresponding to the upper surface of the P-type region 34a of the polysilicon diode 34, and an opening 35b is formed at a position corresponding to the upper surface of the N-type region 34b. Yes. A bonding pad / diode connection wiring 36 a is disposed in the opening 35 a, and the bonding pad / diode connection wiring 36 a is electrically connected to the bonding pad 11. A bonding pad / diode connection wiring 36b is disposed in the opening 35b, and the bonding pad / diode connection wiring 36b is electrically connected to the bonding pad 12.

  The third insulating film 37 is formed on the upper surfaces of the bonding pad / diode connection wirings 36 a and 36 b and the second insulating film 35. The third insulating film 37 is made of, for example, a silicon oxide film.

The drain electrode 38 is formed on the lower surface of the drain region 21. The drain electrode 38 is made of a metal such as gold, silver, copper, or nickel.
The source electrode 39 is formed on the exposed upper surface of the base region 23, the source region 24, and the P well region 25, and electrically connects the base region 23, the source region 24, and the P well region 25. The source electrode 39 is made of a metal such as gold, silver, copper, or nickel. The drain electrode 38 and the source electrode 39 constitute a pair of main electrodes of the semiconductor device 10.

  In the semiconductor device 10 configured as described above, the second element portion 14b and the third element portion 14c are formed so as to surround the outer periphery of the bonding pads 11 and 12 from the end of the first element portion 14a. The third element portion 14c is formed so as to surround in a direction opposite to the direction surrounding the second element portion 14b. For this reason, an effective area can be increased compared with the conventional semiconductor device.

  As described above, according to the present embodiment, since the thermal element unit 14 includes the second element unit 14b and the third element unit 14c, the effective area can be increased. Since the effective area can be increased, the temperature of the switching element unit 13 can be easily detected and controlled without increasing the chip size. Further, the temperature of the switching element unit 13 can be accurately detected without increasing the chip size. Further, when the effective area is the same, the chip size can be reduced.

  According to the present embodiment, the second element portion 14b is formed so as to extend along the side 11b, and the third element portion 14c is formed so as to extend along the side 12b. It can be increased further.

  In addition, this invention is not restricted to said embodiment, A various deformation | transformation and application are possible. Hereinafter, other embodiments applicable to the present invention will be described.

  In the above embodiment, the present invention has been described by taking as an example the case where the P-type region 34a and the N-type region 34b are formed in parallel with the semiconductor device 10 viewed from above. For example, FIG. As shown, a plurality of P-type regions 34a and N-type regions 34b may be arranged in series and alternately as viewed from above. However, it is desirable that the P-type region 34a and the N-type region 34b be short-circuited in advance with aluminum or the like at a portion where the reverse characteristics are present.

  In the above-described embodiment, the first element portion 14a includes the sides 11a and 12a of the two bonding pads 11 and 12 so that the thermal element portion 14 is point-symmetric when the semiconductor device 10 is viewed from above. Although the present invention has been described by way of example in which the centers of the sides 11a and 12a are connected to each other, for example, as shown in FIG. Also in this case, the effective area can be increased.

  In the above embodiment, the present invention is described by taking as an example the case where the second element portion 14b is formed so as to surround the side 11b and the third element portion 14c is formed so as to surround the side 12b. As described above, for example, as shown in FIG. 6, the second element portion 14b is formed so as to extend only along the side 11a, and the third element portion 14c is formed so as to extend only along the side 12a. It may be. Also in this case, the effective area can be increased as compared with the conventional semiconductor device.

  In the above embodiment, the present invention has been described by taking as an example the case where the thermal element portion 14 is formed so as to be in contact with the bonding pads 11 and 12 when the semiconductor device 10 is viewed from above. The portion 14 and the bonding pads 11 and 12 may be formed so as to partially overlap.

  In the above embodiment, the present invention has been described by taking as an example the case where the bonding pads 11 and 12 are formed in a rectangular shape when the semiconductor device 10 is viewed from above, but a non-circular shape such as a square shape, a circular shape, or an oval shape is used. It may be. For example, when the bonding pads 11 and 12 are formed in a circular shape, the second element portion 14 b and the third element portion 14 c are formed along the outer periphery (circumference) of the bonding pads 11 and 12. In addition, as shown in FIG. 7, the thermal element portion 14 may be formed so as to surround the outer periphery (circumference) of the bonding pads 11 and 12.

  In the above embodiment, the present invention has been described by taking as an example the case where the control unit that controls the operation of the switching element unit 13 is formed on a substrate different from the switching element unit 13. May be formed on the same substrate.

  In the above embodiment, the present invention has been described by taking the case where a polysilicon diode is used as the thermal element 14 as an example. However, the present invention is not limited to the polysilicon diode, and a desired state of the switching element 13. As long as it can detect. For example, as a method of detecting the temperature of the switching element unit 13, a method using temperature-forward voltage characteristics (VF characteristics) of a polysilicon diode or the like, a method using temperature-forward current characteristics (IF characteristics), a thermistor, etc. There is a method using the temperature-resistance characteristic of the resistor.

  In the above embodiment, the present invention has been described by taking the case where the drain region 21 and the drift region 22 are N-type semiconductor regions as an example. However, the drain region 21 and the drift region 22 are P-type semiconductor regions, and the conductivity of each corresponding member. The mold may be inverted.

It is a top view of the semiconductor device of this Embodiment. It is A-A 'sectional drawing of FIG. It is B-B 'sectional drawing of FIG. It is a top view of the semiconductor device of other embodiments. It is a top view of the semiconductor device of other embodiments. It is a top view of the semiconductor device of other embodiments. It is a top view of the semiconductor device of other embodiments. It is a top view of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11, 12 Bonding pad 11a, 11b, 12a, 12b Side 13 Switching element part 14 Thermal element part 14a 1st element part 14b 2nd element part 14c 3rd element part 20 Semiconductor substrate 21 Drain region 22 Drift Region 23 base region 24 source region 25 P well region 31 gate insulating film 32 gate electrode 33 first insulating film 34 polysilicon diode 35 second insulating film 37 third insulating film 38 drain electrode 39 source electrode

Claims (3)

A semiconductor device having a semiconductor region having a switching function, a detection unit for detecting a state of the semiconductor region, and a pair of electrode pads electrically connected to the detection unit,
The detector is
A first element portion formed so as to connect the pair of electrode pads;
A second element part formed so as to surround the outer periphery of one electrode pad from one end of the first element part;
A third element part formed so as to surround the outer periphery of the other electrode pad from the other end of the first element part, and to surround the second element part in a direction opposite to the direction surrounding the second element part; ,
A semiconductor device comprising:   The second element portion and the third element portion are formed to extend along opposite sides of the pair of electrode pads, respectively, and are formed to extend to adjacent sides so as to surround the electrode pads. The semiconductor device according to claim 1, wherein:   3. The semiconductor device according to claim 1, wherein the first element portion is formed so as to connect the vicinity of the center of the opposing sides of the pair of electrode pads.

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