JP2006091995A - Write-back device of cache memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a write-back device of a cache memory capable of enhancing the efficiency of using a system bus. <P>SOLUTION: The write-back device 1 includes a write-back control part 2 for scanning the indexes of the cache memory 100 and detecting dirty cache lines; a snoop part 4 for monitoring the system bus 200 and detecting the idle state of the system bus 200; and a single-write-back write buffer part 5 for writing back to a main memory 300 via the system bus 200 in a single write for every word if the snoop part 4 detects that the system bus 200 is in the idle state. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a cache memory write-back device.

  In the write-back cache memory system, when the cache line needs to be replaced, the dirty line data in the cache memory is written back to the main memory. At this time, the data read from the cache memory is transferred to the main memory via the system bus.

  By the way, various devices such as a CPU are connected to the system bus. Therefore, conventionally, when executing the write back of the cache memory, the state of the system bus is monitored and the write back is executed during the idle period of the system bus. At this time, when there are a plurality of dirty lines in the cache memory, it has been proposed to perform write back continuously until there are no dirty lines (see, for example, Patent Document 1).

  When performing such continuous write back, if burst write is performed to the main memory, data can be efficiently written to the main memory.

However, generally, the operation speed of the main memory is considerably slower than that of the CPU. For this reason, when the write back to the main memory is performed by burst write, the system bus is occupied for accessing the main memory having a low operation speed during that time, and there is a problem that the use efficiency of the system bus deteriorates.
JP 2002-108702 A (page 7-8, FIGS. 4 and 5)

  SUMMARY OF THE INVENTION An object of the present invention is to provide a cache memory write-back device capable of improving the efficiency of use of a system bus.

  According to one aspect of the present invention, a write back control unit that scans a cache line of a cache memory to detect a dirty cache line, a snoop unit that monitors a system bus and detects an idle state, and the write back control Dirty cache line data detected by the unit is temporarily stored, and when the snoop unit detects an idle state of the system bus, the stored data is stored for each word of the cache line via the system bus. Provided is a cache memory write-back device comprising a single-write backlight buffer unit for writing to a main memory by a single write.

  According to another aspect of the present invention, the FIFO has a FIFO for sequentially storing an index of a newly written cache line, and when executing a store instruction or a cache memory dirty bit clear instruction, An index queue unit that updates and outputs data, a write-back control unit that acquires a cache line of an index output from the index queue unit from the cache memory, and a snoop unit that monitors the system bus and detects an idle state And temporarily storing the data of the cache line acquired by the write back control unit, and the stored data when the snoop unit detects an idle state of the system bus via the system bus Single write for each word in the line Write-back apparatus of cache memory, characterized by comprising a single write-back write buffer portion to be written to the in-memory is provided.

  According to the present invention, dirty cache line data is distributed and written back to the main memory with a single write when the system bus is in an idle state, so that the system bus can be used efficiently.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing an example of the configuration of a cache memory write-back device according to a first embodiment of the present invention.

  The write-back device 1 scans an index of the cache memory 100 to detect a dirty cache line, a snoop unit 4 to monitor the system bus 200 and detect an idle state of the system bus 200, The cache line data detected to be dirty by the write-back control unit 2 is temporarily stored, and then when the snoop unit 4 detects that the system bus 200 is in an idle state, the data is transferred via the system bus 200. And a single write backlight buffer unit 5 for writing back to the main memory 300 by single write for each word.

  The write back device 1 operates as follows.

  The write-back control unit 2 has a counter 3 that increments and increments the index value of the cache line by one, sequentially accesses the cache line of the cache memory 100 according to the output of the counter 3, and the state of the accessed cache line Is read. If the state is dirty, the single write backlight buffer unit 5 is instructed to store the data of the cache line in the single write backlight buffer unit 5. Further, the write back control unit 2 cleans the state of the cache line after the write back is completed.

  When the snoop unit 4 monitors the system bus 200 and detects that the system bus 200 is in an idle state, the snoop unit 4 notifies the single write backlight buffer unit 5 that the system bus 200 is in an idle state.

  The single write backlight buffer unit 5 temporarily stores dirty cache line data in the cache memory 100 in accordance with instructions from the write back control unit 2. When notified from the snoop unit 4 that the system bus 200 is in an idle state, one word of cache line data temporarily stored is written to the main memory 300 via the system bus 200 with a single write. .

  At this time, when there are a plurality of words of cache line data temporarily stored, the single write backlight buffer unit 5 accesses the system bus 200 from other devices every time one word is written. It is confirmed through the snoop unit 4 whether there is a request. When there is an access request from another device, the writing to the memory 300 is terminated at that time. Then, the writing to the memory 300 is resumed when the system bus 200 is in an idle state next time.

  In this way, the single write backlight buffer unit 5 divides the data into a plurality of bus idle periods when all the words on the temporarily stored cache line cannot be written in one bus idle period. Write to memory 300.

  According to the cache memory write-back device of this embodiment, the dirty cache line data detected by sequentially scanning in the order of the index is divided into a plurality of idle periods of the system bus, and a single word for each word. Write back to the main memory. Thereby, the write back to the main memory does not occupy the system bus for a long time, and the system bus can be used efficiently.

  FIG. 2 is a block diagram showing an example of the configuration of the cache memory write-back device according to the second embodiment of the present invention. The configuration of the write back device 11 of the present embodiment is basically the same as that of the write back device of the first embodiment. Therefore, in FIG. 2, blocks having the same functions as those in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and detailed description thereof is omitted here.

  The write-back device 11 according to this embodiment includes a write-back control unit 21 that scans an index of the cache memory 100 to detect a dirty cache line, a snoop unit 4, and a single write backlight buffer unit 5.

  Here, as with the write back control unit 2 of the first embodiment, the write back control unit 21 accesses the cache line of the cache memory 100 and reads the state of the accessed cache line. It operates to instruct the single write backlight buffer unit 5 to store the line data in the single write backlight buffer unit 5. Further, the write back control unit 21 operates so as to clean the state of the cache line after the write back.

  The write back control unit 21 is different from the write back control unit 2 of the first embodiment in that the output of the random number generator 31 is used for scanning the index of the cache memory 100 for accessing the cache line. Thereby, the write-back control unit 21 scans the index of the cache memory 100 at random. That is, the cache line of the cache memory 100 is accessed at random.

  In general, new data is written to the cache memory 100 and the cache line becomes dirty at random at an arbitrary index. On the other hand, it is desirable that the dirty cache line data is written back to the main memory 300 within a short time.

  Therefore, the write-back control unit 21 of this embodiment attempts to increase the probability of accessing the cache line at random and accessing the newly dirty cache line at an early stage.

  According to the cache memory write-back device of this embodiment, since the cache memory is accessed in a random index order, it is possible to prevent the cache line from being dirty for a long time.

  FIG. 3 is a block diagram showing an example of the configuration of the cache memory write-back device according to the third embodiment of the present invention. 3, blocks having the same functions as those in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and detailed description thereof is omitted here.

  The write-back device 12 according to the present embodiment outputs an index queue unit 6 that sequentially stores indexes when stored in the cache memory 100 and forms a queue for accessing a dirty cache line, and is output from the index queue unit 6. The write back control unit 22 that controls the acquisition of the cache line data of the index, the snoop unit 4, and the single write backlight buffer unit 5. In addition, the write back control unit 22 cleans the state of the cache line after the write back is completed.

  Here, an example of the internal configuration and operation of the index queue unit 6 will be described.

  FIG. 4 is a block diagram illustrating an example of the configuration of the index queue unit 6.

  The index queue unit 6 includes a FIFO 61 and a comparison circuit 62.

  The FIFO 61 has a five-stage queue of Q0 to Q4, and the indexes when the store to the cache memory 100 is performed are sequentially stored while being shifted from Q0 to Q4. Therefore, the index written at this time is an index of a dirty cache line that needs to be written back. In FIG. 5, the number of queues is five, but the number of stages is not limited to five and can be any number.

  When a new index is input, the comparison circuit 62 compares the value with the index value stored in the FIFO 61. When the index value stored in the FIFO 61 matches the newly input index value, the cache line of that index has the latest data, so it is necessary to change the queue position to Q0. is there. Therefore, the comparison circuit 62 outputs an invalidation signal to the stage where the corresponding index has been stored so far.

  Further, even when the dirty bit of the cache memory 100 is cleared, the comparison circuit 62 compares the index value of the cache line in which the dirty bit is cleared with the index value stored in the FIFO 61. As a result, if the values match, an invalidation signal is output to the stage that stores the corresponding index of the FIFO 61.

  When the invalidation signal is output from the comparison circuit 62, the FIFO 61 deletes the contents of the stage and shifts the queue one by one toward the empty stage.

  On the other hand, when the invalidation signal is not output from the comparison circuit 62, the queue of the FIFO 61 is shifted to the output side as it is, and the index stored in Q4 is output as the output of the index queue unit 6. In this way, the index queue unit 6 outputs the indexes of the cache lines in the order in which the cache lines become dirty.

  When the index from the index queue unit 6 is input, the write-back control unit 22 instructs the single write backlight buffer unit 5 to store the cache line data because the cache line of the index is dirty. To do.

  Then, when the snoop unit 4 detects the idle state of the system bus 200, the single write backlight buffer unit 5 writes back the stored data to the main memory 300 with a single write.

  According to such a cache memory write-back device of this embodiment, since dirty cache lines are written back in the order in which they become dirty, efficient write-back is possible.

  In each of the above-described embodiments, the cache memory to which the write-back device is connected may be a single-port memory or a multi-port memory. By dedicating one of the ports to the write back device connection, it is possible to easily access the cache line of the write back device.

1 is a block diagram showing an example of the configuration of a cache memory write-back device according to a first embodiment of the present invention; The block diagram which shows the example of a structure of the write-back apparatus of the cache memory based on 2nd Example of this invention. The block diagram which shows the example of a structure of the write-back apparatus of the cache memory based on 3rd Example of this invention. The block diagram which shows the example of a structure of the index queue part contained in the write-back apparatus of the cache memory based on 3rd Example of this invention.

Explanation of symbols

1, 11, 12 Writeback devices 2, 21, 22 Writeback control unit 3 Counter 31 Random number generator 4 Snoop unit 5 Single write backlight buffer unit 6 Index queue unit 61 FIFO
62 Comparison circuit

Claims (5)

A write-back controller that scans the cache lines of the cache memory to detect dirty cache lines;
A snoop unit that monitors the system bus and detects an idle state;
Dirty cache line data detected by the write-back control unit is temporarily stored, and when the snoop unit detects an idle state of the system bus, the stored data is transferred to the cache line via the system bus. A write back device for a cache memory, comprising: a single write backlight buffer unit for writing to the main memory with a single write for each word.   The cache memory write-back device according to claim 1, wherein the write-back control unit sequentially scans cache lines in an index order.   The cache memory write-back device according to claim 1, wherein the write-back control unit scans a cache line at random. An index queue unit that has a FIFO for sequentially storing indexes of newly written cache lines, and that updates and outputs the FIFO data when executing a store instruction or a cache memory dirty bit clear instruction;
A write-back control unit that acquires the cache line of the index output from the index queue unit from the cache memory;
A snoop unit that monitors the system bus and detects an idle state;
The cache line data acquired by the write-back control unit is temporarily stored, and when the snoop unit detects an idle state of the system bus, the stored data is stored in the cache line via the system bus. A cache memory write-back device comprising: a single-write backlight buffer unit for writing to the main memory by single write for each word.   5. The cache according to claim 1, wherein the write-back control unit cleans a state of a cache line that has been written to the main memory by the single write backlight buffer unit. 6. Memory write-back device.

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