JP2005301387A - Cache memory controller and cache memory control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that data in a cache memory can not be completely protected from replacement in a conventional cache memory replacement system. <P>SOLUTION: Each memory of a tag memory is provided with a replacement protection bit L(replacement protection bit) indicating that it is a replacement protection status, and the address region of data to be protected from replacement is designated. When the data in the address region are written in a cache memory according to cache mistake, the replacement protection bit L of the write entry is set as a valid value. When a replacement object way is selected according to the cache mistake according to following access to any region other than the address region, the way of the entry whose replacement protection bit L is valid is prevented from being selected so that the data on the cache memory can be protected from being replaced. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a cache memory control apparatus and a control method therefor, and more particularly to a technique for controlling cache replacement in order to increase a cache hit rate of data that needs to be processed at high speed.

  The cache memory is generally used as a temporary storage device that speeds up access to the main memory and has a high access speed that determines operation performance of a CPU (Central Processing Unit) or the like.

  The storage capacity of the cache memory is usually considerably smaller than the storage capacity of the main memory. Data held in an arbitrary entry in the cache memory is discarded depending on the usage state of the cache memory, and replacement (replacement) of new data is required for the entry. In a cache memory composed of a plurality of ways, there are a LRU (Least Recently Used) method, a FIFO (First-In First-Out) method, a random method, and the like as methods for determining the way of an entry to be replaced.

  A case will be described where three subroutines are repeatedly called by a conditional branch instruction to the “Loop” label and “Loop” label of the main program as shown in FIG. Here, it is assumed that the three subroutines 1 to 3 are mapped to addresses using the same entry on the cache memory. When subroutines 1 to 3 are sequentially called and executed, there are only two cache ways, so subroutine 1 and subroutine 2 are stored in each of the two ways. When executing the subroutine 3, it is necessary to discard either the subroutine 1 or the subroutine 2 and store the subroutine 3. In the LRU method and the FIFO method, subroutine 1 is replaced. Next, when subroutine 1 is called, subroutine 1 does not exist in the cache memory, so a cache miss occurs, and subroutine 2 is replaced.

  As described above, the conventional cache memory has a problem that cache misses frequently occur and performance is deteriorated.

  Furthermore, even when a specific subroutine is desired to be executed at high speed, the cache hit depends on the order of access addresses and so cannot be predicted, and it is difficult to guarantee high speed execution.

In the invention described in Patent Document 1, when a replace operation due to a cache miss is performed, the replace priority set in the replace priority register is stored in the entry of the tag memory. In the subsequent replacement operation due to a cache miss, an entry to be replaced is selected. At this time, a function of preferentially protecting from replacement is realized for an arbitrary address area. As a result, the above-described problem of a decrease in utilization efficiency of the cache memory is improved.
JP-A-10-198604 (pages 3-6, FIGS. 1 and 4)

  However, the invention described in Patent Document 1 merely sets a replacement priority, and does not prevent a specific instruction or data from being replaced. For this reason, there is a problem that it is impossible to reliably protect an instruction or data that is to be reliably held in the cache memory for a certain period from the replacement operation.

  Furthermore, there is a problem that it is not possible to efficiently cope with the need for high-speed execution by holding a specific instruction or data in the cache memory dynamically.

  The present invention takes the following means in order to solve the above problems.

The first cache memory control device according to the present invention is a cache memory composed of a plurality of ways.
A tag memory having a plurality of entries holding valid bits, replacement protection bits, and tag addresses;
A data memory for holding data corresponding to the entry of the tag memory;
A cache hit detection means for detecting a cache hit based on a comparison between the tag address output from the tag memory and an access request address and a value of the valid bit;
A lock area determination unit that compares the address area to be replaced with the access request address and outputs a lock area hit signal when they match,
A replacement control means for selecting the way to be replaced, using the value of the effective bit held by the tag memory and the value of the replacement protection bit as inputs; and
The tag memory enables the replace protection bit of the entry corresponding to the lock area hit signal,
The replacement control means preferentially selects an entry for which the replacement protection bit is not valid as a replacement target.

  According to this configuration, an address area requiring replacement protection is designated in advance. Then, the replace protection bit is validated when data in the designated address area is stored in the cache memory. As a result, the data in this address area can be reliably protected from the subsequent replacement operation, and the designated area can be accessed at high speed.

  In the above configuration, the lock area determination unit includes an address area designating unit that designates the address area to be replaced, and a comparison unit that compares the access request address with a value held by the address area designating unit. The structure provided with is preferable.

  In the above configuration, the tag memory further includes a replacement protection permission bit capable of controlling replacement protection by software, and the replacement control means invalidates the replacement protection that is enabled based on the replacement protection permission bit. It is also preferable to perform the configuration.

  By the way, the first cache memory control device has a problem in that the access frequency to the area to be protected from replacement changes depending on the state at the time of execution of the program. In other words, when data corresponding to the address area subject to replacement protection is stored in the cache memory, if the access frequency to the address area subject to replacement protection changes depending on the state at the time of execution of the program, the replacement protection is enabled / disabled. It becomes difficult to control the switching by a program, or the program increases to determine the state. The second cache memory control device described below solves this problem.

The second cache memory control device according to the present invention is a cache memory composed of a plurality of ways.
A tag memory having a plurality of entries holding valid bits, replacement protection bits, and tag addresses;
A data memory for holding data corresponding to the entry of the tag memory;
A cache hit detection means for detecting a cache hit based on a comparison between the tag address output from the tag memory and an access request address and a value of the valid bit;
A lock area determination unit that compares the address area to be replaced with the access request address and outputs a lock area hit signal when they match,
An access frequency evaluation unit that evaluates the access frequency to the address area to be replaced by the lock area hit signal output from the lock area determination unit and outputs an access frequency decrease signal when the decrease in the access frequency is detected; ,
A replacement control means for selecting a replacement target way with the value of the effective bit held by the tag memory, the value of the replacement protection bit, and the access frequency lowering signal output by the access frequency evaluation means as inputs;
The tag memory enables the replace protection bit of the entry corresponding to the lock area hit signal,
When the access frequency lowering signal is valid, the replacement control unit invalidates the replacement protection and selects a replacement target entry, and when the access frequency lowering signal is invalid, the replacement control unit preferentially selects an entry whose replacement protection bit is not valid. And selecting a replacement target.

  According to this configuration, when the frequency of access to the address area targeted for replacement changes depending on the state at the time of execution of the program and the situation falls outside the protection target, the replacement protection is automatically disabled and the program is disabled. This can be realized without causing an increase, and the cache memory can be used more efficiently.

  In the above configuration, the lock area determination unit includes an address area designating unit that designates the replacement-protected address area, and a comparison unit that compares the access request address with a value held by the address area designating unit. The configuration is preferable.

  Further, in the above configuration, the system further comprises entry invalidating means for invalidating the valid bits of all entries in which both the valid bits and the replacement protection bits have valid values, and the replacement control means includes the access frequency. It is also preferable that the entry invalidating means of the tag memory is operated when the lowering signal becomes valid.

  By the way, in the second cache memory control device, if there is one lock area determination means, the replacement protection area is not one continuous one, but is divided with an area that does not require replacement protection in between. In such a case, in the replacement protection, the protection including the area where the replacement protection is unnecessary is included, and the burden of the replacement protection increases. The third cache memory control device described below solves this problem.

The third cache memory control device according to the present invention is a cache memory composed of a plurality of ways.
A tag memory having a plurality of entries holding valid bits, replacement protection bits, and tag addresses;
A data memory for holding data corresponding to the entry of the tag memory;
A cache hit detection means for detecting a cache hit based on a comparison between the tag address output from the tag memory and an access request address and a value of the valid bit;
A plurality of lock area determination means for comparing the address area to be replaced with the access request address and outputting a lock area hit signal when they match;
An access frequency evaluation unit that evaluates the access frequency to the address area to be replaced by the lock area hit signal output from the lock area determination unit and outputs an access frequency decrease signal when the decrease in the access frequency is detected; ,
A replacement control means for selecting a replacement target way with the value of the effective bit held by the tag memory, the value of the replacement protection bit, and the access frequency lowering signal output by the access frequency evaluation means as inputs;
Set replacement protection for a plurality of address areas by a plurality of the lock area determination means,
The tag memory enables the replace protection bit of the entry corresponding to the lock area hit signal,
When the access frequency lowering signal is valid, the replacement control unit invalidates the replacement protection and selects a replacement target entry, and when the access frequency lowering signal is invalid, the replacement control unit preferentially selects an entry whose replacement protection bit is not valid. And selecting a replacement target.

  The technical feature here is that a plurality of lock area determination means are provided, and a plurality of replacement protection areas are individually set.

  According to this configuration, by using a plurality of lock area determination means, it is possible to set a plurality of areas to be subjected to replacement protection, thereby realizing effective replacement protection.

  By the way, in the third cache memory control device, a plurality of address areas can be designated for replacement protection. However, since the access frequency evaluation means and the replacement protection bits of the tag memory are shared by the plurality of lock area determination means, the lock area determination The replacement protection cannot be set / released for each means. The fourth cache memory control device described below solves this problem.

The fourth cache memory control device according to the present invention is a cache memory composed of a plurality of ways.
A tag memory having a plurality of entries holding valid bits, a plurality of replacement protection bits, and a tag address;
A data memory for holding data corresponding to the entry of the tag memory;
A cache hit detection means for detecting a cache hit based on a comparison between the tag address output from the tag memory and an access request address and a value of the valid bit;
A plurality of lock area determination means for comparing the address area to be replaced with the access request address and outputting a lock area hit signal when they match;
A plurality of access frequency evaluations that evaluate the access frequency to the address area to be replaced by the lock area hit signal output by the lock area determination means and output an access frequency decrease signal when the access frequency decrease is detected Means,
A replacement control means for selecting a replacement target way by inputting the value of the effective bit held in the tag memory, the values of the plurality of replacement protection bits, and the access frequency decrease signal output by the plurality of access frequency evaluation means; With
Set replacement protection for a plurality of address areas by a plurality of the lock area determination means,
The tag memory enables the replace protection bit corresponding to the lock area hit signal of the entry corresponding to a plurality of the lock area hit signals,
When the access frequency lowering signal is valid, the replacement control unit invalidates the replacement protection and selects a replacement target entry, and when the access frequency lowering signal is invalid, the replacement control unit preferentially selects an entry whose replacement protection bit is not valid. And selecting a replacement target.

  The technical feature here is that the tag memory has a plurality of replacement protection bits and that the access frequency evaluation means corresponds to the plurality of lock area determination means.

  According to this configuration, the lock area determination unit has the access frequency evaluation unit, and the replacement control unit sets / cancels the replacement protection for each replacement protection region by evaluating the access frequency for each replacement protection region. It is possible to perform effective replacement protection.

  By the way, in the first cache memory control device, a replacement protection bit indicating a replacement protection state is added to the tag memory for each entry. However, if the capacity of the cache memory is large, the number of entries in the tag memory is small. Therefore, the addition of the replacement protection bit increases the physical area of the tag memory. The fifth cache memory control device described below solves this problem.

The fifth cache memory control device according to the present invention is a cache memory composed of a plurality of ways.
A tag memory having a plurality of entries holding valid bits and tag addresses;
A data memory for holding data corresponding to the entry of the tag memory;
A cache hit detection means for detecting a cache hit based on a comparison between the tag address output from the tag memory and an access request address and a value of the valid bit;
A plurality of lock area determination means for comparing the address area to be protected for replacement with the tag address output from the tag memory and outputting a lock area hit signal when they match.
A replacement control means for selecting the way to be replaced with the value of the effective bit held in the tag memory and the lock area hit signal as inputs, and
Thus, replacement protection is performed by designating an address space.

  The technical feature here is that the tag memory does not have a replacement protection bit, and the lock area determination means uses the tag address directly read from the tag memory as the comparison target of the address area to be replaced. That's what it means.

  According to this configuration, replacement protection can be realized without using a tag memory having a replacement protection bit, and replacement protection is possible without increasing the area of the tag memory due to the addition of the replacement protection bit. It becomes.

A sixth cache memory control device according to the present invention is a cache memory composed of a plurality of ways.
A tag memory having a plurality of entries holding valid bits, replacement protection bits, and tag addresses;
A data memory for holding data corresponding to the entry of the tag memory;
A cache hit detection means for detecting a cache hit based on a comparison between the tag address output from the tag memory and an access request address and a value of the valid bit;
A lock area determination unit that compares a task ID to be replaced with a task ID being executed output by the CPU and outputs a lock area hit signal when they match,
A replacement control means for selecting the way to be replaced, using the value of the effective bit held by the tag memory and the value of the replacement protection bit as inputs; and
Thus, replacement protection with a task ID specified is performed.

  The technical feature here is that the criterion for determination of replacement protection is not an address area but a task ID.

  According to this configuration, replacement protection can be performed in units of tasks by specifying replacement protection as a task ID instead of a memory address. That is, it is not necessary to check the address area used in the task, and easy replacement protection setting is possible.

A seventh cache memory control device according to the present invention is a cache memory composed of a plurality of ways.
A tag memory having a plurality of entries holding valid bits, replacement protection bits, and tag addresses;
A cache hit detection means for detecting a cache hit based on a comparison between the tag address output from the tag memory and an access request address and a value of the valid bit;
A lock area determination unit that compares the interrupt level to be replaced with the interrupt level being executed output by the CPU and outputs a lock area hit signal when they match,
A replacement control means for selecting the way to be replaced, using the value of the effective bit held by the tag memory and the value of the replacement protection bit as inputs; and
It is also preferable that the replacement protection is performed by designating the interrupt level.

  The cache memory control method is preferably configured as follows.

That is, an area determination step for determining whether an access request from the CPU is an access to an address area targeted for replacement protection;
Selection step 1 for selecting an entry for which a valid bit is not set as an entry to be replaced due to a cache miss;
A selection step 2 for selecting an entry in which the replacement protection bit is not set when an entry to be replaced cannot be selected in the selection step 1;
A writing step of writing data to the entry selected by either the selection step 1 or the selection step 2;
And a protection setting step of writing the result of the area determination step into the replacement protection bit of the selected entry.

  The following cache memory control method is also preferable.

An area determination step for determining whether an access request from the CPU is an access to an address area targeted for replacement protection;
An access frequency evaluation step of evaluating an access frequency to the replacement protected address area and outputting an access frequency decrease signal when the access frequency decreases;
Selection step 1 for selecting an entry for which a valid bit is not set as an entry to be replaced due to a cache miss;
An entry in which the replacement protection bit is not set as an entry to be replaced when the entry to be replaced cannot be selected in the selection step 1 and the access frequency lowering signal indicates that the access frequency has not decreased. Selection step 2 for selecting
A selection step 3 for selecting an entry to be replaced regardless of the replacement protection bit when the entry to be replaced cannot be selected in the selection step 1 and the access frequency decrease signal indicates a decrease in the access frequency; ,
A writing step of writing data to the entry selected by any of the selection step 1, the selection step 2 and the selection step 3;
And a protection setting step of writing the result of the area determination step into the replacement protection bit of the selected entry.

  According to the first cache memory control device, an area to be protected from the replace operation is set, and it is possible to reliably protect an instruction or data that is to be reliably held in the cache memory for a certain period from the replace operation. . Further, when it is necessary to execute a high-speed execution by holding a specific instruction or data in the cache memory, the high-speed execution can be reliably realized.

  According to the second cache memory control device, the utilization efficiency of the cache memory can be improved as compared with the first cache memory control device.

  According to the third cache memory control device, it is possible to perform more precise replacement protection than the second cache memory control device, and it is possible to improve the use efficiency of the cache memory.

  According to the fourth cache memory control device, more precise replacement protection can be achieved than in the third cache memory control device, and the utilization efficiency of the cache memory can be improved.

  According to the fifth cache memory control device, the area of the tag memory can be reduced while obtaining the same effect as that of the first cache memory control device.

  According to the sixth cache memory control device, the task ID to be protected from the replace operation is set, and the specified task ID can be executed at high speed by reliably protecting from the replace operation.

  According to the seventh cache memory control device, by setting the interrupt level to be protected from the replace operation and reliably protecting from the replace operation, the interrupt processing at the designated interrupt level can be executed at high speed.

  Embodiments of a cache memory control device according to the present invention will be described in detail below with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing a configuration of a cache memory control apparatus according to the first embodiment of the present invention, FIG. 2 is a flowchart showing an operation of cache memory access control according to the first embodiment, and FIG. FIG. 4 shows a part of a program executed in the first embodiment.

  The cache memory control device according to the present embodiment includes a tag memory 100 of way 0, a tag memory 101 of way 1, a data memory 102 of way 0, a data memory 103 of way 1, hit detectors 104 and 105, an output circuit 106, 107, a lock area determination circuit 111, and a replacement control circuit 112. Reference numeral 108 denotes a CPU, and 800 denotes an external memory.

  The tag memory 100 of way 0 and the tag memory 101 of way 1 hold a tag address, a valid bit V indicating the validity of the entry, and a replacement protection bit L indicating the lock state of the entry for each way entry. is there.

  The hit detectors 104 and 105 perform the following comparison. One element of the comparison is the upper part of the access request address output from the CPU 108 via the address bus. The other element of the comparison is the tag address held in the entry read from the tag memory 100 of way 0 and the tag memory 101 of way 1 using the lower part of the access request address. The hit detectors 104 and 105 compare the upper part of the access request address with the read tag address, and output a hit signal Sh when the results match and the valid bit V is “1”. It is configured to output to the circuits 106 and 107.

  The output circuits 106 and 107 perform output control of data output from the data memory 102 of way 0 and the data memory 103 of way 1 based on the hit signal Sh for each way output from the hit detectors 104 and 105. It is configured.

  The lock area determination circuit 111 includes an address area designation register 110 that holds a lock area and a comparator 109. The comparator 109 compares the access request address output from the CPU 108 to the address bus for memory access and the address area designated in the address area designation register 110. If the access is within the range of the lock area, a lock area hit for setting “1” to the replacement protection bit L of the corresponding entry in the tag memory 100 of way 0 and the tag memory 101 of way 1 The signal S1 is output.

  The replace control circuit 112 is configured to control selection of a way to perform a replace operation using the replace protection bit L and the valid bit V of each entry of the tag memory 100 of way 0 and the tag memory 101 of way 1 as input signals. Has been.

  Next, the replacement control operation of the cache memory control device will be described with reference to the flowcharts of FIGS.

  First, the basic operation of the cache memory access control will be described based on the flowchart of FIG.

  The cache memory access control operation starts the processing after step A1 in response to an access request from the CPU.

  In step A1, the CPU 108 determines whether the data to be accessed is a cache hit or a cache miss. If it is a cache hit, the process branches to step A2, and if it is a cache miss, the process branches to step A3.

  In step A2 in the case of a cache hit, the cache memory is accessed, and the access from the CPU 108 ends.

  On the other hand, in step A3 in the case of a cache miss, it is determined whether or not there is an entry whose effective bit V is “0” in the entry to be accessed. If there is, branch to step A6. If not, the process branches to step A4.

  In step A6 when there is an entry for which the valid bit V is “0”, one of the entries for which the valid bit V is “0” is selected. Then, the process proceeds to Step A10.

  On the other hand, in step A4 when there is no entry for which the valid bit V is “0”, it is determined whether or not there is an entry for which the replacement protection bit L is “0” in the entry to be accessed. If there is, the process branches to step A7, and if not, the process branches to step A5.

  In step A7 when there is an entry whose replacement protection bit L is “0” among the entries to be accessed, one of the entries whose replacement protection bit L is “0” is selected. Then, the process proceeds to Step A10.

  On the other hand, in the case where there is no entry whose replacement protection bit L is “0” in the entry to be accessed, it is determined whether or not the lock area hit signal S1 is “1”. If "", the process branches to step A8. If "0", the process branches to step A9.

  In step A8 when the lock area hit signal S1 is "1", one entry to be accessed is selected. At this time, as a method for selecting an entry, an LRU method, a FIFO method, a method for selecting at random, or the like can be used. Next, the process proceeds to Step A10.

  On the other hand, in step A9 when the lock area hit signal S1 is “0”, the access requested by the CPU 108 is executed with respect to the external memory 800, and the access ends.

  In step A10 after one entry is selected, data requested by the CPU 108 is read from the external memory 800 and written to the selected entry.

  Next, in Step A11, it is determined whether or not the lock area hit signal S1 is “1”. If “1”, the process branches to Step A12, and if it is “0”, the process branches to Step A13. Then, the process proceeds to Step A14.

  In Step A12 when the lock area hit signal S1 is “1”, “1” is set to the replacement protection bit L of the selected entry.

  On the other hand, in step A13 when the lock area hit signal S1 is “0”, “0” is set to the replacement protection bit L of the selected entry. Then, the process proceeds to Step A14.

  In step A14, the access requested by the CPU 108 is executed, and the access ends.

  Next, the operation of the lock area determination circuit 111 will be described based on the flowchart of FIG.

  In response to an access request from the CPU 108, the lock area determination circuit 111 starts the processing after step B1.

  In step B1, it is evaluated whether or not the access request address from the CPU 108 is within the range designated in the address area designation register 110. If it is within the range, the process branches to step B2, and if outside the range, step B3 is entered. Branch to

  In step B2, "1" is output to the lock area hit signal S1 and the flow is terminated.

  On the other hand, in step B3, "0" is output to the lock area hit signal S1 and the flow is terminated.

  As a specific example, the operation of the cache replacement control in the present embodiment in the program as shown in FIG. 4 is shown below.

  In the cache replacement control cache memory control device shown in FIGS. 1, 2, and 3, a subroutine that is repeatedly called from the main program as shown in FIG. 4 and is mapped to an address that uses the same entry on the cache memory. Suppose there are 1-3. Furthermore, it is assumed that subroutine 1 is a program that requires high-speed execution.

  Before executing the repeated processing starting with the label “Loop” in the main program of FIG. 4, the address of the subroutine 1 that requires high-speed execution is stored in the address area designation register 110 in the lock area determination circuit 111 in advance by the program. The end address is specified as the lock area. The cache memory is initialized for both way 0 and way 1, and the valid bits V of all entries are cleared to “0”.

  Thereafter, the main program repeatedly executes calls of subroutines 1 to 3.

  First, subroutine 1 is called from the main program, and the instruction of subroutine 1 is executed. In this case, since this is the first time, a cache miss occurs. The way 0 is selected by the control of the replacement control circuit 112, and the corresponding entry of the way 0 is replaced by the data read from the external memory 800 (step A1, step A3, step A6, step A10).

  At this time, the lock area determination circuit 111 determines whether the address of the address bus to be accessed is the address of the designated address area (step A11). “1” is set to the area hit signal S1.

  The tag memory 100 of the way 0 sets the replacement protection bit L of the entry that has been replaced to “1” when the lock area hit signal S1 of the lock area determination circuit 111 is set to “1” ( Step A12).

  Then, the CPU 108 executes the data read from the external memory 800 (Step A14).

  When the processing of the subroutine 1 is completed and the process returns to the main program, the subroutine 2 is called from the main program and the instruction of the subroutine 2 is executed. At this time, a cache miss occurs even when the instruction of subroutine 2 is executed, and way 1 with both valid bit V and replacement protection bit L being “0” is selected by the control of replacement control circuit 112, and the data read from external memory 800 is used. The corresponding entry of way 1 is replaced (step A1 → step A3 → step A6 → step A10).

  At this time, the lock area determination circuit 111 determines whether or not the address of the address bus to be accessed is the address of the designated address area (step A11). “0” is set to the hit signal S1.

  The tag memory 101 of way 1 sets the replacement protection bit L of the entry that has been replaced to “0” when the lock area hit signal S1 of the lock area determination circuit 111 is set to “0” ( Step A13).

  Then, the CPU 108 executes the data read from the external memory 800 (Step A14).

  When the processing of the subroutine 2 is completed and the process returns to the main program, the subroutine 3 is called from the main program and the instruction of the subroutine 3 is executed. At this time, a cache miss also occurs when the instruction of subroutine 3 is executed. The valid bit V is already set to “1” for both way 0 and way 1. Therefore, the process proceeds to step A4, and the way 1 whose replacement protection bit L is “0” is selected by the control of the replacement control circuit 112. The corresponding entry of the way 1 is replaced by the data read from the external memory 800 (step A1 → step A3 → step A4 → step A7 → step A10).

  That is, the subroutine 1 stored in the way 0 is protected from the replacement and held in the cache memory because the replacement protection bit L is “1”.

  At this time, the lock area determination circuit 111 determines whether or not the address of the address bus to be accessed is an address of the designated address area (step A11). “0” is set to the area hit signal S1.

  The tag memory 101 of way 1 sets the replacement protection bit L of the entry that has been replaced to “0” when the lock area hit signal S1 of the lock area determination circuit 111 is set to “0” ( Step A13).

  Then, the CPU 108 executes the data read from the external memory 800 (Step A14).

  When the processing of the subroutine 3 is completed and the process returns to the main program, the next conditional branch instruction is executed. In the conditional branch instruction, the branch to the Loop label is performed according to the determination of the condition, and the main program calls the subroutine 1 again. A cache hit occurs, and the CPU 108 reads and executes an instruction from the cache memory (step A1 → step A2).

  When the processing of the subroutine 1 is completed, the main program sequentially calls the subroutine 2 and the subroutine 3 as described above, and the processing is performed. However, the replacement control circuit 112 when the instructions of the subroutine 2 and the subroutine 3 are executed is performed. In the same way as described above, the replacement is made to the entry of the way 1 whose replacement protection bit L is “0” (step A 1 → step A 3 → step A 4 → step A 7 → step A 10).

  In this way, it is possible to reliably protect the instruction of subroutine 1 that requires high-speed execution from the replace operation due to a cache miss.

  As described above, according to the present embodiment, a specific area is designated by the address area designation register 110, and when the designated area is stored in the cache memory, the replace protection bit L is set to “1”. The subsequent replacement operation can be surely protected, and the designated area can be accessed at high speed.

  In addition to the above-described function of the replacement control circuit 112 described in the present embodiment, a replacement protection enable register controlled by software is provided, thereby enabling the replacement protection to be enabled / disabled by the replacement control. Then, the cache memory can be used more efficiently.

(Second Embodiment)
The second embodiment of the present invention also takes into consideration the following problems in the first embodiment. This is a problem when the frequency of access to the area to be protected from replacement changes depending on the program execution state. That is, in the first embodiment, the address area to be replaced is specified in the address area specifying register 110 in the lock area determination circuit 111. When data corresponding to that range is stored in the cache memory, if the access frequency to the address area subject to replacement protection changes depending on the program execution status, the program controls whether to enable or disable replacement protection. There is a problem that it is difficult to do, or that the program increases to determine the state.

  In the second embodiment, the replacement protection is automatically switched between valid / invalid using the access frequency information.

  FIG. 5 is a block diagram showing the configuration of the cache memory control device according to the second embodiment of the present invention, FIG. 6 is a flowchart showing the operation of the cache memory access control according to the second embodiment, and FIG. It is a flowchart which shows operation | movement of a circuit.

  The cache memory control device according to the present embodiment includes the way 0 tag memory 100, the way 1 tag memory 101, the way 0 data memory 102, the way 1 data memory 103, and the hit detection described in the first embodiment. And 104, 105, output circuits 106 and 107, a lock area determination circuit 111, a replacement control circuit 112a whose structure has been changed this time, and an access frequency counter 113.

  Hereinafter, the access frequency counter 113 and the replacement control circuit 112a, which are different from those in the first embodiment, will be described.

  The access frequency counter 113 is a down counter that subtracts a value at regular intervals, and the count value is designated in advance when the output of the lock area hit signal S1 output from the lock area determination circuit 111 is “1”. When the count value underflows, the access frequency decrease signal Sf is output.

  The replacement control circuit 112a receives, as input signals, the replacement protection bit L and the valid bit V of each entry of the tag memory 100 of way 0 and the tag memory 101 of way 1 and the access frequency decrease signal Sf output from the access frequency counter 113. Controls the selection of the way to perform the replacement operation.

  The replacement control operation of the cache memory control device will be described below with reference to the flowcharts of FIGS.

  First, the operation of the cache replacement control will be described based on the flowchart of FIG. Here, changes from the cache replacement control operation in the first embodiment shown in FIG. 2 will be described.

  In step C1, it is determined whether or not there is an entry whose effective bit V is “0” in the entry to be accessed. If there is, the process branches to step A6, and if not, the process branches to step C2. .

  In step C2, it is determined whether or not the access frequency decrease signal Sf output from the lock area determination circuit 111 is “1”. If it is “1”, the process branches to step C3 and is not “1”. In this case, the process branches to step A4.

  In step C3, regardless of the value of the replacement protection bit L of the entry, one of the entries to be accessed is selected. At this time, the entry selection method is the LRU method. Note that the method for selecting an entry is not limited to the LRU method, but may be a FIFO method or a method of selecting at random.

  Next, the operation of the lock area determination circuit 111 will be described based on the flowchart of FIG. Here, changes from the cache replacement control operation in the first embodiment shown in FIG. 3 will be described.

  In step B4, when the lock area hit signal S1 output from the comparator 109 becomes “1”, the count value of the access frequency counter 113 is set to a preset initial value, and down-counting is started at the same time.

  In step B5, it is determined whether or not an underflow has occurred in the address counter. If not, the process branches to step B6, and if it has occurred, the process branches to step B7.

  In step B6 when no underflow has occurred, “0” is output to the access frequency lowering signal Sf, and the flow is terminated.

  In step B7 when underflow has occurred, "1" is output to the access frequency lowering signal Sf, and the flow ends.

  As described above, according to the present embodiment, after the data in the address area for which replacement protection is set in the lock area determination circuit 111 is stored in the cache memory, the access issued by the CPU 108 is within the designated area. By evaluating the frequency with a down counter that is set to the initial value when an access occurs, it is detected that the program has entered an execution state that does not execute instructions protected from replacement, and replacement protection is automatically disabled. This makes it possible to implement the cache memory efficiently.

  FIG. 8 is a block diagram showing a configuration of a cache memory control device according to a modification of the present embodiment.

  This is a replacement control circuit 112b configured as follows. Depending on the conditions, a lock entry invalidation signal Si is output from the replacement control circuit 112b to the tag memory 100 of way 0 and the tag memory 101 of way 1. That is, when the access frequency lowering signal Sf is output as “1” from the access frequency counter 113, the replacement control circuit 112b determines that the entry with the replacement protection bit L set to “1” becomes unnecessary and the replacement control circuit 112b disables the lock entry. The synthesize signal Si is output. In that case, in the tag memory 100 of way 0 and the tag memory 101 of way 1, the entry is cleared by clearing the valid bit V of the entry whose replacement protection bit L is “1” to “0”. Disable it. As a result, efficient use of the cache memory can be realized.

  Note that the valid bit V of the entry whose replacement protection bit L is “1” is cleared to “0” and invalidated by a control signal output by the CPU 108 executing a special instruction instead of the access frequency lowering signal Sf. May be.

  Note that the access frequency counter subtracts the value every fixed time, but instead, the value may be subtracted for each access. Further, instead of the down counter, an up counter that adds values may be used, and the access frequency lowering signal Sf may be output due to overflow.

(Third embodiment)
The third embodiment of the present invention also takes into account the following problems in the second embodiment.

  In the second embodiment, for an instruction that needs to be held in the cache memory due to the necessity of high-speed execution, the address area where the instruction is arranged is designated as a replacement protection area in the lock area determination circuit. When the data in the replacement protection area is stored in the cache memory, the replacement protection bit L of the tag memory entry is set to “1” to enable protection from the replacement operation, and the cache memory can be used efficiently. It became.

  However, if the instruction to be protected from replacement is not one continuous address area, but two or more address areas with an address area that does not need to be protected from replacement in between, the protection is performed from replacement. Therefore, there is a problem that protection must be performed as one address space including an area that does not need protection.

  FIG. 9 is a block diagram showing the configuration of the cache memory control apparatus according to the third embodiment of the present invention.

  The cache memory control device according to the present embodiment includes the way 0 tag memory 100, the way 1 tag memory 101, the way 0 data memory 102, the way 1 data memory 103, and the hit detection described in the second embodiment. And 104, 105, output circuits 106 and 107, a lock area determination circuit 111, a replacement control circuit 112a, a lock area determination circuit 121 newly added this time, and an OR circuit 118.

  Below, a different part from 2nd Embodiment is demonstrated.

  The lock area determination circuit 121 has the same configuration as the lock area determination circuit 111. The OR circuit 118 is configured to output the logical sum of the lock area hit signals output from the two lock area determination circuits 111 and 121 as the lock area hit signal S1.

  Since the flow of the cache replacement control of the present embodiment is the same as that of the second embodiment shown in FIGS. 6 and 7, the description thereof is omitted here.

  According to the present embodiment, by using a plurality of lock area determination circuits, it is possible to set a plurality of areas to be subjected to replacement protection, thereby realizing effective replacement protection.

  In this embodiment, in order to simplify the description, two lock area determination circuits each including an address area designation register and a comparator are provided, and an OR circuit 118 performs a logical sum of outputs from the two comparators. However, it is also possible to use a configuration in which three or more lock area determination circuits each including an address area designation register and a comparator are used, and an OR circuit that performs a logical sum of outputs from all the comparators is used.

(Fourth embodiment)
The fourth embodiment of the present invention also takes into account the following problems in the third embodiment.

  In the third embodiment, replacement protection to a plurality of address areas is realized by using a plurality of lock area determination circuits, thereby enabling efficient replacement protection.

  However, in the configuration of the cache memory control device according to the third embodiment, a plurality of address areas can be designated for replacement protection, but the access frequency counter and the tag memory replacement protection bit L are shared by a plurality of lock area determination circuits. Therefore, there is a problem that replacement protection cannot be set / released for each lock area determination circuit.

  FIG. 10 is a block diagram showing the configuration of the cache memory control device according to the fourth embodiment of the present invention.

  The cache memory control device according to the present embodiment includes the way 0 data memory 102, the way 1 data memory 103, the hit detectors 104 and 105, the output circuits 106 and 107, and the lock area described in the third embodiment. It comprises a judgment circuit 111, 121, a tag memory 200 of way 0 changed this time, a tag memory 201 of way 1, a replacement control circuit 112c, and an access frequency counter 123 newly added this time. There is no OR circuit 118 shown in FIG. 9 of the third embodiment.

  Below, a different part from 3rd Embodiment is demonstrated.

The tag memory 200 of way 0 and the tag memory 201 of way 1 are a replacement protection bit composed of a tag address for each entry of each way, a valid bit V indicating the validity of the entry, and a plurality of bits indicating the lock state of the entry. L is held. This time, the replacement protection bit L is composed of 2 bits, the 0th bit is controlled by the lock area hit signal S1 ₁ output from the lock area determination circuit 121, and the 1st bit is the lock output from the lock area determination circuit 111. It is controlled by the area hit signal Sl _2.

The replacement control circuit 112c is configured to replace the protection bits L (2 bits) and the valid bits V of the entries in the tag memory 200 of way 0 and the tag memory 201 of way 1 and the access frequency lowering signal output from the access frequency counters 113 and 123. Sf ₂ and Sf ₁ are used as input signals to control the way selection for the replacement operation.

Access frequency counter 123 has the same configuration as the access frequency counter 113, the lock area hit signal Sl ₁ outputted from the lock region determining circuit 121 and the counter initial value setting signal.

  Since the flow of the cache replacement control of the present embodiment is the same as that of the second embodiment shown in FIGS. 6 and 7, the description thereof is omitted here.

  According to the present embodiment, in a cache memory that uses a plurality of lock area determination circuits and performs replacement protection for a plurality of areas, the replacement protection bit L of the tag memory can identify which replacement protection area is being replaced. By configuring the number of bits and having an access frequency counter for each lock area determination circuit to evaluate the access frequency for each replacement protection area, the replacement control circuit sets / releases the replacement protection for each replacement protection area. This makes it possible to implement effective replacement protection.

  For each of the replacement protection areas set by the plurality of lock area determination circuits, a function for performing replacement protection control according to the replacement protection priority is added to the replacement control circuit 112c for the replacement protection priority. If the address where the miss occurred is in the replacement protection area and all the replacement protection bits L of the entry to be replaced are “1”, the entry with the lower priority is replaced, The instruction can be held in the cache memory, and the cache memory can be effectively used.

(Fifth embodiment)
The fifth embodiment of the present invention also takes into account the following problems in the first embodiment.

  In the first embodiment, in order to realize the replacement protection, a replacement protection bit L indicating a replacement protection state for each entry is added to the conventional tag memory. Although the addition of the replacement protection bit L is an effective means for performing the replacement protection, the number of tag memory entries increases when the capacity of the cache memory is large. There is a problem that the increase in area cannot be ignored.

  FIG. 11 is a block diagram showing the configuration of the cache memory control apparatus according to the fifth embodiment of the present invention.

  The cache memory control apparatus according to the present embodiment includes a tag memory 600 of way 0, a tag memory 601 of way 1, a data memory 102 of way 0, a data memory 103 of way 1, hit detectors 104 and 105, an output circuit 106, 107, a CPU 108, a comparator 109, an address area designation register 110, a lock area determination circuit 111, and a replacement control circuit 112d. Reference numeral 108 denotes a CPU, and 800 denotes an external memory.

  Below, a different part from 1st Embodiment is demonstrated.

  The tag memory 600 of way 0 and the tag memory 601 of way 1 hold a tag address and a valid bit V indicating the validity of the entry for each entry of each way.

  The replace control circuit 112d receives the valid bit V of each entry in the tag memory 600 of way 0 and the tag memory 601 of way 1 and the lock area hit signal S1 output from the lock area determination circuit 111 as input signals, and uses the lock area determination circuit. The control signal of the selector 161 that selects the tag addresses output from the tag memories 600 and 601 of the way 0 and the way 1 input to the control unit 111 is used as an output signal to control selection of the way to perform the replacement operation.

  According to the present embodiment, when executing the replacement operation, the replacement control circuit 112d sequentially compares the tag addresses of the entries to be replaced in the way 0 and the way 1 by the lock area determination circuit 111, and performs the cache operation. It is determined whether the data held in the memory is data that reliably protects from the replace operation.

  As a result, replacement protection can be realized without using a tag memory having the replacement protection bit L, and replacement protection can be performed without increasing the area of the tag memory due to the addition of the replacement protection bit L. Become.

  Note that a plurality of comparators 109 may be provided, and the tag addresses of a plurality of ways and the value of the address area designation register 110 may be compared simultaneously.

(Sixth embodiment)
FIG. 12 is a block diagram showing the configuration of the cache memory control apparatus according to the sixth embodiment of the present invention.

  In the first embodiment, replacement protection is performed for a designated address area. In this embodiment, replacement protection is performed in units of tasks.

  The cache memory control device according to the present embodiment includes the way 0 tag memory 100, the way 1 tag memory 101, the way 0 data memory 102, the way 1 data memory 103, and the hit detection described in the first embodiment. And 104, the output circuits 106 and 107, the replacement control circuit 112, and the lock region determination circuit 501 whose structure has been changed this time. The lock area determination circuit 501 includes a task ID specification register 500 that holds a task ID to be replaced and a comparator 109a.

  Below, a different part from 1st Embodiment is demonstrated.

  The CPU 108 is configured to output the task ID of the currently executing task to the lock area determination circuit 501.

  In the comparator 109a, the lock area determination circuit 501 compares the task ID of the replacement protection target held in the task ID designation register 500 with the task ID of the task being executed output from the CPU 108, and the results match. In this case, the lock area hit signal S1 is output. The lock area hit signal S1 sets “1” to the replacement protection bit L of the corresponding entry in the tag memory 100 of way 0 and the tag memory 101 of way 1.

  According to the present embodiment, by specifying replacement protection as a task ID instead of a memory address, replacement protection can be performed in units of tasks, and there is no need to examine an address area used in a task. Easy replacement protection setting is possible.

(Seventh embodiment)
FIG. 13 is a block diagram showing the configuration of the cache memory control apparatus according to the seventh embodiment of the present invention.

  This is a task frequency counter 113a having the same function as the access frequency counter 113 in the fourth embodiment. The task frequency counter 113a uses the lock area hit signal S1 output from the lock area determination circuit 501 to detect that the program has entered an execution state in which the task protected from replacement is not executed. The detection signal is output to the replacement control circuit 112d. The replacement control circuit 112d that has received the detection signal automatically disables the replacement protection. Thereby, the cache memory can be used efficiently.

  FIG. 14 is a block diagram showing the configuration of the cache memory control device according to the embodiment in which the replacement protection is changed to the interrupt level output from the CPU 108 instead of performing the protection in units of tasks.

  The task ID designation register 500 in FIG. 12 is changed to the interrupt level designation register 510, and replacement protection is performed in units of interrupt levels. In that case, the value set in advance in the interrupt level designation register 510 is compared with the interrupt level signal output from the CPU 108, and the lock area hit signal S1 is output. Thereby, the replace protection bit L of the entry is set and replaced. Used for time way selection.

  In the first to sixth embodiments, cache access to instructions has been described, but the same applies to data access.

  Further, the cache memory having the 2-way configuration has been described, but the configuration is the same for configurations other than the 2-way.

  In order to specify the lock area, the start address and the final address of the lock area are set in the address area specifying register 110. However, a common upper part may be set for the address of the area. In this way, it is determined whether or not the address is included in the lock area by comparing only with the set upper part.

  The cache memory control device and the control method of the present invention have a function of setting replacement protection, and are useful for an information processing device using a microprocessor or a cache memory.

The block diagram which shows the structure of the cache memory control apparatus of the 1st Embodiment of this invention The flowchart which shows the operation | movement of the cache memory access control of 1st Embodiment The flowchart which shows operation | movement of the lock area | region determination circuit of 1st Embodiment. Part of the program executed in the first embodiment The block diagram which shows the structure of the cache memory control apparatus of the 2nd Embodiment of this invention The flowchart which shows the operation | movement of the cache memory access control of 2nd Embodiment The flowchart which shows operation | movement of the lock area | region determination circuit of 2nd Embodiment. The block diagram which shows the structure of the cache memory control apparatus of the deformation | transformation form of the 2nd Embodiment of this invention. The block diagram which shows the structure of the cache memory control apparatus of the 3rd Embodiment of this invention The block diagram which shows the structure of the cache memory control apparatus of the 4th Embodiment of this invention The block diagram which shows the structure of the cache memory control apparatus of the 5th Embodiment of this invention The block diagram which shows the structure of the cache memory control apparatus of the 6th Embodiment of this invention The block diagram which shows the structure of the cache memory control apparatus of the 7th Embodiment of this invention Block diagram showing a configuration of a cache memory control device according to a modification of the seventh embodiment of the present invention

Explanation of symbols

100, 200, 301, 600 Way 0 tag memory 101, 201, 302, 601 Way 1 tag memory 102 Way 0 data memory 103 Way 1 data memory 104, 105 Hit detector 106, 107 Output circuit 108 CPU
109, 109a Comparator 110 Address area designation register 111, 121, 501, 511 Lock area determination circuit 112, 112a, 112b, 112c, 112d Replacement control circuit 113, 123 Access frequency counter 113a Task frequency counter 118 OR circuit 500 Task ID designation Register 510 Interrupt level specification register 800 External memory

Claims (19)

A tag memory having a plurality of entries holding valid bits, replacement protection bits, and tag addresses;
A data memory for holding data corresponding to the entry of the tag memory;
A cache hit detection means for detecting a cache hit based on a comparison between the tag address output from the tag memory and an access request address and a value of the valid bit;
A lock area determination unit that compares the address area to be replaced with the access request address and outputs a lock area hit signal when they match,
A replacement control means for selecting the way to be replaced, using the value of the effective bit held by the tag memory and the value of the replacement protection bit as inputs; and
The tag memory enables the replace protection bit of the entry corresponding to the lock area hit signal,
The cache memory control device, wherein the replacement control means preferentially selects an entry for which the replacement protection bit is not valid as a replacement target. The lock area determination means includes
Address area specifying means for specifying the address area to be replaced,
2. The cache memory control device according to claim 1, further comprising a comparison unit that compares the value held by the address area designating unit with the access request address.   The tag memory further includes a replacement protection permission bit capable of controlling replacement protection by software, and the replacement control means invalidates the replacement protection that is enabled based on the replacement protection permission bit. The cache memory control device according to claim 1 or 2. A tag memory having a plurality of entries holding valid bits, replacement protection bits, and tag addresses;
A data memory for holding data corresponding to the entry of the tag memory;
A cache hit detection means for detecting a cache hit based on a comparison between the tag address output from the tag memory and an access request address and a value of the valid bit;
A lock area determination unit that compares the address area to be replaced with the access request address and outputs a lock area hit signal when they match,
An access frequency evaluation unit that evaluates the access frequency to the address area to be replaced by the lock area hit signal output from the lock area determination unit and outputs an access frequency decrease signal when the decrease in the access frequency is detected; ,
A replacement control means for selecting a replacement target way with the value of the effective bit held by the tag memory, the value of the replacement protection bit, and the access frequency lowering signal output by the access frequency evaluation means as inputs;
The tag memory enables the replace protection bit of the entry corresponding to the lock area hit signal,
When the access frequency lowering signal is valid, the replacement control unit invalidates the replacement protection and selects a replacement target entry, and when the access frequency lowering signal is invalid, the replacement control unit preferentially selects an entry whose replacement protection bit is not valid. The cache memory control device is characterized in that it is selected as a replacement target. The lock area determination means includes
Address area specifying means for specifying the address area to be replaced,
5. The cache memory control device according to claim 4, further comprising a comparison unit that compares the value held by the address area designating unit with the access request address. Furthermore, an entry invalidating means for invalidating the valid bit of all entries in which both the valid bit and the replacement protection bit have valid values,
6. The cache memory control device according to claim 4, wherein the replacement control means is configured to operate the entry invalidation means of the tag memory when the access frequency lowering signal becomes valid. A tag memory having a plurality of entries holding valid bits, replacement protection bits, and tag addresses;
A data memory for holding data corresponding to the entry of the tag memory;
A cache hit detection means for detecting a cache hit based on a comparison between the tag address output from the tag memory and an access request address and a value of the valid bit;
A plurality of lock area determination means for comparing the address area to be replaced with the access request address and outputting a lock area hit signal when they match;
An access frequency evaluation unit that evaluates the access frequency to the address area to be replaced by the lock area hit signal output from the lock area determination unit and outputs an access frequency decrease signal when the decrease in the access frequency is detected; ,
A replacement control means for selecting a replacement target way with the value of the effective bit held by the tag memory, the value of the replacement protection bit, and the access frequency lowering signal output by the access frequency evaluation means as inputs;
Set replacement protection for a plurality of address areas by a plurality of the lock area determination means,
The tag memory enables the replace protection bit of the entry corresponding to the lock area hit signal,
When the access frequency lowering signal is valid, the replacement control unit invalidates the replacement protection and selects a replacement target entry, and when the access frequency lowering signal is invalid, the replacement control unit preferentially selects an entry whose replacement protection bit is not valid. The cache memory control device is characterized in that it is selected as a replacement target. The lock area determination means includes
Address area specifying means for specifying the address area to be replaced,
8. The cache memory control device according to claim 7, further comprising a comparison unit that compares the value held by the address area designating unit with the access request address. A tag memory having a plurality of entries holding valid bits, a plurality of replacement protection bits, and a tag address;
A data memory for holding data corresponding to the entry of the tag memory;
A cache hit detection means for detecting a cache hit based on a comparison between the tag address output from the tag memory and an access request address and a value of the valid bit;
A plurality of lock area determination means for comparing the address area to be replaced with the access request address and outputting a lock area hit signal when they match;
A plurality of access frequency evaluations that evaluate the access frequency to the address area to be replaced by the lock area hit signal output by the lock area determination means and output an access frequency decrease signal when the access frequency decrease is detected Means,
A replacement control means for selecting a replacement target way by inputting the value of the effective bit held in the tag memory, the values of the plurality of replacement protection bits, and the access frequency decrease signal output by the plurality of access frequency evaluation means; With
Set replacement protection for a plurality of address areas by a plurality of the lock area determination means,
The tag memory enables the replace protection bit corresponding to the lock area hit signal of the entry corresponding to a plurality of the lock area hit signals,
When the access frequency lowering signal is valid, the replacement control unit invalidates the replacement protection and selects a replacement target entry, and when the access frequency lowering signal is invalid, the replacement control unit preferentially selects an entry whose replacement protection bit is not valid. The cache memory control device is characterized in that it is selected as a replacement target. The lock area determination means includes
Address area specifying means for specifying the address area to be replaced,
The cache memory control device according to claim 9, further comprising a comparison unit that compares the value held by the address area designating unit with the access request address. A tag memory having a plurality of entries holding valid bits and tag addresses;
A data memory for holding data corresponding to the entry of the tag memory;
A cache hit detection means for detecting a cache hit based on a comparison between the tag address output from the tag memory and an access request address and a value of the valid bit;
A plurality of lock area determination means for comparing the address area to be protected for replacement with the tag address output from the tag memory and outputting a lock area hit signal when they match.
A replacement control means for selecting the way to be replaced with the value of the effective bit held in the tag memory and the lock area hit signal as inputs, and
A cache memory control device that performs replacement protection by designating an address space by them. The lock area determination means includes
Address area specifying means for specifying the address area to be replaced,
12. The cache memory control device according to claim 11, further comprising a comparison unit that compares the value held by the address area designating unit with the access request address. A tag memory having a plurality of entries holding valid bits, replacement protection bits, and tag addresses;
A data memory for holding data corresponding to the entry of the tag memory;
A cache hit detection means for detecting a cache hit based on a comparison between the tag address output from the tag memory and an access request address and a value of the valid bit;
A lock area determination unit that compares a task ID to be replaced with a task ID being executed output by the CPU and outputs a lock area hit signal when they match,
A replacement control means for selecting the way to be replaced, using the value of the effective bit held by the tag memory and the value of the replacement protection bit as inputs; and
A cache memory control device that performs replacement protection by designating a task ID using them. The lock area determination means includes
Task ID designation means for designating the task ID of the replacement protection target;
14. The cache memory control device according to claim 13, further comprising a comparison unit that compares the task ID held by the task ID designating unit with the task ID being executed. Further, a task execution frequency evaluation unit that evaluates the execution frequency of a task subject to replacement protection based on the lock region hit signal output from the lock region determination unit and outputs an execution frequency decrease signal when the decrease in the execution frequency is detected. With
The replacement control unit is configured to add an execution frequency decrease signal output from the task execution frequency evaluation unit as an input, and when the execution frequency decrease signal is valid, invalidate the replacement protection and select a replacement target entry. 15. The cache memory control device according to claim 13 or claim 14. A tag memory having a plurality of entries holding valid bits, replacement protection bits, and tag addresses;
A cache hit detection means for detecting a cache hit based on a comparison between the tag address output from the tag memory and an access request address and a value of the valid bit;
A lock area determination unit that compares the interrupt level to be replaced with the interrupt level being executed output by the CPU and outputs a lock area hit signal when they match,
A replacement control means for selecting the way to be replaced, using the value of the effective bit held by the tag memory and the value of the replacement protection bit as inputs; and
A cache memory control device that performs replacement protection by designating an interrupt level. The lock area determination means includes
Interrupt level designating means for designating the interrupt level to be replaced,
17. The cache memory control device according to claim 16, further comprising a comparison unit that compares the interrupt level held by the interrupt level designating unit with the interrupt level being executed. An area determination step for determining whether an access request from the CPU is an access to an address area targeted for replacement protection;
Selection step 1 for selecting an entry for which a valid bit is not set as an entry to be replaced due to a cache miss;
A selection step 2 for selecting an entry in which the replacement protection bit is not set when an entry to be replaced cannot be selected in the selection step 1;
A writing step of writing data to the entry selected by either the selection step 1 or the selection step 2;
A cache memory control method comprising: a protection setting step of writing a result of the area determination step into a replacement protection bit of a selected entry. An area determination step for determining whether an access request from the CPU is an access to an address area targeted for replacement protection;
An access frequency evaluation step of evaluating an access frequency to the replacement protected address area and outputting an access frequency decrease signal when the access frequency decreases;
Selection step 1 for selecting an entry for which a valid bit is not set as an entry to be replaced due to a cache miss;
An entry in which the replacement protection bit is not set as an entry to be replaced when the entry to be replaced cannot be selected in the selection step 1 and the access frequency lowering signal indicates that the access frequency has not decreased. Selection step 2 for selecting
A selection step 3 for selecting an entry to be replaced regardless of the replacement protection bit when the entry to be replaced cannot be selected in the selection step 1 and the access frequency decrease signal indicates a decrease in the access frequency; ,
A writing step of writing data to the entry selected by any of the selection step 1, the selection step 2 and the selection step 3;
A cache memory control method comprising: a protection setting step of writing a result of the area determination step into a replacement protection bit of a selected entry.

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