JP2009505178A - Apparatus and method for storing data and / or instructions in a computer system comprising at least two instruction execution units and at least a first storage device or storage area for data and / or instructions - Google Patents

Abstract

The present invention is an apparatus and method for storing data and / or instructions in a computer system comprising at least two instruction execution units and at least a first storage device or storage area for data and / or instructions. In the apparatus and method in which switching means is provided and switching is performed between at least two drive modes, comparison means is provided, the first drive mode corresponds to the compare mode, and the second drive mode corresponds to the performance mode. Includes a second storage device or storage area, the device is configured as a cache memory system, is provided with at least two different ports, one port is directly connected to the first instruction execution unit, A third device is included between the second port and at least the second instruction execution unit. At least two instruction execution units and data are configured such that the second instruction execution unit accesses the second storage device or storage area via the third device. And / or an apparatus and method for storing data and / or instructions in a computer system comprising at least a first storage device or storage area for instructions.

Description

  The present invention relates to a microprocessor system with a high-speed buffer storage (cache), in this regard, for dual port caches and in particular alternatively functioning independently of each other, or The use of a dual port cache for use in a data processing system comprising at least two instruction execution units that process the same task is described.

  A multiprocessor architecture in which a plurality of instruction execution units (cores, processors) cooperate in various forms, that is, in various drive modes (as described in DE 10332700). At least two different modes must be able to be switched by command. Also, when processing the same task, it must be possible to compare the generated data with each other.

  The processor is provided with a cache to accelerate access to instructions and data. This is indispensable in situations where the amount of data is constantly increasing, while the data processing by processors that are always running at higher speeds is becoming increasingly complex. The cache partially avoids slow access to large (main) storage, and the processor does not have to wait until data is provided. An instruction-dedicated cache and a data-dedicated cache are known, but a unified cache in which data and instructions are stored in the same cache is also known. A system including a plurality of levels (hierarchical levels) of caches is also known. Such a multi-layer (structured) cache optimizes the speed between the processor and the (main) storage device by leveled storage capacity and various types of addressing strategies for the cache at various hierarchical levels. Built in to adjust. In a multiprocessor system, usually, one cache is provided for each processor, or in the case of a multi-level cache, a plurality of caches are provided corresponding thereto. Furthermore, as described in U.S. Pat. No. 4,345,309, there is known a system in which a plurality of (internal) caches that can be addressed by various processors are present.

  In the system as described above except for the present application, a unit (comparator (Verglericher)) for comparing generated data is arranged according to a cache in a possible embodiment. Thus, data can only be compared during a write-back from the cache to main storage, and therefore the evaluation of the validity of the data can be delayed. On the other hand, when the comparator is disposed between the instruction execution unit and the cache, data transfer between the instruction execution unit and the cache is delayed by a relatively high electrical load of the signal.

  An object of the present invention is to confirm that the data comparison is performed almost simultaneously with the storage in the cache and not depending on the response time to the main memory. In doing so, data transfer between at least one instruction execution unit and the cache should not be prevented by a relatively high electrical load.

  The implementation of dual port cache memory (Dual Port Cache-Speicher) is costly in hardware, and therefore has an inventive step in a conventional processor system having one or a plurality of instruction execution units (single core or multi-core). Absent. A multiprocessor architecture in which a plurality of instruction execution units (cores, processors) cooperate in various forms, that is, in various driving modes (as described in German Patent Application Publication No. 10332700). In some cases, a dual port cache architecture is advantageously deployed. An important advantage over a multiprocessor system with multiple caches is that the cache contents need not be cleared or invalidated when switching the drive mode of the multiprocessor system. That is, the data is stored only once and is therefore consistent (data) after switching.

  Therefore, for at least one instruction execution unit, data transfer is performed without interruption in this high-speed region where the data rate is high due to the direct connection with the cache. Nevertheless, immediately after the data is stored in the cache. There may be advantages to embodiments in which the comparison is performed without delay. At this time, the second port of the cache to which the data is read back for comparison is used.

  Dual port caches in multiprocessor systems with multiple drive modes have the advantage that data / instructions do not have to be called into the cache multiple times and possibly processed. Furthermore, even if this data or instruction is used for a plurality of instruction execution units, only one storage cell (Speicherplatz) needs to be provided based on hardware in units of data / instructions. Furthermore, the data does not need to be distinguished in which mode the data was processed or called in the various drive modes of the multiprocessor system. As a special advantage, the cache does not need to be cleared upon switching of drive modes. In a dual port cache, two processors can have read access to the same data / instruction at the same time. Further, as a special advantage, instead of the “write through” mode, a “write back” mode is introduced for the cache. With this method, the (main) storage device does not need to be constantly updated, but is updated only when data is overwritten in the cache. At this time, since the caches for the two processors transmit data of the same source (source), there is no problem of consistency. Furthermore, since the comparison is performed without depending on the write-back to the main storage device, the data comparison time is not related to the consistency problem.

  The advantage of the asymmetric dual port structure is that it does not prevent the writing of data to the cache for at least one instruction execution unit, as proposed here in accordance with the present invention, while the data in the cache There is no need to wait for the comparison until it is written to the main memory. Therefore, when a block in the cache is replaced by another block ("write back" mode), the data is first written back to the main memory in units of blocks (zurueckschriben). For this reason, the data rate on the bus between the cache and the main storage device is slower than the “write-through” mode in which the corresponding data in the main storage device is also changed at every update of the data in the cache. At that time, only the changed data is transmitted to the main storage device in parallel, not for each block. Nevertheless, since a write command is also issued to the bus, the bus load on the main memory is larger (in the sense of data transfer).

  In “write back” mode, the instruction execution unit only works with the cache as long as the data in the cache is available. Therefore, when writing to the cache by the instruction execution unit, a dirty bit (Dirty Bit) indicating that the data in the block no longer matches the main memory is set. As long as the participating instruction execution units work with a common cache, the data in main storage need not be updated as long as the associated block remains in the cache. Furthermore, it is possible to change a plurality of data words a plurality of times without impairing the data consistency of the instruction execution unit.

  Preferably, an apparatus for storing data and / or instructions in a computer system comprising at least two instruction execution units and at least a first storage device or storage area for data and / or instructions, wherein the switching means (Umsaltmitel) Is switched between at least two drive modes, a comparison unit is provided, the first drive mode corresponds to the compare mode, and the second drive mode corresponds to the performance mode. A storage device or a storage area, the device being configured as a cache memory system, comprising at least two different ports, one (first) port directly with the first instruction execution unit; Connected, A third device is included between the two ports and at least the second instruction execution unit, and the third device is configured such that the second instruction execution unit accesses the second storage device or the storage area. It is characterized by being configured to be performed via a third device.

  More preferably, in the apparatus, the switching means and / or the comparison means are provided with at least one storage means (Speichermitel), and the switching is performed by at least one bit in the storage means (s). It is a feature.

  More preferably, the device is characterized in that the switching is performed by at least one external or internal signal to the computer system.

  More preferably, in the performance mode, the device ensures that the third device of the directly connected instruction execution unit ensures read and write access to the second storage device via the connected port. It is a feature.

  More preferably, the apparatus has at least one counter in the cache memory system, and the counter receives data related to the comparison by the first instruction execution unit and sends the first port of the cache memory system (dieser Speicher). Each time it is stored via, it is characterized by being incremented or decremented.

  More preferably, the device outputs a counter value when the counter is switched to the compare mode at a corresponding connected port, and the counter value is stored in a third unit (die write Einheit). It is characterized by.

  More preferably, the device is characterized in that a second counter is provided in the third device, and the counter value of the counter is used to set the second counter of the third unit. .

  Preferably, a method for storing data and / or instructions in a computer system comprising at least two instruction execution units and at least a first storage device or storage area for data and / or instructions, the switching means being provided In the method in which switching is performed between at least two drive modes, a comparison unit is provided, the first drive mode corresponds to the compare mode, and the second drive mode corresponds to the performance mode, the second storage device or the storage area is The second storage device or storage area is included in the cache memory system, and is provided with at least two different ports. The first instruction execution unit is connected to the second storage device or storage via the first port. The second instruction execution unit directly accesses the area, and the second instruction execution unit passes the third device to It is characterized in that access to the 憶領 area.

  Preferably, in the method, the third device includes a storage unit, in which data and / or a signal of a connected instruction execution unit can be stored, and a third unit includes the storage unit It is characterized in that data can be exchanged with the second storage device or the storage means without depending on the state of the connected instruction execution unit.

  Preferably, in the method, the third device acquires data and / or an address and / or a control signal from a second instruction execution unit, and then corresponds to the second storage device or the storage area. It is characterized by reading or writing access to data to be read.

  Preferably, the method is characterized in that the cache memory system determines the presence of data and sends a signal to the third device when there is no data.

  Preferably, the method is characterized in that the validity of the data and / or instructions in the third unit is checked and then transmitted if valid.

  Preferably, the method is characterized in that validity is checked on the basis of additional information stored with the data and / or instructions.

  Preferably, the method is characterized in that, together with switching to the compare mode, a synchronization signal is transmitted to an associated instruction execution unit.

  Preferably, the method is characterized in that a comparison is made and an error is signaled when the data being compared does not match (Abweching).

  Preferably, the method is characterized in that a majority decision (voting) is performed, and a status and / or error is notified by a signal when at least one data of majority decision data does not match.

  Preferably, in the method, a counter is provided in the cache memory system, and the counter outputs a counter value when the compare is also switched to a mode at a corresponding connected port. It is characterized by being stored in 3 units.

  Preferably, the method is characterized in that a second counter is provided in the third device and the counter value of the counter is used to set the second counter of the third unit.

  Preferably, in the above method, a counter provided in the cache memory system is assigned to one port, and is set to a fixed value when the compare mode is activated in a processing device connected to each port. It is characterized by that.

  Further advantages and advantageous embodiments of the invention will become apparent from the appended claims and the description in the appended claims.

  Hereinafter, a processor, a core, a CPU, an FPU (floating point arithmetic unit) (Floating Point Unit), a DSP (digital signal processor) (Digital Signal Processor), a core processor, an ALU (arithmetic logic unit) (Arithmetic Logical Unit) are executed by instructions. Collectively.

  The essential part of the dual port cache 200 based on FIG. 1 is a dual port RAM (dpRAM 230). The dpRAM 230 has two word and bit lines (duplicated), unlike two memory decoders (Address decoder), two data write / read steps, and a single memory cell matrix (Speicherzel-Matrix). (Wort-und Bittleunting). Therefore, at least a read process for any storage cell (Speicherzel) of dpRAM is performed simultaneously from the two ports. (However, according to the semantics, if all access components are not duplicated, so dpRAM can only be accessed through two ports at the same time, this also applies to Anordungung.) Dual port RAM is understood as all RAM with two ports 231 and 232. In doing so, the two ports 231 and 232 determine how long this port needs to perform the configuration for reading or writing, i.e. the requested reading or writing process is possibly configured. Are used independently of each other without regard to how long it takes for the interaction to be terminated by the other port. The two ports of dpRAM are connected to the device 210 or 220 via a signal 201 or 202. The device 210 or 220 executes an inspection of the address, data, and control signal 211 or 221 accessed from the independent instruction execution units 215 and 225, and arbitrarily converts the address. The data is output to the control signal 211 by the device 210 via the signal 201 or output to the control signal 221 by the device 220 via the signal 202 according to the port at the time of reading, or in the opposite direction, respectively. , Written from the instruction execution unit to the cache memory. The two ports of dpRAM are connected to a bus access control 240 connected to a signal 241 via signals 201 and 202. The signal 241 forms a connection to a (main) storage device not shown here, or a connection to the next step cache.

  In FIG. 2, the units 210, 220 and 250 are shown in detail. When accessing the dual port cache, the addresses 212 and 222 of the instruction execution units 215 and 225 included in the signals 211 and 221 are compared with each other in the address comparator 251 of the device 250, and the signals 211 and 221 are also used. Along with the transmitted control signal, the consistency is checked. In the case of a collision, access to the dual port RAM 230 is blocked using a control signal included in the signal 213 or 223. As such a collision, two instruction execution units are trying to write to the same address, or one instruction execution unit is reading the same address while the other instruction execution unit is trying to read from the same address There may be cases where you are trying to write to.

  Caching can be implemented partially or fully associatively. That is, data can be stored in multiple or entirely arbitrary locations in the cache. Furthermore, in order to enable access to dpRAM, an address for accessing the desired data / instruction must be determined. According to the addressing mode, one or a plurality of block addresses to be searched for data in the cache are selected. All these blocks are read and the identifier stored with the data in the cache is compared with the index address (the component of the original address). In the case of a match, the validity is also checked after the validity is additionally checked using the control bits (valid bit, valid bit, process ID, etc.) stored in each block in the cache. A cache hit signal indicating the sex is generated.

  In particular, a table (Table) is introduced for address conversion. The table is arranged in the storage unit 214 or 224 (register or RAM, also referred to as TAG-RAM) shown in FIG. This table is an address translation unit, which not only translates virtual addresses into physical addresses, but in the case of a direct-mapped cache, it is an accurate (unique) cache access address. To communicate. That is, in the case of a plurality of associative cache structures, a plurality of blocks are called. Also, for a complete associative cache, all blocks of the cache must be read and compared. Such an address conversion unit is described in, for example, US Pat. No. 4,669,043.

  For example, in the above table, each block address or address group corresponds to an access address of dpRAM. In the addressing format shown in FIG. 3, the most significant address bit (index address) is used as a table address according to the block capacity of the cache, and the contents thereof are the access address of dpRAM (FIG. 3). ). At this time, when the cache address is read-accessed, a plurality of bytes that are called from the memory to the cache at the time of a cache miss (there is no data necessary for the cache) are designated as a block (Block). Call. Such block transfers are performed either sequentially in time or in parallel, depending on the hardware implementation with multiple components.

  For access to the cache in bytes or words, the most significant address bits for the block are translated by the table, and the remaining (lower) address bits are carried on unchanged.

  For the writing process, for example, one of the two ports is given higher priority. That is, writing by two ports at the same time is prevented. The other port may write only after the port with the higher priority performs the write operation. In some cases, only one processor has write (access) rights to the corresponding allocated memory area. Similarly, during any write operation to a memory cell, the same memory cell is prevented from being read from the other port each time. Alternatively, the read operation is delayed by stopping the processor requesting the read until the end of the write operation. Further, the address comparator (251) of all address bits shown in FIG. 2 includes a corresponding arbiter (Arbiter) 252. Arbiter 252 also evaluates the control signals of the processor and forms output signals 213 and 223 that control this writing process. The output signals 213 and 223 can, in an advantageous embodiment, be in three signal states each time: Select, wait and equal. For a pure instruction cache, write access is not necessary. In other words, in this case, it is sufficient if the signal states of the output signals 213 and 223 are “equal”.

  In the event of a cache miss, data or instructions must be called from program or data memory via the bus system. The recalled data is then transmitted to the instruction execution unit and written to the cache along with the identifier and control bits in parallel. Again, the address comparator prevents recall of data from memory if the equal signal (component or state of 213 and 223) is displayed by the address comparator, even if there is no hit. The equal signal is always formed by only the most significant address bits when reading from both, since all blocks of the storage device are called. Only when the block is stored in the cache, the waiting instruction execution unit can access the cache.

  In yet another advantageous embodiment, two different dual port caches for data and instructions are provided. In a dual port cache for instructions, no write process is provided. In this case, the address comparator always checks only the most significant bit match (Gleichheit) and provides the corresponding control signal “equal” in the signals 213 and 223.

In yet another embodiment, simultaneous read access from both ports is done indefinitely when the requested data is in different (separate) address areas that allow simultaneous access. Therefore, when hardware is implemented, the entire access structure (Zugriff-Mechanism) in the storage device does not need to be duplicated, thereby saving costs. For example, the cache can be implemented in a plurality of sub-storage areas (Teilspeicherberich) that are driven independently of each other. Each sub storage area enables only port execution via a selection signal (select-Signal). FIG. 4 shows such a storage device 230 and includes two sub-storage areas 235 and 236. In the embodiment shown here, the address bits _{A i,} 2 two selection signals _{E 0} and _{E 1 are} the _E 0 = _{1, E} 1 = 0 is the time of _A i = 0, also when _A i = 1 Are formed such that E ₀ = 0 and E ₁ = 1. The signals 233 and 234 include two selection signals and lower address bits A _i−1 ... A ₀ .

In yet another embodiment with four sub-storage devices, each sub-storage device uniquely supplies one specific address area, so that four selection signals are generated from two address bits. The Thus, for example, four sub-storage areas are generated by generating four address signals A _{i + 1} and A 3 by generating four selection signals E _{0 to} E ₃ corresponding to binary values based on FIG. T1 (Table 1). can be called by _i .

  FIG. 5 shows an embodiment for the sub-storage devices 235 and 236 shown in FIG. In this special embodiment, the sub storage device 260 is realized as a single port RAM 280, and its address, data, and control signal are switched according to a request. The switching is performed by a control circuit (Steuerschultung) 270 using a multiplexer (Multiplexer) 275 according to a control signal from the corresponding port and another control signal 2901 or 2902 (reading, writing, etc.). These signals are included in signals 233 and 234 along with data and address and are transmitted to multiplexer 275 via signals 5281 and 5282. The multiplexer 275 connects 5281 or 5282 to the signal 2801 according to the output signal 2701 based on the determination of the control circuit 270. In this embodiment, without being limited to general theory, it is based on direct addressing to the cache (direct-mapped). In the case of a multi-associative cache structure, a validity comparison is performed in unit 275 and a cache hit signal is transmitted to the port. Alternatively, all data is transmitted to port 231 via port 5331 and signal 233, or to port 232 via port 5332 and signal 234, where validity is checked.

  At that time, the control circuit can further switch the signal 5281 or 5282 to the signal 2801 to the single port RAM 280, and can transmit the data and other signals of the (single port RAM) 280 in the reverse direction. Is possible. This is done according to valid control signals, signals 233 and 234, and / or the order in which the port prompts the storage device 280 to read or write via these signals. If signals 233 and 234 cause a read or write signal to become active at the same time, the predefined port is used first. The preferential port is then left connected to 2801 if the read or write signal is not active. The preferential port can optionally be set dynamically by the processor system, but in particular, according to the status information of the processor system.

  This arrangement with a single port RAM is less expensive than a dual port RAM with parallel access. However, when one sub-storage device is accessed (read) at the same time, execution of at least one instruction execution unit is delayed. Depending on the application, the RAM sub-area is divided in various ways so that simultaneous access to the same RAM sub-area is performed as much as possible simultaneously with the formation of instruction sequences and data accesses of various instruction execution units. Is possible. This configuration can also be extended to allow access by more than one processor. Similarly, when switching of address, data, and control signal is continuously provided for each step via a plurality of multiplexers (FIGS. 6 and 7), a multi-port RAM can also be realized.

  FIG. 6 shows such a multiport RAM 290. In the multi-port RAM 290, the port input signals 261 to 267 are decoded into signals 291 to 297 in the decoding devices 331 to 337. This combination generates selection signals for access to the individual RAMs in 281, 282 to 288. FIG. 7 shows in detail an embodiment for the sub storage devices 28x (281... 288). In the sub storage device, in the first step of the control device 370, the selection signals from the control signals 291 to 298 and the control signals 3901 to 3908 are processed into output signals 3701 to 3707. Each of these output signals drives a multiplexer 375. The multiplexer 375 connects the bus 381 or 382 to 387 or 388 with the signals 481 to 488 according to the signal value. In yet another step, similar controller 370 and multiplexer 375 are driven appropriately until signals 5901 and 5902 for the controller are used in the last step. Thereafter, the output signal 5701 connects 581 or 582 to 681 connected to the single port RAM.

  Contrary to the multiplexer 275 shown in FIG. 5, the multiplexer 375 in FIG. 7 connects the control signal of the next step included in 381 to 388 in addition to the address, data and control (related) signals. In addition, a multiplexer 375 can include a comparison unit that determines the validity of the data read from the sub-region during the multiple associative addressing scheme.

In yet another advantageous embodiment, switching from a RAM area to various instruction execution units can be associated with one or more system states or configurations. Thus, FIG. 8 shows an example of a configurable dual port cache. In addition, the system or configuration signal 1000 is used in decoding the input signal for each of the two ports. FIG. T2 (Table 2) shows the possibility of changing the decoding according to the signal 1000, denoted as M. When M = 0, for example, the comparison mode is set in which two ports access all the caches. However, if M = 1 (performance mode, etc.), each port has only access (right) to half of the cache, but is not limited (influenced by the operation of other ports). (Half of the cache) can be accessed. In the performance mode, the address bits A _i are not used for addressing the cache (in the direct map mode), but data different from the address bits in addressing is stored in the same location in the cache. Only when the contents of the cache are read out is the identifier used to identify the data being retrieved and whether or not a cache hit signal is generated accordingly. Depending on where the corresponding comparators are arranged, data including identifiers and control bits is output to ports 331-337 via signals 291-297. Further, signals 261 to 267 are output. Similarly, in the performance mode (M = 1), only port 1 has access to all caches. This further alternative embodiment is shown in Figure T3 (Table 3). The user can arbitrarily divide the cache into other formats by a plurality of configuration signals. As a result, the hit rate (Hit-Rate) is once increased in a relatively large cache area, and accordingly, the necessity of calling data from the main storage device is reduced. On the other hand, when different independent cache areas are accessed through various ports as much as possible, various instruction execution units are not blocked (access). Since this condition depends on a program provided for use, there is an advantage in the case where further different configurations are possible according to use. On the other hand, the cache is automatically switched by the mode signal 1000 directly when the system state (compare mode / performance mode) is switched.

  The possibility of switching ports according to this mode or configuration signal is extended in the multi-port cache 290 of FIG. At that time, the ports 331 to 337 control various sub-RAM areas 281 to 288 using a mode or a configuration signal. This control is ensured by a selection signal included in the signals 291 to 297 generated at the corresponding port.

  FIG. 10 shows yet another embodiment where multiple associative caches exist. In the multiple associative cache, data is read back from each of the sub storage devices 281 to 288 together with an identifier and a control bit. The validity is checked in the comparison devices 2811 to 2817, 2821 to 2827,... 2881 to 2887, and the data of the signals 2910, 2920,. In this case, as an alternative, switching by mode or configuration signal is possible in the same way as already shown and described in FIG. At ports 3310, 3320,... 3370, validity signals and possibly mode and configuration signals 1000 are evaluated, and the corresponding valid data is signal 2610, 2620,. 2670.

  FIG. B1 shows a structure that utilizes a dual port cache for an asymmetric system structure with two instruction execution units. In this case, B110 and B111 are two instruction execution units having unique data / address and control signal B120 or B121. B100 is a switching and comparison unit (UVE: Unmschalt-und Verglecheiheit).

  FIG. B2 shows the basic functions of the switching and comparison unit when connected to the two instruction execution units B10 and B11. Various output signals of the instruction execution units B10 and B11, such as data, control and address signals B20 or B21, are connected to the switching unit.

  Furthermore, there are two output signals B40 and B41 in which at least one synchronization signal, i.e. in a configuration according to an embodiment of the invention. The output signals B40 and B41 are each connected to the comparison unit.

  The switching unit includes at least one control register B15. The controller register has at least one memory element for a binary signal (Bit) B16. At that time, the binary signal B16 switches the mode of the comparison unit. This bit B16 can take two values 0 and 1, and is set or reset by a signal B20 or B21 of the instruction execution unit or by an internal process of the switching device.

  In the case of permanent adjustment to the compare mode, it is possible to omit the switching unit and the accompanying control register B15 and switching bit B16. At that time, the switching and comparison unit is permanently a comparison unit and the signal B101 is always 1. Therefore, the state shown in FIGS. B3 and B4 does not exist. Thus, in all of the following discussion, it is assumed that bit B16 is set and signal B101 = 1.

  When this bit B16 is set to 1, the switching unit is driven in the compare mode. In this mode, all data signals accessed by B20 are compared with the data signals of B21 as long as certain configurable control conditions for signals B20 and B21 and / or address signal comparison conditions are met. Control and / or address signals signal the validity of the data and the schedule for comparison of the data to be accessed.

  When this comparison condition is satisfied simultaneously by the two signals B20 and B21, the data of these signals are directly compared, and an error signal B17 is set when they do not match. When only the comparison condition of either the signal B20 or B21 is satisfied, the corresponding synchronization signal B40 or B41 is set. This signal stops processing in the corresponding instruction execution unit B10 or B11. Furthermore, it prevents the subsequent switching of the corresponding signals that have not been compared with each other before. The signal B40 or B41 remains set as long as the comparison condition of the corresponding other instruction execution unit B21 or B20 is satisfied. In this case, a comparison is made and the corresponding synchronization signal is reset.

  When the data to be compared is not provided at the same time as described above, in order to ensure the comparison by the two instruction execution units, the corresponding synchronization signal B40 or B41 resets the data of the corresponding instruction execution unit and the comparison condition. Until it is done, it must be set to the corresponding value. Alternatively, the initially provided data must be stored at the switching unit until a comparison is made.

  Depending on which instruction execution unit first provides data, an instruction execution unit that further executes its own program or process must wait as long as the other instruction execution unit provides corresponding comparison data.

  In a special embodiment of the switching unit according to FIG. B2, one of the signals B40 or B41 can be omitted. That is, if it is always guaranteed that the instruction execution unit to which the signal is attached does not provide comparison data earlier than the other execution instruction unit, the signal B40 or B41 is omitted. When B16 is not set, the synchronization signals B40 and B41 and the error signal B17 are always set to 0. In this case, no comparison is performed, and both instruction execution units are driven in the performance mode independently of each other.

  In the performance mode, the two instruction execution units based on FIG. B1 independently process a program, program part or program segment. The instruction execution unit B111 accesses the cache B105 via the B121, and the cache is connected to the main storage device or another storage device via the B161. The instruction execution unit B110 similarly accesses the dual port cache via the device 106 (adjusted inactive in the performance mode by the control signal B101), and uses the second port of this cache (in this case). (See FIG. B3). The switching and comparison unit (UVE) B100 is inactive. That is, the data is not compared (B16 is not set). In yet another embodiment, for access through the cache by the instruction execution unit B110, but in yet another embodiment herein, direct access to main storage or other storage via B160. Access is provided (see FIG. B4). However, this further alternative has the disadvantage that the data in the cache is no longer consistent. Accordingly, the corresponding block must be invalidated by resetting the valid bit in the cache. That is, the corresponding block must be invalidated either by the processing unit (Bearbeginningheit) B110 itself or by the cache that monitors the bus B161 and detects whether a block provided in the cache is written. . This process is called bus snooping. In contrast, yet another embodiment of FIG. B3 is advantageous because it is less expensive.

  The compare mode of the structure based on FIG. B1 is shown in detail in FIG. B5. When the compare mode is driven by setting B16 in the UVEB 100, both instruction execution units start executing the same program. This program is executed in various ways in both instruction execution units. That is, various algorithms and / or instructions that generate data to be compared are utilized. The instruction execution unit B110 outputs the data to be compared with each other together with the corresponding identifier to the switching or comparison device (UVE) B100.

  This operation prompts storage of a control signal (such as writing) in the read request unit B106. In some cases, an identifier (state or process information, processing cycle) is additionally stored in the storage element B1061, and an address attached to the identifier is additionally stored in the storage element B1062. Therefore, the unit B106 uses the control signal (reading, etc.) generated from B1061 of the control unit B1064, the identifier in B1021, and the address signal B1022 to the dual port cache B105 output by B1062 to read. Start the process. In a read process in a cache for the purpose of comparison, it is always assumed that an instruction execution unit directly connected to the cache has already written data into the cache. This is ensured by the instruction execution unit switching to the compare mode and starting the program processing at an appropriate time (see the paragraph on synchronization below). In compare mode, if the data to be compared is not yet available in the cache (cache miss), the cache must not yet request this data in main storage, and the instruction is directly connected to the cache. The read access must be repeated until it is written by the execution unit and exists in the cache. A counter that counts time monitoring or failed attempts generates an error signal when the data has not been processed in the allowed time domain or within a specific number of attempts (within).

  The data value received accordingly is written to B1063 via B1023. The validity of the data is indicated in the received control signal B1024 (evaluation of the cache hit signal and valid bits, when valid, the data, address and appropriate control signals are compared via B1003, B1002 and B1001 To be provided to B100). At that time, in the read request unit B106, the identifier (control bit) sent back together with the data of the cache is compared with the identifier being processed (aktuell). If the identifiers do not match, a new read process to the same address in the cache is started. Only when the identifier is valid, the data is used with an appropriate control signal B1001 for comparison, possibly with an address that can also be used as an additional identifier. Until the comparison value is available (or when the signal B120 is not temporarily stored in B100, in some cases until the comparison is completed), the instruction execution unit B110 controls the control signal B140 (wait, interrupt, etc.) ) Is stopped via. Therefore, it is ensured that the comparison data of B110 is still present in the signal B120. If the signal B120 is stored in a first-in first-out (FIFO) contained in B100, the instruction execution unit B110 does not need to be stopped until the FIFO capacity is completely full. At this time, a storage unit that can store a plurality of data words and outputs the first stored data again first is called a FIFO (first in first out).

  The synchronization of the two instruction execution units is such that the instruction execution unit B111 stores the comparison data in the cache together with the identifier (address, additional bit, valid bit, dirty bit, process ID, etc.) and the validity is appropriate before the comparison. It is done by being inspected. Further, the stored address data and valid bits are used for generating a cache hit signal. The dirty bit only indicates whether the data in the associated block of the cache has been changed and has not yet been written back to main memory. At this time, the process ID is a program execution identifier that is changed each time valid data is newly written into the cache by the B 111. Therefore, when the process ID is set to a specific value, for example with the start of the compare mode, and is changed, eg, incremented, in a known manner, the data reality is checked.

  FIG. T4 (Table 4) shows the internal structure of the cache. Each row corresponds to a data block.

  The address date (Address-Tag) is a component of the address. It is related to access to the block and is compared with the address index during actual access. A cache hit signal is generated when it matches a valid valid bit (a component of the control bit). A data block can contain data from a few bits to multiple kilobytes. FIG. T5 (Table 5) shows an example of the control bits.

  For example, a counter B1059 is provided in the cache B105 in order to guarantee the increment of the process ID (FIG. B6). The counter B1059 is set to a defined value via the signals B1021 and 1022 at the start of the compare mode (B101 = 1). This value can be, for example, the hexadecimal value 0x0000 when the first compare mode is started. This counter can be continuously incremented each time data related to the comparison is written by B111. In this context, the comparison related to the comparison means that the address and / or other control signals can be used to set whether data is provided for comparison.

  When a counter value as a process ID is stored together with each data in the cache, the data state (Datestand) is uniquely labeled (kennicheen). Using the same type of counter B1069 of unit B106, it is determined by simple comparison whether the corresponding data already exists in the cache. Further, the counter B1069 is set to the same starting value in particular, similarly to the counter B1059, with the operation of B101 (compare mode), and is incremented with each write signal of related data by B110. If the process ID bit in the read block is the same value as the B1069 counter value or higher than the counter value, the data is valid. At this time, since various data may be written to the block a plurality of times, the counter value may be relatively high. The counter needs to be reset with the start of a new cycle. At that time, in the new cycle, data not yet compared must be prevented from being overwritten.

  Yet another embodiment of the counter is to store the lower address bits (address bits 0,..., K−1 not related to block addressing according to FIG. 3) as a component of the process ID. On the other hand, other process ID bits label the cycle. If the word width is greater than 1 byte, the corresponding lower-order bit is omitted. Therefore, it is possible to detect which word in the block was written latest. Further, in the program sequence, for example, data is always written with consecutive addresses. Or, when executing a linear fortuffend program, the value written most recently by B111 is uniquely associated with the current comparison value of B110 using a conversion table. It is possible to make it.

  A further possibility is not to store the counter state as a process ID in the cache together with the data block, but to transmit the current counter state to B106 via the control signal B1064 for each read access by B106. is there. As the process ID, only the ongoing cycle is stored in some memory bits correspondingly. Since cache data blocks can typically contain up to 64 kilobytes today, storage capacity is not essentially reduced. For example, the 16 additional process ID bits (occupancy in the data block) are less than 0,0031%.

  Yet another embodiment of synchronization without using the counters B1059 and B1069 is to send a control signal B141 (such as an interrupt) to the instruction execution unit B111 in order to request a compare mode. The instruction execution unit B111 starts program execution in the compare mode after a known maximum cycle T. The instruction execution unit B110 is appropriately initialized and prepares for the compare mode, and at the same time starts with a delay of the maximum period T. Therefore, it is guaranteed that the comparison data in the dual port cache B106 is always ready before the instruction execution unit B110 outputs the corresponding data. At that time, it is also considered that the data is variously calculated in the value T depending on the case. That is, it is considered that the time (Zeitdauer) consumed in the instruction execution unit B111, which is longer than (consumed in) the instruction execution unit B110, is added to T due to (computation) diversity. .

  Regardless of how the realism of the comparison data is protected, the instruction execution unit B111 is prevented from overwriting data that has not been compared yet when the data is periodically updated, for example. . Further, the reset of the bit B16 can prompt the reset of the control signal B141 to the instruction execution unit B111, for example. As long as B <b> 141 is set, the instruction execution unit B <b> 111 is prevented from overwriting data of the latest cycle when data is periodically updated. At that time, the instruction execution unit B111 executes an operation that may enter a standby loop or that may not have a data comparison. Along with the reset of B141, no further data for comparison is requested from unit B106, and a signal informs that the comparison operation so far has been completed. Unless B141 is newly set, the instruction execution unit B111 is driven in the performance mode. Therefore, the cache data can be overwritten again, but the compare mode is started again only after the reactivation of B141.

  In yet another embodiment, signal B141 is always active for a short period of time to prepare for comparison mode with an interrupt. At this time, B141 is set again for a short time, and the overwriting started thereby prevents overwriting of data until jumping to the relevant program location that newly provides the comparison data (springing).

  The time until the comparison data is prepared by the instruction execution unit B111 after the start of comparison (Zeitdauer) is always longer than the time required for data comparison with the data of the instruction execution unit B110, and the data of B111 is always at least simultaneously. Alternatively, the data is prepared earlier than the data of B110, and by temporarily storing the data of B110 in a single storage device or FIFO in B100, the instruction execution unit B110 does not need to be stopped by the signal B140 for the purpose of synchronization. If this is ensured by an appropriate process, all synchronization processes can be omitted. With regard to the method proposed here, necessary processing is performed for each application (Anending).

  In yet another advantageous embodiment, the dual port cache need not be implemented with dual port RAM, but a single port RAM B 1056 is utilized (see FIG. B7). By the access control B 1057, the two ports are used in accordance with the request in order. However, at any given time, only access to the RAM via signal B 1058 will use both ports. Therefore, when an access conflict occurs, the readback (Rucklesen) by B106 can be additionally delayed by one or more clocks depending on the case, but the data is anyway by two instruction execution units. Since it is transmitted asynchronously, it is not a disadvantage in various uses. What is important is that the instruction execution unit B111 is given a higher priority and is not blocked at the time of access. Furthermore, even if the above-described delay may occur, it is important that sufficient access possibility (chance) is provided to the second port from the overall balance. The advantage of this embodiment is that the hardware for the second port is clearly saved. As long as the signal B1058 is directly connected to the signal B121 in FIG. B7 and neither B1057 nor B102 is omitted, a normal single port cache according to the prior art is provided. The expansion by the sequence control B1057 and the consequent possible connection of B102 is clearly less expensive than incorporating a truly parallel dual port RAM.

  Unit B 106 need not be a separate unit, but can be integrated into UVEB 100 or integrated into a chip with a cache or instruction execution unit.

  If a cache with two or more ports according to FIG. 6, ie multiport cache B 205 is used, corresponding to FIG. 8, two or more processors compare data in compare mode, or A majority decision can be made. That is, it is possible to determine an effective value by majority vote. For each additional instruction execution unit B112,..., An additional read request unit B107,... Is provided according to FIG. B8, so that the UVEB 200 has a corresponding number of inputs. There must be. In the compare or majority decision (voting) mode, the instruction execution unit directly connected to the cache directly writes data for comparison or majority decision to the cache. Of the remaining instruction execution units B110, B112,..., The instruction execution unit (dienige) that first prepares data for comparison / majority determination is connected via the connected read request units B106, B107,. In addition, the corresponding data is requested through the port to which the cache B 205 is connected. Furthermore, this state is transmitted to other instruction execution units and UVEs using a signal B8105. After the data is prepared by the cache via B102, B104,..., The data is prepared for comparison via B8105 of UVEB 200. If all relevant instruction execution units are provided with corresponding data, a comparison / majority decision is made. In some cases, other instruction execution units may control signals B140, B142. ... must be stopped via. In doing so, time monitoring ensures that a comparison is made within an allowed time slot or that an error is signaled.

  Instead of a RAM storage device, a configuration according to an embodiment of the present invention can also include additional alternative storage technologies such as MRAM, FERAM, and the like.

Fig. 2 illustrates a dual port cache for data and / or instructions. The details of the dual port cache are shown. It is a conversion table (Transformationtable) of 214 or 224. The division into two sub-regions of dpRAM is shown. The two sub-regions are driven independently of each other and controlled at the time of access by two separate selection signals for each port. The generation of four selection signals from two address bits using decoding is shown. It shows the realization of a dual port RAM area in a single port RAM using port switching. The division of a multiple port RAM having p ports into a plurality of subaddress areas to be processed in parallel is shown. The realization of a multi-port RAM area in a single-port RAM using port switching is shown. Fig. 6 illustrates partitioning of RAM area for ports according to system state or configuration. The generation of two selection signals from the address bits at each port, taking into account system state or configuration signals, is shown. FIG. 6 illustrates the generation of two select signals from each address bit at each port, taking into account system status or configuration signals, in yet another embodiment. Fig. 4 illustrates the division of a multi-port RAM area by generation of a corresponding selection signal according to the system state or configuration. The division of the area | region with multiple associative access of multiport RAM is shown. Fig. 2 illustrates the principle of an asymmetric DCSL architecture with dual port cache. Fig. 4 illustrates the principle of switching and comparing units for two instruction execution units. The read request unit B106 in the inactive state is shown. The figure shows an alternative access to the storage device by the instruction execution unit via the switching and comparison unit without using the cache when the comparison bit is not set. This shows a read request to the cache by the unit when the comparison bit is set and data is output from the instruction execution unit B110. The structure of the cache is shown. A possible structure of control bits is described. Fig. 5 illustrates a dual port cache and access control using a single port RAM. 2 shows the basic structure of an asymmetric data processing unit that can be switched to multiple modes and multi-port caches.

Claims (19)

An apparatus for storing data and / or instructions in a computer system comprising at least two instruction execution units and at least a first storage device or storage area for data and / or instructions, wherein switching means is provided, and at least In an apparatus in which switching between two drive modes is performed, a comparison unit is provided, the first drive mode corresponds to the compare mode, and the second drive mode corresponds to the performance mode.
In the device, a second storage device or a storage area is included, the device is configured as a cache memory system, provided with at least two different ports, one port directly connected to the first instruction execution unit, A third device is included between the two ports and at least the second instruction execution unit, and the third device is configured to allow the second instruction execution unit to access the second storage device or the storage area. Data in a computer system comprising at least two instruction execution units and at least a first storage device or storage area for data and / or instructions, characterized in that it is arranged to be performed via three devices A device that stores instructions.   2. The apparatus according to claim 1, wherein the switching means and / or the comparing means are provided with at least one storage means, and the switching is performed by at least one bit in the storage means.   The apparatus according to claim 1, characterized in that the switching is performed by at least one external or internal signal to the computer system.   2. The method according to claim 1, wherein in the performance mode, the third device of the directly connected instruction execution unit ensures read and write access to the second storage device via the connected port. The device described.   There is at least one counter in the cache memory system, and the counter is incremented or decremented each time data relating to comparison is stored by the first instruction execution unit via the first port of the cache memory system. The apparatus according to claim 1, wherein:   6. The apparatus of claim 5, wherein the counter outputs a counter value when switched to the compare mode at a corresponding connected port, and the counter value is stored in a third unit.   6. The device according to claim 5, wherein a second counter is provided in the third device, and the counter value of the counter is used to set the second counter of the third unit. . A method of storing data and / or instructions in a computer system comprising at least two instruction execution units and at least a first storage device or storage area for data and / or instructions, comprising switching means, In a method in which switching between the two drive modes is performed, a comparison unit is provided, the first drive mode corresponds to the compare mode, and the second drive mode corresponds to the performance mode.
A second storage device or storage area is provided, the second storage device or storage area is included in the cache memory system, and is provided with at least two different ports, and the first instruction execution unit is connected via the first port. At least two instruction execution units, wherein the second storage unit or storage area is directly accessed, and the second instruction execution unit accesses the second storage unit or storage area via a third unit; A method for storing data and / or instructions in a computer system comprising at least a first storage device or storage area for data and / or instructions.   The third device includes storage means, wherein the storage means can store (von) data and / or signals of a connected instruction execution unit, and a third unit is connected to the connected device. 9. The method according to claim 8, wherein data can be exchanged with the second storage device or storage means without depending on the state of the instruction execution unit.   The third device acquires data and / or an address and / or control signal from a second instruction execution unit, and then reads or writes to the corresponding data in the second storage device or storage area. The method according to claim 8.   9. The method of claim 8, wherein the cache memory system determines the presence of data and sends a signal to the third device if no data is present.   Method according to claim 8, characterized in that the validity of the data and / or instructions in the third unit is checked and then transmitted if valid.   13. The method of claim 12, wherein the validity is checked based on additional information stored with data and / or instructions.   The method according to claim 8, wherein a synchronization signal is transmitted to an associated instruction execution unit together with switching to the compare mode.   9. The method according to claim 8, wherein an error is signaled when a comparison is made and the data being compared do not match.   9. The method according to claim 8, wherein a majority decision is made and a status and / or error is signaled when at least one of the data to be majority decided does not match.   A counter is provided in the cache memory system, and the counter outputs a counter value when switched to the compare mode at a corresponding connected port, and the counter value is stored in the third unit. The method according to claim 8, wherein:   The method according to claim 17, wherein a second counter is provided in the third device, and the counter value of the counter is used to set a second counter of the third unit.   A counter provided in the cache memory system is assigned to one port, and is set to a fixed value when the compare mode is activated in a processing device connected to each port. The method of claim 17.

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