JP2006086456A - Circuit for logical change, and semiconductor device having the circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a circuit for logical changes for reducing power consumption, by suppressing the generation of leak currents and a semiconductor device having the circuit for logic changes. <P>SOLUTION: This circuit for logical change is provided for use in the change of the logic configuration of a logic circuit, and this semiconductor device is provided with the circuit for logic changes. The circuit for logic changes is provided with a logic element for use in the change of the logic configuration, and connection wiring for connecting power source wiring or ground wiring is connected to the logic elements; when the logic element is used, the connection wiring and the power source wiring are connected via a contact; and when the logic element is not used, the connection wiring and the ground wiring are connected via the contact. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a logic change circuit including a logic element separately provided to change a logic configuration of a logic circuit formed of a logic element formed on a semiconductor substrate, and a semiconductor device having the logic change circuit. is there.

  2. Description of the Related Art Conventionally, a semiconductor device in which a logic circuit is configured by forming logic elements such as NAND elements and NOR elements on a semiconductor substrate at a required position is known (see, for example, Patent Document 1).

  When a logic circuit is configured on a semiconductor substrate in this way, not only a desired logic circuit but also a logic changing circuit configured by a plurality of NAND elements or the like so that the logic configuration of the formed logic circuit can be changed. Is provided.

  If there is a need to change the logic configuration of the logic circuit and the change is possible by using a NAND element or the like of the logic changing circuit, a logic circuit having a desired logic configuration can be obtained by changing the wiring pattern. Thus, a large design change is prevented from occurring in the semiconductor device, and the manufacturing cost is reduced.

  For example, the NAND element in such a logic change circuit includes a first p-channel transistor 110 and a second p-channel transistor 120 connected in parallel, and a first n-channel transistor connected in series, as shown in the layout diagram of FIG. 210 and a second n-channel transistor 220.

  That is, the sources of the first and second p-channel transistors 110 and 120 are connected to the power supply wiring 300, respectively, and the drains of the first and second p-channel transistors 210 and 220 are connected to the output wiring 400. The drain of the second n-channel transistor 220 is connected to the source of the first n-channel transistor 210, and the drain of the first n-channel transistor 210 is connected to the ground wiring 500. ing.

  Further, the first element wiring 610 is connected to the gate of the first p-channel transistor 110 and the gate of the first n-channel transistor 210, and the gate of the second p-channel transistor 210 and the gate of the second n-channel transistor 220 are connected to the first n-channel transistor 210. Two-element wiring 620 is connected.

In such a NAND element, the first and second p-channel transistors 110 and 120 are always connected to the power supply wiring 300, and the current is cut off by the first and second p-channel transistors.
Japanese Patent Laid-Open No. 08-288400

  However, as the above-described transistors are miniaturized as the miniaturization technology is improved in response to the demand for higher integration of semiconductor circuits, in particular, power source wirings are provided at the sources of the first and second p-channel transistors. There is a problem that leakage current tends to occur due to the constant connection.

  In particular, the logic change circuit consumes power due to the occurrence of leakage current even though it does not need to be used if there is no problem in the logic configuration of the logic circuit, which may hinder the reduction of power consumption. was there.

  Therefore, in the logic change circuit according to the present invention, in the logic change circuit having the logic element used for changing the logic configuration of the logic circuit, the logic element is provided with a connection wiring that can connect a power supply wiring or a ground wiring.

  In addition, the connection wiring is provided with a contact formation area that can be connected to the power supply wiring by a contact that overlaps the power supply wiring and a contact formation area that can be connected to the ground wiring by a contact that overlaps the ground wiring. When using logic elements, connect the connection wiring and power supply wiring via contacts. When not using logic elements, connect the connection wiring and ground wiring to the contacts. The connection is also characteristic.

  In the semiconductor device of the present invention, in the semiconductor device having the logic change circuit used for changing the logic configuration of the logic circuit, the logic change circuit is provided with a logic element used for changing the logic configuration. Connection wiring that enables connection of power supply wiring or ground wiring is provided.

  In addition, the connection wiring is provided with a contact formation area that can be connected to the power supply wiring by a contact that overlaps the power supply wiring and a contact formation area that can be connected to the ground wiring by a contact that overlaps the ground wiring. When using logic elements, connect the connection wiring and power supply wiring via contacts. When not using logic elements, connect the connection wiring and ground wiring to the contacts. The connection is also characteristic.

  According to the first aspect of the present invention, in the logic changing circuit having the logic element used for changing the logic configuration of the logic circuit, the logic element is provided with the connection wiring that can connect the power supply wiring or the ground wiring. As a result, the logic element and the power supply wiring can be disconnected, and leakage current can be prevented from being generated, thereby reducing power consumption.

  According to the second aspect of the present invention, the connection wiring can be connected to the power supply wiring by being contacted with the power supply wiring by being vertically connected to the power supply wiring, and can be connected to the ground wiring by being contacted by being vertically overlapped with the ground wiring. By changing the contact formation position of the mask pattern used for forming the contact, the connection state between the logic element and the power supply wiring can be switched. It is possible to reduce the cost by reducing the number of mask patterns that need to be changed along with the change.

  According to the third aspect of the present invention, when the logic element is used, the connection wiring and the power supply wiring are connected via the contact, and when the logic element is not used, the connection wiring and the ground wiring are contacted. When the logic element is not used, it is possible to prevent generation of extra leakage current and parasitic capacitance by connecting the ground wiring to the logic element.

  According to the fourth aspect of the present invention, in the semiconductor device having the logic changing circuit used for changing the logic configuration of the logic circuit, the logic changing circuit is provided with the logic element used for changing the logic configuration. By providing the connection wiring that can connect the power supply wiring or the ground wiring, the logic element and the power supply wiring can be disconnected from each other in the same manner as in the first aspect of the invention. Thus, a semiconductor device with reduced power consumption can be provided.

  According to the fifth aspect of the present invention, the connection wiring can be connected to the power supply wiring by being contacted with the power supply wiring in the vertical direction, and can be connected to the ground wiring by being contacted with the ground wiring in the vertical direction. In the same manner as in the second aspect of the present invention, by changing the formation position of the contact of the mask pattern used for forming the contact, the connection between the logic element and the power supply wiring is achieved. The state can be switched, and mask patterns that need to be changed in accordance with the change in the logical configuration can be reduced, so that the cost of the semiconductor device can be reduced.

  According to the sixth aspect of the present invention, when the logic element is used, the connection wiring and the power supply wiring are connected via the contact, and when the logic element is not used, the connection wiring and the ground wiring are contacted. When the logic element is not used, the ground wiring is connected to the logic element to prevent generation of extra leakage current and parasitic capacitance. Thus, a semiconductor device with reduced power consumption can be provided.

  The logic change circuit of the present invention and the semiconductor device having the logic change circuit are provided with a logic element used for changing the logic configuration of the logic circuit in the logic change circuit. Alternatively, connection wiring that enables connection of ground wiring is provided.

  That is, the logic element uses connection wiring to physically disconnect from the power supply wiring, and the logic element and ground wiring can be connected by this connection wiring as necessary. It is.

  In this manner, since the logic element is physically disconnected from the power supply wiring, generation of a leakage current can be suppressed and power consumption can be reduced.

  In addition, when logic elements are used, connection wiring and power supply wiring are connected via contacts, and when logic elements are not used, connection wiring and ground wiring are connected via contacts. In some cases, by connecting a ground wiring to the logic element when the logic element is not used, it is possible to prevent the occurrence of extra leakage current and parasitic capacitance, thereby further reducing power consumption.

  In addition, the connection wiring is provided with a contact formation area that can be connected to the power supply wiring by a contact that overlaps the power supply wiring and a contact formation area that can be connected to the ground wiring by a contact that overlaps the ground wiring. Accordingly, the connection state between the logic element and the power supply wiring can be easily switched only by changing the contact formation position of the mask pattern used for forming the contact. Therefore, it is possible to reduce the number of mask patterns that need to be changed in accordance with the change in the logical configuration, and to reduce the cost.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. As shown in the schematic diagram of FIG. 1, the semiconductor device of the present invention has a semiconductor circuit formed on a semiconductor substrate 10 using a known semiconductor circuit forming technique. Is provided with a logic circuit region 11 in which a plurality of logic elements are formed and a logic circuit having a required logic configuration is formed by connecting each logic element with a required wiring.

  In the vicinity of the logic circuit area 11, a logic change circuit provided with a preliminary logic element such as a NAND element or a NOR element used when the logic configuration constructed in the logic circuit area 11 is to be changed is provided. A logic change circuit region 12 to be formed is provided. The logic elements formed in the logic change circuit region 12 are formed simultaneously with the formation of the logic elements formed in the logic circuit region 11.

  The logic elements of the logic changing circuit formed in the logic changing circuit area 12, such as NAND elements, are configured as follows.

  As shown in the layout diagram of FIG. 2, the NAND element 20 in the logic change circuit region 12 includes a first p-channel transistor 31 and a second p-channel transistor 32 connected in parallel, and a first n-channel transistor 41 connected in series. The second n-channel transistor 42 is used.

  That is, the drains of the first and second p-channel transistors 31, 32 are connected to the output wiring 50, and this output wiring 50 is connected to the source of the second n-channel transistor 42 in FIG. Are connected to the source of the first n-channel transistor 41, and the drain of the first n-channel transistor 41 is connected to the ground wiring 60 through the ground connection wiring 60a.

  Further, the first element wiring 71 is connected to the gate of the first p-channel transistor 31 and the gate of the first n-channel transistor 41, and the gate of the second p-channel transistor 41 and the gate of the second n-channel transistor 42 are connected to the first n-channel transistor 41. Two-element wiring 72 is connected.

  In particular, in the present embodiment, the sources of the first and second p-channel transistors 31, 32 connected to the power supply wiring 80 are the source electrode 31s of the first p-channel transistor 31 and the source electrode 32s of the second p-channel transistor 32, respectively. The first connection wiring 91 and the second connection wiring 92 provided via a required insulating layer (not shown) above are connected.

  That is, the first connection wiring 91 is provided with a first element connection contact formation region 91a extending vertically so as to overlap the source electrode 31s, and is extended so as to overlap vertically with the power supply wiring 80. A contact formation region 91b for wiring connection is provided.

  A first element contact 31c for connecting the source electrode 31s and the first connection wiring 91 is provided in the first element connection contact formation area 91a, and a power supply wiring is provided in the first power supply wiring connection contact formation area 91b. By providing a first power supply wiring contact 81 c that connects 80 and the first connection wiring 91, the first p-channel transistor 31 and the power supply wiring 80 are connected by the first connection wiring 91.

  In addition, the second connection wiring 92 is provided with a second element connection contact formation region 92a extending so as to overlap with the source electrode 32s, and is extended so as to overlap with the power supply wiring 80 so as to overlap the second power supply. A contact formation region 92b for wiring connection is provided.

  A second element contact 32c for connecting the source electrode 32s and the second connection wiring 92 is provided in the second element connection contact formation area 92a, and a power supply wiring is provided in the second power supply wiring connection contact formation area 92b. By providing a second power supply wiring contact 82 c that connects 80 and the second connection wiring 92, the second p-channel transistor 32 and the power supply wiring 80 are connected by the second connection wiring 92.

  In FIG. 2, reference numeral 81 denotes a power supply wiring 80 and a first power supply wiring connection contact formation region 91 b of the first connection wiring 91 to facilitate connection by the first power supply wiring contact 81 c. The drawn-out first power supply lead portion 82 is provided to facilitate connection of the power supply wiring 80 and the second power supply wiring connection contact forming region 92b of the second connection wiring 92 by the second power supply wiring contact 82c. This is a second power lead portion drawn from the power wiring 80.

  Here, when the first power supply wiring contact 81c and the second power supply wiring contact 82c are not formed, the first connection wiring 91 and the power supply wiring 80, and the second connection wiring 92 and the power supply wiring 80 are not connected. Thus, the first p-channel transistor 31 and the second p-channel transistor 32 can be disconnected from the power supply wiring 80.

  Thus, by making the first p-channel transistor 31 and the second p-channel transistor 32 disconnected from the power supply wiring 80, it is possible to suppress the occurrence of a leakage current and to suppress power consumption.

  In other words, in the logic element that is not used in the logic element of the logic change circuit, the power supply wiring contacts such as the first power supply wiring contact 81c and the second power supply wiring contact 82c used for connection to the power supply wiring 80 are not formed. By disconnecting from the power supply wiring 80, the occurrence of leakage current is suppressed, and the increase in power consumption is suppressed.

  Further, the first connection wiring 91 is provided with a first ground wiring connection contact formation region 91c extending so as to overlap the ground wiring 60, and the second connection wiring 92 is provided above and below the ground wiring 60. A second ground wiring connection contact formation region 92c is provided so as to be overlapped.

  In FIG. 1, reference numeral 61 denotes a first ground lead drawn from the ground wiring 60 to facilitate connection by forming a contact between the ground wiring 60 and the first ground wiring connection contact forming region 91 c of the first connection wiring 91. 62 is a second ground lead drawn from the ground wiring 60 for facilitating connection by forming a contact between the ground wiring 60 and the second ground wiring connection contact forming region 92c of the second connection wiring 92. Part.

  If the NAND element 20 is not connected to the power supply line 80 by not providing the first power supply line contact 81c and the second power supply line contact 82c, as shown in FIG. A first ground wiring contact 61c for connecting the ground wiring 60 and the first connection wiring 91 is provided in the connection contact formation region 91c, and the first p-channel transistor 31 and the ground wiring 60 are connected by the first connection wiring 91. At the same time, a second ground wiring contact 62c for connecting the ground wiring 60 and the first connection wiring 91 is provided in the second ground wiring connection contact forming region 92c, and the second p-channel type transistor 32 is provided by the second connection wiring 92. And the ground wiring 60 are connected.

  As described above, a logic element that is not used as a non-connection with the power supply wiring 80 is connected to the ground wiring 60 via the first connection wiring 91 and the second connection wiring 92, thereby causing extra leakage to the unused logic elements. Generation of current and parasitic capacitance can be suppressed.

  In the NAND element 20 ′ of FIG. 3, the first power supply lead 81 and the second power supply lead 82 are not provided on the power supply wiring 80, and the first ground lead 61 and the second ground lead 62 are not provided on the ground wiring 60. Is.

  As described above, the connection of the NAND elements 20, 20 'to the power supply wiring 80 or the ground wiring 60 via the first connection wiring 91 and the second connection wiring 92 is performed by connecting the first power supply wiring contact 81c and the second power supply wiring. Contact 82c, or mask pattern contacts 81c, 82c, 61c, 62c used to form the contacts 81c, 82c, 61c, 62c by the first ground wiring contact 61c and the second ground wiring contact 62c. By changing the formation position, the connection state between the NAND elements 20, 20 ′, which are logic elements, and the power supply wiring 80 or the ground wiring 60 can be switched.

  Therefore, it is possible to reduce the number of mask patterns that need to be changed as the logical configuration changes, and to reduce the cost.

1 is a schematic plan view of a semiconductor device according to the present invention. FIG. 4 is a layout diagram of a logic change circuit according to the present invention. FIG. 6 is a layout diagram of a logic change circuit according to another embodiment. It is a layout diagram of a conventional logic change circuit.

Explanation of symbols

20 NAND element
31 First p-channel transistor
31c Contact for first element
32 2nd p-channel transistor
32c Contact for second element
41 1st n-channel transistor
42 2nd n-channel transistor
50 Output wiring
60 Ground wiring
60a Ground connection wiring
61c First ground wiring contact
62c Contact for second ground wiring
71 First element wiring
72 Second element wiring
80 Power supply wiring
81c Contact for first power supply wiring
82c Contact for second power supply wiring
91 First connection wiring
91a Contact formation region for first element connection
91b Contact formation area for connecting the first power supply wiring
91c Contact formation area for first ground wiring connection
92 Second connection wiring
92a Contact formation area for second element connection
92b Second power line connection contact formation area
92c Contact formation area for second ground wiring connection

Claims (6)

In a logic changing circuit having a logic element used for changing the logic configuration of the logic circuit,
A logic change circuit, wherein the logic element is provided with a connection wiring that can connect a power supply wiring or a ground wiring.   The connection wiring includes a contact formation region that can be connected to the power supply wiring by a contact that overlaps the power supply wiring and a contact formation region that can be connected to the ground wiring by a contact that overlaps the ground wiring. The logic changing circuit according to claim 1, wherein: When using the logic element, connect the connection wiring and the power supply wiring through a contact,
3. The logic change circuit according to claim 1, wherein when the logic element is not used, the connection wiring and the ground wiring are connected via a contact. 4. In a semiconductor device having a logic change circuit used for changing the logic configuration of a logic circuit,
The logic changing circuit is provided with a logic element used for changing the logic configuration,
A semiconductor device characterized in that the logic element is provided with a connection wiring capable of connecting a power supply wiring or a ground wiring.   The connection wiring includes a contact formation region that can be connected to the power supply wiring by a contact that overlaps the power supply wiring and a contact formation region that can be connected to the ground wiring by a contact that overlaps the ground wiring. The semiconductor device according to claim 4, wherein: When using the logic element, connect the connection wiring and the power supply wiring through a contact,
6. The semiconductor device according to claim 4, wherein when the logic element is not used, the connection wiring and the ground wiring are connected through a contact.

Images