JP2007073885A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit constituted of a plurality of basic cells and capable of supplying a plurality of sorts of power without reducing the degree of integration. <P>SOLUTION: In each of basic cells 1 formed on an SOI (Silicon-ON-Insulator) substrate, an n-type diffusion area 12 is formed in a part of an n well area 8 in which a PMOS (P-channel Metal-Oxide Semiconductor) transistor is formed and a VDD power supply wire 11 is formed on the n-type diffusion area 12 so as to be electrically connected. A p-type diffusion area 17 is formed in a part of a p well area 9 in which an NMOS (N-channel Metal-Oxide Semiconductor) transistor is formed and a GND power supply wire 16 is formed on the p-type diffusion area 17 so as to be electrically connected. The VDD power supply wire 11 and the GND power supply wire 16 are formed in the basic cell 1 at a prescribed distance without being brought into contact with a cell boundary 10 of the basis cell 1. The n-type diffusion area 12 and the p-type diffusion area 17 correspond to body contact areas for setting the back gate potential levels of the PMOS transistor and the NMOS transistor. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit including a plurality of basic cells formed in an SOI structure.

  A semiconductor integrated circuit can be realized by combining a plurality of basic cells (standard cells). In a semiconductor integrated circuit in which low power consumption is important, in order to realize low power consumption, a power supply separation function for cutting off power supply to a circuit portion that does not operate at the chip design stage is provided.

  Since the conventional basic cell uses a structure in which the power line is shared between adjacent cells at the cell boundary, in order to realize the above power separation function, it is classified according to the type of power supplied in units of basic cells. A plurality of cell placement areas are divided and a cell formation area such as a transistor in one cell placement area is electrically separated from a well area in another cell placement area. There was a need to do. Further, as a basic cell for a plurality of power supplies, for example, Patent Document 1 discloses a structure in which the well region is arranged away from the entire peripheral boundary of the cells and a power supply line is in contact between adjacent cells.

Japanese Patent Laid-Open No. 2004-22877

  However, dividing the plurality of cell arrangement areas separately provides an extra space for forming the separation area between the cell arrangement areas that supply different power sources in order to physically separate the plurality of cell arrangement areas. Since this is necessary, there is a problem that the circuit area increases and the degree of integration is impaired.

  Further, in order to reduce power consumption, when the power supply to a predetermined cell arrangement area is cut off among a plurality of cell arrangement areas, the stored data in the predetermined cell arrangement area is data necessary after the power supply is resumed. In this case, it is necessary to provide a data saving path for saving stored data in another cell arrangement area where the power supply is not cut off before the power supply is cut off. However, as described above, there is always a separation between the plurality of cell arrangement areas. Since the area is formed, the data saving path is inevitably long, which causes a delay in data saving time and reduces the wiring efficiency of the entire circuit.

  The present invention has been made to solve the above problems, and an object of the present invention is to obtain a semiconductor integrated circuit which is composed of a plurality of basic cells and which can supply a plurality of types of power without impairing the degree of integration.

  A semiconductor integrated circuit according to a first aspect of the present invention is a circuit formed on an SOI substrate including a semiconductor substrate, a buried insulating film, and an SOI layer, and the semiconductor integrated circuit includes a plurality of basic cells, Each of the plurality of basic cells is electrically connected to an element formation region provided in the SOI substrate, at least one semiconductor element formed in the element formation region, and a predetermined region of the at least one semiconductor element. A potential setting region and an in-cell power supply wiring that is electrically connected to the potential setting region, and the in-cell power supply wiring is formed without protruding into the basic cell.

  In the plurality of basic cells of the semiconductor integrated circuit according to the first aspect of the present invention, since the in-cell power supply wiring provided to be electrically connected on the potential setting region is formed without protruding into the basic cell, Even if the basic cells are arranged adjacent to each other without a gap, the in-cell power supply wirings do not have an electrical relationship between the adjacent basic cells.

  Therefore, when arranging a plurality of basic cells that supply different power sources using the power wiring in the cell, it is possible to arrange them efficiently in an area without providing a gap for power source separation, so it is necessary to supply a plurality of types of power sources. Even when a plurality of basic cells are mixed and formed, a highly integrated semiconductor integrated circuit can be obtained.

<Embodiment 1>
(Basic cell structure)
1 is a plan view showing a layout structure of a basic cell used in a semiconductor integrated circuit according to Embodiment 1 of the present invention. As shown in the figure, the basic cell 1 of the first embodiment is composed of an N well region 8 and a P well region 9 which are element formation regions provided on an SOI substrate. A P-type transistor diffusion region 13 is selectively formed in the N-well region 8, and a PMOS is formed on the N-transistor body region (not shown) between the P-type transistor diffusion regions 13 via a gate insulating film (not shown). A gate electrode 14 is formed.

  On the other hand, an N-type transistor diffusion region 18 is selectively formed in the P-well region 9, and a gate insulating film (not shown) is interposed on the P-transistor body region (not shown) between the N-type transistor diffusion regions 18. Thus, the NMOS gate electrode 19 is formed.

  The P-type transistor diffusion region 13 and the PMOS gate electrode 14 constitute a PMOS transistor (first MOS transistor) as a semiconductor element, and the N-type transistor diffusion region 18 and the NMOS gate electrode 19 constitute an NMOS transistor (semiconductor element). A second MOS transistor) is formed.

  An N-type diffusion region 12 (first diffusion region), which is a (body) potential setting region, is selectively formed in a part of the N-well region 8 (upper part in FIG. 1). Then, a VDD power supply wiring 11 (first power supply wiring) which is an in-cell power supply wiring is formed. On the other hand, a P-type diffusion region 17 (second diffusion region), which is a (body) potential setting region, is selectively formed in a part of the P-well region 9 (lower part in FIG. 1). A GND power supply wiring 16 (second power supply wiring), which is an in-cell power supply wiring, is formed on the wiring board 17.

  The VDD power supply wiring 11 and the GND power supply wiring 16 are provided in the cell at a predetermined distance without contacting the cell boundary 10 of the basic cell 1. Therefore, even if the basic cells 1 are arranged adjacent to each other without providing a gap, the VDD power supply wiring 11 or the GND power supply wiring 16 does not exhibit an electrical connection relationship with each other.

  The N type diffusion region 12 corresponds to a body contact region provided for setting the back gate potential of the PMOS transistor formed in the N well region 8, and the P type diffusion region 17 is an NMOS formed in the P well region 9. This corresponds to a body contact region provided for setting the back gate potential of the transistor.

  FIG. 2 is an explanatory diagram schematically showing the basic cell 1 shown in FIG. As shown in the figure, in the N well region 8, a partial isolation region (PTI) 104 (first partial isolation region) is formed on the extension line of the PMOS gate electrode 14 between the PMOS gate electrode 14 and the N-type diffusion region 12. Is formed. Similarly, in the P well region 9, a partial isolation region 114 (second partial isolation region) is formed on the extension line of the NMOS gate electrode 19 between the NMOS gate electrode 19 and the P-type diffusion region 17.

  FIG. 3 is a cross-sectional view showing the AA cross section of FIG. As shown in the figure, the basic cell 1 is formed on an SOI layer 103 of an SOI substrate including a semiconductor substrate 101, a buried insulating film 102 and an SOI layer 103.

  The N type diffusion region 12 is electrically connected to the N transistor body region 108 (predetermined region of the semiconductor element) under the PMOS gate electrode 14 via the N lower layer diffusion region 107 remaining in the SOI layer 103 under the partial isolation region 104. Connected. Therefore, by applying a predetermined body potential to the N-type diffusion region 12, the body potential of the N transistor body region 108 of the PMOS transistor can be set.

  Similarly, the P-type diffusion region 17 is connected to the P transistor body region 118 (predetermined region of the semiconductor element) under the NMOS gate electrode 19 via the P lower layer diffusion region 117 remaining in the SOI layer 103 under the partial isolation region 114. And electrically connected. Therefore, the body potential of the P transistor body region 118 of the NMOS transistor can be set by applying a predetermined body potential to the P type diffusion region 17.

  Note that the N well region 8 and the P well region 9 are completely separated by a complete isolation region (STI) 110 formed through the SOI layer 103, and SOI layers are formed at both ends of the AA cross section of FIG. By providing complete isolation regions 106 (N-type diffusion region 12 side) and 116 (P-type diffusion region 17 side) penetrating through 103, complete electrical isolation from other cells adjacent in the AA cross-sectional direction Is realized.

  4 is a cross-sectional view showing a BB cross section of FIG. As shown in the figure, the NMOS gate electrode 19 (not shown in the lower gate insulating film) is formed of N-type diffusion regions 18 and 18 with the surface of the P transistor body region 118 under the NMOS gate electrode 19 as a channel region. An NMOS transistor having a source / drain region is formed.

  Further, complete separation regions 111 and 112) penetrating the SOI layer 103 are provided at both ends of the BB cross section in FIG. 2, so that complete electrical connection with other cells adjacent in the BB cross section direction is achieved. Separation is realized. That is, as shown in FIGS. 3 and 4, the basic cell 1 can be completely electrically separated from adjacent cells.

(Semiconductor integrated circuit configuration example)
FIG. 5 is an explanatory view schematically showing a semiconductor integrated circuit constituted by using the basic cell 1 according to the first embodiment shown in FIG. The semiconductor integrated circuit shown in FIG. 5 is configured to receive two types of power supply.

  The semiconductor integrated circuit shown in FIG. 5 includes a plurality of basic cells 1 and is arranged so that the VDD power supply wiring 11 and the GND power supply wiring 16 are alternately switched in the column direction (vertical direction in the figure). That is, in FIG. 5, the first and third columns are arranged such that the VDD power supply wiring 11 is positioned above the GND power supply wiring 16 in the figure, and the central second column is the GND power supply wiring 16. Is arranged above the VDD power supply wiring 11 in the figure.

  Then, a first basic cell group (basic cell 1 other than the power supply isolation region 73) that receives the first GND potential and the first VDD potential from the upper layer GND wiring 81 and the upper layer VDD wiring 91, and an upper layer GND wiring 82 and the upper layer VDD wiring 92, respectively. The cell is classified into a second basic cell group (basic cell 1 in the power supply isolation region 73) that receives the second GND potential and the second VDD potential. The upper layer GND wirings 81 and 82 and the upper layer VDD wirings 91 and 92 are formed in an upper layer than the VDD power source wiring 11 and the GND power source wiring 16 formed in the basic cell 1.

  In the basic cell 1 of the first basic cell group described above, the GND power supply wiring 16 and the VDD power supply wiring 11 are electrically connected to the upper layer GND wiring 81 and the upper layer VDD wiring 91 through the via holes 71, respectively. The VDD power supply wiring 11 and the GND power supply wiring 16 between the basic cells 1 and 1 adjacent in the row direction (left and right in the figure) are electrically connected via the intercell connection auxiliary power supply wiring 72, respectively. The first GND potential and the first VDD potential are set.

  On the other hand, in the basic cell 1 of the second basic cell group (within the power supply isolation region 73), the GND power supply wiring 16 and the VDD power supply wiring 11 are electrically connected to the upper layer GND wiring 82 and the upper layer VDD wiring 92 through the via holes 71, respectively. In addition, the VDD power supply wiring 11 and the GND power supply wiring 16 between the basic cells 1 and 1 adjacent to each other on the left and right in the drawing are electrically connected via the inter-cell connection auxiliary power supply wiring 72, respectively. Thus, the second GND potential and the second VDD potential are set. Then, the inter-cell connection auxiliary power supply wiring 72 is not formed between the cells 1x and 1y adjacent in the row direction at the boundary between the power supply isolation region 73 and the outside of the power supply isolation region 73. Maintain separation.

  As described above, the semiconductor integrated circuit according to the first embodiment has the power source separation at the boundary between the power source isolation regions 73, that is, the boundary between the basic cell 1 of the first basic cell group and the basic cell 1 of the second basic cell group. Therefore, the basic cells of the first and second basic cell groups can be arranged adjacent to each other without a gap.

  Therefore, the first effect is obtained that a semiconductor integrated circuit with an improved degree of integration can be obtained as much as the separation region for power source separation can be eliminated. Hereinafter, this effect will be described in detail.

  FIG. 6 is an explanatory diagram schematically showing a chip area when there are a plurality of general power supply areas. As shown in the figure, when it is necessary to supply different power supplies and there are power supply areas SP1 to SP9 each consisting of at least one basic cell, these power supply areas SP1 to SP9 are respectively connected to other power supply areas. Therefore, it is necessary to provide a power separation gap GV between the adjacent power supply regions among the power supply regions SP1 to SP9 so as to be electrically separated from the power supply regions SP1 to SP9.

  FIG. 7 is an explanatory diagram schematically showing a chip region in the case where a plurality of power supply regions exist when the basic cell 1 of the first embodiment is used. As shown in FIG. 5, even if there are power supply regions SP1 to SP9 that need to supply different power, there is no need to provide a power separation gap as shown in FIG. Regions SP1 to SP9 can be arranged. As a result, compared to the case shown in FIG. 6, the degree of integration for the reduced region CR shown in FIG. 7 can be improved.

  As described above, the semiconductor integrated circuit according to the first embodiment also forms a semiconductor integrated circuit in which the first and second cell groups that require different body potentials of the MOS transistors are set. Since the basic cells 1 of the first and second cell groups can be arranged adjacent to each other without a gap, the first embodiment in which the degree of integration can be improved as much as the separation region for power source separation can be eliminated. The effect of.

  Further, when a plurality of power supply areas are provided, power supply to a predetermined power supply area may be temporarily interrupted in order to reduce power consumption. In this case, if the data stored in the cells in the predetermined power supply area is data necessary after restarting the power supply to the predetermined power supply area, the power supply is not interrupted before the power supply is interrupted. It is necessary to provide a data saving path for saving stored data.

  FIG. 8 is an explanatory diagram schematically showing a conventional evacuation signal path. As shown in the figure, it is assumed that there are a first power supply region A1 and a second power supply region A2, and the second power supply region A2 is a region where power supply is temporarily interrupted. In this case, as shown in FIG. 8, it is necessary to save the data stored in the cells C21 to C24 in the second power supply area A2 to the save register RG in the first power supply area A1.

  However, since it is necessary to provide a power supply separation gap between the first power supply region A1 and the second power supply region A2 for electrical separation, the save signal path RT1 connecting the cells C21 to C24 and the save register RG. Will inevitably become longer.

  FIG. 9 is an explanatory diagram schematically showing a save signal path when the basic cell 1 of the first embodiment is used. As shown in the figure, save registers RG1 to RG4 for supplying a first power supply in a plurality of power supply areas A3 in which a plurality of types of power supply areas are mixed, and a second power supply different from the first power supply is supplied. The cells C11 to C14 can be formed together without providing a power supply separation gap.

  Therefore, in order to associate the save registers RG1 to RG4 formed relatively close to the cells C11 to C14 and save the data stored in the cells C11 to C14 in the save registers RG1 to RG4, the save signal path RT2 is set. Since it can be provided, the length of the evacuation signal path RT2 can be minimized.

  FIG. 10 is an explanatory diagram showing the configuration of FIG. 9 more specifically. The first power supply line VL1 receives the first power supply VDD1 through the switch SW1, and the second power supply line VL2 receives the supply of the second power supply VDD2 through the switch SW2.

  The cells C11 to C14 are electrically connected to the first power supply line VL1 wired nearby, and the save registers RG1 to RG4 are electrically connected to the second power supply line VL2 wired nearby. . Then, the save registers RG1 to RG4 provided relatively close to the cells C11 to C14 are selected as the data save registers for the cells C11 to C14.

  As a result, the save signal paths RT21 to RT24 from the cells C11 to C14 to the save registers RG1 to RG4 can be suppressed to the minimum necessary lengths, respectively.

  As described above, since the semiconductor integrated circuit according to the first embodiment can minimize the data saving path, the data saving time is not delayed and the wiring efficiency of the entire circuit is not lowered. Therefore, even if the power supply to a part of the power supply area is temporarily interrupted, there will be no delay in operation time, deterioration in wiring efficiency, etc., so that low power consumption can be achieved without any problem. There is a second effect of being able to.

<Embodiment 2>
(Basic cell structure)
FIG. 11 is a plan view showing a layout structure of a basic cell used in the semiconductor integrated circuit according to the second embodiment of the present invention. As shown in the figure, the basic cell 2 is composed of an N well region 8 and a P well region 9. A P-type transistor diffusion region 23 is selectively formed in the N-well region 8, and a PMOS is formed on the N-transistor body region (not shown) between the P-type transistor diffusion regions 23 via a gate insulating film (not shown). A gate electrode 24 is formed.

  On the other hand, an N-type transistor diffusion region 28 is selectively formed in the P-well region 9, and a gate insulating film (not shown) is interposed on the P-transistor body region (not shown) between the N-type transistor diffusion regions 28. Thus, the NMOS gate electrode 29 is formed.

  The P-type transistor diffusion region 23 and the PMOS gate electrode 24 constitute a PMOS transistor, and the N-type transistor diffusion region 28 and the NMOS gate electrode 29 constitute an NMOS transistor.

  An N-type diffusion region 22 is selectively formed in a part of the N-well region 8 (upper part of FIG. 11), and is electrically connected to the N-type diffusion region 22 to supply power for VDD as an in-cell power supply wiring. A wiring 21 (first power supply wiring) is formed. On the other hand, a P-type diffusion region 27 is selectively formed in a part of the P-well region 9 (lower part in FIG. 11), and is electrically connected to the P-type diffusion region 27 to connect to the GND power supply wiring 26 (first 2 power supply wirings) are formed.

  The VDD power wiring 21 is electrically separated from adjacent cells by being provided in the cell at a predetermined distance without contacting the cell boundary 20 of the basic cell 2. On the other hand, the GND power supply wiring 26 is formed on the cell boundary 20 of the basic cell 2 (on the lower boundary line in FIG. 11) so as to be shared between adjacent cells.

  The N type diffusion region 22 corresponds to a body contact region provided for setting the back gate potential of the PMOS transistor formed in the N well region 8, and the P type diffusion region 27 is an NMOS formed in the P well region 9. This corresponds to a body contact region provided for setting the back gate potential of the transistor.

(Semiconductor integrated circuit configuration example)
FIG. 12 is an explanatory diagram schematically showing a semiconductor integrated circuit configured using the basic cell 2 of the second embodiment shown in FIG. The semiconductor integrated circuit shown in FIG. 12 is configured to receive two types of power supply.

  The semiconductor integrated circuit shown in FIG. 12 includes a plurality of basic cells 2 and is arranged so that the VDD power supply wiring 21 and the GND power supply wiring 26 are alternately switched in the column direction (vertical direction in the figure). That is, in FIG. 12, the first and third columns are arranged such that the VDD power supply wiring 21 is positioned above the GND power supply wiring 26 in the figure, and the central second column is the GND power supply wiring 26. Is arranged above the VDD power supply wiring 21 in the figure. The GND power line 26 is shared between the basic cells 2 and 2 in the first and second columns.

  The semiconductor integrated circuit according to the second embodiment having such a configuration has a first basic cell group that receives the first GND potential and the first VDD potential from the upper layer GND wiring 81 and the upper layer VDD wiring 91 (basic cells 2 other than the power source isolation region 73). ) And the second basic cell group (basic cell 2 in the power supply isolation region 73) that receives the second VDD potential from the upper layer VDD wiring 92. The upper layer GND wirings 81 and 82 and the upper layer VDD wirings 91 and 92 are formed in an upper layer than the VDD power source wiring 21 and the GND power source wiring 26 formed in the basic cell 2.

  In the basic cell 2 of the first basic cell group described above, the GND power supply wiring 26 and the VDD power supply wiring 21 are electrically connected to the upper layer GND wiring 81 and the upper layer VDD wiring 91 through the via holes 71, respectively. By electrically connecting the VDD power supply wiring 21 and the GND power supply wiring 26 between the basic cells 2 and 2 adjacent in the row direction (left-right direction in the figure) via the inter-cell connection auxiliary power supply wiring 72, respectively. The first GND potential and the first VDD potential are set.

  On the other hand, in the basic cell 2 of the second basic cell group (in the power supply isolation region 73), the VDD power supply wiring 21 is electrically connected to the upper layer VDD wiring 92 through the via hole 71, and adjacent to the left and right in the figure. The VDD power supply line 21 between the basic cells 2 and 2 to be connected is electrically connected via the inter-cell connection auxiliary power supply line 72, whereby the second VDD potential is set.

  On the other hand, the basic cell 2 of the second basic cell group shares the GND power supply wiring 26 with the basic cell 2 of the first basic cell group adjacent to the upper side, so that the first GND similarly to the first basic cell group. Set to potential. Normally, the GND potential is often common even when different power supplies are received, so that there is almost no operational problem caused by setting the GND potential in common between the first and second basic cell groups.

  Then, the inter-cell connection auxiliary power supply wiring 72 is not formed between the cells 2x and 2y adjacent in the row direction at the boundary between the power supply isolation region 73 and the outside of the power supply isolation region 73, whereby the first and second VDD Maintains electrical separation with respect to potential.

  As described above, the semiconductor integrated circuit according to the second embodiment has the power source separation at the boundary between the power source isolation regions 73, that is, the boundary between the basic cell 2 in the first basic cell group and the basic cell 2 in the second basic cell group. Therefore, the basic cells of the first and second basic cell groups can be arranged adjacent to each other without a gap.

  Therefore, the first effect that the semiconductor integrated circuit with an improved degree of integration can be obtained in the same manner as in the first embodiment because the power supply isolation region can be eliminated.

  Also in the second embodiment, it is possible to form a region for supplying a plurality of types of power without providing a power source separation gap. Therefore, the semiconductor integrated circuit composed of the basic cells 2 of the second embodiment has a delay in operation time even if the power supply to a part of the power supply region is temporarily interrupted, as in the first embodiment. Since the deterioration of the wiring efficiency is not caused, the second effect that the low power consumption can be achieved without hindrance is achieved.

  In addition, since the basic cell 2 of the second embodiment has a configuration in which the GND power supply wiring 26 is shared between the adjacent basic cells 2 and 2, the cell area is larger than that of the basic cell 1 of the first embodiment. There is an inherent effect that can be reduced.

  In the second embodiment, the configuration in which the GND power supply wiring is shared between the cells is shown. However, the configuration in which the VDD power supply wiring is shared between the cells can be used instead. The effect of.

<Embodiment 3>
(Basic cell structure)
FIG. 13 is a plan view showing a layout structure of a basic cell used in a semiconductor integrated circuit according to the third embodiment of the present invention. As shown in the figure, the basic cell 3 is composed of an N well region 8 and a P well region 9. A P-type transistor diffusion region 33 is selectively formed in the N-well region 8, and a PMOS is formed on the N-transistor body region (not shown) between the P-type transistor diffusion regions 33 via a gate insulating film (not shown). A gate electrode 34 is formed.

  On the other hand, an N-type transistor diffusion region 38 is selectively formed in the P-well region 9, and a gate insulating film (not shown) is interposed on the P-transistor body region (not shown) between the N-type transistor diffusion regions 38. Thus, the NMOS gate electrode 39 is formed.

  The P-type transistor diffusion region 33 and the PMOS gate electrode 34 constitute a PMOS transistor, and the N-type transistor diffusion region 38 and the NMOS gate electrode 39 constitute an NMOS transistor.

  An N-type diffusion region 32a (first diffusion region) is selectively formed in a part of the N-well region 8 (upper part of FIG. 13), and is electrically connected to the N-type diffusion region 32a for VDD. A power supply wiring 31a (first power supply wiring) is formed. Further, an N-type diffusion region 32b (third diffusion region) is selectively formed in another part (lower part of FIG. 13) in the N-well region 8, and is electrically connected to the N-type diffusion region 32b. Thus, the VDD power supply wiring 31b (third power supply wiring) is formed.

  On the other hand, a P-type diffusion region 37a (second diffusion region) is selectively formed in a part (lower part of FIG. 13) in the P-well region 9, and is electrically connected to the P-type diffusion region 37a. A GND power supply wiring 36a (second power supply wiring) is formed. Further, a P-type diffusion region 37b (fourth diffusion region) is selectively formed in another part (upper part of FIG. 13) in the P-well region 9, and is electrically connected to the P-type diffusion region 37b. Thus, the GND power supply wiring 36b (fourth power supply wiring) is formed.

  The VDD power supply wirings 31a and 31b and the GND power supply wirings 36a and 36b are electrically separated from adjacent cells by being provided in the cell at a predetermined distance without contacting the cell boundary 30 of the basic cell 3, respectively. Is done.

  The N type diffusion regions 32a and 32b correspond to body contact regions provided for setting the back gate potential of the PMOS transistor formed in the N well region 8, respectively. The P type diffusion regions 37a and 37b are in the P well region 9. This corresponds to the body contact region provided for setting the back gate potential of the NMOS transistor formed in step (b).

  Further, in the N well region 8, a partial isolation region 35a (first partial isolation region) is formed on the extension line of the PMOS gate electrode 34 between the PMOS gate electrode 34 and the N-type diffusion region 32a. 34, a partial isolation region 35b (third partial isolation region) is formed on the extended line of the PMOS gate electrode 34 between the N-type diffusion region 32b. Similarly, in the P-well region 9, a partial isolation region 35a (second partial isolation region) is formed on the extended line of the NMOS gate electrode 39 between the NMOS gate electrode 39 and the P-type diffusion region 37a. A partial isolation region 35b (fourth partial isolation region) is formed on the extended line of the NMOS gate electrode 39 between the gate electrode 39 and the P-type diffusion region 37b.

  FIG. 14 is a cross-sectional view corresponding to the CC cross section of basic cell 1 of the first embodiment shown in FIG. As shown in the figure, the VDD power supply wiring 11 is formed on the N-type diffusion region 12a via the contact hole 109, so that the contact hole 109, the N-type diffusion region 12a, and the part are connected from the VDD power supply wiring 11. The body potential of the N transistor body region 108 of the PMOS transistor can be set via the N lower layer diffusion region 107 under the isolation region 104.

  Similarly, the GND power supply wiring 16 is formed on the P-type diffusion region 17 via the contact hole 119, so that the contact hole 119, the P-type diffusion region 17, and the partial isolation region 114 are formed from the GND power supply wiring 16. The body potential of the P transistor body region 118 of the NMOS transistor can be set through the P lower layer diffusion region 117 of the NMOS transistor. The other structure is the same as the AA cross-sectional structure shown in FIG. 2 shown in FIG.

  FIG. 15 is a cross-sectional view showing the DD cross-sectional structure of FIG. As shown in the figure, the basic cell 3 according to the third embodiment is formed on the SOI layer 123 of the SOI substrate including the semiconductor substrate 121, the buried insulating film 122 and the SOI layer 123.

  In the N well region 8, the N type diffusion region 32a is electrically connected to the N transistor body region 128 under the PMOS gate electrode 34 via the N lower layer diffusion region 127a remaining in the SOI layer 123 under the partial isolation region 35a. The Further, the N type diffusion region 32b is electrically connected to the N transistor body region 128 under the PMOS gate electrode 34 via the N lower layer diffusion region 127b remaining in the SOI layer 123 under the partial isolation region 35b.

  The VDD power supply wiring 31a is electrically connected to the N-type diffusion region 32a via a contact hole 129a, and the VDD power supply wiring 31b is electrically connected to the N-type diffusion region 32b via a contact hole 129b. Connected to. Therefore, the body potential of the N transistor body region 128 can be set by applying a predetermined body potential to the N-type diffusion regions 32a and 32b from the VDD power supply wires 31a and 31b.

  Similarly, in the P well region 9, the P type diffusion region 37a is electrically connected to the P transistor body region 138 under the NMOS gate electrode 39 via the N lower layer diffusion region 137a remaining in the SOI layer 123 under the partial isolation region 35a. Connected. Further, the P-type diffusion region 37b is electrically connected to the P-transistor body region 138 under the NMOS gate electrode 39 via the N lower layer diffusion region 137b remaining in the SOI layer 123 under the partial isolation region 35b.

  The GND power supply wiring 36a is electrically connected to the P-type diffusion region 37a through the contact hole 139a, and the GND power supply wiring 36b is electrically connected to the P-type diffusion region 37b through the contact hole 139b. Connected to. Therefore, the body potential of the P transistor body region 138 can be set by applying a predetermined body potential to the P-type diffusion regions 37a and 37b from the GND power supply wirings 36a and 36b.

  Note that the N well region 8 and the P well region 9 are completely separated by a complete isolation region 130 formed so as to penetrate the SOI layer 123, and penetrate the SOI layer 123 at both ends of the DD cross section of FIG. By providing the complete isolation region 126 (N-type diffusion region 32a side) and 136 (P-type diffusion region 37a side), complete electrical isolation from other cells adjacent in the DD cross-sectional direction is realized. ing.

(First Configuration Example of Semiconductor Integrated Circuit)
FIG. 16 is an explanatory diagram schematically showing a first configuration example of a semiconductor integrated circuit configured using the basic cell 3 of the third embodiment shown in FIG. The semiconductor integrated circuit shown in FIG. 16 is configured to receive two types of power supply.

  The first configuration example of the semiconductor integrated circuit shown in FIG. 16 includes a plurality of basic cells 3, and includes a VDD power supply wiring 31a (and 31b) and a GND power supply wiring 36a (and 36b) in the column direction (vertical direction in the figure). ) Are alternately arranged. That is, in FIG. 16, the first and third columns are arranged so that the VDD power supply wiring 31a, the VDD power supply wiring 31b, the GND power supply wiring 36b, and the GND power supply wiring 36a are positioned from the upper side in the figure. The second column in the center is arranged in the completely reverse order (the order of 36a, 36b, 31b, 31a) as described above.

  Then, a first basic cell group (basic cell 3 other than the power supply isolation region 73) that receives the first GND potential and the first VDD potential from the upper layer GND wiring 81 and the upper layer VDD wiring 91, and an upper layer GND wiring 82 and the upper layer VDD wiring 92, respectively. The cell is classified into a second basic cell group (basic cell 3 in the power supply isolation region 73) that receives the second GND potential and the second VDD potential. The upper layer GND wirings 81 and 82 and the upper layer VDD wirings 91 and 92 are formed in an upper layer than the VDD power source wirings 31a and 31b and the GND power source wirings 36a and 36b formed in the basic cell 3.

  In the basic cell 3 of the first basic cell group, the GND power supply wiring 36a and the VDD power supply wiring 31a are electrically connected to the upper layer GND wiring 81 and the upper layer VDD wiring 91 through the via holes 71, respectively, and in the row direction. The VDD power supply wiring 31a and the GND power supply wiring 36a between the basic cells 3 and 3 adjacent to each other in the left-right direction in the figure are electrically connected via the inter-cell connection auxiliary power supply wiring 72, respectively. The 1GND potential and the first VDD potential are set.

  On the other hand, in the basic cell 3 of the second basic cell group (in the power supply isolation region 73), the GND power supply wiring 36a and the VDD power supply wiring 31a are electrically connected to the upper layer GND wiring 82 and the upper layer VDD wiring 92 through the via holes 71, respectively. And the VDD power supply wirings 31a and 36a between the basic cells 3 and 3 adjacent to each other on the left and right in the drawing are electrically connected via the intercell connection auxiliary power supply wiring 72, whereby the second VDD The potential and the second GND potential are set.

  Then, the inter-cell connection auxiliary power supply wiring 72 is not formed between the cells 3x and 3y adjacent in the row direction at the boundary between the power supply isolation region 73 and the outside of the power supply isolation region 73, whereby the first and second VDD An electrical isolation relationship is maintained with respect to the potential and the first and second GND potentials.

  As described above, the first configuration example of the semiconductor integrated circuit according to the third embodiment is the boundary of the power supply isolation region 73, that is, the basic cell 3 of the first basic cell group and the basic cell 3 of the second basic cell group. Therefore, it is not necessary to provide a separation region for power supply separation at the boundary between the first and second basic cell groups, and the basic cells can be arranged adjacent to each other without a gap.

  Therefore, the first effect that the semiconductor integrated circuit with an improved degree of integration can be obtained in the same manner as in the first embodiment because the power supply isolation region can be eliminated.

  Further, in the semiconductor integrated circuit of the first configuration example constituted by the basic cells 3 of the third embodiment, even if the power supply to a part of the power supply region is temporarily interrupted, as in the first embodiment. In addition, since the operation time is not delayed and the wiring efficiency is not deteriorated, the second effect that the reduction in power consumption can be achieved without any trouble is achieved.

(Second Configuration Example of Semiconductor Integrated Circuit)
FIG. 17 is an explanatory diagram schematically showing a second configuration example of a semiconductor integrated circuit configured using the basic cell 3 of the third embodiment shown in FIG. The semiconductor integrated circuit shown in FIG. 17 is configured to receive two types of power supplies.

  The second configuration example of the semiconductor integrated circuit shown in FIG. 17 includes a plurality of basic cells 3, and, similar to the first configuration example, the VDD power supply wiring 31a (and 31b) and the GND power supply wiring 36a (in the column direction). And 36b) are alternately arranged.

  Then, a first basic cell group (basic cell 3 other than the power supply isolation region 73) that receives the first GND potential and the first VDD potential from the upper layer GND wiring 81 and the upper layer VDD wiring 91, and an upper layer GND wiring 82 and the upper layer VDD wiring 92, respectively. The cell is classified into a second basic cell group (basic cell 3 in the power supply isolation region 73) that receives the second GND potential and the second VDD potential.

  In the basic cell 3 of the first basic cell group, the GND power supply wiring 36a and the VDD power supply wiring 31a are electrically connected to the upper layer GND wiring 81 and the upper layer VDD wiring 91 through the via holes 71, respectively. 36b and the VDD power supply wiring 31b are also electrically connected to the upper layer GND wiring 81 and the upper layer VDD wiring 91 through the via holes 71, respectively.

  Then, the VDD power supply wirings 31a and 31b and the GND power supply wirings 36a and 36b between the basic cells 3 and 3 adjacent in the row direction are electrically connected through the inter-cell connection auxiliary power supply wiring 72, respectively. The first GND potential and the first VDD potential are set.

  On the other hand, in the basic cell 3 of the second basic cell group (in the power supply isolation region 73), the GND power supply wiring 36a and the VDD power supply wiring 31a are electrically connected to the upper layer GND wiring 82 and the upper layer VDD wiring 92 through the via holes 71, respectively. The GND power supply wiring 36b and the VDD power supply wiring 31b are also electrically connected to the upper layer GND wiring 82 and the upper layer VDD wiring 92 through the via holes 71, respectively.

  Then, the VDD power supply wirings 31a and 31b and the GND power supply wirings 36a and 36b between the basic cells 3 and 3 adjacent to each other on the left and right in the drawing are electrically connected via the inter-cell connection auxiliary power supply wiring 72. The second VDD potential and the second GND potential are set.

  Then, by not forming the inter-cell connection auxiliary power supply wiring 72 between the other cells 3x and 3y adjacent in the row direction outside the power supply isolation region 73, the electrical isolation relationship is established with respect to the first and second VDD potentials. maintain.

  As described above, the second configuration example of the semiconductor integrated circuit according to the third embodiment is the boundary of the power supply isolation region 73, that is, the basic cell 3 of the first basic cell group and the basic cell 3 of the second basic cell group. Therefore, it is not necessary to provide a separation region for power supply separation at the boundary between the first and second basic cell groups, and the basic cells can be arranged adjacent to each other without a gap.

  Therefore, the first effect that the semiconductor integrated circuit with an improved degree of integration can be obtained in the same manner as in the first embodiment because the power supply isolation region can be eliminated.

  Furthermore, in the semiconductor integrated circuit of the second configuration example constituted by the basic cells 3 of the third embodiment, even if the power supply to a part of the power supply region is temporarily interrupted as in the first embodiment. In addition, since the operation time is not delayed and the wiring efficiency is not deteriorated, the second effect that the reduction in power consumption can be achieved without any trouble is achieved.

  In addition, in the second configuration example, in addition to the VDD power supply wiring 31a (GND power supply wiring 36a), the body potential setting of the PMOS transistor (NMOS transistor) is also performed from the VDD power supply wiring 31b (GND power supply wiring 36b). The structure which performs is shown. That is, since the body potential can be set from two locations to the same body region, the resistance value from the VDD power supply wiring to the N transistor body region of the PMOS transistor and the P transistor of the NMOS transistor from the GND power supply wiring are comprehensively set. Since the resistance value to the body region can be kept low, the potential setting of the body region can be stabilized accordingly, and the third effect is achieved in that the transistor characteristics can be improved.

<Embodiment 4>
(Basic cell structure)
FIG. 18 is a plan view showing a layout structure of basic cells used in the semiconductor integrated circuit according to the fourth embodiment of the present invention. As shown in the figure, the basic cell 4 is composed of an N well region 8 and a P well region 9. A P-type transistor diffusion region 43 is selectively formed in the N-well region 8, and a PMOS is formed on the N-transistor body region (not shown) between the P-type transistor diffusion regions 43 via a gate insulating film (not shown). A gate electrode 44 is formed.

  On the other hand, an N-type transistor diffusion region 48 is selectively formed in the P-well region 9, and a gate insulating film (not shown) is interposed on the P-transistor body region (not shown) between the N-type transistor diffusion regions 48. Thus, an NMOS gate electrode 49 is formed.

  The P-type transistor diffusion region 43 and the PMOS gate electrode 44 constitute a PMOS transistor, and the N-type transistor diffusion region 48 and the NMOS gate electrode 49 constitute an NMOS transistor.

  An N-type diffusion region 42a is selectively formed in a part of the N-well region 8 (upper part of FIG. 18), and a plurality (three in FIG. 18) are electrically connected on the N-type diffusion region 42a. VDD power supply wirings 41a (first partial power supply wirings) are formed discretely. Further, an N-type diffusion region 42b is selectively formed in the other part of the N-well region 8 (lower part of FIG. 18), and a plurality of (in FIG. 18) are electrically connected on the N-type diffusion region 42b. Three (3) VDD power supply wires 41b (third partial power supply wires) are discretely formed.

  On the other hand, a P-type diffusion region 47a is selectively formed in a part of the P-well region 9 (lower part of FIG. 18), and a plurality (three in FIG. 18) are electrically connected on the P-type diffusion region 47a. ) GND power supply wiring 46a (second partial power supply wiring). Furthermore, a P-type diffusion region 47b is selectively formed in the other part (upper part of FIG. 18) in the P-well region 9, and a plurality of (in FIG. 18) are electrically connected on the P-type diffusion region 47b. Three (3) GND power supply wirings 46b (fourth partial power supply wirings) are formed.

  The VDD power supply wirings 41a and 41b and the GND power supply wirings 46a and 46b are electrically separated from adjacent cells by being provided in the cell with a predetermined distance without contacting the cell boundary 40 of the basic cell 4, respectively. Is done.

  The N type diffusion regions 42a and 42b correspond to body contact regions provided for setting the back gate potential of the PMOS transistor formed in the N well region 8, respectively. The P type diffusion regions 47a and 47b are in the P well region 9. This corresponds to the body contact region provided for setting the back gate potential of the NMOS transistor formed in step (b).

  Further, in the N well region 8, a partial isolation region 45a is formed on the extension line of the PMOS gate electrode 44 between the PMOS gate electrode 44 and the N type diffusion region 42a, and between the PMOS gate electrode 44 and the N type diffusion region 42b. A partial isolation region 45 b is formed on the extended line of the PMOS gate electrode 44. Similarly, in the P well region 9, a partial isolation region 45a is formed on the extension line of the NMOS gate electrode 49 between the NMOS gate electrode 49 and the P type diffusion region 47a. A partial isolation region 45b is formed on the extension line of the NMOS gate electrode 49 between 47b.

  Similarly to the basic cell 3 of the third embodiment, the basic cell 4 of the fourth embodiment also applies a predetermined body potential to each of the N-type diffusion regions 42a and 42b from the VDD power wirings 41a and 41b. The body potential of the PMOS transistor formed in the well region 8 can be set. Similarly, the body potential of the NMOS transistor formed in the P well region 9 is set by applying predetermined body potentials to the P type diffusion regions 47a and 47b from the GND power supply wirings 46a and 46b, respectively. Can do.

(First Configuration Example of Semiconductor Integrated Circuit)
FIG. 19 is an explanatory diagram schematically showing a first configuration example of a semiconductor integrated circuit configured using the basic cell 4 of the fourth embodiment shown in FIG. The semiconductor integrated circuit shown in FIG. 19 is configured to receive two types of power supply.

  The first configuration example of the semiconductor integrated circuit shown in FIG. 19 includes a plurality of basic cells 4, and includes a VDD power supply wiring 41a (and 41b) and a GND power supply wiring 46a (and 46b) in the column direction (vertical direction in the figure). ) Are alternately arranged. That is, in FIG. 19, the first and third columns are arranged in the order of the VDD power supply wiring 41a, the VDD power supply wiring 41b, the GND power supply wiring 46b, and the GND power supply wiring 46a from the top in the figure. The second column in the center is arranged in the completely reverse order (the order of 46a, 46b, 41b, 41a) as described above.

  Then, a first basic cell group (basic cell 4 other than the power supply isolation region 73) that receives the first GND potential and the first VDD potential from the upper layer GND wiring 81 and the upper layer VDD wiring 91, and an upper layer GND wiring 82 and the upper layer VDD wiring 92, respectively. It is classified into a second basic cell group (basic cell 4 in the power supply isolation region 73) that receives the second GND potential and the second VDD potential. The upper layer GND wirings 81 and 82 and the upper layer VDD wirings 91 and 92 are formed in an upper layer than the VDD power source wirings 41 a and 41 b and the GND power source wirings 46 a and 46 b formed in the basic cell 4.

  In the basic cell 4 of the first basic cell group, the GND power supply wiring 46a and the VDD power supply wiring 41a are electrically connected to the upper layer GND wiring 81 and the upper layer VDD wiring 91 through the via holes 71, respectively. Further, in each basic cell 4, inter-cell terminal connection auxiliary power wiring 74 is formed between discrete VDD power wirings 41a and 41a, and inter-cell terminal connection auxiliary is formed between discrete GND power wirings 46a and 46a. The power supply wiring 74 is formed, and the VDD power supply wiring 41a and the GND power supply wiring 46a between the basic cells 4 and 4 adjacent in the row direction (left-right direction in the figure) are respectively connected via the inter-cell connection auxiliary power supply wiring 72. By being electrically connected, the first GND potential and the first VDD potential are set.

  On the other hand, in the basic cell 4 of the second basic cell group (in the power supply isolation region 73), the GND power supply wiring 46a and the VDD power supply wiring 41a are electrically connected to the upper layer GND wiring 82 and the upper layer VDD wiring 92 through the via holes 71, respectively. Connected. Further, in each basic cell 4, inter-cell terminal connection auxiliary power wiring 74 is formed between discrete VDD power wirings 41a and 41a, and inter-cell terminal connection auxiliary is formed between discrete GND power wirings 46a and 46a. By forming the power supply wiring 74 and electrically connecting the VDD power supply wirings 41a and 46a between the basic cells 4 and 4 adjacent on the left and right in the figure through the inter-cell connection auxiliary power supply wiring 72, The 2VDD potential and the second GND potential are set.

  Then, by not forming the inter-cell connection auxiliary power supply wiring 72 between the other cells 4x and 4y adjacent in the row direction outside the power supply isolation region 73, the electrical isolation relationship is established with respect to the first and second VDD potentials. maintain.

  As described above, the first configuration example of the semiconductor integrated circuit according to the fourth embodiment is the boundary of the power supply isolation region 73, that is, the basic cell 4 of the first basic cell group and the basic cell 4 of the second basic cell group. Therefore, it is not necessary to provide a separation region for power supply separation at the boundary between the first and second basic cell groups, and the basic cells can be arranged adjacent to each other without a gap.

  Therefore, the first effect that the semiconductor integrated circuit with an improved degree of integration can be obtained in the same manner as in the first embodiment because the power supply isolation region can be eliminated.

  Further, in the semiconductor integrated circuit of the first configuration example constituted by the basic cells 4 of the fourth embodiment, as in the first embodiment, even if power supply to a part of the power supply region is temporarily interrupted. In addition, since the operation time is not delayed and the wiring efficiency is not deteriorated, the second effect that the reduction in power consumption can be achieved without any trouble is achieved.

  In addition, in the basic cell 4 of the fourth embodiment, the VDD power supply wirings 41a and 41b and the GND power supply wirings 46a and 46b are discretely formed. Therefore, as in the first configuration example, the VDD power supply wirings When the 41b and GND power supply wirings 46b are not used as power supply wirings, the region where the VDD power supply wiring 41b and the GND power supply wiring 46b are not formed can be effectively used for other purposes such as a signal wiring region. There is a fourth effect.

  In the first configuration example, the VDD power supply wiring 41b and the GND power supply wiring 46b are not used as power supply wirings in both the first and second basic cell groups. However, the first and second basic cell groups are not used. For one of the cell groups, a configuration in which the VDD power supply wiring 41b and the GND power supply wiring 46b are used as the power supply wiring is also conceivable.

(Second Configuration Example of Semiconductor Integrated Circuit)
FIG. 20 is an explanatory diagram schematically showing a second configuration example of the semiconductor integrated circuit configured using the basic cell 4 of the fourth embodiment shown in FIG. The semiconductor integrated circuit shown in FIG. 20 is configured to receive two types of power supply.

  The second configuration example of the semiconductor integrated circuit shown in FIG. 20 is composed of a plurality of basic cells 4. Like the first configuration example, the VDD power supply wiring 41a (and 41b) and the GND power supply wiring 46a (in the column direction). And 46b) are alternately arranged.

  Then, a first basic cell group (basic cell 4 other than the power supply isolation region 73) that receives the first GND potential and the first VDD potential from the upper layer GND wiring 81 and the upper layer VDD wiring 91, and an upper layer GND wiring 82 and the upper layer VDD wiring 92, respectively. It is classified into a second basic cell group (basic cell 4 in the power supply isolation region 73) that receives the second GND potential and the second VDD potential.

  In the basic cell 4 of the first basic cell group, the GND power supply wiring 46a and the VDD power supply wiring 41a are electrically connected to the upper layer GND wiring 81 and the upper layer VDD wiring 91 through the via holes 71, respectively. 46b and the VDD power supply wiring 41b are also electrically connected to the upper layer GND wiring 81 and the upper layer VDD wiring 91 through the via holes 71, respectively.

  In addition, inter-cell terminal connection auxiliary power wires 74 are provided between the VDD power wires 41a and 41b and the GND power wires 46a and 46b, which are discretely formed in the basic cell 4, and adjacent to each other in the row direction. The VDD power wirings 41a and 41b and the GND power wirings 46a and 46b between the basic cells 4 and 4 are electrically connected via the inter-cell connection auxiliary power wiring 72, so that the first GND potential and the first VDD Set to potential.

  On the other hand, in the basic cell 4 of the second basic cell group (in the power supply isolation region 73), the GND power supply wiring 46a and the VDD power supply wiring 41a are electrically connected to the upper layer GND wiring 82 and the upper layer VDD wiring 92 through the via holes 71, respectively. The GND power supply wiring 46b and the VDD power supply wiring 41b are also electrically connected to the upper layer GND wiring 82 and the upper layer VDD wiring 92 through the via holes 71, respectively.

  In addition, inter-cell terminal connection auxiliary power wires 74 are provided between the VDD power wires 41a and 41b and the GND power wires 46a and 46b, which are discretely formed in the basic cell 4, and adjacent to the left and right in the figure. The VDD power wirings 41a and 41b and the GND power wirings 46a and 46b between the basic cells 4 and 4 to be connected are electrically connected via the inter-cell connection auxiliary power wiring 72, so that the second VDD potential and the second GND are connected. Set to potential.

  Then, by not forming the inter-cell connection auxiliary power supply wiring 72 between the other cells 4x and 4y adjacent in the row direction outside the power supply isolation region 73, the electrical isolation relationship is established with respect to the first and second VDD potentials. maintain.

  As described above, the second configuration of the semiconductor integrated circuit according to the fourth embodiment has the boundary between the power source isolation regions 73, that is, the basic cell 4 in the first basic cell group and the basic cell 4 in the second basic cell group. Since it is not necessary to provide a separation region for power source separation at the boundary, the basic cells of the first and second basic cell groups can be arranged adjacent to each other without a gap.

  Therefore, the first effect that the semiconductor integrated circuit with an improved degree of integration can be obtained in the same manner as in the first embodiment because the power supply isolation region can be eliminated.

  Further, in the semiconductor integrated circuit of the second configuration example constituted by the basic cells 4 of the fourth embodiment, even if power supply to a part of the power supply region is temporarily interrupted as in the first embodiment. In addition, since the operation time is not delayed and the wiring efficiency is not deteriorated, the second effect that the reduction in power consumption can be achieved without any trouble is achieved.

  Further, in the second configuration example of the fourth embodiment, in addition to the VDD power supply wiring 41a (GND power supply wiring 46a), the VDD power supply wiring 41b (GND power supply wiring 46b) also includes a PMOS transistor (NMOS transistor). Thus, the third effect that the transistor characteristics can be improved can be obtained as in the second configuration example of the third embodiment.

<Embodiment 5>
(Basic cell structure)
FIG. 21 is a plan view showing a layout structure of a basic cell used in the semiconductor integrated circuit according to the fifth embodiment of the present invention. As shown in the figure, the basic cell 5 is composed of an N well region 8 and a P well region 9. A P-type transistor diffusion region 53 is selectively formed in the N-well region 8, and a PMOS is formed on the N-transistor body region (not shown) between the P-type transistor diffusion regions 53 via a gate insulating film (not shown). A gate electrode 54 is formed.

  On the other hand, an N-type transistor diffusion region 58 is selectively formed in the P-well region 9, and a gate insulating film (not shown) is interposed on the P-transistor body region (not shown) between the N-type transistor diffusion regions 58. Thus, an NMOS gate electrode 59 is formed.

  The P-type transistor diffusion region 53 and the PMOS gate electrode 54 constitute a PMOS transistor, and the N-type transistor diffusion region 58 and the NMOS gate electrode 59 constitute an NMOS transistor.

  An N-type diffusion region 52a is selectively formed in a part of the N-well region 8 (upper part of FIG. 21), and a VDD power supply wiring 51a is formed by being electrically connected to the N-type diffusion region 52a. . Furthermore, two (predetermined number) of N-type diffusion regions 52b (third partial diffusion regions) are separately formed on the left and right in the figure in the other part (lower part of FIG. 21) in the N well region 8. The VDD power supply wiring 51b is formed by being electrically connected to the N-type diffusion region 52b. Thus, two N-type diffusion regions 52b are formed discretely corresponding to the two PMOS transistors (PMOS gate electrode 54) formed in the N well region 8.

  On the other hand, a P-type diffusion region 57a is selectively formed in a part of the P-well region 9 (lower part of FIG. 21), and a GND power supply wiring 56a is formed by being electrically connected to the P-type diffusion region 57a. Is done. Furthermore, two (predetermined number) of P-type diffusion regions 57b (fourth partial diffusion regions) are separately formed on the left and right in the drawing in the other part (upper part of FIG. 21) in the P well region 9. Then, a GND power supply wiring 56b is formed on the P-type diffusion region 57b. In this manner, two P-type diffusion regions 57b are discretely formed corresponding to the two NMOS transistors (NMOS gate electrodes 59) formed in the P well region 9.

  The VDD power supply wirings 51a and 51b and the GND power supply wirings 56a and 56b (first, third, second, and fourth power supply wirings) are separated from each other by a predetermined distance without contacting the cell boundary 50 of the basic cell 5. By being provided in a cell, it is electrically isolated from adjacent cells.

  The N type diffusion regions 52a and 52b correspond to body contact regions provided for setting the back gate potential of the PMOS transistor formed in the N well region 8, respectively. The P type diffusion regions 57a and 57b are in the P well region 9. This corresponds to the body contact region provided for setting the back gate potential of the NMOS transistor formed in step (b).

  Further, in the N well region 8, a partial isolation region 55a (first partial isolation region) is formed on the extension line of the PMOS gate electrode 54 between the PMOS gate electrode 54 and the N-type diffusion region 52a. A partial isolation region 55b (third partial isolation region) is formed between each end on the PMOS gate electrode 54 and the left and right N-type diffusion regions 52b.

  Similarly, in the P well region 9, a partial isolation region 55a (second partial isolation region) is formed on the extended line of the NMOS gate electrode 59 between the NMOS gate electrode 59 and the P-type diffusion region 57a. Partial isolation regions 55b (fourth partial isolation regions) are formed between the respective ends on the left and right NMOS gate electrodes 59 and the left and right P-type diffusion regions 57b.

  Similar to the basic cell 3 of the third embodiment, the basic cell 5 is formed in the N well region 8 by applying a predetermined body potential to the N type diffusion regions 52a and 52b from the VDD power wirings 51a and 51b. The body potential of the PMOS transistor to be set can be set, and is formed in the P well region 9 by applying a predetermined body potential to the P type diffusion regions 57a and 57b from the GND power supply wirings 56a and 56b, respectively. The body potential of the NMOS transistor can be set.

(Semiconductor integrated circuit)
By using the basic cell 5 of the fifth embodiment to form a semiconductor integrated circuit similar to the first configuration example of the third embodiment shown in FIG. 16, the first configuration example of the third embodiment and Similarly, the first and second effects can be exhibited.

  Further, by using the basic cell 5 of the fifth embodiment to form a semiconductor integrated circuit similar to the second configuration example of the third embodiment shown in FIG. 17, the second configuration of the third embodiment. Similar to the example, the first to third effects can be exhibited.

(Inherent effect of the fifth embodiment)
Furthermore, the basic cell 5 according to the fifth embodiment has the following effects by discretely forming the N-type diffusion region 52b and the P-type diffusion region 57b.

  FIG. 22 is an explanatory diagram showing an example of gate connection between MOS transistors by the basic cell 3 of the third embodiment. As shown in the figure, the basic cell 3 of the third embodiment is electrically connected to a PMOS gate electrode 34 formed in the N well region 8 and an NMOS gate electrode 39 formed in the P well region 9. For the connection, a metal wiring 85 disposed above the VDD power supply wiring 31b and the GND power supply wiring 36b is provided, and the metal wiring 85, the PMOS gate electrode 34 and the NMOS gate electrode 39 are connected to the poly upper contact hole 84. It is realized by electrically connecting with. In practice, the metal wiring 85 is electrically connected to the PMOS gate electrode 34 and the NMOS gate electrode 39 through an intermediate conductive layer (not shown).

  FIG. 23 is an explanatory diagram showing an example of gate connection between MOS transistors by the basic cell 5 of the fifth embodiment. As shown in the figure, in the basic cell 5, the N-type diffusion region 52b and the P-type diffusion region 57b are discretely formed and are not formed on the extension lines of the PMOS gate electrode 54 and the NMOS gate electrode 59. .

  Therefore, by providing the poly wiring 75 at the same formation height as the PMOS gate electrode 54 and the NMOS gate electrode 59 on the extension line between the PMOS gate electrode 54 and the NMOS gate electrode 59, the PMOS gate electrode 54 is provided. Thus, electrical connection between the NMOS gate electrodes 59 can be realized. The VDD power supply wiring 51b and the GND power supply wiring 56b are formed in the upper layer of the PMOS gate electrode 54 and the NMOS gate electrode 59. Therefore, the poly wiring 75 and the VDD power supply wiring 51b or the GND power supply wiring 56b are provided. There is no electrical connection.

  As described above, the basic cell 5 of the fifth embodiment has the fifth effect of improving the wiring efficiency in the cell by discretely forming the N-type diffusion region 52b and the P-type diffusion region 57b. .

<Embodiment 6>
(Basic cell structure)
FIG. 24 is a plan view showing a basic cell layout structure according to the sixth embodiment of the present invention. As shown in the figure, the basic cell 6 is composed of an N well region 8 and a P well region 9. A P-type transistor diffusion region 63 is selectively formed in the N-well region 8, and a PMOS is formed on the N-transistor body region (not shown) between the P-type transistor diffusion regions 63 via a gate insulating film (not shown). A gate electrode 64 is formed.

  On the other hand, an N-type transistor diffusion region 68 is selectively formed in the P-well region 9, and a gate insulating film (not shown) is interposed on the P-transistor body region (not shown) between the N-type transistor diffusion regions 68. Thus, an NMOS gate electrode 69 is formed.

  The P-type transistor diffusion region 63 and the PMOS gate electrode 64 constitute a PMOS transistor, and the N-type transistor diffusion region 68 and the NMOS gate electrode 69 constitute an NMOS transistor.

  An N type diffusion region 62a is selectively formed in a part of the N well region 8 (upper part of FIG. 24), and a plurality (three in FIG. 24) are electrically connected on the N type diffusion region 62a. VDD power supply wirings 61a (first partial power supply wirings) are formed discretely.

  Further, two N-type diffusion regions 62b (third partial diffusion regions) are separately formed on the left and right in the drawing in the other part of the N-well region 8 (lower part of FIG. 21). A plurality (three in FIG. 24) of VDD power supply wirings 61b (third partial power supply wirings) are discretely formed on the region 62b. The VDD power supply wiring 61b in which the N-type diffusion region 62b exists below among the plurality of VDD power supply wirings 61b is electrically connected to the lower N-type diffusion region 62b through a contact hole (not shown).

  In this way, two N-type diffusion regions 62b are formed discretely corresponding to the two PMOS transistors (PMOS gate electrode 64) formed in the N well region 8. Each of the two N-type diffusion regions 62b is electrically connected to the corresponding VDD power supply wiring 61b among the plurality of VDD power supply wirings 61b.

  On the other hand, a P-type diffusion region 67a is selectively formed in a part of the P-well region 9 (lower part in FIG. 24), and a plurality (three in FIG. 24) are electrically connected on the P-type diffusion region 67a. ) GND power supply wiring 66a (second partial power supply wiring).

  Further, two N-type diffusion regions 67b (fourth partial diffusion regions) are separately formed on the left and right in the drawing in the other part (lower part of FIG. 21) in the P-well region 9, and these N-type diffusions are formed. A plurality (three in FIG. 24) of GND power supply wirings 66b (fourth partial power supply wirings) are discretely formed on the region 67b. Among the plurality of GND power supply wirings 66b, the GND power supply wiring 66b in which the N-type diffusion region 67b exists below is electrically connected to the lower N-type diffusion region 67b through a contact hole (not shown).

  Thus, two P-type diffusion regions 67b are formed discretely corresponding to the two NMOS transistors (NMOS gate electrodes 69) formed in the P-well region 9. The two P-type diffusion regions 67b are electrically connected to the corresponding GND power supply wiring 66b among the plurality of GND power supply wirings 66b.

  The VDD power supply wirings 61a and 61b and the GND power supply wirings 66a and 66b are electrically separated from adjacent cells by being provided within the cell at a predetermined distance without contacting the cell boundary 60 of the basic cell 6. Is done.

  The N type diffusion regions 62a and 62b correspond to body contact regions provided for setting the back gate potential of the PMOS transistor formed in the N well region 8, respectively. The P type diffusion regions 67a and 67b are in the P well region 9. This corresponds to the body contact region provided for setting the back gate potential of the NMOS transistor formed in step (b).

  Further, in the N well region 8, a partial isolation region 65a (first partial isolation region) is formed on the extension line of the PMOS gate electrode 64 between the PMOS gate electrode 64 and the N-type diffusion region 62a. A partial isolation region 65b (third partial isolation region) is formed between each end on the PMOS gate electrode 64 and the left and right N-type diffusion regions 62b.

  Similarly, in the P well region 9, a partial isolation region 65a (second partial isolation region) is formed on the extended line of the NMOS gate electrode 69 between the NMOS gate electrode 69 and the P-type diffusion region 67a. Partial isolation regions 65b (fourth partial isolation regions) are formed between the respective ends on the left and right NMOS gate electrodes 69 and the left and right P-type diffusion regions 67b.

  Similarly to the basic cell 4 of the fourth embodiment, the basic cell 6 of the sixth embodiment also applies a predetermined body potential to each of the N-type diffusion regions 62a and 62b from the VDD power wirings 61a and 61b. The body potential of the PMOS transistor formed in the well region 8 can be set. Similarly, the body potential of the NMOS transistor formed in the P well region 9 is set by applying predetermined body potentials to the P-type diffusion regions 67a and 67b from the GND power supply wirings 66a and 66b, respectively. Can do.

(Semiconductor integrated circuit)
By using the basic cell 6 of the sixth embodiment and configuring a semiconductor integrated circuit similar to the first configuration example of the fourth embodiment shown in FIG. 19, the first configuration example of the fourth embodiment and Similarly, the first and second effects can be exhibited.

  Further, by using the basic cell 6 of the sixth embodiment to configure a semiconductor integrated circuit similar to the second configuration example of the fourth embodiment shown in FIG. 20, the second configuration of the fourth embodiment. Similar to the example, the first to third effects can be exhibited.

  Further, in the basic cell 6 of the sixth embodiment, as in the fifth embodiment, the N-type diffusion region 62b and the P-type diffusion region 67b are discretely formed to improve the wiring efficiency in the cell. There is a fifth effect.

  Further, in the basic cell 6 of the sixth embodiment, the N-type diffusion region 62b and the P-type diffusion region 67b are discretely formed, so that the N-type diffusion region 62b and the P-type diffusion region 67b are not formed. Since the poly wiring can be formed, the wiring efficiency in the cell can be further improved by exhibiting the fourth effect.

<Others>
In the basic cells 3 to 6 shown in the third to sixth embodiments, a configuration in which the GND power supply wiring is shared between adjacent cells can be adopted as in the basic cell 2 of the second embodiment. . For example, in the basic cell 3 of the third embodiment shown in FIG. 13, the GND power supply wiring 36a is shared between adjacent cells, thereby reducing the cell area as in the second embodiment. It is possible to produce an effect of being able to.

  Further, as described in the description of the second embodiment, it is also possible to adopt a configuration in which the VDD power supply wiring is shared between the cells instead of the configuration in which the GND power supply wiring is shared between the cells. The effect of.

It is a top view which shows the layout structure of the basic cell which is Embodiment 1 of this invention. It is explanatory drawing which showed typically the basic cell shown in FIG. It is sectional drawing which shows the AA cross section of FIG. It is sectional drawing which shows the BB cross section of FIG. FIG. 2 is an explanatory diagram schematically showing a semiconductor integrated circuit configured using the basic cell 1 of the first embodiment shown in FIG. 1. It is explanatory drawing which shows a chip | tip area | region typically when a general some power supply area | region exists. FIG. 3 is an explanatory diagram schematically showing a chip region when there are a plurality of power supply regions when the basic cell of the first embodiment is used. It is explanatory drawing which shows the conventional signal signal for evacuation typically. FIG. 3 is an explanatory diagram schematically showing a save signal path when the basic cell according to the first embodiment is used. It is explanatory drawing which showed the structure of FIG. 9 more concretely. It is a top view which shows the layout structure of the basic cell which is Embodiment 2 of this invention. FIG. 12 is an explanatory diagram schematically showing a semiconductor integrated circuit configured using the basic cell of the second embodiment shown in FIG. 11. It is a top view which shows the layout structure of the basic cell which is Embodiment 3 of this invention. FIG. 3 is a cross-sectional view showing a CC cross section of FIG. 1 in the basic cell of the first embodiment. It is sectional drawing which shows DD sectional structure of FIG. FIG. 14 is an explanatory diagram schematically illustrating a first configuration example of a semiconductor integrated circuit configured using the basic cell of the third embodiment illustrated in FIG. 13. FIG. 14 is an explanatory diagram schematically illustrating a second configuration example of a semiconductor integrated circuit configured using the basic cell of the third embodiment illustrated in FIG. 13. It is a top view which shows the layout structure of the basic cell which is Embodiment 4 of this invention. FIG. 19 is an explanatory diagram schematically illustrating a first configuration example of a semiconductor integrated circuit configured using the basic cell of the fourth embodiment illustrated in FIG. 18. FIG. 19 is an explanatory diagram schematically illustrating a second configuration example of a semiconductor integrated circuit configured using the basic cell 4 of the fourth embodiment illustrated in FIG. 18. It is a top view which shows the layout structure of the basic cell which is Embodiment 5 of this invention. FIG. 10 is an explanatory diagram illustrating an example of gate connection between MOS transistors by a basic cell according to a third embodiment. These are explanatory drawings showing an example of gate connection between MOS transistors by the basic cell 5 of the fifth embodiment. It is a top view which shows the layout structure of the basic cell which is Embodiment 6 of this invention.

Explanation of symbols

1-6 basic cells, 11, 21, 31a, 31b, 41a, 41b, 51a, 51b, 61a, 61b VDD power supply wiring, 12, 22, 32, 32a, 32b, 42, 42a, 42b, 52a, 52b, 62a, 62b N-type diffusion region, 16, 26, 36a, 36b, 46a, 46b, 56a, 56b, 66a, 66b GND power supply wiring, 17, 27, 37, 37a, 37b, 47, 47a, 47b, 57a, 57b, 67a, 67b P-type diffusion region, 45a, 45b, 55a, 55b, 104, 114, 124a, 124b, 134a, 134b Partial isolation region, 70 inter-cell power wiring, 71 via hole, 72 auxiliary power wiring for inter-cell connection 73 Power supply isolation region, 74 Inter-terminal connection auxiliary power supply wiring, 75 Poly wiring, 81, 82 Upper layer GND wiring, 85 metal wiring, 91, 92 upper layer VDD wiring, 101, 121 semiconductor substrate, 102, 122 buried insulating film, 103, 123 SOI layer, 106, 110-112, 116, 126, 130, 136 complete isolation region, 108 N Transistor body region, 118 P transistor body region, A1 first power supply region, A2 second power supply region, A3 multiple power supply region, AC chip region, C11 to C14, C21 to C24 cells, CR reduction region, GV power supply isolation Gap, RG, RG1 to RG4 saving register, SP0 power supply region group, SP1 to SP9 power supply region, VL1 first power supply line, VL2 second power supply line.

Claims (8)

A semiconductor integrated circuit formed on an SOI substrate comprising a semiconductor substrate, a buried insulating film and an SOI layer,
The semiconductor integrated circuit includes a plurality of basic cells,
Each of the plurality of basic cells is
An element formation region provided in the SOI substrate;
At least one semiconductor element formed in the element formation region;
A potential setting region electrically connected to a predetermined region of the at least one semiconductor element;
In-cell power supply wiring provided in electrical connection on the potential setting region, the in-cell power supply wiring is formed without protruding into the basic cell,
Semiconductor integrated circuit. A semiconductor integrated circuit according to claim 1,
The element formation region includes first and second well regions of first and second conductivity types,
The at least one semiconductor element includes at least one first and second MOS transistors of second and first conductivity types formed in the first and second well regions,
The predetermined region includes first and second body regions of the at least one first and second MOS transistors;
The potential setting region includes first and second diffusion regions of the first and second conductivity types, which are formed with the first and second body regions and the first and second partial isolation regions interposed therebetween. The first and second partial isolation regions are formed by leaving a part of the SOI layer without penetrating the SOI layer, and the first and second diffusion regions are respectively formed by the first and second diffusion regions. Electrically connected to the first and second body regions via a portion of the SOI layer under two partial isolation regions;
Semiconductor integrated circuit. A semiconductor integrated circuit according to claim 2, wherein
The in-cell power supply wiring includes first and second power supply wirings that are electrically connected to the first and second diffusion regions.
Semiconductor integrated circuit. A semiconductor integrated circuit according to claim 2, wherein
The in-cell power supply wiring includes a first power supply wiring provided to be electrically connected to the first diffusion region,
And a second power supply wiring that is electrically connected to the second diffusion region. The second power supply wiring is a cell that can be shared between adjacent basic cells among the plurality of basic cells. Placed on the boundary,
Semiconductor integrated circuit. A semiconductor integrated circuit according to claim 3, wherein
The potential setting region includes first and second conductivity type third and fourth diffusion regions formed between the first and second body regions and the third and fourth partial isolation regions. In addition, the third and fourth partial isolation regions are formed by leaving a part of the SOI layer without penetrating the SOI layer, and the third and fourth diffusion regions are formed by the third and fourth diffusion regions. Electrically connected to the first and second body regions through a part of the SOI layer under the partial isolation region 4;
The in-cell power supply wiring further includes third and fourth power supply wirings that are electrically connected to the third and fourth diffusion regions.
Semiconductor integrated circuit. A semiconductor integrated circuit according to claim 5, wherein
The first to fourth power supply wirings include a plurality of first to fourth partial power supply wirings, and the plurality of first to fourth partial power supply wirings are discretely formed in the basic cell.
Semiconductor integrated circuit. A semiconductor integrated circuit according to claim 5, wherein
The at least one first and second MOS transistors each include a predetermined number of first and second NMOS transistors;
The third and fourth diffusion regions include a predetermined number of third and fourth partial diffusion regions corresponding to the predetermined number of first and second MOS transistors, and the plurality of third and fourth diffusion regions. Each of the partial diffusion regions is discretely formed in the basic cell.
Semiconductor integrated circuit. A semiconductor integrated circuit according to claim 6, wherein
The at least one first and second MOS transistors each include a predetermined number of first and second NMOS transistors;
The third and fourth diffusion regions include a predetermined number of third and fourth partial diffusion regions corresponding to the predetermined number of first and second MOS transistors, and the predetermined number of third and fourth diffusion regions. Each of the fourth partial diffusion regions is discretely formed in the basic cell,
The predetermined number of third partial diffusion regions are electrically connected to the corresponding third partial power supply wires among the plurality of third partial power supply wires, and the predetermined number of fourth partial diffusion regions are Electrically connected to the corresponding fourth partial power supply wiring among the plurality of fourth partial power supply wirings,
Semiconductor integrated circuit.

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