JP2006080234A5 - - Google Patents

Claims (9)

In the semiconductor device in which the wiring layer is formed of an alloy material containing Cu,
A semiconductor device comprising: a wiring in the same wiring layer, wherein the wiring is formed of a Cu alloy material in which a ratio of an additive material that forms an alloy with Cu is changed according to a width of the wiring.   2. The semiconductor device according to claim 1, wherein a ratio of an additive material that forms an alloy with Cu decreases as the width of the wiring increases. A first wiring layer having a wiring made of Cu patterned into a predetermined shape;
An insulating layer formed on the first wiring layer;
A second wiring layer having a wiring made of Cu patterned in a predetermined shape on the insulating layer;
A plug formed on the insulating layer to electrically connect the wiring of the first wiring layer and the wiring of the second wiring layer, made of an additive material that forms an alloy with Cu;
The semiconductor device is characterized in that the plug and the wiring in the vicinity of the plug in the first and second wiring layers are formed of an alloy material of Cu and the additive material.   4. The semiconductor device according to claim 3, wherein the number of plugs provided between the wirings is changed in accordance with the thickness of the wirings of the first or second wiring layer. A method of manufacturing a semiconductor device having a wiring layer,
Forming first and second wiring grooves at predetermined positions on the insulating layer of the substrate;
Forming a seed layer made of a first conductive material containing Cu and an additive material on the side wall and bottom of the wiring groove;
Forming a wiring made of a second conductive material containing Cu on the seed layer by an electrolytic plating method;
Annealing the seed layer and the wiring to diffuse each other to form a wiring material layer in the first and second wiring grooves ;
Including
The wiring width of the first wiring groove is larger than the wiring width of the second wiring groove, and the content ratio of the additive material in the wiring material layer in the first wiring groove is the second wiring groove. A method for manufacturing a semiconductor device, wherein the content ratio of the additive material in the wiring material layer is lower . The additive material is any material selected from Al, Mg, Ti, Mn, Fe, Zn, Zr, Nb, Mo, Ru, Pd, Ag, In, a lanthanoid metal, and an actinoid metal . 6. The method of manufacturing a semiconductor device according to claim 5, wherein the conductive material of 2 is Cu metal. The seed layer is composed of two layers of an additive metal film made of a material that forms an alloy with Cu and a Cu metal film formed on the additive metal film,
6. The method of manufacturing a semiconductor device according to claim 5, wherein the second conductive material is Cu metal. A method of manufacturing a semiconductor device having a wiring layer,
Forming a first wiring layer having a lower wiring made of Cu metal at a predetermined position on the insulating layer of the substrate;
Forming an interlayer insulating film on the first wiring layer;
Forming a connection hole for embedding a plug for connecting to the lower layer wiring at a predetermined position of the interlayer insulating film, and a wiring groove for embedding an upper layer wiring constituting the second wiring layer;
Forming a barrier metal layer only on the side wall of the connection hole and the side wall and bottom of the wiring groove;
Forming an additive metal layer made of an additive element that forms an alloy with Cu in the connection hole;
Forming a Cu metal film in the wiring groove by electrolytic plating;
Annealing the connection hole and the first and second wiring layers in the vicinity of the connection portion of the connection hole so as to be a Cu alloy of Cu and the additive element;
A method for manufacturing a semiconductor device, comprising:   The additive material is any material selected from Al, Mg, Ti, Mn, Fe, Zn, Zr, Nb, Mo, Ru, Pd, Ag, In, a lanthanoid metal, and an actinide metal. The semiconductor device according to claim 2.