JP2006080181A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2006080181A
JP2006080181A JP2004260569A JP2004260569A JP2006080181A JP 2006080181 A JP2006080181 A JP 2006080181A JP 2004260569 A JP2004260569 A JP 2004260569A JP 2004260569 A JP2004260569 A JP 2004260569A JP 2006080181 A JP2006080181 A JP 2006080181A
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solid
semiconductor device
translucent substrate
state imaging
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Yoichiro Kondo
陽一郎 近藤
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Seiko Epson Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device receiving a solid imaging element in a package whose mounting area is more reduced, and reflow mounting, and also to provide its manufacturing method. <P>SOLUTION: The semiconductor device comprises: a translucent substrate 11 having at least a transparent electrode 12 and a transparent electrode pattern 13; the solid imaging element 14 having an electrode region 15 around the main surface side and provided with a space S between the electrode region 15 and the translucent substrate 11, since the electrode region 15 is connected electrically to the transparent electrode 12; a circuit substrate 21 arranged on the rear surface side of the solid imaging element 14, and provided with a connecting unit 22 connected to the translucent substrate 11 while being provided with the signal transfer route of the solid imaging element 14 formed thereon; and a plurality of external terminals 28 provided on the external mounting surface of the circuit substrate 21 and having respective connecting relation with the signal transfer route. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、特に固体撮像素子のパッケージ化を実現する半導体装置及びその製造方法に関する。   The present invention particularly relates to a semiconductor device that realizes packaging of a solid-state imaging device and a method for manufacturing the same.

近年、固体撮像素子の小型化実装は、携帯機器等、カメラ機能を持つ電子製品に欠かせない技術となっている。例えば、TABテープ等フレキシブルな配線基板に光学ガラス板を貼り付ける。固体撮像素子は、この配線基板にフェイスダウン実装される(例えば、特許文献1参照)。
特開2000−183368号公報(3頁、4頁、図1、図2)
In recent years, miniaturized mounting of solid-state imaging devices has become an indispensable technology for electronic products having camera functions such as portable devices. For example, an optical glass plate is attached to a flexible wiring board such as a TAB tape. The solid-state image sensor is mounted face-down on this wiring board (see, for example, Patent Document 1).
JP 2000-183368 A (page 3, page 4, FIGS. 1 and 2)

固体撮像素子等のセンサICに関し、メインの回路基板との接続はリフロー実装を利用したい。その理由は、技術も確立しており、安価で、他のICと同様に実装できるからである。しかしながら、フレキシブルな配線基板を使用した構造では、リフロー実装できない。フレキシブルな配線基板の代りに薄板状の配線基板を使用する構成も考えられる。これにより、リフロー実装が可能な構成が考えられるが、実装面積の縮小化は困難である。つまり上記構成では、ハンダ付けは、少なくともセンサICの外側周辺に張り出した配線基板に形成されることになる。これにより、パッケージサイズの小型化、実装面積の縮小化に不利である。   For sensor ICs such as solid-state image sensors, reflow mounting is desired for connection to the main circuit board. The reason is that the technology is established, is inexpensive, and can be mounted in the same manner as other ICs. However, reflow mounting is not possible with a structure using a flexible wiring board. A configuration using a thin wiring board instead of a flexible wiring board is also conceivable. As a result, a configuration capable of reflow mounting is conceivable, but it is difficult to reduce the mounting area. In other words, in the above configuration, the soldering is formed on a wiring board that protrudes at least around the outside of the sensor IC. This is disadvantageous in reducing the package size and the mounting area.

本発明は上記のような事情を考慮してなされたもので、より実装面積の縮小されたパッケージ内に固体撮像素子を収め、リフロー実装可能な高信頼性の半導体装置及びその製造方法を提供しようとするものである。   The present invention has been made in consideration of the above-described circumstances, and provides a highly reliable semiconductor device that can be reflow mounted by placing a solid-state imaging device in a package with a smaller mounting area, and a method for manufacturing the same. It is what.

本発明に係る半導体装置は、少なくとも透明電極を有する透光性基板と、主表面側の周辺に電極領域を有し、前記電極領域が前記透明電極と電気的に接続されることにより前記透光性基板との間に空間が設けられた固体撮像素子と、前記固体撮像素子の裏面側に配され、前記透光性基板との接続部を有すると共に前記固体撮像素子の信号伝達経路が形成された回路基材と、前記回路基材の外部実装面に設けられ、前記信号伝達経路とそれぞれ接続関係を有する複数の外部端子と、を含む。   The semiconductor device according to the present invention includes a translucent substrate having at least a transparent electrode, an electrode region around the main surface side, and the electrode region is electrically connected to the transparent electrode, thereby transmitting the translucent substrate. A solid-state image sensor provided with a space between the light-transmitting substrate and a back surface side of the solid-state image sensor, and having a connection portion with the translucent substrate and forming a signal transmission path of the solid-state image sensor. And a plurality of external terminals provided on the external mounting surface of the circuit substrate and having a connection relationship with the signal transmission path.

上記本発明に係る半導体装置によれば、固体撮像素子の裏面側に回路基材が設けられ、この回路基材の外部実装面に外部端子が設けられている。このため実装面積が小さくなる。また、ハンドリング等の外力に対してより強靭である。外部端子の構成次第で、より多端子実装にも対応し得る。また、リフロー実装にも対応可能となる構成にし易い。   According to the semiconductor device of the present invention, the circuit base is provided on the back side of the solid-state imaging device, and the external terminals are provided on the external mounting surface of the circuit base. This reduces the mounting area. Moreover, it is stronger against external forces such as handling. Depending on the configuration of the external terminals, more terminals can be mounted. In addition, it is easy to adopt a configuration that can support reflow mounting.

なお、上記本発明に係る半導体装置において、次のいずれかの特徴を有することにより、信頼性や量産性、または経済性に関してより好ましい構成となり得る。
前記固体撮像素子における前記電極領域は、複数のバンプ電極を含むことを特徴とする。
前記固体撮像素子における前記電極領域は、異方性導電部材を用いて前記透明電極に接続されていることを特徴とする。
前記回路基材における前記接続部は、前記固体撮像素子の周辺において前記回路基材上に設けられた導電パターンと、前記導電パターンが前記透光性基板の所定部に電気的に接続されるための異方性導電部材を含むことを特徴とする。
前記固体撮像素子の電極領域及び前記回路基材における前記透光性基板との接続部において、前記固体撮像素子と前記透光性基板との間の空間に通じる気道を設けたことを特徴とする。
前記回路基材における前記接続部は、前記固体撮像素子の周辺において、前記固体撮像素子の厚さに前記電極領域の高さを加えた分より大きい厚さで形成されていることを特徴とする。
前記回路基材は前記固体撮像素子が収まる窪みが設けられていることを特徴とする。
前記外部端子は、はんだボールを含みアレイ状に形成されていることを特徴とする。
Note that the semiconductor device according to the present invention can have any of the following characteristics, whereby a more preferable configuration can be obtained in terms of reliability, mass productivity, or economic efficiency.
The electrode region in the solid-state imaging device includes a plurality of bump electrodes.
The electrode region in the solid-state imaging device is connected to the transparent electrode using an anisotropic conductive member.
The connection part of the circuit base material is electrically connected to a conductive pattern provided on the circuit base material in the periphery of the solid-state imaging device and the conductive pattern to a predetermined part of the translucent substrate. The anisotropic conductive member is included.
An air passage leading to a space between the solid-state image sensor and the translucent substrate is provided in a connection portion between the electrode region of the solid-state image sensor and the translucent substrate in the circuit base material. .
The connection portion in the circuit base material is formed with a thickness larger than the thickness of the solid-state imaging device plus the height of the electrode region in the periphery of the solid-state imaging device. .
The circuit substrate is provided with a recess in which the solid-state image sensor is accommodated.
The external terminals are formed in an array including solder balls.

本発明に係る半導体装置の製造方法は、少なくとも透明電極を有する透光性基板に、固体撮像素子主表面側周辺の電極領域を電気的に接続させ前記透光性基板と前記固体撮像素子主表面が空間を隔てて対向する第1ユニットを形成する工程と、一方面側の周辺領域に前記透光性基板との接続部材を配し、内部に前記固体撮像素子に応じた信号伝達経路を配備する回路基材であって、他方面側にこれら信号伝達経路に関わる外部端子領域を設ける第2ユニットを形成する工程と、前記第2ユニットの一方面側を前記第1ユニットにおける前記固体撮像素子の裏面側に対向させ、前記第2ユニットの前記接続部材を前記透光性基板と電気的に接続させる工程と、を含む。   In the method for manufacturing a semiconductor device according to the present invention, at least a translucent substrate having a transparent electrode is electrically connected to an electrode region around the solid-state image sensor main surface side, and the translucent substrate and the solid-state image sensor main surface Forming a first unit that faces each other with a space therebetween, a connecting member for connecting the translucent substrate in a peripheral region on one side, and a signal transmission path corresponding to the solid-state image sensor inside Forming a second unit that is provided with external terminal regions related to these signal transmission paths on the other surface side, and the solid-state image pickup device in the first unit on one surface side of the second unit. And electrically connecting the connecting member of the second unit to the translucent substrate.

上記本発明に係る半導体装置の製造方法によれば、第1ユニットを形成する工程によって、固体撮像素子主表面が透光性基板によって保護される。これにより、その後の取り扱いが容易となる。第2ユニットの回路基材は、一方面側を第1ユニットにおける固体撮像素子の裏面側に対向させ、固体撮像素子に重なるような他方面側において外部端子領域を広く設けることができる。   According to the method for manufacturing a semiconductor device according to the present invention, the main surface of the solid-state imaging device is protected by the light-transmitting substrate by the step of forming the first unit. Thereby, subsequent handling becomes easy. The circuit base of the second unit can be provided with a wide external terminal region on the other surface side that overlaps the solid-state image sensor with one surface facing the back surface side of the solid-state image sensor in the first unit.

なお、上記本発明に係る半導体装置の製造方法において、次のいずれかの特徴を有することにより、信頼性や量産性、または経済性に関してより好ましい製造方法となり得る。
前記第1ユニットにおける前記固体撮像素子の前記電極領域は、所定高さの複数のバンプ電極を有し、異方性導電部材を用いて前記透光性基板の透明電極に接続することを特徴とする。
前記第2ユニットの前記接続部材は、所定高さで導電パターンを形成し、異方性導電部材を用いて前記第1ユニットにおける前記透光性基板の所定部に電気的に接続することを特徴とする。
前記第1ユニット及び前記第2ユニットにおいて、前記固体撮像素子と前記透光性基板との間の空間に通じる気道を設けることを特徴とする。
前記第2ユニットにおいて、前記回路基材は前記固体撮像素子を収める窪みを予め設けることを特徴とする。
前記外部端子領域は、はんだボールの形成によって、メイン回路基板への実装時にリフロー実装することを特徴とする。
In addition, in the manufacturing method of the semiconductor device which concerns on the said invention, it can become a more preferable manufacturing method regarding reliability, mass-productivity, or economical efficiency by having either of the following characteristics.
The electrode region of the solid-state imaging device in the first unit has a plurality of bump electrodes having a predetermined height, and is connected to the transparent electrode of the translucent substrate using an anisotropic conductive member. To do.
The connection member of the second unit forms a conductive pattern at a predetermined height, and is electrically connected to a predetermined portion of the translucent substrate in the first unit using an anisotropic conductive member. And
In the first unit and the second unit, an air passage leading to a space between the solid-state imaging device and the translucent substrate is provided.
In the second unit, the circuit base material is previously provided with a recess for accommodating the solid-state imaging device.
The external terminal region is reflow-mounted when mounted on the main circuit board by forming solder balls.

発明を実施するための形態BEST MODE FOR CARRYING OUT THE INVENTION

図1は、本発明の第1実施形態に係る半導装置の要部構成を示す断面図である。固体撮像素子を封止したICパッケージ構造である。
透光性基板としてのガラス基板11は、周辺領域に透明電極12とこれに接続関係を有するパターンとして透明電極パターン13が形成されている。透明電極12及びそのパターン13は、ITO(indium tin oxide)膜等が考えられる。固体撮像素子14は、主表面側の周辺に信号を伝達する電極領域15を有する。電極領域15は、例えば所定高さの複数のバンプ電極15Bからなり、それぞれガラス基板11の透明電極12と接続されている。バンプ電極15Bと透明電極12との接続は、例えば異方性導電部材16が用いられる。異方性導電部材16は、ACF(異方性導電膜)やACP(異方性導電ペースト)等を用いることが考えられる。このように電極領域15が透明電極12と電気的に接続されることにより、ガラス基板11との間に空間Sが設けられている。
FIG. 1 is a cross-sectional view showing a main configuration of a semiconductor device according to a first embodiment of the present invention. This is an IC package structure in which a solid-state image sensor is sealed.
As for the glass substrate 11 as a translucent board | substrate, the transparent electrode pattern 13 is formed as a pattern which has the transparent electrode 12 and a connection relation with this in the peripheral region. The transparent electrode 12 and its pattern 13 may be an ITO (indium tin oxide) film or the like. The solid-state image sensor 14 has an electrode region 15 that transmits a signal around the main surface. The electrode region 15 includes a plurality of bump electrodes 15B having a predetermined height, for example, and is connected to the transparent electrode 12 of the glass substrate 11, respectively. For example, an anisotropic conductive member 16 is used to connect the bump electrode 15B and the transparent electrode 12. The anisotropic conductive member 16 may be made of ACF (anisotropic conductive film), ACP (anisotropic conductive paste), or the like. As described above, the electrode region 15 is electrically connected to the transparent electrode 12, thereby providing a space S between the glass substrate 11.

また、回路基材21が固体撮像素子14の裏面側に配されている。回路基材21は、多層の配線層24を有する。回路基材21は、内部の配線層24によって固体撮像素子14の信号伝達経路が形成されている。回路基材21は、ガラス基板11の透明電極パターン13による端子エリアとの電気的な接続部22を有する。接続部22は、固体撮像素子14周辺側の回路基材21上において、固体撮像素子14の厚さにバンプ電極15Bの高さを加えた分より大きい厚さで形成された導電パターン22Pを有する。導電パターン22Pは、例えば所定のメッキ処理が施された所定高さを有し、異方性導電部材23を利用してガラス基板11側との導通がとられる。異方性導電部材23は、ACFやACP等を用いることが考えられる。このような構成により、固体撮像素子14は、導電パターン22Pの段差をもってガラス基板11と回路基材21の間に収められる。   Further, the circuit substrate 21 is disposed on the back side of the solid-state imaging device 14. The circuit substrate 21 has a multilayer wiring layer 24. In the circuit base material 21, a signal transmission path of the solid-state imaging device 14 is formed by an internal wiring layer 24. The circuit base 21 has an electrical connection portion 22 with a terminal area by the transparent electrode pattern 13 of the glass substrate 11. The connecting portion 22 has a conductive pattern 22P formed on the circuit substrate 21 on the peripheral side of the solid-state imaging device 14 and having a thickness larger than the thickness of the solid-state imaging device 14 plus the height of the bump electrode 15B. . The conductive pattern 22P has, for example, a predetermined height that has been subjected to a predetermined plating process, and is electrically connected to the glass substrate 11 side using the anisotropic conductive member 23. The anisotropic conductive member 23 may be ACF, ACP, or the like. With such a configuration, the solid-state imaging device 14 is accommodated between the glass substrate 11 and the circuit base 21 with a step of the conductive pattern 22P.

外部端子28は、回路基材21内の配線層24による信号伝達経路と繋がり、回路基材21の外部実装面側に設けられている。外部端子28は、メインの回路基板30に実装するために設けられている。外部端子28は、例えば、はんだボールであり、回路基材21の外部実装面のランド25に対応して設けられる。   The external terminal 28 is connected to a signal transmission path by the wiring layer 24 in the circuit base 21 and is provided on the external mounting surface side of the circuit base 21. The external terminal 28 is provided for mounting on the main circuit board 30. The external terminal 28 is, for example, a solder ball, and is provided corresponding to the land 25 on the external mounting surface of the circuit substrate 21.

上記第1実施形態の構成によれば、固体撮像素子14の裏面側に回路基材21が設けられ、この回路基材21の外部実装面に外部端子28が設けられている。このため実装面積が小さくなる。また、回路基材21側面はハンドリング等の外力に対してより強靭である。また、外部端子28の占有面積は広く、より多端子実装にも対応し得る。また、外部端子28として、はんだボールを設けることで、リフロー実装にも対応可能となる構成にし易い。   According to the configuration of the first embodiment, the circuit base 21 is provided on the back surface side of the solid-state imaging device 14, and the external terminals 28 are provided on the external mounting surface of the circuit base 21. This reduces the mounting area. Further, the side surface of the circuit substrate 21 is stronger against external forces such as handling. In addition, the area occupied by the external terminals 28 is large, and it is possible to deal with mounting more terminals. Further, by providing solder balls as the external terminals 28, it is easy to adopt a configuration that can cope with reflow mounting.

図2、図3は、それぞれ本発明の第2実施形態に係る半導体装置の製造方法の要部を工程順に示す断面図であり、前記第1実施形態の構成を実現するための要部工程を示している。図1と同様の箇所には同一の符号を付して説明する。   2 and 3 are cross-sectional views showing the main part of the manufacturing method of the semiconductor device according to the second embodiment of the present invention in the order of steps, and the main part process for realizing the configuration of the first embodiment is shown. Show. The same parts as those in FIG. 1 are described with the same reference numerals.

図2に示すように、透光性基板としてのガラス基板11に、固体撮像素子14をフェイスダウン実装する。すなわち、ガラス基板11は、周辺領域に透明電極12とこの透明電極12に接続関係を有する透明電極パターン13が形成されている。固体撮像素子14は、ICとして50μm程度の厚みを有する。また、固体撮像素子14は、主表面側の周辺に信号を伝達する電極領域15として、例えば高さ20μm程度のバンプ電極15Bを有する。   As shown in FIG. 2, a solid-state imaging device 14 is mounted face-down on a glass substrate 11 as a light-transmitting substrate. That is, the glass substrate 11 is formed with a transparent electrode 12 and a transparent electrode pattern 13 having a connection relationship with the transparent electrode 12 in the peripheral region. The solid-state imaging device 14 has a thickness of about 50 μm as an IC. Further, the solid-state imaging device 14 has, for example, a bump electrode 15B having a height of about 20 μm as an electrode region 15 that transmits a signal to the periphery on the main surface side.

固体撮像素子14は、ガラス基板11の透明電極12にバンプ電極15Bを電気的に接続させる。バンプ電極15Bと透明電極12との接続は、異方性導電部材16(ACFやACP等)を介して達成される。バンプ電極15Bは所定高さを有し、固体撮像素子14はガラス基板11との間に所定の空間が得られ易い。これにより、ガラス基板11と固体撮像素子14主表面が空間Sを隔てて対向する第1ユニットU1を形成する。
なお、上記空間Sは、密封されるよりも僅かな気道が設けられる方が、熱膨張対策として有用である。電極間の異方性導電部材16の隙間を利用することも考えられる。
The solid-state imaging device 14 electrically connects the bump electrode 15 </ b> B to the transparent electrode 12 of the glass substrate 11. The connection between the bump electrode 15B and the transparent electrode 12 is achieved through an anisotropic conductive member 16 (ACF, ACP, etc.). The bump electrode 15 </ b> B has a predetermined height, and the solid-state imaging device 14 can easily obtain a predetermined space between the glass substrate 11. Thereby, the 1st unit U1 which the glass substrate 11 and the solid-state image sensor 14 main surface oppose across the space S is formed.
In addition, it is more useful as a countermeasure against thermal expansion if the space S is provided with a slight airway rather than being sealed. It is also conceivable to use a gap in the anisotropic conductive member 16 between the electrodes.

次に、図3に示すように、回路基材21を形成する。すなわち、回路基材21は、内部に多層の配線層24を形成し、一方面側の周辺領域にメッキ処理等を経て所定高さの導電パターン22Pを形成する。導電パターン22Pは、少なくともバンプ電極15B付きの固体撮像素子14よりも厚い、高さ71μm以上あるものとする。これにより、固体撮像素子14をガラス基板11と回路基材21の間に収めるだけの段差が得られる。さらに、回路基材21の他方面側(外部実装面)に外部端子領域としてランド25を形成する。このような回路基材21によって、固体撮像素子14の信号伝達経路を実現する第2ユニットU2を形成する。   Next, as shown in FIG. 3, the circuit base material 21 is formed. That is, the circuit substrate 21 has a multilayer wiring layer 24 formed therein, and a conductive pattern 22P having a predetermined height is formed in a peripheral region on one surface side through a plating process or the like. The conductive pattern 22P is thicker than at least the solid-state imaging device 14 with the bump electrode 15B and has a height of 71 μm or more. Thereby, the level | step difference which can accommodate the solid-state image sensor 14 between the glass substrate 11 and the circuit base material 21 is obtained. Further, lands 25 are formed as external terminal regions on the other surface side (external mounting surface) of the circuit substrate 21. The circuit unit 21 forms the second unit U2 that realizes the signal transmission path of the solid-state imaging device 14.

その後、第2ユニットU2の一方面側を第1ユニットU1における固体撮像素子14の裏面側に対向させ、組み合わせる。すなわち、回路基材21の導電パターン22Pをガラス基板11の透明電極パターン13による端子エリアに接続させる。この接続は、異方性導電部材23(ACFやACP等)を介して達成される。これにより、固体撮像素子のICパッケージが構成される。   Thereafter, the one surface side of the second unit U2 is opposed to the back surface side of the solid-state imaging device 14 in the first unit U1, and combined. That is, the conductive pattern 22 </ b> P of the circuit substrate 21 is connected to the terminal area by the transparent electrode pattern 13 of the glass substrate 11. This connection is achieved through the anisotropic conductive member 23 (ACF, ACP, etc.). Thereby, an IC package of the solid-state imaging device is configured.

図示しないが、この後、例えば図1に示すように、回路基材21のランド25に外部端子28としてのはんだボールを配備すれば、メインの回路基板30にリフロー実装することも可能である。   Although not shown, after that, as shown in FIG. 1, for example, if solder balls as external terminals 28 are provided on the lands 25 of the circuit base 21, reflow mounting on the main circuit board 30 is possible.

上記第2実施形態の方法によれば、第1ユニットU1を形成する工程によって、固体撮像素子14主表面がガラス基板11によって別途保護される。これにより、その後の取り扱いが容易となる。例えば、その後の取り扱い、製造ラインにおいてクリーンルームの清浄度のクラスが下げられることも利点の一つである。製造コストの低減につながる。
また、第2ユニットU2の回路基材21は、一方面側を第1ユニットU1における固体撮像素子14の裏面側に対向させ、固体撮像素子14に重なるような他方面側において外部端子領域を広く設けることができる。これにより、多端子実装にも対応可能である。
According to the method of the second embodiment, the main surface of the solid-state imaging device 14 is separately protected by the glass substrate 11 in the step of forming the first unit U1. Thereby, subsequent handling becomes easy. For example, one of the advantages is that the cleanliness class of the clean room is lowered in the subsequent handling and production line. This leads to a reduction in manufacturing costs.
Further, the circuit base member 21 of the second unit U2 has one side facing the back side of the solid-state image sensor 14 in the first unit U1, and a wide external terminal area on the other side that overlaps the solid-state image sensor 14. Can be provided. As a result, multi-terminal mounting can also be supported.

図4は、本発明の第3実施形態に係る半導体装置の要部を示す平面図であり、前記第1実施形態の構成における熱膨張対策をより具体的に示したものである。図1と同様の箇所には同一の符号を付して説明する。   FIG. 4 is a plan view showing the main part of the semiconductor device according to the third embodiment of the present invention, and more specifically shows countermeasures against thermal expansion in the configuration of the first embodiment. The same parts as those in FIG. 1 are described with the same reference numerals.

透光性基板としてのガラス基板11下に、フェイスダウン実装された固体撮像素子14がある。固体撮像素子14は、主表面中央領域にMLA(マイクロレンズ・アレイ)が配備されている。固体撮像素子14は、主表面周辺の電極領域15(バンプ電極15B)により、ガラス基板11の透明電極(図1の12)と接続され、ガラス基板11との間に空間Sを得ている。バンプ電極15Bと透明電極との接続には、例えばACFやACP等の異方性導電部材16が用いられる。   Under the glass substrate 11 as a translucent substrate, there is a solid-state imaging device 14 mounted face-down. The solid-state imaging device 14 is provided with an MLA (microlens array) in the central area of the main surface. The solid-state imaging device 14 is connected to the transparent electrode (12 in FIG. 1) of the glass substrate 11 by the electrode region 15 (bump electrode 15B) around the main surface, and obtains a space S between the glass substrate 11. For example, an anisotropic conductive member 16 such as ACF or ACP is used to connect the bump electrode 15B and the transparent electrode.

また、回路基材21が固体撮像素子14の裏面側に配されている。回路基材21は、内部の配線層(図1の24)によって固体撮像素子14の信号伝達経路が形成されている。回路基材21は、ガラス基板11周辺の透明電極パターン13による端子エリア(図示せず)との電気的な接続部22を有する。この接続部22の構成においても、例えば所定高さの導電パターン22P及び異方性導電部材23が用いられる。異方性導電部材23は、ACFやACP等を用いることが考えられる。   Further, the circuit substrate 21 is disposed on the back side of the solid-state imaging device 14. In the circuit substrate 21, a signal transmission path of the solid-state imaging device 14 is formed by an internal wiring layer (24 in FIG. 1). The circuit base 21 has an electrical connection portion 22 with a terminal area (not shown) by the transparent electrode pattern 13 around the glass substrate 11. Also in the configuration of the connection portion 22, for example, the conductive pattern 22P and the anisotropic conductive member 23 having a predetermined height are used. The anisotropic conductive member 23 may be ACF, ACP, or the like.

この第3実施形態では、固体撮像素子14の電極領域15及び回路基材21における接続部22において、固体撮像素子14とガラス基板11との間の空間Sに通じる気道41を設けている。これにより、メインの回路基板(図1の30)にリフローはんだ付けする際に、熱膨張した内部空気を外部に放出することができる。   In the third embodiment, an air passage 41 communicating with the space S between the solid-state image sensor 14 and the glass substrate 11 is provided in the electrode region 15 of the solid-state image sensor 14 and the connection portion 22 in the circuit base material 21. Thereby, when reflow soldering is performed on the main circuit board (30 in FIG. 1), the thermally expanded internal air can be discharged to the outside.

上記第3実施形態によれば、固体撮像素子14とガラス基板11との間の空間Sに通じる気道41を設けた。これにより、リフロー実装に、より優れた対応力を有する固体撮像素子のICパッケージが実現できる。
なお、この第3実施形態においては、気道41が四方に設けてあるが、気道の設ける位置も、本数も他の配備の仕方が様々考えられる。電極領域15や接続部22の配置の妨げにならないように配備すればよい。
According to the third embodiment, the airway 41 leading to the space S between the solid-state imaging device 14 and the glass substrate 11 is provided. Thereby, it is possible to realize an IC package of a solid-state imaging device having a more excellent capability for reflow mounting.
In the third embodiment, the airway 41 is provided in all directions, but there are various ways of arranging the airway and the number of positions and the number of airways. What is necessary is just to arrange | position so that arrangement | positioning of the electrode area | region 15 or the connection part 22 may not be prevented.

図5は、本発明の第4実施形態に係る半導装置の要部構成を示す断面図であり、前記図1の変形例としての、固体撮像素子を封止したICパッケージ構造である。
透光性基板としてのガラス基板51は、周辺領域に透明電極52とこれに接続関係を有するパターンとして透明電極パターン53が形成されている。透明電極52及びそのパターン53は、ITO(indium tin oxide)膜等が考えられる。固体撮像素子54は、主表面側の周辺に信号を伝達する電極領域55を有する。電極領域55は、例えば所定高さの複数のバンプ電極55Bからなり、それぞれガラス基板51の透明電極52と接続されている。バンプ電極55Bと透明電極52との接続は、例えばACFやACP等の異方性導電部材56が用いられる。このように電極領域55が透明電極52と電気的に接続されることにより、ガラス基板51との間に空間Sが設けられている。
FIG. 5 is a cross-sectional view showing the main configuration of a semiconductor device according to the fourth embodiment of the present invention, and shows an IC package structure in which a solid-state image sensor is sealed as a modification of FIG.
As for the glass substrate 51 as a translucent board | substrate, the transparent electrode pattern 53 is formed in the peripheral region as a pattern which has the transparent electrode 52 and a connection relation with this. The transparent electrode 52 and its pattern 53 may be an ITO (indium tin oxide) film or the like. The solid-state imaging device 54 has an electrode region 55 that transmits a signal around the main surface. The electrode region 55 includes a plurality of bump electrodes 55B having a predetermined height, for example, and is connected to the transparent electrode 52 of the glass substrate 51, respectively. For the connection between the bump electrode 55B and the transparent electrode 52, for example, an anisotropic conductive member 56 such as ACF or ACP is used. As described above, the electrode region 55 is electrically connected to the transparent electrode 52, thereby providing a space S between the glass substrate 51.

また、回路基材61が固体撮像素子54の裏面側に配されている。回路基材61は、多層の配線層64を有する。回路基材61は、内部の配線層64によって固体撮像素子54の信号伝達経路が形成されている。回路基材61は、固体撮像素子54が収まる窪み66を有する。回路基材61は、ガラス基板51の透明電極パターン53による端子エリアとの電気的な接続部62を有する。接続部62は、例えば所定のメッキ処理が施された所定高さの導電パターン62Pを有し、異方性導電部材63を利用してガラス基板51側との導通がとられる。異方性導電部材63は、ACFやACP等を用いることが考えられる。   In addition, the circuit base 61 is disposed on the back side of the solid-state image sensor 54. The circuit substrate 61 has a multilayer wiring layer 64. In the circuit base 61, a signal transmission path of the solid-state imaging device 54 is formed by an internal wiring layer 64. The circuit substrate 61 has a recess 66 in which the solid-state imaging element 54 is accommodated. The circuit base 61 has an electrical connection 62 with a terminal area by the transparent electrode pattern 53 of the glass substrate 51. The connecting portion 62 has, for example, a conductive pattern 62P having a predetermined height subjected to a predetermined plating process, and is electrically connected to the glass substrate 51 side using the anisotropic conductive member 63. The anisotropic conductive member 63 may be made of ACF, ACP, or the like.

外部端子68は、回路基材61内の配線層64による信号伝達経路と繋がり、回路基材61の外部実装面側に設けられている。外部端子68は、メインの回路基板30に実装するために設けられている。外部端子68は、例えば、はんだボールであり、回路基材61の外部実装面のランド65に対応して設けられる。   The external terminal 68 is connected to the signal transmission path by the wiring layer 64 in the circuit base 61 and is provided on the external mounting surface side of the circuit base 61. The external terminal 68 is provided for mounting on the main circuit board 30. The external terminal 68 is, for example, a solder ball, and is provided corresponding to the land 65 on the external mounting surface of the circuit substrate 61.

上記第4実施形態の構成によれば、固体撮像素子54の裏面側に固体撮像素子54が収まる窪み66を有する回路基材61が配されている。これにより、第1実施形態の構成に比べてより厚みの小さいパッケージ構成となり得る。また、第1実施形態の構成に比べてより厚みの大きい固体撮像素子54の搭載が容易になし得る。   According to the configuration of the fourth embodiment, the circuit base 61 having the recess 66 in which the solid-state image sensor 54 is accommodated is disposed on the back side of the solid-state image sensor 54. As a result, the package configuration can be made thinner than the configuration of the first embodiment. Further, it is possible to easily mount the solid-state imaging element 54 having a larger thickness than the configuration of the first embodiment.

その他の効果は前記第1実施形態と同様である。すなわち、回路基材61の外部実装面に外部端子68が設けられている。このため実装面積が小さくなる。また、回路基材61側面はハンドリング等の外力に対してより強靭である。また、外部端子68の占有面積は広く、より多端子実装にも対応し得る。また、外部端子68として、はんだボールを設けることで、リフロー実装にも対応可能となる構成にし易い。もちろん、前記第3実施形態で示すような、気道(41)を設けてもよい。   Other effects are the same as those of the first embodiment. That is, the external terminals 68 are provided on the external mounting surface of the circuit substrate 61. This reduces the mounting area. Further, the side surface of the circuit substrate 61 is more tough against external forces such as handling. In addition, the area occupied by the external terminals 68 is large, and it is possible to deal with mounting more terminals. Further, by providing solder balls as the external terminals 68, it is easy to adopt a configuration that can cope with reflow mounting. Of course, an airway (41) as shown in the third embodiment may be provided.

なお、上記各実施形態の構成及び方法において、ガラス基板11または51は、赤外線カットフィルタを付加してもよい。さらに、反射防止コートを追加してもよく、性能向上に寄与する。また、接続部22や62は、導電パターン22Pや62Pで示したが、バンプ電極を形成してもよい。   In addition, in the structure and method of each said embodiment, the glass substrate 11 or 51 may add an infrared cut filter. Furthermore, an antireflection coating may be added, which contributes to improved performance. Moreover, although the connection parts 22 and 62 were shown by the conductive patterns 22P and 62P, you may form a bump electrode.

以上説明したように本発明によれば、固体撮像素子の裏面側に回路基材が設けられ、この回路基材の外部実装面に外部端子が設けられている。このため実装面積が小さくなる。また、パッケージ側面は大部分が回路基材側部であり、ハンドリング等の外力に対してより強靭である。外部端子の構成次第で、より多端子実装にも対応し得る。また、リフロー実装にも対応可能となる構成にし易い。この結果、より実装面積の縮小されたパッケージ内に固体撮像素子を収め、リフロー実装可能な高信頼性の半導体装置及びその製造方法を提供することができる。   As described above, according to the present invention, the circuit substrate is provided on the back surface side of the solid-state imaging device, and the external terminals are provided on the external mounting surface of the circuit substrate. This reduces the mounting area. Further, most of the side surfaces of the package are the circuit substrate side portions, and are more tough against external forces such as handling. Depending on the configuration of the external terminals, more terminals can be mounted. In addition, it is easy to adopt a configuration that can support reflow mounting. As a result, it is possible to provide a highly reliable semiconductor device that can be reflow-mounted and housed in a package with a smaller mounting area, and a manufacturing method thereof.

第1実施形態に係る半導装置の要部構成を示す断面図。Sectional drawing which shows the principal part structure of the semiconductor device which concerns on 1st Embodiment. 第2実施形態に係る半導体装置の製造方法を工程順に示す第1断面図。The 1st sectional view showing the manufacturing method of the semiconductor device concerning a 2nd embodiment in order of a process. 図2に続く第2断面図。The 2nd sectional view following Drawing 2. 第3実施形態に係る半導体装置の要部を示す平面図。The top view which shows the principal part of the semiconductor device which concerns on 3rd Embodiment. 第4実施形態に係る半導装置の要部構成を示す断面図。Sectional drawing which shows the principal part structure of the semiconductor device which concerns on 4th Embodiment.

符号の説明Explanation of symbols

11,51…ガラス基板、12,52…透明電極、13,53…導電パターン、14,54…固体撮像素子、15,55…電極領域、15B,55B…バンプ電極、16,23,56,63…異方性導電部材、21,61…回路基材、22,62…接続部、22P,62P…導電パターン、24,64…配線層、25,65…ランド、28,68…外部端子、30…メインの回路基板、41…気道、66…窪み、S…空間、U1…第1ユニット、U2…第2ユニット。   DESCRIPTION OF SYMBOLS 11,51 ... Glass substrate, 12, 52 ... Transparent electrode, 13, 53 ... Conductive pattern, 14, 54 ... Solid-state image sensor, 15, 55 ... Electrode area | region, 15B, 55B ... Bump electrode, 16, 23, 56, 63 ... anisotropic conductive member, 21, 61 ... circuit substrate, 22, 62 ... connection part, 22P, 62P ... conductive pattern, 24, 64 ... wiring layer, 25, 65 ... land, 28, 68 ... external terminal, 30 ... main circuit board, 41 ... airway, 66 ... depression, S ... space, U1 ... first unit, U2 ... second unit.

Claims (14)

少なくとも透明電極を有する透光性基板と、
主表面側の周辺に電極領域を有し、前記電極領域が前記透明電極と電気的に接続されることにより前記透光性基板との間に空間が設けられた固体撮像素子と、
前記固体撮像素子の裏面側に配され、前記透光性基板との接続部を有すると共に前記固体撮像素子の信号伝達経路が形成された回路基材と、
前記回路基材の外部実装面に設けられ、前記信号伝達経路とそれぞれ接続関係を有する複数の外部端子と、
を含む半導体装置。
A translucent substrate having at least a transparent electrode;
A solid-state imaging device having an electrode region around the main surface side, and a space provided between the electrode region and the translucent substrate by being electrically connected to the transparent electrode;
A circuit base material disposed on the back side of the solid-state image sensor, having a connection part with the translucent substrate and having a signal transmission path of the solid-state image sensor;
A plurality of external terminals provided on the external mounting surface of the circuit substrate, each having a connection relationship with the signal transmission path;
A semiconductor device including:
前記固体撮像素子における前記電極領域は、複数のバンプ電極を含む請求項1記載の半導体装置。 The semiconductor device according to claim 1, wherein the electrode region in the solid-state imaging device includes a plurality of bump electrodes. 前記固体撮像素子における前記電極領域は、異方性導電部材を用いて前記透明電極に接続されている請求項1または2記載の半導体装置。 The semiconductor device according to claim 1, wherein the electrode region of the solid-state imaging device is connected to the transparent electrode using an anisotropic conductive member. 前記回路基材における前記接続部は、前記固体撮像素子の周辺において前記回路基材上に設けられた導電パターンと、前記導電パターンが前記透光性基板の所定部に電気的に接続されるための異方性導電部材を含む請求項1〜3いずれか一つに記載の半導体装置。 The connection part of the circuit base material is electrically connected to a conductive pattern provided on the circuit base material in the periphery of the solid-state imaging device and the conductive pattern to a predetermined part of the translucent substrate. The semiconductor device as described in any one of Claims 1-3 containing these anisotropic conductive members. 前記固体撮像素子の電極領域及び前記回路基材における前記透光性基板との接続部において、前記固体撮像素子と前記透光性基板との間の空間に通じる気道を設けた請求項1〜4いずれか一つに記載の半導体装置。 5. The air passage leading to a space between the solid-state image sensor and the translucent substrate is provided at a connection portion between the electrode region of the solid-state image sensor and the translucent substrate in the circuit base material. The semiconductor device according to any one of the above. 前記回路基材における前記接続部は、前記固体撮像素子の周辺において、前記固体撮像素子の厚さに前記電極領域の高さを加えた分より大きい厚さで形成されている請求項1〜5いずれか一つに記載の半導体装置。 The said connection part in the said circuit base material is formed in the circumference | surroundings of the said solid-state image sensor with thickness larger than the part which added the height of the said electrode area | region to the thickness of the said solid-state image sensor. The semiconductor device according to any one of the above. 前記回路基材は前記固体撮像素子が収まる窪みが設けられている請求項1〜5いずれか一つに記載の半導体装置。 The semiconductor device according to claim 1, wherein the circuit substrate is provided with a recess in which the solid-state imaging element is accommodated. 前記外部端子は、はんだボールを含みアレイ状に形成されている請求項1〜7いずれか一つに記載の半導体装置。 The semiconductor device according to claim 1, wherein the external terminals include solder balls and are formed in an array. 少なくとも透明電極を有する透光性基板に、固体撮像素子主表面側周辺の電極領域を電気的に接続させ前記透光性基板と前記固体撮像素子主表面が空間を隔てて対向する第1ユニットを形成する工程と、
一方面側の周辺領域に前記透光性基板との接続部材を配し、内部に前記固体撮像素子に応じた信号伝達経路を配備する回路基材であって、他方面側にこれら信号伝達経路に関わる外部端子領域を設ける第2ユニットを形成する工程と、
前記第2ユニットの一方面側を前記第1ユニットにおける前記固体撮像素子の裏面側に対向させ、前記第2ユニットの前記接続部材を前記透光性基板と電気的に接続させる工程と、
を含む半導体装置の製造方法。
A first unit in which an electrode region around the main surface side of a solid-state image sensor is electrically connected to a translucent substrate having at least a transparent electrode, and the translucent substrate and the solid-state image sensor main surface are opposed to each other with a space therebetween. Forming, and
A circuit base material in which a connection member to the translucent substrate is disposed in a peripheral region on one surface side, and a signal transmission path corresponding to the solid-state imaging device is provided therein, and these signal transmission paths are disposed on the other surface side. Forming a second unit for providing an external terminal area related to
Making one surface side of the second unit face the back surface side of the solid-state imaging device in the first unit, and electrically connecting the connection member of the second unit to the translucent substrate;
A method of manufacturing a semiconductor device including:
前記第1ユニットにおける前記固体撮像素子の前記電極領域は、所定高さの複数のバンプ電極を有し、異方性導電部材を用いて前記透光性基板の透明電極に接続する請求項9記載の半導体装置の製造方法。 The electrode region of the solid-state imaging device in the first unit has a plurality of bump electrodes having a predetermined height, and is connected to the transparent electrode of the translucent substrate using an anisotropic conductive member. Semiconductor device manufacturing method. 前記第2ユニットの前記接続部材は、所定高さで導電パターンを形成し、異方性導電部材を用いて前記第1ユニットにおける前記透光性基板の所定部に電気的に接続する請求項9または10記載の半導体装置の製造方法。 The connection member of the second unit forms a conductive pattern at a predetermined height, and is electrically connected to a predetermined portion of the translucent substrate in the first unit using an anisotropic conductive member. Or a method of manufacturing a semiconductor device according to 10; 前記第1ユニット及び前記第2ユニットにおいて、前記固体撮像素子と前記透光性基板との間の空間に通じる気道を設ける請求項9〜11いずれか一つに記載の半導体装置の製造方法。 12. The method of manufacturing a semiconductor device according to claim 9, wherein an air passage leading to a space between the solid-state imaging device and the translucent substrate is provided in the first unit and the second unit. 前記第2ユニットにおいて、前記回路基材は前記固体撮像素子を収める窪みを予め設ける請求項9〜12いずれか一つに記載の半導体装置の製造方法。 13. The method of manufacturing a semiconductor device according to claim 9, wherein in the second unit, the circuit base material is provided with a depression for accommodating the solid-state imaging element in advance. 前記外部端子領域は、はんだボールの形成によって、メイン回路基板への実装時にリフロー実装する請求項9〜13いずれか一つに記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 9, wherein the external terminal region is reflow-mounted when mounted on the main circuit board by forming solder balls.
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Cited By (1)

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Publication number Priority date Publication date Assignee Title
JP2007273822A (en) * 2006-03-31 2007-10-18 Matsushita Electric Ind Co Ltd Connection structure of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007273822A (en) * 2006-03-31 2007-10-18 Matsushita Electric Ind Co Ltd Connection structure of semiconductor device

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