JP2006080136A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the manufacturing method of a semiconductor device which suppresses a punch-through phenomenon. <P>SOLUTION: The manufacturing method of a semiconductor device comprises a process for preparing a silicon substrate; a channel area formation process for forming a gate electrode and in a silicon substrate and a source region and a drain region arranged at the both sides of the gate electrode, making as a channel area the area which is sandwiched between the source region and the drain region; a metal film formation process for forming a metal film for covering the source region and the drain region; a silicide process for forming a metal silicide layer in the surface of the source region and a drain region, by reacting a metal film and the source region and the drain region; and an implantation process for forming so that a punch-through stopper region where a conductivity type differs from the source region and the drain region may be adjoined to the source region and the drain region, by performing ion implantation to the channel region using the metal silicide layer as an ion-implantation mask. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device and a manufacturing method thereof that prevent punch-through by a simple process.

In the conventional MOSFET, after the source / drain region is formed by implanting the first conductivity type ions, the entire source / drain region is prevented in order to prevent the punch-through phenomenon that occurs as the gate length becomes shorter. The second conductivity type ions have been implanted (Halo implantation) (for example, Non-Patent Document 1).
Taua Nin: “Basics of Latest VLSI”, Maruzen, pp.53

  However, in the conventional technique, since ion implantation is performed on the entire source / drain region, the doping concentration (Na) is increased, and the junction capacitance Cj represented by the following formula (1) is increased.

ここで、Ｗｄｊ：空乏層幅、Ｎａ：ドーピング濃度、Ｖｊ：接合にかかる逆方向バイアス電圧、ψｂｉ：内蔵電圧、ε：誘電率、ｑ：電子の電荷量（１．６×１０^−１９クーロン）である。

Where Wdj: depletion layer width, Na: doping concentration, Vj: reverse bias voltage applied to the junction, ψbi: built-in voltage, ε: dielectric constant, q: electron charge (1.6 × 10 ⁻¹⁹ coulomb) It is.

  For this reason, with an increase in the junction capacitance Cj, problems such as a delay in switching speed of the MOSFET occurred.

  Accordingly, an object of the present invention is to provide a semiconductor device and a manufacturing method thereof in which the punch-through phenomenon is suppressed.

  The present invention provides a step of preparing a silicon substrate, a gate electrode, a source region and a drain region disposed on both sides of the gate electrode are formed on the silicon substrate, and a region sandwiched between the source region and the drain region is defined as a channel region. A channel region forming step, a metal film forming step for forming a metal film covering the source region and the drain region, a reaction between the metal film, the source region and the drain region, and a metal silicide on the surface of the source region and the drain region. A silicide process for forming a layer, and a metal silicide layer as an ion implantation mask are used to implant ions into the channel region, and a punch-through stopper region having a conductivity type different from that of the source region and the drain region is adjacent to the source region and the drain region. A method of manufacturing a semiconductor device, comprising: an injection step of forming the semiconductor device That.

  Further, the present invention includes a silicon substrate, a gate electrode provided on the silicon substrate, a source region and a drain region disposed on both sides of the gate electrode, a channel region sandwiched between the source region and the drain region, A metal silicide layer formed on the surface of the source region and the drain region, and a punch-through stopper region having a conductivity type different from that of the source region and the drain region formed in the channel region so as to be adjacent to the source region and the drain region It is also a semiconductor device characterized by including.

  As described above, by using the method for manufacturing a semiconductor device according to the present invention, it is possible to manufacture a semiconductor device in which the punch-through phenomenon is suppressed without increasing the number of manufacturing steps.

  FIG. 1 is a cross-sectional view of a MOSFET manufacturing process according to the present embodiment, and the manufacturing method includes the following processes 1 to 6.

  Step 1: As shown in FIG. 1A, a p-type silicon semiconductor substrate 1 is prepared, and an insulating region 2 made of silicon oxide and a well region 3 sandwiched between the insulating regions 2 are formed. The well region 3 is formed, for example, by diffusing a p-type impurity such as boron, and channel impurities such as boron that determine the threshold value of the transistor are introduced by an ion implantation method or the like (not shown).

  Step 2: As shown in FIG. 1B, a gate electrode 5 is formed on the well region 3 via a gate oxide film 4. The gate electrode 5 is made of, for example, polycrystalline silicon. Subsequently, n-type ions 6 are implanted using the gate electrode 5 as a mask for ion implantation. As a result, an n-type region 7 ′ that is an extension region having an LDD (Lightly Doped Drain) structure is formed.

  Step 3: As shown in FIG. 1C, a silicon nitride film is formed on the entire surface, followed by dry etching, and sidewalls 8 are formed from the remaining silicon nitride film. Subsequently, n-type ions 9 are implanted using the gate electrode 5 and the sidewalls 8 as a mask for ion implantation. Thereby, an n-type region 7 having an impurity concentration higher than that of the n-type region 7 'is formed. Source / drain regions having an LDD structure are formed from the n-type region 7 and the n-type region 7 '.

  Step 4: As shown in FIG. 1D, a metal film 10 of, for example, Co, Ti, Ni or the like is deposited on the entire surface. When Co is used for the metal film 10, the film thickness is about 70 mm.

Step 5: As shown in FIG. 1E, a heat treatment such as RTA (Rapid Thermal Anneal) is performed to form a silicide film 11 in a portion where the metal film 10 is in contact with silicon. Specifically, the first RTA is performed at a low temperature such as 430 ° C., and silicon and cobalt are eutectic to form CoSi. Subsequently, the metal film 10 that is not eutectic is removed by wet etching or the like, and further, a second RTA is performed at a high temperature such as 760 ° C. to eutectic silicon and cobalt to form CoSi. As a result, a silicide film 11 made of low-resistance CoSi ₂ is formed on the n-type region 7 and the gate electrode 5.

Note that the consumption of silicon atoms per metal atom due to silicidation is 3.64 atoms when CoSi ₂ is formed, 2.27 atoms when TiSi ₂ is formed, and NiSi ₂ is formed. In this case, it is 3.65 atoms. For example, when the thickness of the metal film 8 made of Co is 70 mm, the thickness of the silicide film 11 made of silicided CoSi ₂ is 254.8 mm.

Step 6: As shown in FIG. 1F, for example, p-type ions 12 such as boron are sandwiched between n-type regions 7 and 7 'in the channel region (p-type well region 3 from an oblique direction). Implant (Halo implantation) into the region, not shown.
Here, when boron ions are implanted at an implantation energy of 10 keV, the projected range Rp is about 400 中 で in silicon, about 243 中 で in CoSi, and about 534 中 で in SiN. Therefore, the implantation angle, implantation energy, film thickness of the sidewall 8 and the like are adjusted so that boron ions or the like passing through the sidewall 8 made of SiN form the punch-through stopper region 13 just in the channel region.

By performing step rotation implantation using an appropriate implantation angle / implantation energy and the like, the silicide film 11 has a heavy projection region Rp because the implanted region is heavy, and the silicon substrate 1 has almost no ions. Not injected.
On the other hand, immediately below the sidewall 8 and the gate electrode 5, the element in the implanted region is light, so the projection range Rp becomes deep, and the implanted ion species reaches the channel region to form the punch-through stopper region 13. The
Through the above steps, a MOSFET represented as a whole by 100 is completed.

  As described above, in the method of manufacturing the semiconductor device according to the present embodiment, the channel region is formed without increasing the number of manufacturing steps by performing the Halo implantation using the silicide film 11 formed in the normal manufacturing steps as the implantation mask. Thus, the punch-through stopper region (source-side punch-through stopper region and drain-side punch-through stopper region) 13 adjacent to the source / drain region can be formed.

2A is a cross-sectional view of the MOSFET according to the present embodiment, the whole being represented by 100, and FIG. 2B is a cross-sectional view of the MOSFET having the conventional structure, the whole being represented by 200. .
As shown in FIG. 2A, in the MOSFET 100, the punch-through stopper region 13 is formed only in the channel region sandwiched between the n-type regions 7 ′ constituting the source / drain regions. On the other hand, in the conventional MOSFET 200, the punch-through stopper region 14 is formed over a wide range so as to wrap around the source / drain regions (n-type regions 7, 7 ′).

FIG. 3A shows n-type and p-type ion concentration profiles implanted in the n-type region 7 of the MOSFET 100 according to the present embodiment, and FIG. 3B shows the n-type region 7 of the conventional MOSFET 200. FIG.
The concentration profiles shown in FIGS. 3 (a) and 3 (b) are profiles in the cross sections AA in FIG. 2 (a) and BB in FIG. 2 (b), respectively.
3A and 3B, a well region (P well) 3 is formed by p-type impurities, and an n-type region (N +) 7 is formed by n-type impurities. In FIG. 3B, the punch-through stopper region (Halo) 14 is formed, but is not formed in FIG. 3A.

As described above, in the MOSFET 100 according to the present embodiment, by forming the p-type punch-through stopper region 13 in the channel region, the punch-through phenomenon can be suppressed and the influence of the short channel effect can be reduced.
In particular, in the MOSFET 100, the amount of ions implanted to form the p-type punch-through stopper region 13 is reduced, and the value of Na in the above equation (1) is reduced. As a result, by using the structure of the present invention, it is possible to reduce the p-type impurity concentration (n-type impurity concentration in the case of PMOS) under the N + layer (P + layer in the case of PMOS) while suppressing the short channel effect. Therefore, the junction capacitance Cj can be reduced. The junction capacitance is a factor that determines the capacitance of resistance, capacitance, and inductance that determine product delay in a high-speed product. By reducing this, product delay can be suppressed, and the characteristics of MOSFET 100 such as switching speed are improved.

  Note that although the n-channel MOSFET 100 has been described in this embodiment, the present invention can also be applied to a p-channel MOSFET. In this case, n-type ions such as phosphorus are used as implantation ions for Halo implantation.

  Further, the source / drain region may be a normal source / drain structure instead of the LDD structure. In this case, the side wall need not be formed.

  Furthermore, the present invention can be applied to semiconductor devices other than MOSFETs such as MESFETs.

  FIG. 4 is a schematic diagram of a CMOS inverter in which MOSFETs according to the present embodiment are combined. The delay time of such a CMOS inverter can be expressed by the following formulas (formula 2) to (formula 4).

式（２）〜式（４）において、
τ ：ＰＭＯＳ＋ＮＭＯＳの遅延時間
τ_ｎ ：ＮＭＯＳの遅延時間
τ_ｐ ：ＰＭＯＳの遅延時間
Ｉ_ｎｓａｔ：ＮＭＯＳ飽和電流
Ｉ_ｐｓａｔ：ＰＭＯＳ飽和電流
Ｗ_ｎ ：ＮＭＯＳ活性領域幅
Ｗ_ｐ ：ＮＭＯＳ活性領域幅
Ｖ_ｄｄ ：電源電圧
を表す。

In Formula (2)-Formula (4),
τ: PMOS + NMOS delay time τ _n : NMOS delay time τ _p : PMOS delay time _Insat : NMOS saturation current I _psat : PMOS saturation current W _n : NMOS active region width W _p : NMOS active region width V _dd : Power supply Represents voltage.

Here, in NMOS and PMOS, the capacitance C in the above equation is
1) NMOS and PMOS drain junction capacitance: Cj
2) Wiring capacity: Cw
3) Gate capacity: Cg
4) Miller capacitance (capacitance due to overlap between gate and drain): has a component such as Cm.
In the CMOS inverter according to the present embodiment, the value of the junction capacitance Cj can be greatly reduced, and as a result, the delay time of the inverter can be shortened.

It is sectional drawing of the manufacturing process of MOSFET concerning this Embodiment. (A) It is sectional drawing of MOSFET concerning this Embodiment, (b) It is sectional drawing of conventional MOSFET. (A) Concentration profile of source / drain region of MOSFET according to this embodiment, (b) Concentration profile of source / drain region of conventional MOSFET. It is the schematic of the CMOS inverter using MOSFET concerning this Embodiment.

Explanation of symbols

1 silicon substrate, 2 insulating region, 3 well region, 4 gate oxide film, 5 gate electrode, 6 n-type ion, 7, 7 ′ n-type region, 8 sidewall, 9 n-type ion, 10 metal film, 11 silicide film , 12 p-type ions, 13, 14 punch-through stopper region, 100, 200 MOSFET.

Claims (7)

Preparing a silicon substrate;
Forming a gate electrode on the silicon substrate, a source region and a drain region disposed on both sides of the gate electrode, and a channel region forming step using a region sandwiched between the source region and the drain region as a channel region;
A metal film forming step of forming a metal film covering the source region and the drain region;
A silicide step of reacting the metal film with the source region and the drain region to form a metal silicide layer on the surfaces of the source region and the drain region;
Ions are implanted into the channel region using the metal silicide layer as an ion implantation mask so that a punch-through stopper region having a conductivity type different from that of the source region and the drain region is adjacent to the source region and the drain region. A method for manufacturing a semiconductor device, comprising: an implantation step for forming a semiconductor device. Forming the extension region in the silicon substrate by ion implantation using the gate electrode as an ion implantation mask;
Side walls are formed on both sides of the gate electrode, and ions are implanted to overlap the extension region using the gate electrode and the sidewall as an ion implantation mask, thereby forming the source region and the drain region of the LDD structure. The manufacturing method according to claim 1, wherein the manufacturing method is performed. The metal film forming step is a step of forming the metal film also on the gate electrode made of silicon,
3. The manufacturing method according to claim 1, wherein the silicide process is a process in which the metal film and the gate electrode are reacted to form the metal silicide layer on the gate electrode. The step of implanting ions from a direction inclined to the source region side from the normal direction of the silicon substrate to form a source side punch-through stopper region adjacent to the source region;
And a step of implanting ions from a direction inclined to the drain region side from a normal direction of the silicon substrate to form a drain side punch-through stopper region adjacent to the drain region. 4. The production method according to any one of 3 above. A silicon substrate;
A gate electrode provided on the silicon substrate;
A source region and a drain region disposed on both sides of the gate electrode;
A channel region sandwiched between the source region and the drain region;
A metal silicide layer formed on surfaces of the source region and the drain region;
A semiconductor device comprising: a punch-through stopper region having a conductivity type different from that of the source region and the drain region formed in the channel region so as to be adjacent to the source region and the drain region.   6. The semiconductor device according to claim 5, wherein the punch-through stopper region includes a source-side punch-through stopper region adjacent to the source region and a drain-side punch-through stopper region adjacent to the drain region.   6. The semiconductor device according to claim 5, wherein each of the source region and the drain region has an LDD structure including a low concentration region near the channel region and a high concentration region outside the channel region.

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