JP2006073700A

JP2006073700A - Semiconductor device and manufacturing method thereof

Info

Publication number: JP2006073700A
Application number: JP2004253967A
Authority: JP
Inventors: Akiyasu Hatashita; 晶保畑下; Hiroshi Tobimatsu; 博飛松
Original assignee: Renesas Technology Corp
Current assignee: Renesas Technology Corp
Priority date: 2004-09-01
Filing date: 2004-09-01
Publication date: 2006-03-16

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device not generating peeling of a film at the interface between FSG film and anti-reflection film, and also to provide a method of manufacturing the semiconductor device. <P>SOLUTION: The semiconductor manufacturing method comprises the processes of forming a metal film 2 on a substrate via an oxide film 1, forming an anti-reflection film 3 on the metal film, forming a resist pattern 4 on the anti-reflection film, etching the anti-reflection film and metal film using the resist pattern as a mask, forming a plurality of metal wires 5, forming an interlayer insulating film 6 formed of fluorine-added silicon oxide film (FSG film) on the metal wires and between the metal wires, executing heat treatment after formation of the interlayer insulating film, forming a TEOS film 7 on the FSG film after the heat treatment, flattening the upper surface by polishing the TEOS film, or TEOS film and FSG film with the CMP method, and forming a silicon oxide film 8 on the flattened surface. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

この発明は半導体装置、特にメタル配線間の層間絶縁膜としてフッ素添加の酸化シリコン膜（ＦＳＧ：Fluorinated Silicate Glass膜）を用いた半導体装置及びその製造方法に関するものである。 The present invention relates to a semiconductor device, and more particularly to a semiconductor device using a fluorine-added silicon oxide film (FSG: Fluorinated Silicate Glass film) as an interlayer insulating film between metal wirings and a method for manufacturing the same.

図４は、従来のこの種の半導体装置の製造方法を工程順に示した概略断面図である。
先ず、図４（ａ）に示すように、基板（図示せず）上に形成したシリコン酸化膜１０１上にアルミ（Al）などの金属からなるメタル膜１０２及び反射防止膜１０３を順次形成する。 FIG. 4 is a schematic cross-sectional view showing a conventional method of manufacturing this type of semiconductor device in the order of steps.
First, as shown in FIG. 4A, a metal film 102 made of a metal such as aluminum (Al) and an antireflection film 103 are sequentially formed on a silicon oxide film 101 formed on a substrate (not shown).

その後、反射防止膜１０３上の全面にレジスト膜を塗布し、周知の写真製版技術（フォトリソグラフィ）により、配線工程用レジストパターン１０４を形成する。
次に、図４（ｂ）に示すように、配線工程用レジストパターン１０４をマスクとして反射防止膜１０３及びメタル膜１０２をドライエッチングし、アルミ（Al）などの金属からなる複数個のメタル配線１０５を形成する。 Thereafter, a resist film is applied to the entire surface of the antireflection film 103, and a resist pattern 104 for wiring process is formed by a well-known photolithography technique (photolithography).
Next, as shown in FIG. 4B, the antireflection film 103 and the metal film 102 are dry-etched using the wiring process resist pattern 104 as a mask, and a plurality of metal wirings 105 made of a metal such as aluminum (Al). Form.

続いて、図４（ｃ）に示すように、配線工程用レジストパターン１０４を除去した後、メタル配線１０５間及びメタル配線１０５上に層間絶縁膜としてＦＳＧ膜１０６を形成する。この膜は、高密度プラズマＣＶＤにより、ガス種としてSiF₄、SiH₄、O₂、Ar等を用いて約４００度以上の高温で成膜されるものである。さらに、ＦＳＧ膜１０６上にプラズマ励起ＣＶＤによりＴＥＯＳ及びO₂ガスを用いて成膜されるＴＥＯＳ膜１０７を形成する。 Subsequently, as shown in FIG. 4C, after removing the wiring process resist pattern 104, an FSG film 106 is formed as an interlayer insulating film between the metal wirings 105 and on the metal wirings 105. This film is formed at a high temperature of about 400 ° C. or higher by high-density plasma CVD using SiF ₄ , SiH ₄ , O ₂ , Ar, or the like as a gas species. Further, a TEOS film 107 formed using TEOS and O ₂ gas is formed on the FSG film 106 by plasma-excited CVD.

その後、図４（ｄ）に示すように、ＣＭＰによってＴＥＯＳ膜１０７及びＦＳＧ膜１０６を研磨し、上面を平坦化した後、熱処理を施こし、その後、平坦面にシリコン酸化膜１０８を形成し、配線構造を得る。（例えば特許文献１参照）。 Thereafter, as shown in FIG. 4D, the TEOS film 107 and the FSG film 106 are polished by CMP, and the upper surface is flattened, and then heat treatment is performed. Thereafter, a silicon oxide film 108 is formed on the flat surface, A wiring structure is obtained. (For example, refer to Patent Document 1).

特開２００２−１００６２８号公報（段落００２０−００２６、図１）JP 2002-1000062 (paragraphs 0020-0026, FIG. 1)

従来の半導体装置の製造方法は以上のように構成され、ＦＳＧ膜１０６を高温で成膜するため、メタル膜１０２がダメージを受けるという問題点があった。
また、メタル膜１０２へのダメージを抑制するためにＦＳＧ膜１０６を低温で成膜すると、メタル膜１０２に与えるダメージは低減することができるが、ＦＳＧ膜１０６中のフッ素が過剰となり、ＦＳＧ膜１０６と反射防止膜１０３との界面で膜剥がれが発生するという問題点があった。 The conventional method for manufacturing a semiconductor device is configured as described above, and the FSG film 106 is formed at a high temperature, so that the metal film 102 is damaged.
Further, when the FSG film 106 is formed at a low temperature in order to suppress damage to the metal film 102, damage to the metal film 102 can be reduced, but fluorine in the FSG film 106 becomes excessive, and the FSG film 106. There is a problem that film peeling occurs at the interface between the antireflection film 103 and the antireflection film 103.

詳細に説明すると、ＦＳＧ膜には、膜中に遊離フッ素やＯＨ基が多く存在しており、反射防止膜には膜中にＯＨ基や、吸着したH₂Oが存在しているため、次工程のＴＥＯＳ成膜時に成膜中の温度上昇で発生するＦやH₂OがＦＳＧ膜と反射防止膜との界面で発泡し膜剥がれが発生するものと考えられる。 More specifically, the FSG film has a lot of free fluorine and OH groups in the film, and the antireflection film has OH groups and adsorbed H ₂ O in the film. It is considered that F or H ₂ O generated due to a temperature rise during film formation during TEOS film formation in the process is foamed at the interface between the FSG film and the antireflection film and film peeling occurs.

この発明は、上記のような問題点に対処するためになされたもので、ＦＳＧ膜と反射防止膜との界面で膜剥がれが生じない半導体装置及びその製造方法を提供することを目的とする。 The present invention has been made to address the above-described problems, and an object thereof is to provide a semiconductor device in which film peeling does not occur at the interface between the FSG film and the antireflection film and a method for manufacturing the same.

この発明に係る半導体装置の製造方法は、基板上に酸化膜を介してメタル膜を形成する工程と、上記メタル膜上に反射防止膜を形成する工程と、上記反射防止膜上にレジストパターンを形成し、このレジストパターンをマスクとして上記反射防止膜及びメタル膜をエッチングし、複数個のメタル配線を形成する工程と、上記メタル配線上及びメタル配線間にフッ素添加の酸化シリコン膜（ＦＳＧ膜）からなる層間絶縁膜を形成する工程と、上記層間絶縁膜の形成後に熱処理を行なう工程と、上記熱処理後に上記ＦＳＧ膜上にＴＥＯＳ膜を形成する工程と、ＣＭＰにより上記ＴＥＯＳ膜またはＴＥＯＳ膜及びＦＳＧ膜を研磨し上面を平坦化する工程と、平坦化された面にシリコン酸化膜を形成する工程とを含むものである。 A method of manufacturing a semiconductor device according to the present invention includes a step of forming a metal film on a substrate via an oxide film, a step of forming an antireflection film on the metal film, and a resist pattern on the antireflection film. Forming a plurality of metal wirings by etching the antireflection film and the metal film using the resist pattern as a mask, and a fluorine-added silicon oxide film (FSG film) on and between the metal wirings Forming an interlayer insulating film comprising: a step of performing a heat treatment after the formation of the interlayer insulating film; a step of forming a TEOS film on the FSG film after the heat treatment; and the TEOS film or the TEOS film and the FSG by CMP. The method includes a step of polishing the film and planarizing the upper surface, and a step of forming a silicon oxide film on the planarized surface.

この発明に係る半導体装置及びその製造方法は上記のように構成されており、ＦＳＧ膜の成膜後に熱処理を施こすことで、ＦＳＧ膜中の遊離ＦやH₂Oを膜外に放出しているため、ＦＳＧ膜と反射防止膜との界面における膜剥がれを効果的に抑制することができる。 The semiconductor device and the manufacturing method thereof according to the present invention are configured as described above, and by performing heat treatment after forming the FSG film, free F and H ₂ O in the FSG film are released to the outside of the film. Therefore, film peeling at the interface between the FSG film and the antireflection film can be effectively suppressed.

実施の形態１．
以下、この発明の実施の形態１を図にもとづいて説明する。図１は、実施の形態１による半導体装置の構成を示す概略断面図である。
基板（図示せず）上に形成したシリコン酸化膜１上にアルミ（Al）などの金属からなるメタル膜２及び反射防止膜３が順次形成されている。また、メタル膜２間及び反射防止膜３上には層間絶縁膜としてＦＳＧ膜６が形成され、その上にＴＥＯＳ膜７が形成された状態で上面が平坦化され、平坦面にシリコン酸化膜８が形成されている。 Embodiment 1 FIG.
Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic cross-sectional view showing the configuration of the semiconductor device according to the first embodiment.
A metal film 2 made of a metal such as aluminum (Al) and an antireflection film 3 are sequentially formed on a silicon oxide film 1 formed on a substrate (not shown). Further, an FSG film 6 is formed as an interlayer insulating film between the metal films 2 and on the antireflection film 3, and the upper surface is flattened with the TEOS film 7 formed thereon, and the silicon oxide film 8 is formed on the flat surface. Is formed.

図１に示す半導体装置の製造方法を図２に工程順に示している。即ち、図２（ａ）に示すように、基板（図示せず）上に形成したシリコン酸化膜１上にアルミ（Al）などの金属からなるメタル膜２及び反射防止膜３を順次形成する。 A method of manufacturing the semiconductor device shown in FIG. 1 is shown in the order of steps in FIG. That is, as shown in FIG. 2A, a metal film 2 made of a metal such as aluminum (Al) and an antireflection film 3 are sequentially formed on a silicon oxide film 1 formed on a substrate (not shown).

その後、反射防止膜３上の全面にレジスト膜を塗布し、周知の写真製版技術（フォトリソグラフィ）により、配線工程用レジストパターン４を形成する。
次に、図２（ｂ）に示すように、配線工程用レジストパターン４をマスクとして反射防止膜３及びメタル膜２をドライエッチングし、アルミ（Al）などの金属からなる複数個のメタル配線５を形成する。 Thereafter, a resist film is applied on the entire surface of the antireflection film 3, and a resist pattern 4 for wiring process is formed by a well-known photolithography technique (photolithography).
Next, as shown in FIG. 2B, the antireflection film 3 and the metal film 2 are dry-etched using the wiring process resist pattern 4 as a mask, and a plurality of metal wirings 5 made of metal such as aluminum (Al). Form.

続いて、図２（ｃ）に示すように、配線工程用レジストパターン４を除去した後、メタル配線５間及びメタル配線５上に層間絶縁膜としてＦＳＧ膜６を形成する。このＦＳＧ膜は、高密度プラズマＣＶＤにより、ガス種としてSiF₄、SiH₄、O₂、Ar等を用いて成膜されるものである。 Subsequently, as shown in FIG. 2C, after removing the wiring process resist pattern 4, an FSG film 6 is formed as an interlayer insulating film between the metal wirings 5 and on the metal wirings 5. This FSG film is formed by high-density plasma CVD using SiF ₄ , SiH ₄ , O ₂ , Ar, or the like as a gas species.

この次の工程で熱処理を施すのがこの発明の特徴である。熱処理の温度は、熱処理工程後にプラズマ励起ＣＶＤによりＴＥＯＳ及びO₂ガスを用いて成膜されるシリコン酸化膜が通常４００度程度にて処理されることから、それと同等もしくはそれ以上の温度として約４００度以上で処理される。雰囲気は特に定めることはなくN₂やH₂とする。 It is a feature of the present invention that heat treatment is performed in the next step. Since the silicon oxide film formed using TEOS and O ₂ gas by plasma-excited CVD is usually processed at about 400 ° C. after the heat treatment process, the temperature of the heat treatment is about 400 or so. Processed at more than degrees. The atmosphere is not particularly defined and is N ₂ or H ₂ .

次に、図２（ｄ）に示すように、ＦＳＧ膜６上の全面にプラズマ励起ＣＶＤによりＴＥＯＳ膜７を成膜する。その後、図２（ｅ）に示すように、ＣＭＰによってＴＥＯＳ膜７及びＦＳＧ膜６を研磨し、上面を平坦化した後、図２（ｆ）に示すように、平坦面にシリコン酸化膜８を上述したように約４００度で成膜し、配線構造を得る。
なお、図３に示すように、図２（ｄ）の状態からＴＥＯＳ膜７のみをＣＭＰによって研磨し、上面を平坦化した後、平坦面にシリコン酸化膜８を成膜する構成としても同様の効果が得られる。 Next, as shown in FIG. 2D, a TEOS film 7 is formed on the entire surface of the FSG film 6 by plasma enhanced CVD. Thereafter, as shown in FIG. 2E, the TEOS film 7 and the FSG film 6 are polished by CMP to flatten the upper surface, and then the silicon oxide film 8 is formed on the flat surface as shown in FIG. As described above, the film is formed at about 400 degrees to obtain a wiring structure.
As shown in FIG. 3, the same configuration may be adopted in which only the TEOS film 7 is polished by CMP from the state of FIG. 2D and the upper surface is flattened, and then the silicon oxide film 8 is formed on the flat surface. An effect is obtained.

この発明の実施の形態１による半導体装置の構成を示す概略断面図である。1 is a schematic sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention. 実施の形態１の製造方法を工程順に示す概略断面図である。It is a schematic sectional drawing which shows the manufacturing method of Embodiment 1 in order of a process. 実施の形態１の他の実施工程の例を示す概略断面図である。FIG. 10 is a schematic cross sectional view showing an example of another implementation process in the first embodiment. 従来の半導体装置の製造方法を工程順に示す概略断面図である。It is a schematic sectional drawing which shows the manufacturing method of the conventional semiconductor device in order of a process.

Explanation of symbols

１シリコン酸化膜、２メタル膜、３反射防止膜、４配線工程用レジストパターン、５メタル配線、６ＦＳＧ膜、７ＴＥＯＳ膜、８シリコン酸化膜。 DESCRIPTION OF SYMBOLS 1 Silicon oxide film, 2 Metal film, 3 Anti-reflective film, 4 Resist pattern for wiring processes, 5 Metal wiring, 6 FSG film, 7 TEOS film, 8 Silicon oxide film

Claims

Forming a metal film on the substrate via an oxide film, forming an antireflection film on the metal film, forming a resist pattern on the antireflection film, and using the resist pattern as a mask, the reflection Etching the prevention film and the metal film to form a plurality of metal wirings; and forming an interlayer insulating film made of a fluorine-added silicon oxide film (FSG film) on and between the metal wirings; A step of performing a heat treatment after the formation of the interlayer insulating film, a step of forming a TEOS film on the FSG film after the heat treatment, a step of polishing the TEOS film or the TEOS film and the FSG film by CMP, and planarizing an upper surface. And a step of forming a silicon oxide film on the planarized surface.

2. The semiconductor device according to claim 1, wherein the heat treatment is performed at a temperature equal to or higher than a film formation temperature of a TEOS film formed on the FSG film or a silicon oxide film formed on a flat surface. Manufacturing method.

A semiconductor device manufactured by the method according to claim 1.