JP2006066750A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the disconnection of an assisting gate when manufacturing a flash memory having an assisting-gate electrode in addition to its controlling electrode and its charge accumulating element. <P>SOLUTION: The manufacturing method of the flash memory includes a process for forming first electrodes at a predetermined space on the surface of a semiconductor substrate, a process for forming a second conductive film as the material film for a second electrode on the regions each of which is sandwiched between the pair of first electrodes, a process for so forming next an insulating film on the second conductive film as to form on this insulating film a third conductive film as the material film for a third electrode, a process for so forming next third electrodes by patterning the third conductive film as to pattern at this time the third conductive film under the condition of leaving its portions having a predetermined film thickness on the first electrodes, a process for removing next the insulating film by using as a mask the third electrodes and the residual third conductive films, and a process for so patterning further the second conductive film by using as a mask the third electrodes, the residual third conductive films and the insulating films as to etch at the same time completely the third conductive films left on the first electrodes. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device. More specifically, the present invention relates to a technique suitable as a method for manufacturing a semiconductor device having a nonvolatile memory.

  At present, along with the miniaturization and high integration of semiconductor devices, the miniaturization of non-volatile memories and the increase in capacity have progressed, and various non-volatile memory structures have been proposed in consideration of the writing speed and device reliability. .

  For example, in addition to a floating gate electrode (hereinafter referred to as “FG electrode”) and a control gate electrode (hereinafter referred to as “CG electrode”), an assist gate ( A nonvolatile memory having a third electrode (hereinafter referred to as “AG electrode”) called an “Assist Gate” has been devised. This non-volatile memory is configured by arranging a plurality of planar strip-shaped AG electrodes in parallel with each other via an oxide film on the main surface of a semiconductor substrate. A concave FG electrode is provided in a groove between adjacent AG electrodes via an insulating film covering the AG electrode. On the FG electrode, a CG electrode is provided via an interlayer film.

  In addition, for example, an auxiliary electrode is formed as a semiconductor device having a small variation in the write characteristics to the memory cell, and this is used for hot electron injection when writing to the memory cell. An auxiliary electrode has also been proposed (see, for example, Patent Document 1).

JP 2004-152977 A

  However, as the element becomes finer, the size of the FG electrode also becomes smaller. At this time, in order to ensure the writing / erasing speed as usual or to further increase the speed, the height of the FG electrode is increased to increase the contact area with the CG electrode, It is necessary to improve the coupling ratio.

  Here, the FG electrode and the CG electrode are separated by an insulating film. Therefore, when forming such a nonvolatile memory, after forming the CG electrode, the insulating film on the FG electrode is first removed using this as a mask. Thereafter, the FG electrode is patterned using the CG electrode as a mask.

  In general, a dry etching technique is used for etching the FG electrode. In order to increase the coupling ratio between the FG electrode and the CG electrode, it is necessary to increase the FG electrode. That is, the difference in height between the AG electrode and the FG electrode needs to be sufficiently large.

  When etching the CG electrode, an insulating film is provided on the AG electrode, and this insulating film serves as a protective film. However, as the FG electrode becomes higher, the difference in film thickness between the CG electrode and the AG electrode increases. For this reason, in order to avoid the etching of the AG electrode at the time of the CG electrode, it is necessary to make the insulating film provided at the interface of the CG electrode sufficiently thick.

  However, when the insulating film becomes thicker, on the contrary, it takes a long time to etch the insulating film. And when this etching time becomes long, the cap film formed on the AG electrode may be removed. In this case, when etching the FG electrode after removing the insulating film, the AG electrode may be etched and disconnected.

  Accordingly, the present invention provides a method for manufacturing a semiconductor device, which is an improved semiconductor device including a nonvolatile memory having an AG electrode as a third electrode so that the disconnection of the AG electrode during the manufacture can be suppressed. It is.

  According to a method of manufacturing a semiconductor device of the present invention, a first electrode forming step of forming a plurality of first electrodes made of a first conductive film on a surface of a semiconductor substrate at a predetermined interval, and sandwiched between the first electrodes A second conductive film forming step of forming a second conductive film for the second electrode on the region of the semiconductor substrate; and an insulating film forming step of forming an insulating film on the semiconductor substrate including the second conductive film. And a third conductive film forming step of forming a third conductive film for the third electrode on the insulating film, and the third conductive film at a predetermined interval in the direction intersecting the first electrode. A third electrode forming step of forming a third electrode by patterning so as to be disposed, and an insulating film for removing a part of the insulating film on the upper surface and side surface of the second conductive film using the third electrode as a mask Removing step and patterning the second conductive film with the third electrode as a mask. And comprises a second electrode forming step of forming a second electrode. The third electrode forming step is performed under a condition that the third conductive film disposed on the first electrode is left for a predetermined thickness, and the second electrode forming step is performed during the third electrode forming step. The third conductive film left on the first electrode is used as a protective film for the first electrode, and the third conductive film left on the first electrode is patterned together with the patterning of the second conductive film. This is performed under the condition of complete etching.

Alternatively, in the method of manufacturing a semiconductor device according to the present invention, a first electrode forming step of forming a plurality of first electrodes made of a first conductive film on a surface of a semiconductor substrate at a predetermined interval; A second conductive film forming step of forming a second conductive film for a second electrode on the sandwiched region of the semiconductor substrate; and an insulating film formation for forming an insulating film on the semiconductor substrate including the second conductive film A step of forming a third conductive film for forming a third conductive film for the third electrode on the insulating film; and a third gap between the third conductive film and the first electrode. A third electrode forming step of forming a third electrode by patterning so as to be disposed, and a protective film forming step of forming a protective film on a portion of the first electrode where the third electrode is not formed, The second conductive film is patterned using the third electrode and the protective film as a mask. And training, and the second electrode forming step of forming a second electrode,
A protective film removing step for removing the protective film.

In the present invention, in the etching for forming the third electrode, the third conductive film is not completely removed, and a predetermined film thickness is left on the first electrode. Therefore, the etching time for forming the third electrode can be shortened, and the insulating film that insulates the second electrode from the third electrode can be made thin.
In the etching for forming the second electrode, the etching can be performed using the third conductive film remaining on the first electrode and the third electrode as a mask. Therefore, when the second electrode is formed, the first electrode can be prevented from being etched, and disconnection of the first electrode can be prevented.

In the present invention, the organic film can be used as a protective film in the case where an organic film is formed on the first electrode instead of leaving the third conductive film. Even in this case, similarly, when the second electrode is formed, the first electrode can be prevented from being etched, and disconnection of the first electrode can be prevented.

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof is simplified or omitted.
In addition, in the following embodiments, when referring to the number of each element, quantity, quantity, range, etc., the reference is made unless otherwise specified or the number is clearly specified in principle. The number is not limited. Further, the structures described in the embodiments, steps in the method, and the like are not necessarily essential to the present invention unless otherwise specified or clearly specified in principle.

Embodiment 1 FIG.
In the first embodiment, a semiconductor device having an AND flash memory will be described.
1 and 2 are schematic views for explaining the structure of the flash memory of the semiconductor device according to the first embodiment of the present invention. FIG. 1 shows a top view and FIG. 2 shows a cross section. 2A, 2B, and 2C represent cross sections in the XX ′ direction, Y1-Y1 ′, and Y2-Y2 ′ direction in FIG. 1, respectively. In these drawings, for the sake of simplicity, the metal wiring is omitted.

  As shown in FIG. 1, the flash memory according to the first embodiment of the present invention includes an element isolation MOS (or assist gate electrode; hereinafter referred to as “AG electrode”) 2, a charge storage element (or floating gate electrode); Hereinafter, it has a control electrode (or control gate electrode; hereinafter referred to as “CG electrode”) 6.

  The AG electrodes 2 are band-like electrodes as viewed from above, and are arranged in parallel at predetermined intervals horizontally. Hereinafter, in this specification, in FIG. 1, the direction in which the AG electrode 2 is disposed is referred to as “X direction”, and the direction perpendicular thereto is referred to as “Y direction”.

  An extraction electrode is formed at one end of the AG electrode 2, and power of different voltages can be independently supplied to the AG electrode 2. Further, in the flash memory according to the first embodiment, when one AG electrode 2 has an extraction electrode on the left side in the X direction among the AG electrodes 2 adjacent to each other, the other AG electrode 2 is extracted on the right side. It has a structure having electrodes. The width of the thin part of the AG electrode 2 is, for example, about 90 nm, and the interval between the adjacent AG electrodes 2 is, for example, about 90 nm.

  In the Y direction, a plurality of CG electrodes 6 are arranged in parallel at a predetermined interval. As shown in FIG. 1, the CG electrode 6 is a belt-like electrode as viewed from the top. One end of the CG electrode 6 is connected to a word line so that predetermined power is supplied. Further, in the CG electrodes 6 adjacent to each other, when one electrode is connected to the word line in the upper part in the Y direction, the other electrode is connected to the word line in the lower part in the Y direction. The width of the thin portion of the CG electrode 6 is, for example, about 90 nm, and the interval between adjacent CG electrodes 6 is, for example, about 90 nm.

  Further, the FG electrode 4 is formed below the CG electrode 6 so as to overlap with the CG electrode 6 and between the adjacent AG electrodes 2. The width of the FG electrode 4 in the X direction is about 90 nm, for example, and the width in the Y direction is about 60 nm, for example.

Next, a cross-sectional structure of the flash memory will be described with reference to FIGS.
First, an insulating film 12 is formed on the substrate 10. An AG electrode 2 is formed on the insulating film 12. The AG electrode 2 is made of Poly-Si. The height of the AG electrode 2 is, for example, about 70 nm. An SiN film 14 is formed on the AG electrode 2 as a cap film. The film thickness of the SiN film 14 is about 70 nm. A SiO ₂ film 16 is formed on the side surface of the AG electrode 2.

The FG electrodes 4 are arranged in a convex shape on the substrate 10 between the adjacent AG electrodes 2 and at a position below the CG electrodes 6. The FG electrode 4 is made of Poly-Si. The FG electrode 4 is formed sufficiently higher than the AG electrode 2. Specifically, the height of the FG electrode 4 is, for example, about 300 nm. Further, the AG electrode 2 and the FG electrode 4 are insulated by the SiO ₂ film 16.

Further, an ONO film 18 is formed on the SiN film 14 and the FG electrode 4 of the AG electrode 2 formed in this way. ONO film 18 is composed of, in order from the AG electrode 2 and the FG electrode 4 side, the SiO ₂ film, a SiN film, film SiO ₂ film is formed by laminating, the thickness of each layer in turn, for example, about 5nm , About 10 nm, about 5 nm.

  On the ONO film 18, a strip-shaped CG electrode 6 is formed in the Y direction. The CG electrode 6 is formed by stacking a Poly-Si film 20 and a WSi film 22 formed thereon. The film thickness of the Poly-Si film 20 is, for example, about 300 nm in the thick part, that is, the part located on the AG electrode 2, and about 150 nm in the thin part, that is, the part located on the FG electrode 4. is there. The film thickness of the WSi film 22 is, for example, about 100 nm. Here, the height of the AG electrode 2 is about 70 nm and is sufficiently smaller than the FG electrode 4. That is, the contact area between the CG electrode 6 and the FG electrode 4 via the ONO film 18 is sufficiently large, and therefore a sufficiently large coupling ratio required for high-speed operation can be ensured. Yes.

  In the flash memory configured as described above, a portion indicated by a dotted line in FIG. 1 represents one unit of the memory cell. This memory cell controls the number of electrons stored in the FG electrode 4 to record four or more values such as “00” / “01” / “10” / “11” in one unit. A value storing operation can be performed. That is, the flash memory of this embodiment is an AND type flash memory. In addition, this flash memory is characterized by a structure employing the AG electrode 2, which prevents separation between the FG electrodes 4 by the AG electrode 2 and performs high-speed writing with a small channel area. Operation such as reading can be realized.

The operation of the flash memory according to this embodiment will be specifically described below.
In this flash memory, a source side is selected through a non-selected memory cell, and writing is performed by a source side hot electron injection method by constant charge injection.

  In the data write operation, a predetermined voltage (for example, about 1.5 V) is applied to the CG electrode 6 to which the selected memory cell is connected. The other CG electrodes 6 are set to 0V. On the other hand, a predetermined voltage (for example, about 1 V) is applied to the AG electrode 2 for forming the source of the selected memory cell. Thereby, an inversion layer for forming a source is formed on the main surface of the substrate 10 facing the AG electrode 2 to which a voltage is applied. In addition, a predetermined voltage (for example, about 7 V) higher than the source side is applied to the AG electrode 2 for forming the drain. Thereby, an inversion layer for forming a drain is formed on the main surface of the substrate 10 facing the AG electrode 2 to which a voltage is applied. The other AG electrode 2 is set to 0 V so that no inversion layer is formed on the substrate 10 in this portion. Thereby, the selected and non-selected memory cells can be separated.

  In this state, a write current flows from the drain side to the source side of the inversion layer generated in the substrate 10 of the selected memory cell. At this time, the charge accumulated in the inversion layer is converted into a certain channel current. As a result, the FG electrode 4 is efficiently injected through the insulating film. As a result, data is written to the selected memory at a high speed. On the other hand, since an inversion layer is not formed in a non-selected memory cell, no write current flows and data is not written.

In the read operation, a read current flows in a direction opposite to the write current.
Specifically, as in the case of writing, a predetermined voltage (for example, about 5 V) is applied to the AG electrode 2 for forming the source and drain of the selected memory cell. Thereby, inversion layers for forming a source and a drain are formed on the main surface of the substrate 10 facing the AG electrode 2 to which a voltage is applied. Further, the other AG electrode 2 is set to 0 V, so that the inversion layer is not formed on the substrate 10 in this portion, and the non-selected memory cells are separated. A predetermined voltage (for example, about 2 to 5 V) is applied to the CG electrode 6 to which the selected memory cell is connected. At this time, the threshold voltage of the selected memory cell differs depending on the accumulation state of the FG electrode 4. Therefore, the data of the memory cell can be determined based on the current flowing between the source / drain of the selected memory cell.

  When erasing data, a tunnel current from the FG electrode to the substrate is caused to flow by setting the CG electrode 4 to be selected as a negative voltage. That is, a predetermined negative voltage is applied to the CG electrode 6 to be selected, while a positive voltage is applied to the substrate 10. The AG electrode 2 is set to 0 V so that no inversion layer is formed. Thereby, the data in the memory cells of the FG electrode 4 can be erased collectively.

  The operation of the flash memory of the embodiment has been briefly described with respect to memory selection, non-selection method and writing, reading, etc. In actual operation, in addition to the AG electrode 2 and the CG electrode 6, for example, A global bit line and wiring that makes the voltage of this global bit line independent are provided, so that voltage can be supplied to the inversion layer of the substrate so that more appropriate data can be written and read. It can be done.

FIG. 3 is a flowchart for illustrating the manufacturing method of the flash memory according to the first embodiment of the present invention. 4 to 11 are schematic diagrams for explaining states in the manufacturing process of the flash memory according to the first embodiment. Moreover, in each figure of FIGS. 4-11, (a), (b), (c) represents the cross section of X1-X1 ', Y1-Y1', Y2-Y2 'in FIG. 1, respectively.
The flash memory manufacturing method according to the first embodiment of the present invention will be described below with reference to FIGS.

First, as shown in FIG. 4, an insulating film 12 is formed on a Si substrate 10, and an AG electrode Poly-Si film, which is a material film of the AG electrode 2, is formed thereon (step S2). Here, for example, the film is formed with a film thickness of about 70 nm by a CVD (Chemical Vapor Deposition) method. Thereafter, a SiN film 14 is deposited as a cap film on the poly-Si film for AG electrode (step S4), and a SiO ₂ film 30 is further deposited thereon (step S6). Here, the SiN film 14 is formed to a film thickness of, for example, about 70 nm by the CVD method, and the SiO ₂ film 30 is formed to a film thickness of about 200 nm by the LPCVD method.

Thereafter, a resist mask having a pattern corresponding to the AG electrode 2 is formed, and the SiO ₂ film 30 and the SiN film 14 are etched (step S8). Further, using the SiO ₂ film 30 and the SiN film 14 as a mask, the AG electrode Poly-Si film is etched to be processed into the shape of the AG electrode 2 (step S10). Next, the SiO ₂ film 16 is formed at least on the side surface of the AG electrode 2 by thermal oxidation (step S12). Here, the film thickness of the SiO ₂ film 16 is about 30 nm, for example.

As shown in FIG. 5, an FG electrode poly-Si film 4a, which is a material film of the FG electrode 4, is deposited on the entire surface of the substrate in this state (step S14). Thereafter, the entire surface is etched back until at least the surface of the SiO ₂ film 30 is exposed (step S16).

Next, as shown in FIG. 6, the SiO ₂ film 30 on the AG electrode 2 is removed (step S18). Here, only the SiO ₂ film 30 can be selectively removed by first performing dry etching and then performing treatment using hydrofluoric acid.

In this state, an ONO film 18a is formed on the entire surface of the substrate as shown in FIG. 7 (step S20). Here, the ONO film 18 is a laminated film composed of three layers of a SiO ₂ film, a SiN film, and a SiO ₂ film, and is formed by sequentially depositing these by the CVD method. The thickness of each film is, for example, about 5 nm, about 10 nm, and about 5 nm, respectively, so that the total thickness is about 20 nm.

  Next, as shown in FIG. 8, the Poly-Si film 20a for CG electrode which becomes the material film of the CG electrode 6 is formed on the ONO film 18a (Step S22). Further, the WSi film 22a is formed thereon. (Step S24). Here, the Poly-Si film 20a for CG electrode is formed by, for example, a CVD method so as to have a film thickness of about 150 nm, and the WSi film 22a is formed by, for example, a film thickness of about 100 nm. .

Next, in order to form the hard mask 32 at the time of etching, a SiO ₂ film is formed (step S26), and a resist mask 34 is formed thereon (step S28). Here, the resist mask 34 has a pattern corresponding to the CG electrode 6. The resist mask 34 is formed by applying a resist on the SiO ₂ film and performing predetermined processes such as lithography and development processing. Thereafter, the SiO ₂ film is etched using the resist mask 34 as a mask. As a result, as shown in FIG. 9, a hard mask 32 made of a SiO ₂ film is formed on the WSi film 22a (step S30).

  Next, using this hard mask 32, the WSi film 22a is etched (step S32), and the CG electrode poly-Si film 20a is further etched (step S34). Here, of the portion of the CG electrode Poly-Si film 20a that is finally unnecessary, the portion located on the FG electrode 4 is etched so as to be completely removed, and this portion for the CG electrode is used. The etching is finished when the Poly-Si film 20a is completely etched. That is, the film thickness of the CG electrode Poly-Si film 20a that is completely etched is the film thickness of the portion located above the FG electrode Poly-Si film 4a. Therefore, the hard mask 32 is formed in the portion where the CG electrode Poly-Si film 20a is thick, that is, in the portion where the FG electrode Poly-Si film 4a is not formed and located on the AG electrode 2. Even a portion which is not left is not completely etched and remains. Therefore, as shown in FIG. 10C, the AG electrode 2 in which the FG electrode Poly-Si film 4a is not deposited among the unnecessary portion of the Poly-Si film 20a where the CG electrode 6 is not formed is finally formed. The upper part is not completely etched and remains. The remaining film thickness is about 100 nm, for example. In this way, the thick etching portion of the CG electrode Poly-Si film 20a is stopped at this stage and is not completely removed. Therefore, even when the ONO film 18 is thin as in this embodiment, it is possible to prevent the ONO film 18 from being etched on the FG poly-Si film 4a that has been etched first.

  Next, as shown in FIG. 11, the ONO film 18 is removed (step S36). Here, the ONO film 18 on the FG electrode Poly-Si film 4a other than the part surface where the FG electrode 4 is actually formed is removed. That is, in this etching, the WSi film 22a and the Poly-Si film 20a for CG electrode remaining on the AG electrode 2 are used as a mask, and the ONO film 18 on the FG electrode Poly-Si film 4a that does not overlap with the CG electrode 6 is used. Is removed. Therefore, the etching of the SiN film 14 on the AG electrode 2 can be suppressed when the ONO film 18 is removed.

  Next, the poly-Si film 4a for FG electrode is etched (step S38). Here, the ONO film 18 is removed, and the FG electrode-use Poly-Si film 4a where the surface is exposed is etched. Thereby, the Poly-Si film 4 a for FG electrode that does not overlap with the CG electrode 6 is etched and patterned into the shape of the FG electrode 4.

At the same time, unnecessary portions of the CG electrode poly-Si film 20a remaining on the AG electrode 4 are also removed. Here, the etching of the CG electrode Poly-Si film 20a is completed before the etching of the FG electrode Poly-Si film 4a, and the SiN film 14 on the AG electrode 2 is exposed. However, the CG electrode Poly-Si film 20a is left on the SiN film 14 so that the difference in etching film thickness between the FG electrode Poly-Si film 4a and the CG electrode Poly-Si film 20a is reduced. Thereby, in etching, the time during which the SiN film 14 is exposed to the etching solution can be shortened. Moreover, the etching selectivity between Poly-Si and SiN is relatively large. Therefore, exposure of the surface of the AG electrode 2 due to the progress of etching of the SiN film 14 can be suppressed. Therefore, the etching of the FG electrode 4 can be reliably completed while suppressing the disconnection of the AG electrode 2 during the etching of the FG electrode 4.
As described above, the flash memory as shown in FIG. 1 is formed.

  As described above, in the first embodiment, when the FG electrode poly-Si film 4a is etched, the CG electrode poly-Si film 20a remains on the AG electrode 2 with a certain thickness. It has become. Therefore, in the etching of the FG electrode Poly-Si film 4a, the SiN film 14 on the AG electrode 2 is protected for a certain period of time by the remaining CG electrode Poly-Si film 20a. Thereby, it is possible to suppress the SiN film 14 from being exposed to the etching for a long time during this etching, and to suppress the etching to the AG electrode 2 by completely etching the SiN film 14. Can do. Therefore, even when manufacturing a flash memory in which the height of the FG electrode 4 with respect to the AG electrode 2 is sufficiently high and the contact area between the CG electrode 6 and the FG electrode 4 is large, disconnection of the AG electrode 2 can be suppressed. And a flash memory with good device characteristics can be manufactured.

  In the embodiment, the CG electrode Poly-Si film 20a is left as a protective film for the AG electrode 2 (or SiN film 14) during etching for forming the FG electrode. explained. However, the present invention is not limited to this. The poly-Si film 20a for the CG electrode is completely etched, and then a groove (on the AG electrode 2 formed between the FG electrodes 4 as an etching mask ( That is, in the first embodiment, an organic film may be deposited on a portion where the CG Poly-Si film 20a remains, and this may be used as a protective film to prevent disconnection of the AG electrode 2. An example of such an organic film is a resist.

  Further, the case where the ONO film 18 is used as the insulating film between the FG electrode 4 and the CG electrode 6 has been described. The ONO film 18 is a relatively thin film and is an effective film that reliably insulates the FG electrode 4 and the CG electrode 6. However, in the present invention, the insulating film is not limited to this, and other insulating films may be used as long as they have similar functions.

In the above description, the present invention has been described as a semiconductor device having a flash memory. However, for example, the present invention can also be understood as an invention of a semiconductor device manufactured by the semiconductor device manufacturing method of the present invention as follows.
That is, this semiconductor device has two or more first, second, and third electrodes, respectively. The first electrode is formed on the surface of the semiconductor substrate, and the third electrode is formed in a direction substantially perpendicular to the first electrode. The second electrode is sandwiched between the first electrodes adjacent to each other among the first electrodes, and is formed at a position where the plurality of third electrodes overlap with each other. The second and third electrodes are insulated by an insulating film. Since the semiconductor device is manufactured by the method of manufacturing a semiconductor device according to the present invention, the insulating film that insulates the second and third electrodes is relatively thin. Even when the insulating film is thin, Is in a state in which disconnection due to etching is suppressed.

  In this embodiment, for example, the AG electrode 2, the FG electrode 4, and the CG electrode 6 correspond to the “first electrode”, “second electrode”, and “third electrode” of the present invention, respectively. Further, for example, the poly-Si film for AG electrode in this embodiment corresponds to the “first conductive film” of the present invention, and the poly-Si film 4a for FG electrode corresponds to the “second conductive film” of the present invention. The CG electrode poly-Si film 20a and the WSi film 22a correspond to the "third conductive film" of the present invention. The ONO film 18 corresponds to, for example, the “insulating film” of the present invention, and the SiN film 14 corresponds to, for example, the “cap film” of the present invention.

  Further, for example, in this embodiment, by executing steps S2 to S10, the “first electrode forming step” of the present invention is executed, and by executing steps S14 to S18, “second conductive film formation” is performed. Step S20 is executed, and step S20 is executed to execute “insulating film forming step”. Steps S22 to S24 are executed to execute “third conductive film forming step”, and steps S32 to S34 are executed. By executing, the “third electrode forming step” is executed, by executing step S36, the “insulating film removing step” is executed, and by executing step S38, the “second electrode forming step is executed. The

It is a top schematic diagram for demonstrating the structure of the flash memory of the semiconductor device in Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the structure of the flash memory of the semiconductor device in Embodiment 1 of this invention. It is a flowchart for demonstrating the manufacturing method of the flash memory of the semiconductor device in Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the state in the manufacture process of the semiconductor device in Embodiment 1 of this invention.

Explanation of symbols

2 AG electrode, 4 FG electrode, 4a Poly-Si film for FG electrode, 6 CG electrode, 10 substrate, 12 insulating film, 14 SiN film, 16, 16a SiO ₂ film, 18 ONO film, 20 Poly-Si film, 20a Poly-Si film for CG electrode, 22, 22a WSi film, 30 SiO ₂ film, 32 hard mask, 34 resist mask.

Claims (4)

A first electrode forming step of forming a plurality of first electrodes made of a first conductive film on a semiconductor substrate surface at a predetermined interval;
A second conductive film forming step of forming a second conductive film for the second electrode on the region of the semiconductor substrate sandwiched between the first electrodes;
An insulating film forming step of forming an insulating film on the semiconductor substrate including the second conductive film;
Forming a third conductive film on the insulating film to form a third conductive film for a third electrode;
A third electrode forming step of patterning the third conductive film so as to be arranged at a predetermined interval in a direction crossing the first electrode, thereby forming a third electrode;
Using the third electrode as a mask, an insulating film removing step of removing a part of the insulating film on the upper surface and side surfaces of the second conductive film;
Using the third electrode as a mask, patterning the second conductive film to form a second electrode; and
With
The third electrode forming step is performed under a condition that leaves the third conductive film disposed on the first electrode by a predetermined thickness.
In the second electrode forming step, the third conductive film left on the first electrode in the third electrode forming step is used as a protective film for the first electrode, and together with the patterning of the second conductive film A method of manufacturing a semiconductor device, wherein the third conductive film left on the first electrode is completely etched. A first electrode forming step of forming a plurality of first electrodes made of a first conductive film on a semiconductor substrate surface at a predetermined interval;
A second conductive film forming step of forming a second conductive film for the second electrode on a region of the semiconductor substrate sandwiched between the first electrodes;
An insulating film forming step of forming an insulating film on the semiconductor substrate including the second conductive film;
Forming a third conductive film on the insulating film to form a third conductive film for a third electrode;
A third electrode forming step of patterning the third conductive film so as to be arranged at a predetermined interval in a direction crossing the first electrode, thereby forming a third electrode;
A protective film forming step of forming a protective film on a portion of the first electrode where the third electrode is not formed;
A second electrode forming step of forming a second electrode by patterning a second conductive film using the third electrode and the protective film as a mask;
A protective film removing step for removing the protective film;
A method for manufacturing a semiconductor device, comprising: The insulating film forming step includes
A first silicon oxide film forming step of forming a first silicon oxide film;
A silicon nitride film forming step of forming a silicon nitride film on the first silicon oxide film;
A second silicon oxide film forming step of forming a second silicon oxide film on the silicon nitride film;
The method for manufacturing a semiconductor device according to claim 1, further comprising:   4. The method of manufacturing a semiconductor device according to claim 1, wherein an SiN film is formed on the surface of the first electrode as a cap film. 5.

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