JP4379082B2 - Nonvolatile semiconductor memory device and method of manufacturing nonvolatile semiconductor memory device - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the nonvolatile semiconductor memory device, and is particularly suitable when applied to a split gate type flash memory cell.

  In a conventional split gate flash memory cell, over-etching of an interlayer insulating film is performed to form a bit contact (borderless contact formation). Therefore, in order to prevent the oxide film for element isolation from being over-etched due to mask displacement, the bit contact is formed after covering the entire surface of the semiconductor substrate on which the control gate electrode is formed with a silicon nitride film. Has been done.

For example, Patent Document 1 discloses a method for accurately controlling the film thickness without forming the gate insulating film more than necessary by forming a silicon nitride film on the floating gate electrode.
JP 2001-7227 A

  However, in the conventional split gate type flash memory cell, since a silicon nitride film is formed on the floating gate electrode, charges are exchanged between the floating gate electrode and the silicon nitride film. For this reason, there has been a problem that charges accumulated in the floating gate electrode due to temperature and voltage stress are extracted to the silicon nitride film and cause data retention failure.

  Accordingly, an object of the present invention is to provide a non-volatile semiconductor memory device and a non-volatile semiconductor memory capable of stably storing charges in a floating gate electrode while preventing over-etching of an element isolation oxide film It is to provide a method for manufacturing a device.

In order to solve the above-described problem, according to a nonvolatile semiconductor memory device of one embodiment of the present invention, a floating gate electrode formed over a semiconductor substrate with a first gate insulating film interposed therebetween, and the floating gate electrode An oxide layer formed on the semiconductor substrate, a control gate electrode formed on the semiconductor substrate via a second gate insulating film, and disposed on the floating gate electrode so as to have an end on the floating gate electrode; A source layer disposed on the floating gate electrode side, a drain layer disposed on the control gate electrode side formed on the semiconductor substrate, and a film formed on the semiconductor substrate on which the control gate electrode is formed. a nitride film, the nitride film on the floating gate electrode exposed from the control gate electrode is removed A first opening, an interlayer insulating film formed on the nitride film provided with the first opening, and a second opening formed in the interlayer insulating film and the nitride film and exposing a surface of the drain layer And a wiring layer connected to the drain layer through the second opening and formed on the interlayer insulating film.

  Thus, the nitride film on the floating gate electrode exposed from the control gate electrode can be removed while leaving the nitride film on the element isolation oxide film. For this reason, even when a nitride film for forming a borderless contact is formed, it is possible to prevent exchange of charges between the floating gate electrode and the nitride film, and to stably accumulate charges in the floating gate electrode. Is possible. As a result, even when the interlayer insulating film is over-etched to form the bit contact, it is possible to prevent the element isolation oxide film from being etched and reduce data retention defects.

  In addition, according to the nonvolatile semiconductor memory device of one embodiment of the present invention, the floating gate electrode formed over the semiconductor substrate via the first gate insulating film, the oxide layer formed over the floating gate electrode, A control gate electrode formed on the semiconductor substrate with a second gate insulating film interposed therebetween and disposed on the floating gate electrode so as to have an end portion on the floating gate electrode; A source layer disposed on the semiconductor substrate, the drain layer disposed on the control gate electrode side, a nitride film formed on the semiconductor substrate on which the control gate electrode is formed, and the control gate The nitride film on the floating gate electrode exposed from the electrode and on the source layer is removed. An opening, an interlayer insulating film formed on the nitride film provided with the first opening, and a second opening formed in the interlayer insulating film and the nitride film and exposing the surface of the drain layer; And a wiring layer connected to the drain layer through the second opening and formed on the interlayer insulating film.

  By using an exposure mask for ion implantation for forming the source layer, the nitride film on the floating gate electrode exposed from the control gate electrode is removed while leaving the nitride film on the element isolation oxide film. can do. Therefore, it is possible to form a nitride film for forming a borderless contact without generating a new exposure mask and preventing exchange of electric charges between the floating gate electrode and the nitride film. As a result, it is possible to prevent the element isolation oxide film from being etched while suppressing an increase in cost and to reduce data retention defects.

In addition, according to the nonvolatile semiconductor memory device of one embodiment of the present invention, the floating gate electrode formed over the semiconductor substrate via the first gate insulating film, the oxide layer formed over the floating gate electrode, A control gate electrode formed on the semiconductor substrate with a second gate insulating film interposed therebetween and disposed on the floating gate electrode so as to have an end portion on the floating gate electrode; A source layer disposed on the semiconductor substrate and disposed on a side of the control gate electrode; sidewall spacers provided on sidewalls of the control gate electrode and the floating gate electrode; and the drain A first silicide layer formed on a surface of the layer and the floating layer A second silicide layer formed on the surface of the control gate electrode at a predetermined interval from an end of the control gate electrode disposed on the gate electrode, and a semiconductor substrate on which the control gate electrode is formed. The nitride film is formed on the floating gate electrode, which is formed on the nitride film so that the arrangement position of the end portion corresponds to the end portion of the second silicide layer and is exposed from the control gate electrode. A first opening, an interlayer insulating film formed on the nitride film provided with the first opening, a second insulating film formed on the interlayer insulating film and the nitride film, and exposing a surface of the first silicide layer; An opening, and a wiring layer connected to the first silicide layer through the second opening and formed on the interlayer insulating film.

  Thus, by using an exposure mask for preventing the silicide layer from being formed on the source layer, the nitride on the floating gate electrode exposed from the control gate electrode while leaving the nitride film on the element isolation oxide film is left. The film can be removed. Therefore, it is possible to form a nitride film for forming a borderless contact without generating a new exposure mask and preventing exchange of electric charges between the floating gate electrode and the nitride film. As a result, it is possible to prevent the element isolation oxide film from being etched while suppressing an increase in cost and to reduce data retention defects.

In addition, according to the nonvolatile semiconductor memory device of one aspect of the present invention, the floating gate electrode exposed from the control gate electrode is covered and provided between the nitride film and the control gate electrode. And an oxide film.
Thus, the nitride film can be formed after the oxide film is formed on the floating gate electrode, and the nitride film can be prevented from coming into contact with the floating gate electrode, thereby reducing data retention failure.

  In addition, according to the method for manufacturing a nonvolatile semiconductor memory device of one embodiment of the present invention, the first gate insulating film is formed on the semiconductor substrate, and the floating gate electrode having an oxide layer formed thereon is provided on the first gate insulating film. A step of forming on one gate insulating film; a step of forming a second gate insulating film on the semiconductor substrate; and one end disposed on the floating gate electrode, and the semiconductor substrate through the second gate insulating film Forming a control gate electrode on which the other end is disposed, forming a source layer on the semiconductor substrate on the floating gate electrode side, and forming a drain layer on the semiconductor substrate on the control gate electrode side A step of forming a nitride film on the semiconductor substrate on which the control gate electrode is formed; and an exposure from the control gate electrode Removing the nitride film on the floating gate electrode; forming an interlayer insulating film on the nitride film; and forming an opening in the interlayer insulating film and the nitride film to expose a surface of the drain layer. And a step of forming a wiring layer connected to the drain layer through the opening on the interlayer insulating film.

Thereby, by selectively etching the nitride film for borderless contact formation, it is possible to prevent the exchange of charges between the floating gate electrode and the nitride film, while suppressing the complication of the manufacturing process, Etching of the element isolation oxide film due to mask displacement can be prevented and data retention failure can be reduced.
Further, according to the method for manufacturing a nonvolatile semiconductor memory device according to one aspect of the present invention, the step of removing the nitride film uses the exposure mask for ion implantation for forming the source layer. Forming a resist pattern thereon; and etching the nitride film using the resist pattern as a mask to form an opening from which the nitride film has been removed.

As a result, it is possible to prevent the exchange of charges between the nitride film for forming the borderless contact and the floating gate electrode without newly creating an exposure mask, while suppressing the cost increase, and the element due to the mask displacement It is possible to prevent the separation oxide film from being etched and reduce data retention defects.
In addition, according to the method for manufacturing a nonvolatile semiconductor memory device of one embodiment of the present invention, the first gate insulating film is formed on the semiconductor substrate, and the floating gate electrode having an oxide layer formed thereon is provided on the first gate insulating film. A step of forming on one gate insulating film; a step of forming a second gate insulating film on the semiconductor substrate; and one end disposed on the floating gate electrode, and the semiconductor substrate through the second gate insulating film Forming a control gate electrode having the other end disposed thereon; forming a source layer on the semiconductor substrate on the floating gate electrode side; and sidewall spacers on side walls of the control gate electrode and the floating gate electrode Forming a drain layer on the semiconductor substrate on the control gate electrode side; and Forming an oxide film covering the source layer so as to cover the control gate electrode, forming a silicide-forming metal film on the semiconductor substrate on which the oxide film is formed, and forming the silicide Reacting a metal film with silicon to form a silicide layer on the drain layer and the control gate electrode; forming a nitride film on the semiconductor substrate on which the control gate electrode is formed; Removing the nitride film on the floating gate electrode exposed from the control gate electrode; forming an interlayer insulating film on the nitride film; and an opening exposing the surface of the silicide layer on the drain layer. A step of forming the interlayer insulating film and the nitride film, and the silicon on the drain layer through the opening; The wiring layer connected to the de-layer, characterized in that it comprises a step of forming on the interlayer insulating film.

Thereby, by selectively etching the nitride film for forming the borderless contact, it is possible to prevent the exchange of electric charges between the floating gate electrode and the nitride film, while suppressing the complication of the manufacturing process, Etching of the element isolation oxide film due to mask displacement can be prevented and data retention failure can be reduced.
Further, according to the method for manufacturing the nonvolatile semiconductor memory device of one embodiment of the present invention, the step of removing the nitride film uses the exposure mask for forming an oxide film that covers the source layer. Forming a resist pattern thereon; and etching the nitride film using the resist pattern as a mask to form an opening from which the nitride film has been removed.

  As a result, it is possible to prevent the exchange of charges between the nitride film for forming the borderless contact and the floating gate electrode without newly creating an exposure mask, while suppressing the cost increase, and the element due to the mask displacement It is possible to prevent the separation oxide film from being etched and reduce data retention defects.

A nonvolatile semiconductor memory device and a manufacturing method thereof according to embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a plan view showing a schematic configuration of a nonvolatile semiconductor memory device according to an embodiment of the present invention.
In FIG. 1, a floating gate electrode 4 is provided in a memory cell, and a drain layer 10a and a source layer 10b are provided on both sides of the floating gate electrode 4, respectively.

  The memory cells provided with the floating gate electrode 4 are arranged in a matrix, the drain layer 10a is shared by a pair of memory cells adjacent in the column direction, and the pair of memory cells sharing the drain layer 10a is , Separated in the row direction via STI (Shallow Trench Isolation) 2. Note that LOCOS (Local Oxidation of Silicon) may be used instead of STI (Shallow Trench Isolation).

A source layer 10b extending in the row direction is disposed on the opposite side of the drain layer 10a across the floating gate electrode 4, and the source layer 10b is shared by two rows of memory cells adjacent in the column direction. ing.
Further, the word lines WL1 to WL6 are arranged in the row direction so that the end portions are on the floating gate electrode 4. In the column direction, bit lines BL1 to BL7 are arranged so as to cross the word lines WL1 to WL6, and the bit lines BL1 to BL7 are connected to the drain layer 10a via the bit contacts H1. ing. A source wiring Vss is arranged in the column direction, and the source wiring Vss is connected to each source layer 10b via a source contact H2.

2A is a cross-sectional view taken along the line AA in FIG. 1, FIG. 2B is a cross-sectional view taken along the line BB in FIG. 1, and FIG. It is sectional drawing cut | disconnected by CC line.
In FIG. 2, an STI 2 that divides the drain layer 10 a in the row direction (BB direction) is embedded in the semiconductor substrate 1. In addition, as a material of the semiconductor substrate 1, Si, Ge, SiGe, GaAs, InP, GaP, GaN, SiC etc. can be used, for example.

  A floating gate electrode 4 is formed on the semiconductor substrate 1 in which the STI 2 is embedded via a gate insulating film 3, and an oxide layer 5 is formed on the floating gate electrode 4. A control gate electrode 7 is formed with one end disposed on the floating gate electrode 4 via the oxide layer 5 and the other end disposed on the semiconductor substrate 1 via the gate insulating film 6. The control gate electrodes 7 arranged in the same row are respectively connected to the common word lines WL1 to WL6 in FIG. Side wall spacers 8a and 8b are formed on the side walls of the control gate electrode 7 and the floating gate electrode 4, respectively.

  A drain layer 10a is formed in the semiconductor substrate 1 on the control gate electrode 7 side, and is shared by the floating gate electrodes 4 arranged opposite to each other in the semiconductor substrate 1 on the floating gate electrode 4 side. Thus, the source layer 10b is formed. A silicide layer 11a is formed on the drain layer 10a, and a silicide layer 11b is formed on the control gate electrode 7 with a predetermined distance from the end of the control gate electrode 7 on the oxide layer 5. Yes.

  Here, a silicide layer is not formed on the drain layer 10b, and a silicide layer 11b is formed on the control gate electrode 7 with a predetermined distance from the end of the control gate electrode 7 on the oxide layer 5. By forming, even when the end portion of the control gate electrode 7 is disposed on the floating gate electrode 4, the silicide layer 11b on the control gate electrode 7 and the floating gate electrode 4 are prevented from being short-circuited, It is possible to reduce the resistance of the control gate electrode 11b and the drain layer 9a.

  A silicon nitride film 13 is formed on the entire surface of the semiconductor substrate 1 on which the control gate electrode 7 is formed via a silicon oxide film 12. The film thickness of the silicon nitride film 13 can be about 500 mm, for example. The silicon nitride film 13 has an opening 13 ′ from which the silicon nitride film 13 on the floating gate electrode 4 exposed from the control gate electrode 7 is removed.

  An interlayer insulating film 14 is formed on the silicon nitride film 13 in which the opening 13 ′ is formed, and a bit line BL is formed on the interlayer insulating film 14 in the column direction (AA direction). Yes. The interlayer insulating film 14 is filled with a plug 15 connected to the silicide layer 11a on the drain layer 10a, and the bit line BL is connected to the silicide layer 11a via the plug 15.

  Here, even when the silicon nitride film 13 for forming the borderless contact is formed by removing the silicon nitride film 13 on the floating gate electrode 4 exposed from the control gate electrode 7, the floating gate electrode 5 and the silicon nitride film It is possible to prevent the exchange of charges with 13 and to stably accumulate charges in the floating gate electrode 4. For this reason, even when the interlayer insulating film 14 is over-etched to form the bit contact H1, it is possible to prevent the STI 2 from being etched due to the mask displacement and to reduce the data retention failure. .

Further, the silicon nitride film 13 on the floating gate electrode 4 exposed from the control gate electrode 7 may be removed, and the silicon nitride film 13 on the source layer 10b may be removed.
Thus, the silicon nitride film 13 is left on the STI 2 by using an exposure mask for ion implantation for forming the source layer 10b or an exposure mask for preventing the silicide layer from being formed on the source layer 10b. The nitride film on the floating gate electrode 4 exposed from the control gate electrode 7 can be removed as it is. Therefore, it is possible to form the silicon nitride film 13 for forming the borderless contact without generating a new exposure mask and preventing the exchange of charges between the floating gate electrode 4 and the silicon nitride film 13. And cost increase can be suppressed.

  When the erase operation of the memory cell of FIG. 2 is performed, the source wiring Vss of FIG. 1 is held at the ground potential, the source layers 10b of all the memory cells are held at the ground potential, and all the bit lines BL1 to BL7 are held. Is held at the ground potential, and the drain layers 10a of all the memory cells are held at the ground potential. Further, a high voltage of 11 to 13V is applied to the selected word lines WL1 to WL6, and a high voltage of 11 to 13V is applied to the control gate electrode 7 of the memory cell connected to the selected word lines WL1 to WL6. At the same time, the unselected word lines WL1 to WL6 are held at the ground potential, and the control gate electrodes 7 of the memory cells connected to the unselected word lines WL1 to WL6 are held at the ground potential.

  When a high voltage of 11 to 13 V is applied to the control gate electrode 7 while the drain layer 10 a and the source layer 10 b are held at the ground potential, the control gate electrode 7 and the floating gate electrode 4 are not connected to each other. A high electric field is applied, and an FN (Fowler Nordheim) tunnel current flows between the control gate electrode 7 and the floating gate electrode 4. For this reason, the electrons of the floating gate electrode 4 are extracted to the control gate electrode 7 side, and the data stored in the selected memory cell can be erased.

  Here, as shown in FIG. 2A, the oxide layer 5 on the floating gate electrode 4 is formed in an elliptical shape, and the end of the floating gate electrode 4 is sharpened to form the end of the floating gate electrode 4. The electric field can be concentrated. For this reason, electrons of the floating gate electrode 4 can be efficiently extracted to the control gate electrode 7 side, the number of rewrites can be increased, and the life of the split gate flash memory can be improved.

In the split gate flash memory, all memory cells connected to the selected word lines WL1 to WL6 are collectively erased to select all the word lines WL1 to WL6 simultaneously. Thus, the erase operation of all the memory cells can be performed collectively.
2 is applied, a high voltage of 10 to 11 V is applied to the source wiring Vss of FIG. 1, and a high voltage of 10 to 11 V is applied to the source layer 10b of all the memory cells. . In addition, a voltage of 1V is applied to the selected bit lines BL1 to BL7, a voltage of 1V is applied to the drain layer 10a of the memory cell connected to the selected bit lines BL1 to BL7, and an unselected bit A voltage of 2V is applied to the lines BL1 to BL7, and a voltage of 2V is applied to the drain layer 10a of the memory cell connected to the non-selected bit lines BL1 to BL7. Further, a low voltage of 1.8 V is applied to the selected word lines WL1 to WL6, and a low voltage of 1.8 V is applied to the control gate electrode 7 of the memory cell connected to the selected word lines WL1 to WL6. At the same time, the unselected word lines WL1 to WL6 are held at the ground potential, and the control gate electrodes 7 of the memory cells connected to the unselected word lines WL1 to WL6 are held at the ground potential.

  If the threshold value Vth of the channel region under the control gate electrode 7 is 0.5 V, for example, the channel region of the memory cell connected to the selected word lines WL1 to WL6 is in an inverted state. . For this reason, when 1 V is applied to the drain layer 10a via the selected bit lines BL1 to BL7, the memory cells connected to the selected word lines WL1 to WL6 are transferred from the source layer 10b to the drain layer. Current flows toward 10a. On the other hand, when the threshold value Vth of the channel region under the control gate electrode 7 is 0.5 V, for example, the channel regions of the memory cells connected to the non-selected word lines WL1 to WL6 are in a depleted state. In the memory cells connected to the selected word lines WL1 to WL6, no current flows from the source layer 10b to the drain layer 10a.

  Since a high voltage of 10 to 11 V is applied to the source layer 10b, the potential of the floating gate electrode 4 is raised by capacitive coupling between the source layer 10b and the floating gate electrode 4, and the channel region and the floating gate electrode 4 generates a high electric field. Therefore, when a current flows from the source layer 10 b toward the drain layer 10 a, electrons flowing through the channel region are accelerated by a high electric field to become hot electrons, and electrons are injected into the floating gate electrode 4. As a result, charges are accumulated in the memory cells connected to the selected word lines WL1 to WL6 and the bit lines BL1 to BL7, and data can be written to the selected memory cells.

Here, since the silicon nitride film 13 on the floating gate electrode 4 exposed from the control gate electrode 7 is removed, charges can be stably accumulated in the floating gate electrode 4, and temperature, voltage stress, etc. Even in such a case, it is possible to prevent the charge accumulated in the floating gate electrode 4 from disappearing.
Next, when the read operation of the memory cell of FIG. 2 is performed, the source wiring Vss of FIG. 1 is held at the ground potential, and the source layers 10b of all the memory cells are held at the ground potential. In addition, a low voltage of 1V is applied to the selected bit lines BL1 to BL7, a low voltage of 1V is applied to the drain layer 10a of the memory cell connected to the selected bit lines BL1 to BL7, and no selection is performed. The bit lines BL1 to BL7 are held at the ground potential, and the drain layers 10a of the memory cells connected to the non-selected bit lines BL1 to BL7 are held at the ground potential. Further, a voltage of 3 ± 0.3V is applied to the selected word lines WL1 to WL6, and a voltage of 3 ± 0.3V is applied to the control gate electrode 7 of the memory cell connected to the selected word lines WL1 to WL6. And the non-selected word lines WL1 to WL6 are held at the ground potential, and the control gate electrodes 7 of the memory cells connected to the non-selected word lines WL1 to WL6 are held at the ground potential.

  When the memory cell selected by the bit lines BL1 to BL7 and the word lines WL1 to WL6 is in the erased state, the electrons of the floating gate electrode 4 of the selected memory cell are extracted. For this reason, the channel region under the floating gate electrode 4 of the memory cell in the erased state is on, and is selected when 1 V is applied to the drain layer 10a via the selected bit lines BL1 to BL7. In the memory cells connected to the word lines WL1 to WL6, a current flows from the drain layer 10a toward the source layer 10b.

  On the other hand, when the memory cell selected by the bit lines BL1 to BL7 and the word lines WL1 to WL6 is in the write state, electrons are accumulated in the floating gate electrode 4 of the selected memory cell. For this reason, the channel region under the floating gate electrode 4 of the memory cell in the write state is turned off, and even when 1 V is applied to the drain layer 10a via the selected bit lines BL1 to BL7, the selection is performed. In the memory cells connected to the word lines WL1 to WL6, the current flowing from the drain layer 10a toward the source layer 10b is smaller than that in the erased state. For this reason, the erase state and the write state of the selected memory cell can be determined by detecting the magnitude of the current flowing through the selected memory cell with the sense amplifier.

  Further, the non-selected word lines WL1 to WL6 are held at the ground potential, and the control gate electrode 7 of the memory cell connected to the non-selected word lines WL1 to WL6 is held at the ground potential. The lower channel region can be turned off. For this reason, even when a non-selected memory cell is in an over-erased state, it can be prevented that the non-selected memory cell is always in a conductive state, and a read operation of the selected memory cell is performed normally. Is possible.

3 to 5 are cross-sectional views illustrating a method for manufacturing a nonvolatile semiconductor memory device according to an embodiment of the present invention.
In FIG. 3A, a gate insulating film 3 is formed on the semiconductor substrate 1 by thermal oxidation. Then, a polycrystalline silicon layer 4 ′ is laminated on the semiconductor substrate 1 on which the gate insulating film 3 is formed by a method such as CVD, and an antioxidant film 21 is formed on the polycrystalline silicon layer 4 ′. As the antioxidant film 21, for example, a silicon nitride film or the like can be used. Next, as shown in FIG. 3B, the antioxidant film 21 is patterned using a photolithography technique and an etching technique. Thus, an opening 21 ′ is formed in the antioxidant film 21.

Next, as shown in FIG. 3C, the polycrystalline silicon layer 4 ′ is thermally oxidized using the antioxidant film 21 having the opening 21 ′ formed as a mask, thereby forming an upper portion of the polycrystalline silicon layer 4 ′. The oxide layer 5 is selectively formed.
Next, as shown in FIG. 3D, the antioxidant film 21 on the polycrystalline silicon layer 4 'is removed. Then, the polycrystalline silicon layer 4 ′ is etched using the oxide layer 5 selectively formed on the polycrystalline silicon layer 4 ′ as a mask, thereby forming the floating gate electrode 4 having the oxide layer 5 on the upper side.

  Next, as shown in FIG. 4A, a gate insulating film 6 is formed on the semiconductor substrate 1 by thermal oxidation. Then, a polycrystalline silicon layer is laminated on the semiconductor substrate 1 on which the gate insulating film 6 is formed by a method such as CVD. Then, by patterning the polycrystalline silicon layer using a photolithography technique and an etching technique, one end is disposed on the floating gate electrode 4 via the oxide layer 5 and on the semiconductor substrate 1 via the gate insulating film 6. A control gate electrode 7 having the other end is formed.

  Next, as shown in FIG. 4B, a photoresist layer R1 that covers the semiconductor substrate 1 on the control gate electrode 7 side is formed by using a photolithography technique. Then, ion implantation P1 is performed on the semiconductor substrate 1 using the photoresist layer R1, the floating gate electrode 4 and the control gate electrode 7 as a mask, thereby forming the source layer 10b in the semiconductor substrate 1 on the floating gate electrode 4 side.

  Next, as shown in FIG. 4C, the photoresist layer R1 is removed. Then, a silicon oxide film is laminated on the semiconductor substrate 1 on which the source layer 10b is formed by a method such as CVD. Then, by performing anisotropic etching of the silicon oxide film laminated on the semiconductor substrate 1, side wall spacers 8a and 8b are formed on the side walls of the control gate electrode 7 and the floating gate electrode 4, respectively.

  Next, as shown in FIG. 5A, a photoresist layer R2 that covers the semiconductor substrate 1 on the floating gate electrode 4 side is formed by using a photolithography technique. Then, ion implantation P2 is performed on the semiconductor substrate 1 using the photoresist layer R2, the floating gate electrode 4, the control gate electrode 7 and the side wall spacers 8a and 8b as a mask, whereby a drain is formed in the semiconductor substrate 1 on the control gate electrode 7 side. Layer 10a is formed.

Next, as shown in FIG. 5B, the photoresist layer R2 is removed. Then, a silicon oxide film 22 is laminated on the semiconductor substrate 1 on which the drain layer 10a is formed by a method such as CVD. Then, by using a photolithography technique and an etching technique, the silicon oxide film 22 is patterned so that the source layer 10b is covered so that the end portion is on the control gate electrode 7. Next, FIG. As shown, a silicide forming metal film 23 is laminated on the entire surface of the semiconductor substrate 1 on which the silicon oxide film 22 is formed by a method such as sputtering. As the silicide forming metal film 23, for example, a Ti film, a Co film, a W film, a Mo film, a Ni film, a Pt film, or the like can be used.

Next, as shown in FIG. 6A, the silicide forming metal film 23 is reacted with Si by heat treatment to form silicide layers 11a and 11b on the drain layer 10a and the control gate electrode 7, respectively.
Thus, the silicide layer 11b can be formed at a predetermined interval from the end of the control gate electrode 7 on the oxide layer 5, and the drain layer 10a can be formed without forming a silicide layer on the source layer 10b. The silicide layer 11 can be formed thereon. Therefore, even when the end portion of the control gate electrode 7 is disposed on the floating gate electrode 4, the silicide layer 11b on the control gate electrode 7 and the floating gate electrode 4 are prevented from being short-circuited, and the control gate The resistance of the electrode 7 and the drain layer 10a can be reduced.

Next, as shown in FIG. 6B, a silicon oxide film 12 is formed on the entire surface of the semiconductor substrate 1 on which the silicide layers 11a and 11b are formed, for example, by a method such as low pressure CVD using TEOS. . The film thickness of the silicon oxide film 12 can be about 500 mm, for example.
Then, a silicon nitride film 13 is formed on the silicon oxide film 12 by a method such as plasma CVD. The film thickness of the silicon nitride film 13 can be about 500 mm, for example.

Next, as shown in FIG. 6C, the silicon nitride film 13 on the floating gate electrode 4 exposed from the control gate electrode 7 is patterned by patterning the silicon nitride film 13 using a photolithography technique and an etching technique. The removed opening 13 ′ is formed.
Here, when a resist pattern for forming the opening 13 ′ is formed on the silicon nitride film 13, an exposure mask for forming the photoresist layer R 1 in FIG. 4B can be used. Alternatively, an exposure mask for forming the silicon oxide film 22 in FIG. 5B can be used. When the exposure mask for forming the silicon oxide film 22 shown in FIG. 5B is used, the positive resist is changed to the negative resist.

Then, as shown in FIG. 2, an interlayer insulating film 14 is deposited on the silicon nitride film 13 in which the opening 13 'is formed by a method such as CVD. Then, an opening exposing the surface of the silicide layer 11a is formed in the interlayer insulating film 14, the silicon nitride film 13, and the silicon oxide film 12.
Then, for example, by depositing tungsten on the interlayer insulating film 14 in which the opening is formed by a method such as sputtering, and performing etch back of tungsten, the interlayer insulating film 14, the silicon nitride film 13, and the silicon oxide film 12 are processed. The plug 15 embedded in the opening formed in is formed.

Then, for example, Al is deposited on the interlayer insulating film 14 in which the plug 15 is embedded by a method such as sputtering, and the Al is patterned by using a photolithography technique and an etching technique, thereby being connected to the plug 15. Bit lines BL are formed on the interlayer insulating film 14.
Here, by forming the silicon nitride film 13 for forming the borderless contact, the bit contact H1 can be formed in a state where the STI 2 beside the drain layer 10a is covered with the silicon nitride film 13. For this reason, even when a mask shift occurs when the bit contact H1 is formed, the etching of the STI2 due to the overetching of the interlayer insulating film 14 can be prevented.

1 is a plan view showing a schematic configuration of a nonvolatile semiconductor memory device according to an embodiment. 1 is a cross-sectional view showing a schematic configuration of a nonvolatile semiconductor memory device according to an embodiment. Sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on one Embodiment. Sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on one Embodiment. Sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on one Embodiment. Sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on one Embodiment.

Explanation of symbols

WL1 to WL6 Word line, BL1 to BL7, BL bit line Vss source wiring, H1 bit contact, H2 source contact, 1 semiconductor substrate, 2 STI, 3, 6 gate insulating film, 4 floating gate electrode, 5 oxide layer, 7 control Gate electrode, 8a, 8b Side wall spacer, 10a drain layer, 10b source layer, 11a, 11b silicide layer, 12 silicon oxide film, 13 silicon nitride film, 14 interlayer insulation film, 15 plug, 4 ′ polycrystalline silicon layer, 21 Antioxidation film, 13 ', 21' opening, P1, P2 ion implantation, R1, R2 photoresist

Claims (8)

A floating gate electrode formed on the semiconductor substrate via the first gate insulating film;
An oxide layer formed on the floating gate electrode;
A control gate electrode formed on the semiconductor substrate via a second gate insulating film and disposed so as to have an end on the floating gate electrode;
A source layer formed on the semiconductor substrate and disposed on the floating gate electrode side;
A drain layer formed on the semiconductor substrate and disposed on the control gate electrode side;
A nitride film formed on the semiconductor substrate on which the control gate electrode is formed;
A first opening from which the nitride film on the floating gate electrode exposed from the control gate electrode is removed;
An interlayer insulating film formed on the nitride film provided with the first opening;
A second layer formed on the interlayer insulating film and the nitride film and exposing a surface of the drain layer;
An opening,
A nonvolatile semiconductor memory device comprising: a wiring layer connected to the drain layer through the second opening and formed on the interlayer insulating film. A floating gate electrode formed on the semiconductor substrate via the first gate insulating film;
An oxide layer formed on the floating gate electrode;
A control gate electrode formed on the semiconductor substrate via a second gate insulating film and disposed so as to have an end on the floating gate electrode;
A source layer formed on the semiconductor substrate and disposed on the floating gate electrode side;
A drain layer formed on the semiconductor substrate and disposed on the control gate electrode side;
A nitride film formed on the semiconductor substrate on which the control gate electrode is formed;
A first opening from which the nitride film on the floating gate electrode exposed from the control gate electrode and the source layer is removed;
An interlayer insulating film formed on the nitride film provided with the first opening;
A second layer formed on the interlayer insulating film and the nitride film and exposing a surface of the drain layer;
An opening,
A nonvolatile semiconductor memory device comprising: a wiring layer connected to the drain layer through the second opening and formed on the interlayer insulating film. A floating gate electrode formed on the semiconductor substrate via the first gate insulating film;
An oxide layer formed on the floating gate electrode;
A control gate electrode formed on the semiconductor substrate via a second gate insulating film and disposed so as to have an end on the floating gate electrode;
A source layer formed on the semiconductor substrate and disposed on the floating gate electrode side;
A drain layer formed on the semiconductor substrate and disposed on the control gate electrode side;
Side wall spacers provided on the side walls of the control gate electrode and the floating gate electrode,
A first silicide layer formed on a surface of the drain layer;
A second silicide layer formed on the surface of the control gate electrode at a predetermined interval from an end of the control gate electrode disposed on the floating gate electrode;
A nitride film formed on the semiconductor substrate on which the control gate electrode is formed;
A first opening disposed on the floating gate electrode, which is formed in the nitride film such that an end position corresponds to an end of the second silicide layer, and is exposed from the control gate electrode;
An interlayer insulating film formed on the nitride film provided with the first opening;
A second opening formed in the interlayer insulating film and the nitride film and exposing a surface of the first silicide layer;
A nonvolatile semiconductor memory device comprising: a wiring layer connected to the first silicide layer through the second opening and formed on the interlayer insulating film. 4. The semiconductor device according to claim 1, further comprising an oxide film provided between the nitride film and the control gate electrode so as to cover the floating gate electrode exposed from the control gate electrode. The nonvolatile semiconductor memory device according to claim 1. Forming a first gate insulating film on the semiconductor substrate;
Forming a floating gate electrode provided with an oxide layer on the first gate insulating film;
Forming a second gate insulating film on the semiconductor substrate;
Forming a control gate electrode having one end disposed on the floating gate electrode and the other end disposed on the semiconductor substrate via the second gate insulating film;
Forming a source layer on the semiconductor substrate on the floating gate electrode side;
Forming a drain layer on the semiconductor substrate on the control gate electrode side;
Forming a nitride film on the semiconductor substrate on which the control gate electrode is formed;
Removing the nitride film on the floating gate electrode exposed from the control gate electrode;
Forming an interlayer insulating film on the nitride film;
Forming an opening exposing the surface of the drain layer in the interlayer insulating film and the nitride film;
Forming a wiring layer connected to the drain layer through the opening on the interlayer insulating film. A method for manufacturing a nonvolatile semiconductor memory device, comprising: The step of removing the nitride film includes
Forming a resist pattern on the nitride film using an exposure mask for ion implantation for forming the source layer;
6. The method of manufacturing a nonvolatile semiconductor memory device according to claim 5, further comprising: forming an opening from which the nitride film is removed by etching the nitride film using the resist pattern as a mask. . Forming a first gate insulating film on the semiconductor substrate;
Forming a floating gate electrode provided with an oxide layer on the first gate insulating film;
Forming a second gate insulating film on the semiconductor substrate;
Forming a control gate electrode having one end disposed on the floating gate electrode and the other end disposed on the semiconductor substrate via the second gate insulating film;
Forming a source layer on the semiconductor substrate on the floating gate electrode side;
Forming sidewall spacers on sidewalls of the control gate electrode and the floating gate electrode;
Forming a drain layer on the semiconductor substrate on the control gate electrode side;
Forming an oxide film covering the source layer such that an end thereof is on the control gate electrode;
Forming a silicide-forming metal film on the semiconductor substrate on which the oxide film is formed;
Forming a silicide layer on the drain layer and the control gate electrode by reacting the silicide-forming metal film with silicon; and
Forming a nitride film on the semiconductor substrate on which the control gate electrode is formed;
Removing the nitride film on the floating gate electrode exposed from the control gate electrode;
Forming an interlayer insulating film on the nitride film;
Forming an opening in the interlayer insulating film and the nitride film to expose the surface of the silicide layer on the drain layer;
Forming a wiring layer connected to the silicide layer on the drain layer through the opening on the interlayer insulating film. A method for manufacturing a nonvolatile semiconductor memory device, comprising: The step of removing the nitride film includes
Forming a resist pattern on the nitride film using an exposure mask for forming an oxide film covering the source layer;
8. The method of manufacturing a nonvolatile semiconductor memory device according to claim 7, further comprising: forming an opening from which the nitride film is removed by etching the nitride film using the resist pattern as a mask. .

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