JP2001085543A - Split gate memory cell - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory cell which is free of excessive erasure, has a large cell current for reading operation to easily make an accurate data read, has no variance in characteristics, and can be made fine. SOLUTION: A split gate memory cell 1 has an N type source region 3 and a drain region 4 formed on a single-crystal silicon substrates 9, a channel region 5 sandwiched between the regions 3 and 4, a floating gate electrode 6 formed on the channel region 5 across a floating gate insulating film 10, a control gate electrode 7 formed on the channel region 5 across a control gate insulating film 11, and an erasure gate electrode 8 formed on a projection part 6a of the floating gate electrode 6 across an erasure gate insulating film 15. The floating gate electrode 6 is formed aligning itself with the control gate 7, a drain region 4 with the control gate electrode 7, and a source region 3 with the floating gate electrode 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a split gate type memory cell, and more particularly to a split gate type memory cell having three gate electrodes (a floating gate electrode, a control gate electrode, and an erase gate electrode). .

[0002]

2. Description of the Related Art Conventionally, US Pat.
11/40), US Pat. No. 5,045,488 (H01L 21/265), and discloses a semiconductor memory (flash EEPROM (Electrically Erasable and Programmable) using a split gate type memory cell (split gate type transistor) disclosed in US Pat.
ble Read Only Memory)) is known.

[0003] The present applicant also discloses Japanese Patent Application Laid-Open No. 9-32115.
No. 6, JP-A-11-31801 (H01L 21/82)
74 H01L 29/788 H01L 29 / 792H01L 27/115), which proposes a technique which is an improvement of the invention described in the aforementioned US Patent Publication. This split gate type memory cell has a two-layer structure of polysilicon formed on a silicon substrate. A floating gate electrode is formed by first-layer polysilicon, and a control gate electrode is formed by second-layer polysilicon. Have been. Then, an end of the control gate electrode is arranged on the channel region of the silicon substrate, and a select gate electrode is formed by the end of the control gate electrode.

In this split gate type memory cell, in a write operation for writing data to the memory cell, a high electric field is generated between the channel region and the floating gate electrode,
The high electric field accelerates electrons in the channel region into hot electrons, injects the hot electrons into the floating gate electrode, and accumulates charges in the floating gate electrode. Therefore, charge is accumulated in the floating gate electrode of the memory cell in a data writing state, and the channel region immediately below the floating gate electrode is in an off state.
Further, no charge is accumulated in the floating gate electrode of the memory cell in the data erased state, and the channel region immediately below the floating gate electrode is in the ON state.

In a read operation for reading data from a memory cell, a memory cell in a written state is more likely to be connected to a source region than a memory cell in an erased state due to the on / off state of the channel region. By utilizing the fact that the cell current flowing to the cell decreases, the difference in the cell current is detected by a sense amplifier,
It is determined whether the memory cell is in a write state or an erase state.

In an erasing operation for erasing data in a memory cell, a voltage of more than ten volts is applied to a control gate electrode,
A high electric field is generated between the floating gate electrode and the control gate electrode, and the high electric field causes a Fowler-Nordheim tunneling current (Fowl) from the control gate electrode to the floating gate electrode.
er-Nordheim Tunnel Current (hereinafter referred to as “FN tunnel current”) is caused to flow, and electrons in the floating gate electrode are extracted to the control gate electrode side. As a result, the threshold voltage of the memory cell decreases. At this time, even if the charge is excessively extracted from the floating gate electrode (even if a phenomenon called “excessive erasure” occurs), the channel region can be controlled to be turned off by the selection gate electrode. The problem that the memory cell remains in the erased state and cannot be put into the written state due to excessive erasure can be avoided.

[0007]

In recent years, with the miniaturization of memory cells, the cell current at the time of the above-mentioned read operation has become smaller, and the difference between the cell currents between the written state and the erased state has also become smaller. . Therefore, in order to accurately read data, it is required to increase the sensitivity of the sense amplifier that detects the magnitude of the cell current.However, there is a limit to increasing the sensitivity of the sense amplifier, and the memory becomes increasingly smaller. It has become difficult to handle cells.

Therefore, in order to increase the cell current, the thickness of the gate insulating film formed between the control gate electrode and the channel region may be reduced. However, when the gate insulating film between the control gate electrode and the channel region is thinned, a high electric field is applied between the control gate electrode and the channel region when a voltage of more than ten volts is applied to the control gate electrode during an erase operation. This causes a problem that the gate insulating film is broken by the high electric field.

By the way, conventionally, a split gate type memory cell has been proposed in which an electrode dedicated to erasing (erase electrode) is added to the above-mentioned split gate type memory cell. This memory cell has a three-layer structure of polysilicon formed on a silicon substrate, a floating gate electrode is formed by first-layer polysilicon, and a control gate electrode is formed by second-layer polysilicon. Since the erase gate electrode is formed by the polysilicon of the layer,
Generally, it is called a split gate memory cell using three-layer polysilicon, a three-layer polysilicon flash memory cell, a three-layer memory cell, or the like. In this memory cell (hereinafter, referred to as “three-layer type memory cell”), the erase gate electrode is arranged so as to partially cover the floating gate electrode. The structure and operation of the three-layer type memory cell are described in various documents (for example, Flash Memory Technology Handbook (published in 1993, issuance office: Science Forum Co., Ltd.)) and are well known.

In the following description, the above-mentioned split gate memory cell is referred to as a "two-layer memory cell" in order to distinguish it from a three-layer memory cell. The write operation and read operation of the three-layer memory cell are the same as those of the two-layer memory cell. In the erasing operation of the three-layer type memory cell, a voltage of more than ten volts is applied to the erasing gate electrode to generate a high electric field between the floating gate electrode and the erasing gate electrode. An FN tunnel current flows from the electrode to the floating gate electrode, and electrons in the floating gate electrode are drawn to the erase gate electrode side.

As described above, in the three-layer type memory cell, since the erase gate electrode is provided in addition to the control gate electrode,
A gate insulating film formed between the control gate electrode and the channel region (hereinafter, referred to as "control gate insulating film")
And the gate insulating film between the erase gate electrode and the floating gate electrode (hereinafter, referred to as “erased gate insulating film”) can be independent and separate insulating films. Therefore, even when the control gate insulating film is sufficiently thin to increase the cell current during the read operation, when a voltage of more than ten volts is applied to the erase gate electrode during the erase operation, the control gate electrode and the No high electric field is generated between the region and the region, and the problem that the thin control gate insulating film is broken by the high electric field can be avoided. In addition, by making the erase gate insulating film sufficiently thick, the charge accumulation time in the floating gate electrode is lengthened, and electrons are erroneously injected from the erase gate electrode into the floating gate electrode during a write operation ( The occurrence of a so-called “erroneous write” phenomenon can be prevented.

However, in the three-layer type memory cell, each gate electrode (floating gate electrode, control gate electrode, erase gate electrode) is independently formed into a desired shape by using a photolithography technique and an anisotropic etching technique. You.
Therefore, the positional relationship between the gate electrodes varies due to the positional deviation of the etching mask for forming each gate electrode, and various characteristics (write characteristics, read characteristics, There is a problem that the erasing characteristics also vary.

In order to prevent the variation in the positional relationship between the gate electrodes, it is sufficient that the positional relationship between the gate electrodes has a sufficient margin. There is a problem that cell miniaturization is hindered. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to eliminate the problem of excessive erasure, to provide a large cell current at the time of a read operation, to easily perform accurate data read, and to have a variation in characteristics. It is an object of the present invention to provide a memory cell which can be miniaturized without any problem.

[0014]

Means for Solving the Problems and Effects of the Invention According to the first aspect of the present invention, there is provided a semiconductor device comprising: a source region and a drain region formed on a semiconductor substrate; a source region and a drain region; A floating gate electrode formed on the channel region via a floating gate insulating film, a control gate electrode formed on the channel region via a control gate insulating film, and a floating gate electrode And an erase gate electrode formed via an erase gate insulating film.The floating gate insulating film and the erase gate insulating film are composed of separate insulating films independent of each other, and the floating gate electrode is self-aligned with the control gate electrode. The gist of the present invention is a split gate type memory cell formed in a typical manner.

Therefore, according to the present invention, the control gate electrode turns off the channel region even if the charge is excessively extracted from the floating gate electrode during the erase operation, resulting in excessive erasure. Can be
The problem that the memory cell remains in the erased state and cannot be put into the written state due to excessive erasure can be avoided.

Further, since the control gate insulating film and the erasing gate insulating film are independent and independent insulating films, even if the control gate insulating film is made sufficiently thin to increase the cell current at the time of the read operation, the erasing operation is not performed. When a high voltage is applied to the erase gate electrode during operation, a high electric field does not occur between the control gate electrode and the channel region, and the problem that the control gate insulating film is broken by the high electric field is avoided. be able to. Therefore, by making the control gate insulating film sufficiently thin to increase the cell current during the read operation, accurate data reading from the memory cell can be easily performed without increasing the sensitivity of the sense amplifier.

By making the erase gate insulating film sufficiently thick, the charge accumulation time in the floating gate electrode is extended, and electrons are erroneously injected from the erase gate electrode to the floating gate electrode during a write operation. The occurrence of the erroneous writing phenomenon can be prevented. Furthermore, since the floating gate electrode is formed in a self-aligned manner with respect to the control gate electrode,
Even when the memory cell is miniaturized, it is possible to accurately align the control gate electrode and the floating gate electrode, and there is no variation in the write characteristics and the read characteristics related to the control gate electrode and the floating gate electrode. A memory cell can be obtained. In addition, according to the present invention, control is performed as in the above-described conventional three-layer type memory cell (each gate electrode is independently formed into a desired shape using photolithography technology and anisotropic etching technology). Since there is no need to provide a margin in the positional relationship between the gate electrode and the floating gate electrode, it is possible to prevent the miniaturization of the memory cell from being hindered by the margin in the positional relationship.

Next, a second aspect of the present invention is directed to the first aspect.
In the split gate memory cell according to the above, the drain region is formed in a self-aligned manner with respect to the control gate electrode, and the source region is formed in a self-aligned manner with respect to the floating gate electrode. And

Therefore, according to the present invention, the drain region is formed in self-alignment with the control gate electrode and the source region is formed in self-alignment with the floating gate electrode. The alignment between the drain region and the control gate electrode, and the alignment between the source region and the floating gate electrode can be accurately performed, and a memory cell with no variation in characteristics can be obtained.

Next, the third aspect of the present invention is the first aspect.
Alternatively, the gist of the split gate memory cell according to claim 2 is that a protrusion protruding from the floating gate electrode toward the erase gate electrode is provided. Therefore, according to the present invention, in the erase operation, the electrons in the floating gate electrode jump out of the projections and move to the erase gate electrode side, so that the movement of the electrons is facilitated and the electrons in the floating gate electrode are efficiently removed. The erasing characteristic can be improved because the erasing characteristics can be improved.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a partial schematic cross-sectional view of a memory cell array 2 in a flash EEPROM using the memory cells 1 of the present embodiment.

The split gate type memory cell (split gate type transistor) 1 includes a source region 3, a drain region 4, a channel region 5, a floating gate electrode 6, a control gate electrode 7, and an erase gate electrode 8. The memory cell 1 has a three-layer structure of polysilicon formed on a P-type single-crystal silicon substrate 9, has a control gate electrode 7 formed by first-layer polysilicon, and a floating gate formed by second-layer polysilicon. This is a three-layer memory cell in which an electrode 6 is formed and an erase gate electrode 8 is formed by a third layer of polysilicon.

An N-type source region 3 and a drain region 4 are formed on the substrate 9, and the respective regions 3 and 3 on the substrate 9 are formed.
A channel region 5 is formed in a portion sandwiched between the four. A floating gate electrode 6 is formed on the source region 3 and the channel region 5 via a floating gate insulating film 10 so as to cover a part of the regions 3 and 5. On the channel region 5 on the drain region 4 side, a control gate electrode 7 is formed via a control gate insulating film 11. A floating gate insulating film 10 is formed between the floating gate electrode 6 and the control gate electrode 7.

That is, the memory cell 1 includes a transistor 13 (hereinafter referred to as a "floating gate transistor") composed of a floating gate electrode 6 and each of the regions 3 to 5, a control gate electrode 7 and each of the regions 3 to 5. (Hereinafter, referred to as “selection transistor”) 14 are connected in series.

The upper end of the floating gate electrode 6 protrudes upward, and the protruding portion forms a protrusion 6a. On the protrusion 6a of the floating gate electrode 6, an erase gate electrode 8 is formed via an erase gate insulating film 15. Source wiring 16 is formed on source region 3. Between the source wiring 16 and the floating gate electrode 6,
An insulating film 17 is formed. Further, an erase gate insulating film 15 is formed between the source line 16 and the erase gate electrode 8. An insulating film 18 and an erase gate insulating film 15 are formed between the control gate electrode 7 and the erase gate electrode 8. In addition, the floating gate insulating film 10 and the erase gate insulating film 15 formed on the drain region 4
Between them, an interlayer insulating film 19 is formed. Further, an interlayer insulating film 20 is formed on the memory cell 1.

The memory cell array 2 includes a plurality of memory cells 1 formed on a substrate 9. In order to reduce the occupied area on the substrate 9, each adjacent memory cell 1 (hereinafter, "1a""1
b) indicates that the source region 3 or the drain region 4 is made common and the respective electrodes 6 to 8 are inverted with respect to the common source region 3 or the drain region 4 (the source region perpendicular to the substrate 9). The electrodes 6 to 8 are arranged symmetrically with respect to the center line of the drain region 3 or the drain region 4).
In addition, each memory cell 1a, 1
The respective erase gate electrodes 8 of b are connected.

FIG. 2 is a partial plan view of the memory cell array 2. FIG. 1 is a sectional view taken along line AA in FIG. A field insulating film 21 is formed on the substrate 9, and the field insulating film 21 performs element isolation between the memory cells 1.

Each memory cell 1 arranged in the vertical direction in FIG.
The source region 3 (not shown), the source wiring 16, and the erase gate electrode 8 are common to each other. The control gate electrode 7 of each memory cell 1 arranged in the vertical direction in FIG. 2 is common, and the control gate electrode 7 forms a word line. The drain region 4 arranged in the lateral direction in FIG. 2 is formed through the floating gate insulating film 10, the interlayer insulating film 19, the erase gate insulating film 15, and the bit line contact 22 formed in the interlayer insulating film 20. Insulating film 2
It is connected to a bit line 23 formed on 0. Therefore, the source wiring 16 and the word line are arranged in parallel,
The bit line 23 is orthogonal to the word line.

Then, peripheral circuits are connected to the memory cell array 2 configured as described above to
OM is configured. The circuit configuration of the flash EEPROM using the memory cell 1 which is a three-layer type memory cell is described in various documents (for example, P.25- of Flash Memory Technology Handbook (published in 1993, published by Science Forum Co., Ltd.)). P.52 etc.) and are well-known, so that the description is omitted here.

Next, each operation of the memory cell 1 (write operation,
The read operation and the erase operation will be described. In the write operation, the source line 16 (source region 3), the bit line 23
(Drain region 4), word line (control gate electrode 7),
By controlling the potential of the erase gate electrode 8, a high electric field is generated between the channel region 5 and the floating gate electrode 6, and the high electric field accelerates electrons in the channel region 5 to generate hot electrons. Electrons are injected into the floating gate electrode 6 through the floating gate insulating film 10 and charge is accumulated in the floating gate electrode 6. Therefore, charges are accumulated in the floating gate electrode 6 of the memory cell 1 in a data writing state, and the channel region 5 immediately below the floating gate electrode 6 is in an off state. Further, no charge is accumulated in the floating gate electrode 6 of the memory cell 1 in the data erased state, and the channel region 5 immediately below the floating gate electrode 6 is in the ON state.

In the read operation, the cell current flowing from the drain region 4 to the source region 3 in the memory cell 1 in the write state is smaller than that in the memory cell 1 in the erase state due to the on / off state of the channel region 5 described above. Utilizing this fact, the difference between the cell currents is detected using a sense amplifier (not shown) connected to the bit line 23 to determine whether the memory cell 1 is in the written state or the erased state. I do.

In the erase operation, the potentials of the source line 16 (source region 3), the bit line 23 (drain region 4), the word line (control gate electrode 7) and the erase gate electrode 8 are controlled so that the erase gate electrode 8 A voltage of more than ten volts is applied to generate a high electric field between the floating gate electrode 6 and the erase gate electrode 8, and the high electric field causes the FN tunnel from the erase gate electrode 8 to the floating gate electrode 6 through the erase gate insulating film 15. A current is caused to flow, and electrons in the floating gate electrode 6 are drawn to the erase gate electrode 8 side. As a result, the threshold voltage of the memory cell 1 decreases.

At this time, each gate electrode 6, 8 is capacitively coupled via the erase gate insulating film 15. However, since the floating gate electrode 6 has the projection 6 a, the floating gate electrode 6 The electrons jump out of the protrusion 6a and move to the erase gate electrode 8 side. Therefore, the movement of the electrons is facilitated and the electrons in the floating gate electrode 6 can be efficiently extracted, so that the erasing characteristics can be improved.

Since the memory cell 1 is provided with the selection transistor 14, each memory cell 1 constituting the memory cell array 2 has a function of selecting itself. In other words, the control gate electrode 7 can turn off the channel region 5 even if excessive erasure occurs due to excessive bleeding of charges when extracting charges from the floating gate electrode 6 in the erasing operation. Therefore, even if an over-erasure occurs, the on / off state of the memory cell 1 can be controlled by the selection transistor 14, so that the over-erasure leaves the memory cell 1 in the erased state and enters the write state. The problem of being unable to do so can be avoided.

In the memory cell 1, the control gate insulating film 11 and the erase gate insulating film 15 are independent and separate insulating films. Even when the voltage is increased, a high electric field does not occur between the control gate electrode 7 and the channel region 5 when a voltage of more than ten volts is applied to the erase gate electrode 8 during the erase operation. The problem that the control gate insulating film 11 is destroyed by the electric field can be avoided. Therefore, by making the control gate insulating film 11 sufficiently thin to increase the cell current in the read operation, accurate data reading from the memory cell 1 can be easily performed without increasing the sensitivity of the sense amplifier. .

In addition, by making the erase gate insulating film 15 sufficiently thick, the charge accumulation time in the floating gate electrode 6 is extended, and electrons are transferred from the erase gate electrode 8 to the floating gate electrode 6 during a write operation. It is possible to prevent an erroneous writing phenomenon that is erroneously injected.

Next, a method of manufacturing the memory cell array 2 will be described with reference to FIGS.
This will be described with reference to FIG. Step 1 (see FIG. 2): LOCOS (Local Oxidation of
A field insulating film 21 is formed on a P-type single-crystal silicon substrate 9 by using a silicon (Si) method or a shallow trench isolation (STI) method.

Step 2 (see FIG. 3A): A control gate insulating film 11 (thickness: about 10 nm) made of a silicon oxide film is formed on the substrate 9 by using a thermal oxidation method. Next, LP
By using a CVD (Low Pressure Chemical Vapor Deposition) method, a first-layer doped polysilicon film 31 (film thickness: 15) to be the control gate electrode 7 is formed on the control gate insulating film 11.
(About 0 nm). Subsequently, CVD (Chemical
A silicon nitride film 32 (thickness: about 400 nm) is deposited on the doped polysilicon film 31 by using a vapor deposition method. Then, using a photolithography technique and an anisotropic etching technique, the silicon nitride film 32 is formed.
Is patterned.

Step 3 (see FIG. 3B): A silicon oxide film 33 (thickness: about 400 nm) is deposited on the entire surface of the device manufactured in the above step by using the LPCVD method.
Next, the entire surface is etched back (for example, RIE (Reactive
Only the silicon oxide film 33 on the side wall of the silicon nitride film 32 is left by using the ion etching (Ion Etching) method. as a result,
The silicon oxide film 33 remaining on the side wall of the silicon nitride film 32 becomes the insulating film 18.

Step 4 (see FIG. 3C): The silicon nitride film 32 is selectively removed by etching. Next, the insulating film 1
The doped polysilicon film 31 and the control gate insulating film 11 are selectively etched away by an anisotropic etching method (for example, RIE method) using 8 as an etching mask. As a result, the control gate electrode 7 is formed by the remaining doped polysilicon film 31.

Step 5 (see FIG. 4A): Thermal oxidation method and L
The floating gate insulating film 1 made of a silicon oxide film is formed on the entire surface of the device manufactured in the above-mentioned process by using the PCVD method together.
0 (thickness: about 10 nm) is formed. Then, the insulating film 18 made of a silicon oxide film and the floating gate insulating film 10 are laminated and integrated.

Step 6 (see FIG. 4B): A second-layer doped polysilicon film 34 serving as the floating gate electrode 6 is formed on the entire surface of the device manufactured in the above-described step by using the LPCVD method.
(Thickness: about 200 nm) is deposited. Next, only the doped polysilicon film 34 at least on the sidewall portions on both sides of the control gate electrode 7 is left by using the entire surface etch back method. At this time, the top portion of the doped polysilicon film 34 has a shape protruding upward.

Step 7 (see FIG. 4 (c)): Using a photolithography technique, a photoresist film 35 is formed so as to cover the two insulating films 18 disposed on the substrate 9 with the portion serving as the source region 3 interposed therebetween. Form. Next, the doped polysilicon film 34 formed in a portion to be the drain region 4 on the substrate 9 is selectively etched away by an anisotropic etching method using the photoresist film 35 as an etching mask. As a result, the remaining doped polysilicon film 34 becomes the floating gate electrode 6. here,
Since the top portion of the doped polysilicon film 34 has a shape protruding upward, the protruding portion becomes the protrusion 6 a of the floating gate electrode 6. Subsequently, the insulating film 1
8, floating gate insulating film 10 and photoresist film 35
The substrate 9 is doped with phosphorus ions by an ion implantation method using as a mask for ion implantation to form the drain region 4.

Step 8 (see FIG. 5A): An interlayer insulating film 19 (thickness: 1000 nm) made of a silicon oxide film is formed on the entire surface of the device manufactured in the above-mentioned process by using the LPCVD method.
Degree). Then, the floating gate insulating film 10 made of a silicon oxide film and the interlayer insulating film 19 are laminated and integrated. Next, CMP (Chemical Mechanical Polishin)
g), the surface of the interlayer insulating film 19 is planarized, and the top portion of the insulating film 18 and the floating gate insulating film 10 formed on the portion are reduced until the protrusion 6a of the floating gate electrode 6 is not exposed. Is removed.

Step 9 (see FIG. 5B): A photoresist film 38 is formed by photolithography so as to cover a portion of the substrate 9 other than the source region 3. Next, the interlayer insulating film 19 deposited between the adjacent floating gate electrodes 6 is removed by etching using an anisotropic etching method using the photoresist film 38 and the floating gate electrode 6 as an etching mask. Floating gate insulating film 1 formed between floating gate electrodes 6
0 is removed by etching.

Step 10 (see FIG. 5C): An insulating film 17 made of a silicon oxide film is formed on the entire surface of the device manufactured in the above-mentioned steps by using both the thermal oxidation method and the LPCVD method. Here, in the thermal oxidation method, the oxidation rate of the doped polysilicon film is higher than that of the single crystal silicon substrate. Therefore, the thickness of the insulating film 17 on the surface of the floating gate electrode 6 is larger than that of the insulating film 17 on the surface of the substrate 9. Next, when the insulating film 17 is removed by using the entire surface etch back method until the surface of the substrate 9 is exposed, the insulating film 17 (film thickness: about 10 nm) remains only on the surface of the floating gate electrode 6.

Step 11 (see FIG. 6A): LPCVD
Using a method, a doped polysilicon film 36 is deposited on the entire surface of the device manufactured in the above steps. Next, the doped polysilicon film 36 is removed using a CMP method until the surface of the interlayer insulating film 19 is exposed, leaving only the doped polysilicon film 36 between the adjacent floating gate electrodes 6. Subsequently, only the doped polysilicon film 36 between the adjacent floating gate electrodes 6 is selectively removed by etching using the whole surface etch back method, and the surface of the interlayer insulating film 19 is covered with the doped polysilicon film 36. The surface is dug down by a certain depth (about 10 nm) so that the surface of the doped polysilicon film 36 is lower than the tip of the protrusion 6 a of the floating gate electrode 6. As a result, the remaining doped polysilicon film 36 becomes the source wiring 16. Then, when the temperature becomes high in the subsequent steps, N-type impurities (such as phosphorus) in the doped polysilicon film 36 are thermally diffused to the surface of the substrate 9, and the source region 3 is formed on the substrate 9.

Step 12 (see FIG. 6B): The interlayer insulating film 19 and the insulating film 18 are selectively removed by etching using the entire surface etch-back method, and the protrusion 6 of the floating gate electrode 6 is formed.
Expose a. Step 13 (see FIG. 6C): Using the thermal oxidation method and the LPCVD method together, the erase gate insulating film 15 (film thickness: 1) made of a silicon oxide film is formed on the entire surface of the device manufactured in the above step.
(About 0 nm). Then, the interlayer insulating film 19 made of a silicon oxide film and the erase gate insulating film 15 are laminated and integrated. Next, a third layer of a doped polysilicon film 37 (thickness: about 150 nm) is deposited on the entire surface of the device manufactured in the above process by LPCVD, and photolithography and anisotropic etching are performed. Then, the erased gate electrode 8 made of the doped polysilicon film 37 is formed by patterning the doped polysilicon film 37.

The method of forming each of the doped polysilicon films 31, 34, 36, and 37 serving as the control gate electrode 7, the floating gate electrode 6, the source wiring 16, and the erase gate electrode 8 is as follows. Method 1: When a polysilicon film is formed by using the LPCVD method, a gas containing impurities is mixed into a source gas.

Method 2: After forming a non-doped polysilicon film by using the LPCVD method, an impurity diffusion source layer (such as POCl 3) is formed on the polysilicon film, and an impurity is diffused from the impurity diffusion source layer into the polysilicon film. Spread. Method 3: After forming a non-doped polysilicon film by using the LPCVD method, impurity ions are implanted.

Step 14 (see FIG. 1): An interlayer insulating film 20 made of a silicon oxide film is deposited on the entire surface of the device manufactured in the above step by using the LPCVD method. Then, the erase gate insulating film 15 made of a silicon oxide film and the interlayer insulating film 20 are stacked and integrated. Next, a bit line contact 22 is formed on the floating gate insulating film 10, the interlayer insulating film 19, the erase gate insulating film 15, and the interlayer insulating film 20 on the drain region 4.
To form Next, PVD (Physical Vapor Deposit)
depositing a metal (eg, aluminum alloy) film on the entire surface of the device including the inside of the bit line contact 22 using an ion (ion) method, and patterning the metal film using a photolithography technique and an anisotropic etching technique. Thus, when the bit line 23 made of the metal film is formed, the memory cell array 2 is completed.

As described in detail above, according to the manufacturing method of the present embodiment, the following operations and effects can be obtained. [1] In step 3, the insulating film 18 (silicon oxide film 33) as a side wall spacer is formed on the side wall of the silicon nitride film 32. Then, in step 4, the doped polysilicon film 31 is selectively etched away by an anisotropic etching method using the insulating film 18 as an etching mask, thereby forming a control gate electrode made of the doped polysilicon film 31. 7 is formed. Thereafter, in step 5, a floating gate insulating film 10 is formed on the side wall of the control gate electrode 7, and in steps 6 and 7,
A floating gate electrode 6 (doped polysilicon film 3) serving as a side wall spacer is provided on a side wall portion of the control gate electrode 7.
4) is formed. Therefore, the position of the floating gate electrode 6 is defined by the control gate electrode 7,
Since the floating gate electrode 6 is formed in a self-aligned manner, the gate electrodes 6 and 7 can be accurately positioned even when the memory cell 1 is miniaturized. Therefore, it is possible to obtain the memory cell 1 in which the write characteristics and the read characteristics related to the respective gate electrodes 6 and 7 do not vary.

[2] In the step 7, the control gate electrode 7
Insulating film 18 and floating gate insulating film 10 formed thereon
The substrate 9 is doped with phosphorus ions by an ion implantation method using as a mask for ion implantation to form the drain region 4. Therefore, the position of the drain region 4 is defined by the end of the control gate electrode 7, and the drain region 4 is formed in a self-aligned manner with respect to the control gate electrode 7. Therefore, even when the memory cell 1 is miniaturized, The alignment between the control gate electrode 7 and the drain region 4 can be performed accurately.

[3] In step 11, N is transferred from the source line 16 (doped polysilicon film 36) formed on the end of the floating gate electrode 6 via the insulating film 17 to the substrate 9.
The source region 3 is formed by thermally diffusing the mold impurities. Therefore, the position of the source region 3 is defined by the end of the floating gate electrode 6, and the source region 3 is formed in a self-aligned manner with respect to the floating gate electrode 6. Therefore, even when the memory cell 1 is miniaturized, Alignment between floating gate electrode 6 and source region 3 can be performed accurately.

[4] According to the above [1] to [3], the constituent members of the memory cell 1 (floating gate electrode 6, control gate electrode 7, source region 3, drain region 4, channel region 5)
Are formed in a self-aligned manner with each other, and accurate positioning of these members can be performed. Therefore, it is possible to obtain a memory cell 1 having no variation in characteristics.

According to the present embodiment, as in the above-described conventional three-layer type memory cell (each gate electrode is independently formed into a desired shape using a photolithography technique and an anisotropic etching technique). In addition, since there is no need to provide a margin for the positional relationship between the floating gate electrode and the control gate electrode, the memory cell 1
Can be prevented from being hindered.

The present invention is not limited to the above-described embodiment, but may be embodied as follows. Even in such a case, the same operation or effect as that of the above-described embodiment can be obtained. . (1) The insulating films 10, 11, 15, 17, and 18 are not limited to silicon oxide films, but may be replaced with any insulating film having sufficient insulating characteristics. For example, an insulating film containing silicon nitride oxide or silicon nitride as a main component or a structure in which a plurality of different insulating films are stacked may be used.

(2) The interlayer insulating films 19 and 20 are not limited to silicon oxide films, and may be replaced with any insulating film having sufficient insulating characteristics and flatness. For example, a BPSG film formed using a plasma CVD method or a structure in which a plurality of the BPSG film and a silicon oxide film formed using an LPCVD method are stacked may be used.

(3) The gate electrodes 5 to 8 and the source wiring 16 are not limited to the doped polysilicon film, but may be replaced with any electrode material having sufficient conductivity. For example, amorphous silicon, single crystal silicon, various metals including high melting point metals, metal silicide, or the like may be used.

(4) The method of forming the source region 3 in the steps 10 and 11 is replaced by the following method. First, in the state shown in FIG. 5B, an N-type impurity is ion-implanted into the exposed substrate 9 by ion implantation using the photoresist film 38 and the floating gate electrode 6 as an ion implantation mask, and thermally diffused. The source region 3 is formed.
Thereby, the area of the source region 3 can be defined with high accuracy, and the alignment between the floating gate electrode 6 and the source region 3 can be performed accurately.
And the overlap amount between the source region 3 and the source region 3 can be adjusted with good controllability.

Thereafter, a doped polysilicon film 36 doped with arsenic is deposited. At this time, arsenic is deposited on the substrate 9.
, The area of the source region 3 does not increase. (5) The impurity for forming the source region 3 and the drain region 4 is not limited to phosphorus, and any N-type impurity (such as arsenic or antimony) may be used.

(6) The P-type single crystal silicon substrate 9 may be replaced with a P-type well. (7) The P-type single-crystal silicon substrate 9 is replaced with an N-type single-crystal silicon substrate or an N-type well, and P-type impurities (boron, indium, etc.) are used as impurities for forming the source region 3 and the drain region 4. You may.

[Brief description of the drawings]

FIG. 1 is a partial schematic cross-sectional view of an embodiment embodying the present invention.

FIG. 2 is a partial plan view of one embodiment.

FIG. 3 is a partial schematic cross-sectional view illustrating a manufacturing method according to one embodiment.

FIG. 4 is a partial schematic cross-sectional view illustrating a manufacturing method according to one embodiment.

FIG. 5 is a partial schematic cross-sectional view illustrating a manufacturing method according to one embodiment.

FIG. 6 is a partial schematic cross-sectional view illustrating a manufacturing method according to one embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Split gate type memory cell 2 ... Memory cell array 3 ... Source region 4 ... Drain region 5 ... Channel region 6 ... Floating gate electrode 7 ... Control gate electrode 8 ... Erase gate electrode 9 ... P type single crystal silicon substrate 10 ... Floating gate Insulating film 11: Control gate insulating film 15: Erase gate insulating film

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (3)

[Claims] A source region and a drain region formed on a semiconductor substrate; a channel region sandwiched between the source region and the drain region; a floating gate electrode formed on the channel region via a floating gate insulating film; A control gate electrode formed on the channel region via a control gate insulating film; and an erase gate electrode formed on the floating gate electrode via an erase gate insulating film. A split gate memory cell comprising a separate insulating film independent of a film, wherein a floating gate electrode is formed in a self-aligned manner with respect to a control gate electrode. 2. The split gate memory cell according to claim 1, wherein said drain region is formed in a self-aligned manner with respect to said control gate electrode, and said source region is formed in a self-aligned manner with said floating gate electrode. A split gate type memory cell formed in a semiconductor device. 3. The split gate memory cell according to claim 1, further comprising: a protrusion protruding from said floating gate electrode toward said erase gate electrode. cell.