JP2006065145A - Liquid crystal display element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display element with which narrowing of the gap and the picture frame is advantageously achieved by preventing a display defect due to seeping of a sealing material from being produced without increasing the number of manufacturing man-hours. <P>SOLUTION: On a display peripheral area Df which is outside a display area Dd having pixel electrodes 8 aligned in a matrix and inside the sealing material 4, a parallel detouring part 7a of a source wire 7 to apply display signal voltage to a source electrode 9e of a thin film transistor 9, which is routed in parallel to the extending direction of the sealing material 4, is arranged on a position of an installing route of the source wire 7 close to the sealing material 4. The seeping of the sealing material toward the display area Dd in joining substrates is suppressed with the parallel detouring part 7a, and a malfunction of display defect production caused by access of the seeping to the display area Dd is prevented. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a narrow gap type liquid crystal display device having a thin liquid crystal layer thickness (gap between substrates).

  The liquid crystal display element is formed by joining a pair of substrates with a frame-shaped sealing material, and encapsulating liquid crystal in a space surrounded by the pair of substrates and the frame-shaped sealing material. As the sealing material in this case, a thermosetting resin such as an epoxy resin or a mixed resin with a silicone resin or the like is usually used.

  In order to join the substrates using the sealing material described above, first, an uncured sealing material is applied to the peripheral edge of one substrate in a frame shape by screen printing or the like, and then the other substrate is pasted while positioning. In addition, pressurization and heating (hereinafter referred to as thermocompression bonding) are performed to obtain a predetermined substrate gap, and the sealing material is cured. In the thermocompression bonding process of this substrate, the uncured sealing material whose viscosity has been reduced by heating is crushed and spreads so as to melt along the surface of the substrate (hereinafter referred to as squeeze out). Is not uniform.

  That is, in the sealing material application area, wiring drawn from the inside of the sealing material to the outside in order to apply a voltage to the electrodes formed on the opposing surfaces of the pair of substrates is disposed. Since the gap is narrowed at least by the height of the wiring, the sandwiched sealing material squeezes the narrowed gap between the wiring and one substrate by capillary action. To spread.

  On the other hand, in recent years, the inter-substrate gap (liquid crystal layer thickness) has been narrowed in order to increase the response speed of the liquid crystal display element so as to be suitable for moving image display. The ratio of the gap between the non-existing portion and the non-existing portion is increased, and the seal material squeezes out along the wiring. This expands to the display area and causes display defects such as “white spots”.

Conventionally, as a method for preventing the occurrence of display defects due to the above-described squeezing of the sealing material into the display area, the spread of the squeezing between the sealing material and the display area as shown in Patent Document 1 is prevented. A method of arranging a wall member for this purpose has been proposed. However, this method increases the number of manufacturing steps because the wall member needs to be formed of a material different from the sealing material, that is, a material that does not easily squeeze even if it is thermocompression bonded. In addition, since it is necessary to secure an area for disposing the wall member around the display region, it is disadvantageous for narrowing the frame that has been demanded in recent years in order to promote downsizing of the liquid crystal display element.
Japanese Patent Laid-Open No. 2001-51282

  An object of the present invention is to provide a liquid crystal display element that can prevent the occurrence of display defects due to squeezing of a sealing material without increasing the number of manufacturing steps, and is advantageous for promoting narrowing and narrowing of the frame.

The liquid crystal display element of the present invention includes a pair of substrates, a frame-shaped sealing material that joins the pair of substrates with a predetermined gap therebetween, electrodes formed on respective inner surfaces facing the pair of substrates,
The liquid crystal sealed in a space surrounded by the inner surfaces of the frame-shaped sealing material and the pair of substrates facing each other, and the liquid crystal sealed space from the outside of the sealing material to the inside in order to apply a voltage to the electrode A plurality of pixels formed by regions where both electrodes disposed on each of the inner surfaces of the pair of substrates face each other, and a display region for performing display. A liquid crystal display element forming a display peripheral region located between the display region and the sealing material, wherein a wiring length of the wiring in the display peripheral region is such that the wiring is the display region and the display peripheral It is characterized by being formed longer than the distance between the boundary and the sealing material at a position intersecting with the boundary of the region.

  According to the liquid crystal display element of the present invention, the wiring length of the wiring in the display peripheral region is longer than the distance between the boundary and the sealing material at the position where the wiring intersects the boundary between the display region and the display peripheral region. That is, since the distance of the wiring routed in the display peripheral area outside the display area inside the seal material is set longer than the width of the display peripheral area at the position entering the display peripheral area from the display area, The expansion of the seal material along the wiring of the seal material in the direction of the seal width will be reduced by the extended amount, and the narrow gap causes the seal material to squeeze into the display area, causing a display defect. Can be prevented without increasing the number of manufacturing steps.

  In the liquid crystal display element of the present invention, it is preferable that at least a part of the wiring is arranged around the display peripheral region in parallel with the extending direction of the sealing material. Advances substantially parallel to the extending direction of the sealing material, and the squeezing out along the wiring is suppressed by the wiring part parallel to the sealing material, so that the problem that the sealing material squeezes out to the display area is surely prevented. .

  The liquid crystal display element of the present invention is more preferably applied to an active matrix type liquid crystal display element in which a wiring is a source wiring and a gate wiring connected to a thin film transistor provided for each pixel electrode. The narrowing of the gap of the liquid crystal display element can be promoted to a high degree without causing a display defect due to the sticking out of the sealing material.

Hereinafter, preferred embodiments of the present invention will be described.
FIG. 1 is a schematic plan view showing an active matrix type liquid crystal display device as one embodiment of the present invention, FIG. 2 is a detailed view of a Q portion thereof, and FIG. 3 is a sectional view taken along line III-III in FIG.

  In the liquid crystal display element 1 of the present embodiment, a pair of large and small substrates 2 and 3 that are both transparent and rectangular are joined together with a frame-shaped sealing material 4 with a predetermined gap therebetween. A liquid crystal 5 (see FIG. 3) is sealed between the opposing surfaces (hereinafter referred to as inner surfaces) of the enclosed large and small substrates 2 and 3. The large and small substrates 2 and 3 are joined with their corresponding two adjacent sides aligned. Accordingly, the other two adjacent sides of the large substrate 2 are extended outward by a predetermined width from the two adjacent sides of the small substrate 3 corresponding to these two sides, and the adjacent extending portions 2a and 2b are formed. Is formed.

  The sealing material 4 is made of a thermosetting resin such as an epoxy resin. In the joining process, an uncured thermosetting resin as a sealing material is applied in a frame shape along the peripheral edge of the small substrate 3 by screen printing. The other large substrate 2 is bonded to this while aligning, and is pressurized with a predetermined pressure while being heated to a predetermined temperature. As a result, the thermosetting resin is cured, and the large and small substrates 2 and 3 are joined with a predetermined gap therebetween.

  On the inner surface (opposing surface) of the large substrate 2 facing the small substrate 3, a plurality of wirings 6 and 7 are arranged in parallel at equal intervals in directions orthogonal to each other. As shown in FIG. 2, pixel electrodes 8 are disposed in the individual areas surrounded by the orthogonal wirings 6 and 7, respectively. The individual pixel electrodes 8 and the wirings 6 and 7 are electrically connected via thin film transistors 9 as switching elements.

  As shown in FIG. 3, the thin film transistor 9 includes a gate electrode 9a formed on the inner surface of the large substrate 2, and a gate insulating film 9b formed so as to cover the gate electrode 9a and cover almost the entire inner surface of the large substrate 2. And an i-type semiconductor film 9c disposed opposite to the gate electrode 9a on the gate insulating film 9b, and n-type semiconductor films 9d serving as ohmic contact layers on both sides of the i-type semiconductor film 9c. The source electrode 9e and the drain electrode 9f, and the blocking layer 9g covering the central portion of the i-type semiconductor film 9c corresponding to the channel region where the end faces of the source electrode 9e and the drain electrode 9f face each other.

  In the thin film transistor 9 of this embodiment, as shown in FIG. 2, a predetermined portion of one wiring 6 is used as a gate electrode, and a predetermined portion of the other wiring 7 is extended by a predetermined length in a perpendicular direction to form a source electrode 9e. Therefore, the wiring 6 is a gate wiring, the wiring 7 is a source wiring, and each thin film transistor 9 is installed on the gate wiring 6. Although the gate wiring 6 is directly installed on the inner surface of the large substrate 2, the source wiring 7 is installed on the gate insulating film 9b. Further, the thickness of the source wiring 7 is set to be sufficiently thicker than that of the gate wiring 6 in order to suppress a decrease in the signal voltage output to each pixel electrode due to its electrical resistance.

  Then, as shown in FIG. 3, on the inner surface of the large substrate 2, the thin film transistor 9, the wirings 6 and 7, and the gate insulating film 9 b are covered and opened in areas corresponding to the plurality of pixel electrodes 8 described above. The insulating protective film 10 on which is formed is applied over substantially the entire inner surface (in the liquid crystal sealing space) of the sealing material 4.

  On the other hand, on the inner surface of the small substrate 3 on the opposite side, at least an area facing the area where the pixel electrodes 8 on the large substrate 2 side are arranged in a matrix, the single-layer counter electrode 11 is attached. A region in which the counter electrode 11 and the pixel electrode 8 are opposed to each other through the liquid crystal 5 is a pixel for display. Accordingly, in the present embodiment, the pixel electrode 8 shown in FIG. As shown, a display region Dd in which pixels are arranged in a matrix is formed inside the sealing material 4. A light shielding film 12 is provided on the inner surface of the small substrate 3 surrounding the display area Dd, thereby demarcating the range of the display area Dd and preventing light leakage from the periphery of the display area Dd. Although not shown in the drawing, an alignment film for regulating the alignment of the liquid crystal is deposited on the surfaces of the substrates 2 and 3 that are in contact with the liquid crystal 5 inside the sealing material 4.

  Returning to FIG. 1, each of the gate wiring 6 and the source wiring 7 described above has one end portion extended from the display region Dd and is routed toward the corresponding substrate extension portions 2a and 2b. A gate driver element 13 and a source driver element 14 are mounted on each of the substrate extension portions 2a and 2b by a COG (Chip On Glass) method, respectively. Therefore, the gate wiring 6 and the source wiring 7 are routed toward the corresponding connection terminal ports in the installation area of the gate driver element 13 and the source driver element 14, respectively.

  Here, in each routing route of the gate wiring 6 and the source wiring 7, a detour for preventing the seal material from squeezing out at the time of substrate bonding is set. That is, as shown in FIG. 2, one end of the source wiring 7 is extended to the vicinity thereof at a right angle toward the sealing material 4, and thereafter, a predetermined distance L in parallel with the extending direction of the sealing material 4. After that, it extends in a direction to enter at right angles to the sealing material 4. Here, the parallel bypass portion 7a having the distance L may be disposed outside the display area Dd and in an area Df inside the arrangement area As of the sealing material 4 (hereinafter referred to as a display peripheral area). A position closer to the sealing material 4 than the center of the width of the region Df is preferable, and a position separated from the sealing material 4 by the approximate line width of the source wiring 7 as in the present embodiment is more preferable. The arrangement area As of the sealing material 4 serving as a reference for the display peripheral region Df is a design target area indicated by a two-dot chain line in the figure, which is determined from the application position and amount of the sealing material and the seal gap dimension. Yes, it is different from the arrangement area of the sealing material 4 actually formed through the joining process.

  In this way, by making the routing route of the source wiring 7 a detour having a parallel detour portion 7a having a distance L extending in parallel with the extending direction of the seal material 4, the seal material squeezes out in the seal width direction. To be suppressed.

  That is, in the substrate bonding step, the applied sealing material is melted by being pressurized while being heated, and the melted sealing material is formed into a narrow gap path on the source wiring 7 (FIG. 3). The source wiring 7 is bent in the direction parallel to the sealing material 4 in the vicinity of the arrangement area indicated by the two-dot chain line of the sealing material 4, so that the sealing due to the capillary phenomenon occurs. The squeezing direction of the material is also bent substantially along the arrangement path of the source wiring 7. Further, the melt seal material may swell locally in the width direction without following the source wiring 7 due to factors other than the capillary phenomenon such as material variation, but such an unexpected squeeze 4a occurs. In addition, the parallel bypass portion 7a of the source wiring 7 serves as a wall to prevent squeezing in the width direction. As a result, the amount of squeezing out of the sealing material does not change, but since the direction of squeezing is along the extending direction of the applied sealing material, the amount of squeezing out in the width direction of the sealing material, that is, the amount of squeezing out is remarkable It is suppressed.

  As described above, in the present embodiment, the bypass portion 7a parallel to the extending direction of the seal material 4 is provided in the routing arrangement path in the display peripheral region Df of the gate line 6 and the source line 7, and therefore heating is performed in the bonding step. The squeezing width of the melted sealing material is remarkably suppressed, whereby the width of the sealing material 4 is locally expanded, and the sealing material 4 advances to the display area Dd to cause display defects such as white spots. Is reliably prevented. In addition, since only a wiring arrangement route is changed and a new process for providing a member for suppressing the sticking out of the sealing material is not required, the number of manufacturing steps is not increased.

  Next, another embodiment of the present invention will be described with reference to FIG. In addition, the same code | symbol is attached | subjected about the component same as the said embodiment, and the description is abbreviate | omitted.

  The liquid crystal display element 20 of the present embodiment is a simple matrix type liquid crystal display element, and a pair of transparent substrates 21 and 22 are joined by a frame-shaped sealing material 23 and surrounded by the frame-shaped sealing material 23. A liquid crystal (not shown) is sealed between the inner surfaces of each. A plurality of display electrodes 23 and a plurality of scanning electrodes 24 are arranged in parallel with each other on the inner surfaces of the pair of transparent substrates 21 and 22, respectively. These display electrodes 23 and the scanning electrodes 24 intersect with each other through the liquid crystal to display pixels, and a display region Dd in which the pixels are arranged in a matrix is formed.

  Driver elements 26 and 27 are installed in the extending portions 21a and 22a of the transparent substrates 21 and 22 by the COG method. The driver elements 26 and 27, the display electrode 23, and the scanning electrode 24 are respectively connected to the respective electrodes. Are electrically connected by wires 28 and 29 extending from one end thereof. In the arrangement path of these wirings 28 and 29, a detour is set for suppressing the squeezing out of the sealing material at the time of substrate bonding.

  As shown in FIG. 4B in which the Q portion in FIG. 4A is enlarged, one end portion of the display electrode 24 is extended to the display peripheral region Df, from which the display electrode driving driver element 26 is extended. The wiring 28 is routed toward the corresponding connection terminal port in the installation area (see FIG. 5A). Therefore, the arrangement path of the wiring 28 is a path that enters obliquely with respect to the arrangement area As of the sealing material 23.

  As described above, in the present embodiment, since the wiring 28 is disposed so as to be inclined with respect to the sealing material arrangement area As, the wiring 28 is disposed with respect to the sealing material arrangement area As. Therefore, the arrangement route in the display peripheral region Df becomes longer than the case of entering from the perpendicular direction (width direction). Thereby, at the time of board | substrate joining, the expansion of the seal width by squeezing is suppressed compared with the case where the sealing material stagnates along the wiring 27 and squeezes in a right angle direction. Also in the area where the wiring 29 of the scanning electrode 25 is provided, the expansion of the seal width is suppressed for the same reason. As a result, it is possible to surely prevent the occurrence of the problem that the sealing material 23 enters the display area Dd and causes display failure.

In addition, this invention is not limited to said embodiment.
For example, in the above-described embodiment, a detour for suppressing the squeezing of the seal material to the display area side is formed in all the wiring paths. However, the detour is not limited to this, and the detour is caused by the squeeze of the seal material. You may selectively provide in the wiring of the area where an increase in the seal width is likely to occur, or the wiring in the area where the increase in the seal width must be particularly suppressed.

1 is a schematic plan view showing a liquid crystal display element as one embodiment of the present invention. FIG. 2 is a partially enlarged plan view showing a Q portion in FIG. 1 in detail. It is the III-III sectional view taken on the line of FIG. FIG. 4 shows another embodiment of the present invention, in which (a) is a schematic plan view thereof, and (b) is a partially enlarged plan view showing in detail a Q portion in (a).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 20 Liquid crystal display element 2, 3, 21, 22 Substrate 4, 23 Sealing material 5 Liquid crystal 6, 7, 28, 29 Wiring 8 Pixel electrode 9 Thin film transistor 10 Insulating protective film 11 Counter electrode 12 Light shielding film 13 Gate driver element 14 Source Driver element 24 Display electrode 25 Scan electrode 26, 27 Driver element

Claims (3)

A pair of substrates;
A frame-shaped sealing material that joins the pair of substrates while maintaining a predetermined gap;
Electrodes formed on the opposing inner surfaces of the pair of substrates,
A liquid crystal sealed in a space surrounded between the inner surfaces of the frame-shaped sealing material and the pair of substrates facing each other;
Both electrodes disposed on the inner surfaces of the pair of substrates, respectively, in order to apply a voltage to the electrodes, and have a wiring routed from the outside of the sealing material to the inside liquid crystal enclosure space. A plurality of pixels formed by regions facing each other, and a liquid crystal display element that forms a display region for performing display and a display peripheral region located between the display region and the sealing material,
The wiring length of the wiring in the display peripheral region is longer than the distance between the boundary and the sealing material at a position where the wiring intersects the boundary between the display region and the display peripheral region. A liquid crystal display element.   2. The liquid crystal display element according to claim 1, wherein at least a part of the wiring is arranged in parallel with the extending direction of the sealing material in the display peripheral region.   3. The liquid crystal display element according to claim 1, wherein the liquid crystal display element is an active matrix liquid crystal display element, and the wiring is a source wiring and a gate wiring connected to a thin film transistor provided for each pixel electrode. A liquid crystal display element according to 1.

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